Linux 5.15-rc6
[muen/linux.git] / drivers / memory / jedec_ddr_data.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * DDR addressing details and AC timing parameters from JEDEC specs
4  *
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  *
7  * Aneesh V <aneesh@ti.com>
8  */
9
10 #include <linux/export.h>
11
12 #include "jedec_ddr.h"
13
14 /* LPDDR2 addressing details from JESD209-2 section 2.4 */
15 const struct lpddr2_addressing
16         lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
17         {B4, T_REFI_15_6, T_RFC_90}, /* 64M */
18         {B4, T_REFI_15_6, T_RFC_90}, /* 128M */
19         {B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
20         {B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
21         {B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
22         {B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
23         {B8, T_REFI_3_9, T_RFC_130}, /* 4G */
24         {B8, T_REFI_3_9, T_RFC_210}, /* 8G */
25         {B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
26         {B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
27 };
28 EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
29
30 /* LPDDR2 AC timing parameters from JESD209-2 section 12 */
31 const struct lpddr2_timings
32         lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
33         /* Speed bin 400(200 MHz) */
34         [0] = {
35                 .max_freq       = 200000000,
36                 .min_freq       = 10000000,
37                 .tRPab          = 21000,
38                 .tRCD           = 18000,
39                 .tWR            = 15000,
40                 .tRAS_min       = 42000,
41                 .tRRD           = 10000,
42                 .tWTR           = 10000,
43                 .tXP            = 7500,
44                 .tRTP           = 7500,
45                 .tCKESR         = 15000,
46                 .tDQSCK_max     = 5500,
47                 .tFAW           = 50000,
48                 .tZQCS          = 90000,
49                 .tZQCL          = 360000,
50                 .tZQinit        = 1000000,
51                 .tRAS_max_ns    = 70000,
52                 .tDQSCK_max_derated = 6000,
53         },
54         /* Speed bin 533(266 MHz) */
55         [1] = {
56                 .max_freq       = 266666666,
57                 .min_freq       = 10000000,
58                 .tRPab          = 21000,
59                 .tRCD           = 18000,
60                 .tWR            = 15000,
61                 .tRAS_min       = 42000,
62                 .tRRD           = 10000,
63                 .tWTR           = 7500,
64                 .tXP            = 7500,
65                 .tRTP           = 7500,
66                 .tCKESR         = 15000,
67                 .tDQSCK_max     = 5500,
68                 .tFAW           = 50000,
69                 .tZQCS          = 90000,
70                 .tZQCL          = 360000,
71                 .tZQinit        = 1000000,
72                 .tRAS_max_ns    = 70000,
73                 .tDQSCK_max_derated = 6000,
74         },
75         /* Speed bin 800(400 MHz) */
76         [2] = {
77                 .max_freq       = 400000000,
78                 .min_freq       = 10000000,
79                 .tRPab          = 21000,
80                 .tRCD           = 18000,
81                 .tWR            = 15000,
82                 .tRAS_min       = 42000,
83                 .tRRD           = 10000,
84                 .tWTR           = 7500,
85                 .tXP            = 7500,
86                 .tRTP           = 7500,
87                 .tCKESR         = 15000,
88                 .tDQSCK_max     = 5500,
89                 .tFAW           = 50000,
90                 .tZQCS          = 90000,
91                 .tZQCL          = 360000,
92                 .tZQinit        = 1000000,
93                 .tRAS_max_ns    = 70000,
94                 .tDQSCK_max_derated = 6000,
95         },
96         /* Speed bin 1066(533 MHz) */
97         [3] = {
98                 .max_freq       = 533333333,
99                 .min_freq       = 10000000,
100                 .tRPab          = 21000,
101                 .tRCD           = 18000,
102                 .tWR            = 15000,
103                 .tRAS_min       = 42000,
104                 .tRRD           = 10000,
105                 .tWTR           = 7500,
106                 .tXP            = 7500,
107                 .tRTP           = 7500,
108                 .tCKESR         = 15000,
109                 .tDQSCK_max     = 5500,
110                 .tFAW           = 50000,
111                 .tZQCS          = 90000,
112                 .tZQCL          = 360000,
113                 .tZQinit        = 1000000,
114                 .tRAS_max_ns    = 70000,
115                 .tDQSCK_max_derated = 5620,
116         },
117 };
118 EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
119
120 const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
121         .tRPab          = 3,
122         .tRCD           = 3,
123         .tWR            = 3,
124         .tRASmin        = 3,
125         .tRRD           = 2,
126         .tWTR           = 2,
127         .tXP            = 2,
128         .tRTP           = 2,
129         .tCKE           = 3,
130         .tCKESR         = 3,
131         .tFAW           = 8
132 };
133 EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);