drm/amdgpu: add uvd enc vm functions (v2)
[muen/linux.git] / drivers / memory / pl172.c
1 /*
2  * Memory controller driver for ARM PrimeCell PL172
3  * PrimeCell MultiPort Memory Controller (PL172)
4  *
5  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
6  *
7  * Based on:
8  * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
9  *
10  * This file is licensed under the terms of the GNU General Public
11  * License version 2. This program is licensed "as is" without any
12  * warranty of any kind, whether express or implied.
13  */
14
15 #include <linux/amba/bus.h>
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_platform.h>
25 #include <linux/time.h>
26
27 #define MPMC_STATIC_CFG(n)              (0x200 + 0x20 * n)
28 #define  MPMC_STATIC_CFG_MW_8BIT        0x0
29 #define  MPMC_STATIC_CFG_MW_16BIT       0x1
30 #define  MPMC_STATIC_CFG_MW_32BIT       0x2
31 #define  MPMC_STATIC_CFG_PM             BIT(3)
32 #define  MPMC_STATIC_CFG_PC             BIT(6)
33 #define  MPMC_STATIC_CFG_PB             BIT(7)
34 #define  MPMC_STATIC_CFG_EW             BIT(8)
35 #define  MPMC_STATIC_CFG_B              BIT(19)
36 #define  MPMC_STATIC_CFG_P              BIT(20)
37 #define MPMC_STATIC_WAIT_WEN(n)         (0x204 + 0x20 * n)
38 #define  MPMC_STATIC_WAIT_WEN_MAX       0x0f
39 #define MPMC_STATIC_WAIT_OEN(n)         (0x208 + 0x20 * n)
40 #define  MPMC_STATIC_WAIT_OEN_MAX       0x0f
41 #define MPMC_STATIC_WAIT_RD(n)          (0x20c + 0x20 * n)
42 #define  MPMC_STATIC_WAIT_RD_MAX        0x1f
43 #define MPMC_STATIC_WAIT_PAGE(n)        (0x210 + 0x20 * n)
44 #define  MPMC_STATIC_WAIT_PAGE_MAX      0x1f
45 #define MPMC_STATIC_WAIT_WR(n)          (0x214 + 0x20 * n)
46 #define  MPMC_STATIC_WAIT_WR_MAX        0x1f
47 #define MPMC_STATIC_WAIT_TURN(n)        (0x218 + 0x20 * n)
48 #define  MPMC_STATIC_WAIT_TURN_MAX      0x0f
49
50 /* Maximum number of static chip selects */
51 #define PL172_MAX_CS            4
52
53 struct pl172_data {
54         void __iomem *base;
55         unsigned long rate;
56         struct clk *clk;
57 };
58
59 static int pl172_timing_prop(struct amba_device *adev,
60                              const struct device_node *np, const char *name,
61                              u32 reg_offset, u32 max, int start)
62 {
63         struct pl172_data *pl172 = amba_get_drvdata(adev);
64         int cycles;
65         u32 val;
66
67         if (!of_property_read_u32(np, name, &val)) {
68                 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
69                 if (cycles < 0) {
70                         cycles = 0;
71                 } else if (cycles > max) {
72                         dev_err(&adev->dev, "%s timing too tight\n", name);
73                         return -EINVAL;
74                 }
75
76                 writel(cycles, pl172->base + reg_offset);
77         }
78
79         dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
80                                 readl(pl172->base + reg_offset));
81
82         return 0;
83 }
84
85 static int pl172_setup_static(struct amba_device *adev,
86                               struct device_node *np, u32 cs)
87 {
88         struct pl172_data *pl172 = amba_get_drvdata(adev);
89         u32 cfg;
90         int ret;
91
92         /* MPMC static memory configuration */
93         if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
94                 if (cfg == 8) {
95                         cfg = MPMC_STATIC_CFG_MW_8BIT;
96                 } else if (cfg == 16) {
97                         cfg = MPMC_STATIC_CFG_MW_16BIT;
98                 } else if (cfg == 32) {
99                         cfg = MPMC_STATIC_CFG_MW_32BIT;
100                 } else {
101                         dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
102                         return -EINVAL;
103                 }
104         } else {
105                 dev_err(&adev->dev, "memory-width property required\n");
106                 return -EINVAL;
107         }
108
109         if (of_property_read_bool(np, "mpmc,async-page-mode"))
110                 cfg |= MPMC_STATIC_CFG_PM;
111
112         if (of_property_read_bool(np, "mpmc,cs-active-high"))
113                 cfg |= MPMC_STATIC_CFG_PC;
114
115         if (of_property_read_bool(np, "mpmc,byte-lane-low"))
116                 cfg |= MPMC_STATIC_CFG_PB;
117
118         if (of_property_read_bool(np, "mpmc,extended-wait"))
119                 cfg |= MPMC_STATIC_CFG_EW;
120
121         if (amba_part(adev) == 0x172 &&
122             of_property_read_bool(np, "mpmc,buffer-enable"))
123                 cfg |= MPMC_STATIC_CFG_B;
124
125         if (of_property_read_bool(np, "mpmc,write-protect"))
126                 cfg |= MPMC_STATIC_CFG_P;
127
128         writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
129         dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
130
131         /* MPMC static memory timing */
132         ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
133                                 MPMC_STATIC_WAIT_WEN(cs),
134                                 MPMC_STATIC_WAIT_WEN_MAX, 1);
135         if (ret)
136                 goto fail;
137
138         ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
139                                 MPMC_STATIC_WAIT_OEN(cs),
140                                 MPMC_STATIC_WAIT_OEN_MAX, 0);
141         if (ret)
142                 goto fail;
143
144         ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
145                                 MPMC_STATIC_WAIT_RD(cs),
146                                 MPMC_STATIC_WAIT_RD_MAX, 1);
147         if (ret)
148                 goto fail;
149
150         ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
151                                 MPMC_STATIC_WAIT_PAGE(cs),
152                                 MPMC_STATIC_WAIT_PAGE_MAX, 1);
153         if (ret)
154                 goto fail;
155
156         ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
157                                 MPMC_STATIC_WAIT_WR(cs),
158                                 MPMC_STATIC_WAIT_WR_MAX, 2);
159         if (ret)
160                 goto fail;
161
162         ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
163                                 MPMC_STATIC_WAIT_TURN(cs),
164                                 MPMC_STATIC_WAIT_TURN_MAX, 1);
165         if (ret)
166                 goto fail;
167
168         return 0;
169 fail:
170         dev_err(&adev->dev, "failed to configure cs%u\n", cs);
171         return ret;
172 }
173
174 static int pl172_parse_cs_config(struct amba_device *adev,
175                                  struct device_node *np)
176 {
177         u32 cs;
178
179         if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
180                 if (cs >= PL172_MAX_CS) {
181                         dev_err(&adev->dev, "cs%u invalid\n", cs);
182                         return -EINVAL;
183                 }
184
185                 return pl172_setup_static(adev, np, cs);
186         }
187
188         dev_err(&adev->dev, "cs property required\n");
189
190         return -EINVAL;
191 }
192
193 static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
194 static const char * const pl175_revisions[] = {"r1"};
195 static const char * const pl176_revisions[] = {"r0"};
196
197 static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
198 {
199         struct device_node *child_np, *np = adev->dev.of_node;
200         struct device *dev = &adev->dev;
201         static const char *rev = "?";
202         struct pl172_data *pl172;
203         int ret;
204
205         if (amba_part(adev) == 0x172) {
206                 if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
207                         rev = pl172_revisions[amba_rev(adev)];
208         } else if (amba_part(adev) == 0x175) {
209                 if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))
210                         rev = pl175_revisions[amba_rev(adev)];
211         } else if (amba_part(adev) == 0x176) {
212                 if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))
213                         rev = pl176_revisions[amba_rev(adev)];
214         }
215
216         dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
217
218         pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
219         if (!pl172)
220                 return -ENOMEM;
221
222         pl172->clk = devm_clk_get(dev, "mpmcclk");
223         if (IS_ERR(pl172->clk)) {
224                 dev_err(dev, "no mpmcclk provided clock\n");
225                 return PTR_ERR(pl172->clk);
226         }
227
228         ret = clk_prepare_enable(pl172->clk);
229         if (ret) {
230                 dev_err(dev, "unable to mpmcclk enable clock\n");
231                 return ret;
232         }
233
234         pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
235         if (!pl172->rate) {
236                 dev_err(dev, "unable to get mpmcclk clock rate\n");
237                 ret = -EINVAL;
238                 goto err_clk_enable;
239         }
240
241         ret = amba_request_regions(adev, NULL);
242         if (ret) {
243                 dev_err(dev, "unable to request AMBA regions\n");
244                 goto err_clk_enable;
245         }
246
247         pl172->base = devm_ioremap(dev, adev->res.start,
248                                    resource_size(&adev->res));
249         if (!pl172->base) {
250                 dev_err(dev, "ioremap failed\n");
251                 ret = -ENOMEM;
252                 goto err_no_ioremap;
253         }
254
255         amba_set_drvdata(adev, pl172);
256
257         /*
258          * Loop through each child node, which represent a chip select, and
259          * configure parameters and timing. If successful; populate devices
260          * under that node.
261          */
262         for_each_available_child_of_node(np, child_np) {
263                 ret = pl172_parse_cs_config(adev, child_np);
264                 if (ret)
265                         continue;
266
267                 of_platform_populate(child_np, NULL, NULL, dev);
268         }
269
270         return 0;
271
272 err_no_ioremap:
273         amba_release_regions(adev);
274 err_clk_enable:
275         clk_disable_unprepare(pl172->clk);
276         return ret;
277 }
278
279 static int pl172_remove(struct amba_device *adev)
280 {
281         struct pl172_data *pl172 = amba_get_drvdata(adev);
282
283         clk_disable_unprepare(pl172->clk);
284         amba_release_regions(adev);
285
286         return 0;
287 }
288
289 static const struct amba_id pl172_ids[] = {
290         /*  PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
291         {
292                 .id     = 0x07041172,
293                 .mask   = 0x3f0fffff,
294         },
295         /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
296         {
297                 .id     = 0x07041175,
298                 .mask   = 0x3f0fffff,
299         },
300         /* PrimeCell MPMC PL176 */
301         {
302                 .id     = 0x89041176,
303                 .mask   = 0xff0fffff,
304         },
305         { 0, 0 },
306 };
307 MODULE_DEVICE_TABLE(amba, pl172_ids);
308
309 static struct amba_driver pl172_driver = {
310         .drv = {
311                 .name   = "memory-pl172",
312         },
313         .probe          = pl172_probe,
314         .remove         = pl172_remove,
315         .id_table       = pl172_ids,
316 };
317 module_amba_driver(pl172_driver);
318
319 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
320 MODULE_DESCRIPTION("PL172 Memory Controller Driver");
321 MODULE_LICENSE("GPL v2");