mmc: omap: Remove cpu_is_omap usage from the driver
[muen/linux.git] / drivers / mmc / host / omap.c
1 /*
2  *  linux/drivers/mmc/host/omap.c
3  *
4  *  Copyright (C) 2004 Nokia Corporation
5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7  *  Other hacks (DMA, SD, etc) by David Brownell
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/omap-dma.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/card.h>
28 #include <linux/clk.h>
29 #include <linux/scatterlist.h>
30 #include <linux/slab.h>
31 #include <linux/platform_data/mmc-omap.h>
32
33 #include <plat/dma.h>
34
35 #define OMAP_MMC_REG_CMD        0x00
36 #define OMAP_MMC_REG_ARGL       0x01
37 #define OMAP_MMC_REG_ARGH       0x02
38 #define OMAP_MMC_REG_CON        0x03
39 #define OMAP_MMC_REG_STAT       0x04
40 #define OMAP_MMC_REG_IE         0x05
41 #define OMAP_MMC_REG_CTO        0x06
42 #define OMAP_MMC_REG_DTO        0x07
43 #define OMAP_MMC_REG_DATA       0x08
44 #define OMAP_MMC_REG_BLEN       0x09
45 #define OMAP_MMC_REG_NBLK       0x0a
46 #define OMAP_MMC_REG_BUF        0x0b
47 #define OMAP_MMC_REG_SDIO       0x0d
48 #define OMAP_MMC_REG_REV        0x0f
49 #define OMAP_MMC_REG_RSP0       0x10
50 #define OMAP_MMC_REG_RSP1       0x11
51 #define OMAP_MMC_REG_RSP2       0x12
52 #define OMAP_MMC_REG_RSP3       0x13
53 #define OMAP_MMC_REG_RSP4       0x14
54 #define OMAP_MMC_REG_RSP5       0x15
55 #define OMAP_MMC_REG_RSP6       0x16
56 #define OMAP_MMC_REG_RSP7       0x17
57 #define OMAP_MMC_REG_IOSR       0x18
58 #define OMAP_MMC_REG_SYSC       0x19
59 #define OMAP_MMC_REG_SYSS       0x1a
60
61 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
62 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
63 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
64 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
65 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
66 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
67 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
68 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
69 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
70 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
71 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
72 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
73 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
74
75 #define mmc_omap7xx()   (host->features & MMC_OMAP7XX)
76 #define mmc_omap15xx()  (host->features & MMC_OMAP15XX)
77 #define mmc_omap16xx()  (host->features & MMC_OMAP16XX)
78 #define MMC_OMAP1_MASK  (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
79 #define mmc_omap1()     (host->features & MMC_OMAP1_MASK)
80 #define mmc_omap2()     (!mmc_omap1())
81
82 #define OMAP_MMC_REG(host, reg)         (OMAP_MMC_REG_##reg << (host)->reg_shift)
83 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
84 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
85
86 /*
87  * Command types
88  */
89 #define OMAP_MMC_CMDTYPE_BC     0
90 #define OMAP_MMC_CMDTYPE_BCR    1
91 #define OMAP_MMC_CMDTYPE_AC     2
92 #define OMAP_MMC_CMDTYPE_ADTC   3
93
94
95 #define DRIVER_NAME "mmci-omap"
96
97 /* Specifies how often in millisecs to poll for card status changes
98  * when the cover switch is open */
99 #define OMAP_MMC_COVER_POLL_DELAY       500
100
101 struct mmc_omap_host;
102
103 struct mmc_omap_slot {
104         int                     id;
105         unsigned int            vdd;
106         u16                     saved_con;
107         u16                     bus_mode;
108         unsigned int            fclk_freq;
109
110         struct tasklet_struct   cover_tasklet;
111         struct timer_list       cover_timer;
112         unsigned                cover_open;
113
114         struct mmc_request      *mrq;
115         struct mmc_omap_host    *host;
116         struct mmc_host         *mmc;
117         struct omap_mmc_slot_data *pdata;
118 };
119
120 struct mmc_omap_host {
121         int                     initialized;
122         int                     suspended;
123         struct mmc_request *    mrq;
124         struct mmc_command *    cmd;
125         struct mmc_data *       data;
126         struct mmc_host *       mmc;
127         struct device *         dev;
128         unsigned char           id; /* 16xx chips have 2 MMC blocks */
129         struct clk *            iclk;
130         struct clk *            fclk;
131         struct dma_chan         *dma_rx;
132         u32                     dma_rx_burst;
133         struct dma_chan         *dma_tx;
134         u32                     dma_tx_burst;
135         struct resource         *mem_res;
136         void __iomem            *virt_base;
137         unsigned int            phys_base;
138         int                     irq;
139         unsigned char           bus_mode;
140         unsigned int            reg_shift;
141
142         struct work_struct      cmd_abort_work;
143         unsigned                abort:1;
144         struct timer_list       cmd_abort_timer;
145
146         struct work_struct      slot_release_work;
147         struct mmc_omap_slot    *next_slot;
148         struct work_struct      send_stop_work;
149         struct mmc_data         *stop_data;
150
151         unsigned int            sg_len;
152         int                     sg_idx;
153         u16 *                   buffer;
154         u32                     buffer_bytes_left;
155         u32                     total_bytes_left;
156
157         unsigned                features;
158         unsigned                use_dma:1;
159         unsigned                brs_received:1, dma_done:1;
160         unsigned                dma_in_use:1;
161         spinlock_t              dma_lock;
162
163         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
164         struct mmc_omap_slot    *current_slot;
165         spinlock_t              slot_lock;
166         wait_queue_head_t       slot_wq;
167         int                     nr_slots;
168
169         struct timer_list       clk_timer;
170         spinlock_t              clk_lock;     /* for changing enabled state */
171         unsigned int            fclk_enabled:1;
172         struct workqueue_struct *mmc_omap_wq;
173
174         struct omap_mmc_platform_data *pdata;
175 };
176
177
178 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
179 {
180         unsigned long tick_ns;
181
182         if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
183                 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
184                 ndelay(8 * tick_ns);
185         }
186 }
187
188 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
189 {
190         unsigned long flags;
191
192         spin_lock_irqsave(&host->clk_lock, flags);
193         if (host->fclk_enabled != enable) {
194                 host->fclk_enabled = enable;
195                 if (enable)
196                         clk_enable(host->fclk);
197                 else
198                         clk_disable(host->fclk);
199         }
200         spin_unlock_irqrestore(&host->clk_lock, flags);
201 }
202
203 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
204 {
205         struct mmc_omap_host *host = slot->host;
206         unsigned long flags;
207
208         if (claimed)
209                 goto no_claim;
210         spin_lock_irqsave(&host->slot_lock, flags);
211         while (host->mmc != NULL) {
212                 spin_unlock_irqrestore(&host->slot_lock, flags);
213                 wait_event(host->slot_wq, host->mmc == NULL);
214                 spin_lock_irqsave(&host->slot_lock, flags);
215         }
216         host->mmc = slot->mmc;
217         spin_unlock_irqrestore(&host->slot_lock, flags);
218 no_claim:
219         del_timer(&host->clk_timer);
220         if (host->current_slot != slot || !claimed)
221                 mmc_omap_fclk_offdelay(host->current_slot);
222
223         if (host->current_slot != slot) {
224                 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
225                 if (host->pdata->switch_slot != NULL)
226                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
227                 host->current_slot = slot;
228         }
229
230         if (claimed) {
231                 mmc_omap_fclk_enable(host, 1);
232
233                 /* Doing the dummy read here seems to work around some bug
234                  * at least in OMAP24xx silicon where the command would not
235                  * start after writing the CMD register. Sigh. */
236                 OMAP_MMC_READ(host, CON);
237
238                 OMAP_MMC_WRITE(host, CON, slot->saved_con);
239         } else
240                 mmc_omap_fclk_enable(host, 0);
241 }
242
243 static void mmc_omap_start_request(struct mmc_omap_host *host,
244                                    struct mmc_request *req);
245
246 static void mmc_omap_slot_release_work(struct work_struct *work)
247 {
248         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
249                                                   slot_release_work);
250         struct mmc_omap_slot *next_slot = host->next_slot;
251         struct mmc_request *rq;
252
253         host->next_slot = NULL;
254         mmc_omap_select_slot(next_slot, 1);
255
256         rq = next_slot->mrq;
257         next_slot->mrq = NULL;
258         mmc_omap_start_request(host, rq);
259 }
260
261 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
262 {
263         struct mmc_omap_host *host = slot->host;
264         unsigned long flags;
265         int i;
266
267         BUG_ON(slot == NULL || host->mmc == NULL);
268
269         if (clk_enabled)
270                 /* Keeps clock running for at least 8 cycles on valid freq */
271                 mod_timer(&host->clk_timer, jiffies  + HZ/10);
272         else {
273                 del_timer(&host->clk_timer);
274                 mmc_omap_fclk_offdelay(slot);
275                 mmc_omap_fclk_enable(host, 0);
276         }
277
278         spin_lock_irqsave(&host->slot_lock, flags);
279         /* Check for any pending requests */
280         for (i = 0; i < host->nr_slots; i++) {
281                 struct mmc_omap_slot *new_slot;
282
283                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
284                         continue;
285
286                 BUG_ON(host->next_slot != NULL);
287                 new_slot = host->slots[i];
288                 /* The current slot should not have a request in queue */
289                 BUG_ON(new_slot == host->current_slot);
290
291                 host->next_slot = new_slot;
292                 host->mmc = new_slot->mmc;
293                 spin_unlock_irqrestore(&host->slot_lock, flags);
294                 queue_work(host->mmc_omap_wq, &host->slot_release_work);
295                 return;
296         }
297
298         host->mmc = NULL;
299         wake_up(&host->slot_wq);
300         spin_unlock_irqrestore(&host->slot_lock, flags);
301 }
302
303 static inline
304 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
305 {
306         if (slot->pdata->get_cover_state)
307                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
308                                                     slot->id);
309         return 0;
310 }
311
312 static ssize_t
313 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
314                            char *buf)
315 {
316         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
317         struct mmc_omap_slot *slot = mmc_priv(mmc);
318
319         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
320                        "closed");
321 }
322
323 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
324
325 static ssize_t
326 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
327                         char *buf)
328 {
329         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
330         struct mmc_omap_slot *slot = mmc_priv(mmc);
331
332         return sprintf(buf, "%s\n", slot->pdata->name);
333 }
334
335 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
336
337 static void
338 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
339 {
340         u32 cmdreg;
341         u32 resptype;
342         u32 cmdtype;
343
344         host->cmd = cmd;
345
346         resptype = 0;
347         cmdtype = 0;
348
349         /* Our hardware needs to know exact type */
350         switch (mmc_resp_type(cmd)) {
351         case MMC_RSP_NONE:
352                 break;
353         case MMC_RSP_R1:
354         case MMC_RSP_R1B:
355                 /* resp 1, 1b, 6, 7 */
356                 resptype = 1;
357                 break;
358         case MMC_RSP_R2:
359                 resptype = 2;
360                 break;
361         case MMC_RSP_R3:
362                 resptype = 3;
363                 break;
364         default:
365                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
366                 break;
367         }
368
369         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
370                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
371         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
372                 cmdtype = OMAP_MMC_CMDTYPE_BC;
373         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
374                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
375         } else {
376                 cmdtype = OMAP_MMC_CMDTYPE_AC;
377         }
378
379         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
380
381         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
382                 cmdreg |= 1 << 6;
383
384         if (cmd->flags & MMC_RSP_BUSY)
385                 cmdreg |= 1 << 11;
386
387         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
388                 cmdreg |= 1 << 15;
389
390         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
391
392         OMAP_MMC_WRITE(host, CTO, 200);
393         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
394         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
395         OMAP_MMC_WRITE(host, IE,
396                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
397                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
398                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
399                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
400                        OMAP_MMC_STAT_END_OF_DATA);
401         OMAP_MMC_WRITE(host, CMD, cmdreg);
402 }
403
404 static void
405 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
406                      int abort)
407 {
408         enum dma_data_direction dma_data_dir;
409         struct device *dev = mmc_dev(host->mmc);
410         struct dma_chan *c;
411
412         if (data->flags & MMC_DATA_WRITE) {
413                 dma_data_dir = DMA_TO_DEVICE;
414                 c = host->dma_tx;
415         } else {
416                 dma_data_dir = DMA_FROM_DEVICE;
417                 c = host->dma_rx;
418         }
419         if (c) {
420                 if (data->error) {
421                         dmaengine_terminate_all(c);
422                         /* Claim nothing transferred on error... */
423                         data->bytes_xfered = 0;
424                 }
425                 dev = c->device->dev;
426         }
427         dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
428 }
429
430 static void mmc_omap_send_stop_work(struct work_struct *work)
431 {
432         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
433                                                   send_stop_work);
434         struct mmc_omap_slot *slot = host->current_slot;
435         struct mmc_data *data = host->stop_data;
436         unsigned long tick_ns;
437
438         tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
439         ndelay(8*tick_ns);
440
441         mmc_omap_start_command(host, data->stop);
442 }
443
444 static void
445 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
446 {
447         if (host->dma_in_use)
448                 mmc_omap_release_dma(host, data, data->error);
449
450         host->data = NULL;
451         host->sg_len = 0;
452
453         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
454          * dozens of requests until the card finishes writing data.
455          * It'd be cheaper to just wait till an EOFB interrupt arrives...
456          */
457
458         if (!data->stop) {
459                 struct mmc_host *mmc;
460
461                 host->mrq = NULL;
462                 mmc = host->mmc;
463                 mmc_omap_release_slot(host->current_slot, 1);
464                 mmc_request_done(mmc, data->mrq);
465                 return;
466         }
467
468         host->stop_data = data;
469         queue_work(host->mmc_omap_wq, &host->send_stop_work);
470 }
471
472 static void
473 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
474 {
475         struct mmc_omap_slot *slot = host->current_slot;
476         unsigned int restarts, passes, timeout;
477         u16 stat = 0;
478
479         /* Sending abort takes 80 clocks. Have some extra and round up */
480         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
481         restarts = 0;
482         while (restarts < maxloops) {
483                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
484                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
485
486                 passes = 0;
487                 while (passes < timeout) {
488                         stat = OMAP_MMC_READ(host, STAT);
489                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
490                                 goto out;
491                         udelay(1);
492                         passes++;
493                 }
494
495                 restarts++;
496         }
497 out:
498         OMAP_MMC_WRITE(host, STAT, stat);
499 }
500
501 static void
502 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
503 {
504         if (host->dma_in_use)
505                 mmc_omap_release_dma(host, data, 1);
506
507         host->data = NULL;
508         host->sg_len = 0;
509
510         mmc_omap_send_abort(host, 10000);
511 }
512
513 static void
514 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
515 {
516         unsigned long flags;
517         int done;
518
519         if (!host->dma_in_use) {
520                 mmc_omap_xfer_done(host, data);
521                 return;
522         }
523         done = 0;
524         spin_lock_irqsave(&host->dma_lock, flags);
525         if (host->dma_done)
526                 done = 1;
527         else
528                 host->brs_received = 1;
529         spin_unlock_irqrestore(&host->dma_lock, flags);
530         if (done)
531                 mmc_omap_xfer_done(host, data);
532 }
533
534 static void
535 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
536 {
537         unsigned long flags;
538         int done;
539
540         done = 0;
541         spin_lock_irqsave(&host->dma_lock, flags);
542         if (host->brs_received)
543                 done = 1;
544         else
545                 host->dma_done = 1;
546         spin_unlock_irqrestore(&host->dma_lock, flags);
547         if (done)
548                 mmc_omap_xfer_done(host, data);
549 }
550
551 static void
552 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
553 {
554         host->cmd = NULL;
555
556         del_timer(&host->cmd_abort_timer);
557
558         if (cmd->flags & MMC_RSP_PRESENT) {
559                 if (cmd->flags & MMC_RSP_136) {
560                         /* response type 2 */
561                         cmd->resp[3] =
562                                 OMAP_MMC_READ(host, RSP0) |
563                                 (OMAP_MMC_READ(host, RSP1) << 16);
564                         cmd->resp[2] =
565                                 OMAP_MMC_READ(host, RSP2) |
566                                 (OMAP_MMC_READ(host, RSP3) << 16);
567                         cmd->resp[1] =
568                                 OMAP_MMC_READ(host, RSP4) |
569                                 (OMAP_MMC_READ(host, RSP5) << 16);
570                         cmd->resp[0] =
571                                 OMAP_MMC_READ(host, RSP6) |
572                                 (OMAP_MMC_READ(host, RSP7) << 16);
573                 } else {
574                         /* response types 1, 1b, 3, 4, 5, 6 */
575                         cmd->resp[0] =
576                                 OMAP_MMC_READ(host, RSP6) |
577                                 (OMAP_MMC_READ(host, RSP7) << 16);
578                 }
579         }
580
581         if (host->data == NULL || cmd->error) {
582                 struct mmc_host *mmc;
583
584                 if (host->data != NULL)
585                         mmc_omap_abort_xfer(host, host->data);
586                 host->mrq = NULL;
587                 mmc = host->mmc;
588                 mmc_omap_release_slot(host->current_slot, 1);
589                 mmc_request_done(mmc, cmd->mrq);
590         }
591 }
592
593 /*
594  * Abort stuck command. Can occur when card is removed while it is being
595  * read.
596  */
597 static void mmc_omap_abort_command(struct work_struct *work)
598 {
599         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
600                                                   cmd_abort_work);
601         BUG_ON(!host->cmd);
602
603         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
604                 host->cmd->opcode);
605
606         if (host->cmd->error == 0)
607                 host->cmd->error = -ETIMEDOUT;
608
609         if (host->data == NULL) {
610                 struct mmc_command *cmd;
611                 struct mmc_host    *mmc;
612
613                 cmd = host->cmd;
614                 host->cmd = NULL;
615                 mmc_omap_send_abort(host, 10000);
616
617                 host->mrq = NULL;
618                 mmc = host->mmc;
619                 mmc_omap_release_slot(host->current_slot, 1);
620                 mmc_request_done(mmc, cmd->mrq);
621         } else
622                 mmc_omap_cmd_done(host, host->cmd);
623
624         host->abort = 0;
625         enable_irq(host->irq);
626 }
627
628 static void
629 mmc_omap_cmd_timer(unsigned long data)
630 {
631         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
632         unsigned long flags;
633
634         spin_lock_irqsave(&host->slot_lock, flags);
635         if (host->cmd != NULL && !host->abort) {
636                 OMAP_MMC_WRITE(host, IE, 0);
637                 disable_irq(host->irq);
638                 host->abort = 1;
639                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
640         }
641         spin_unlock_irqrestore(&host->slot_lock, flags);
642 }
643
644 /* PIO only */
645 static void
646 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
647 {
648         struct scatterlist *sg;
649
650         sg = host->data->sg + host->sg_idx;
651         host->buffer_bytes_left = sg->length;
652         host->buffer = sg_virt(sg);
653         if (host->buffer_bytes_left > host->total_bytes_left)
654                 host->buffer_bytes_left = host->total_bytes_left;
655 }
656
657 static void
658 mmc_omap_clk_timer(unsigned long data)
659 {
660         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
661
662         mmc_omap_fclk_enable(host, 0);
663 }
664
665 /* PIO only */
666 static void
667 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
668 {
669         int n, nwords;
670
671         if (host->buffer_bytes_left == 0) {
672                 host->sg_idx++;
673                 BUG_ON(host->sg_idx == host->sg_len);
674                 mmc_omap_sg_to_buf(host);
675         }
676         n = 64;
677         if (n > host->buffer_bytes_left)
678                 n = host->buffer_bytes_left;
679
680         nwords = n / 2;
681         nwords += n & 1; /* handle odd number of bytes to transfer */
682
683         host->buffer_bytes_left -= n;
684         host->total_bytes_left -= n;
685         host->data->bytes_xfered += n;
686
687         if (write) {
688                 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
689                               host->buffer, nwords);
690         } else {
691                 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
692                              host->buffer, nwords);
693         }
694
695         host->buffer += nwords;
696 }
697
698 #ifdef CONFIG_MMC_DEBUG
699 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
700 {
701         static const char *mmc_omap_status_bits[] = {
702                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
703                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
704         };
705         int i;
706         char res[64], *buf = res;
707
708         buf += sprintf(buf, "MMC IRQ 0x%x:", status);
709
710         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
711                 if (status & (1 << i))
712                         buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
713         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
714 }
715 #else
716 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
717 {
718 }
719 #endif
720
721
722 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
723 {
724         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
725         u16 status;
726         int end_command;
727         int end_transfer;
728         int transfer_error, cmd_error;
729
730         if (host->cmd == NULL && host->data == NULL) {
731                 status = OMAP_MMC_READ(host, STAT);
732                 dev_info(mmc_dev(host->slots[0]->mmc),
733                          "Spurious IRQ 0x%04x\n", status);
734                 if (status != 0) {
735                         OMAP_MMC_WRITE(host, STAT, status);
736                         OMAP_MMC_WRITE(host, IE, 0);
737                 }
738                 return IRQ_HANDLED;
739         }
740
741         end_command = 0;
742         end_transfer = 0;
743         transfer_error = 0;
744         cmd_error = 0;
745
746         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
747                 int cmd;
748
749                 OMAP_MMC_WRITE(host, STAT, status);
750                 if (host->cmd != NULL)
751                         cmd = host->cmd->opcode;
752                 else
753                         cmd = -1;
754                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
755                         status, cmd);
756                 mmc_omap_report_irq(host, status);
757
758                 if (host->total_bytes_left) {
759                         if ((status & OMAP_MMC_STAT_A_FULL) ||
760                             (status & OMAP_MMC_STAT_END_OF_DATA))
761                                 mmc_omap_xfer_data(host, 0);
762                         if (status & OMAP_MMC_STAT_A_EMPTY)
763                                 mmc_omap_xfer_data(host, 1);
764                 }
765
766                 if (status & OMAP_MMC_STAT_END_OF_DATA)
767                         end_transfer = 1;
768
769                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
770                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
771                                 cmd);
772                         if (host->data) {
773                                 host->data->error = -ETIMEDOUT;
774                                 transfer_error = 1;
775                         }
776                 }
777
778                 if (status & OMAP_MMC_STAT_DATA_CRC) {
779                         if (host->data) {
780                                 host->data->error = -EILSEQ;
781                                 dev_dbg(mmc_dev(host->mmc),
782                                          "data CRC error, bytes left %d\n",
783                                         host->total_bytes_left);
784                                 transfer_error = 1;
785                         } else {
786                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
787                         }
788                 }
789
790                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
791                         /* Timeouts are routine with some commands */
792                         if (host->cmd) {
793                                 struct mmc_omap_slot *slot =
794                                         host->current_slot;
795                                 if (slot == NULL ||
796                                     !mmc_omap_cover_is_open(slot))
797                                         dev_err(mmc_dev(host->mmc),
798                                                 "command timeout (CMD%d)\n",
799                                                 cmd);
800                                 host->cmd->error = -ETIMEDOUT;
801                                 end_command = 1;
802                                 cmd_error = 1;
803                         }
804                 }
805
806                 if (status & OMAP_MMC_STAT_CMD_CRC) {
807                         if (host->cmd) {
808                                 dev_err(mmc_dev(host->mmc),
809                                         "command CRC error (CMD%d, arg 0x%08x)\n",
810                                         cmd, host->cmd->arg);
811                                 host->cmd->error = -EILSEQ;
812                                 end_command = 1;
813                                 cmd_error = 1;
814                         } else
815                                 dev_err(mmc_dev(host->mmc),
816                                         "command CRC error without cmd?\n");
817                 }
818
819                 if (status & OMAP_MMC_STAT_CARD_ERR) {
820                         dev_dbg(mmc_dev(host->mmc),
821                                 "ignoring card status error (CMD%d)\n",
822                                 cmd);
823                         end_command = 1;
824                 }
825
826                 /*
827                  * NOTE: On 1610 the END_OF_CMD may come too early when
828                  * starting a write
829                  */
830                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
831                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
832                         end_command = 1;
833                 }
834         }
835
836         if (cmd_error && host->data) {
837                 del_timer(&host->cmd_abort_timer);
838                 host->abort = 1;
839                 OMAP_MMC_WRITE(host, IE, 0);
840                 disable_irq_nosync(host->irq);
841                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
842                 return IRQ_HANDLED;
843         }
844
845         if (end_command && host->cmd)
846                 mmc_omap_cmd_done(host, host->cmd);
847         if (host->data != NULL) {
848                 if (transfer_error)
849                         mmc_omap_xfer_done(host, host->data);
850                 else if (end_transfer)
851                         mmc_omap_end_of_data(host, host->data);
852         }
853
854         return IRQ_HANDLED;
855 }
856
857 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
858 {
859         int cover_open;
860         struct mmc_omap_host *host = dev_get_drvdata(dev);
861         struct mmc_omap_slot *slot = host->slots[num];
862
863         BUG_ON(num >= host->nr_slots);
864
865         /* Other subsystems can call in here before we're initialised. */
866         if (host->nr_slots == 0 || !host->slots[num])
867                 return;
868
869         cover_open = mmc_omap_cover_is_open(slot);
870         if (cover_open != slot->cover_open) {
871                 slot->cover_open = cover_open;
872                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
873         }
874
875         tasklet_hi_schedule(&slot->cover_tasklet);
876 }
877
878 static void mmc_omap_cover_timer(unsigned long arg)
879 {
880         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
881         tasklet_schedule(&slot->cover_tasklet);
882 }
883
884 static void mmc_omap_cover_handler(unsigned long param)
885 {
886         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
887         int cover_open = mmc_omap_cover_is_open(slot);
888
889         mmc_detect_change(slot->mmc, 0);
890         if (!cover_open)
891                 return;
892
893         /*
894          * If no card is inserted, we postpone polling until
895          * the cover has been closed.
896          */
897         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
898                 return;
899
900         mod_timer(&slot->cover_timer,
901                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
902 }
903
904 static void mmc_omap_dma_callback(void *priv)
905 {
906         struct mmc_omap_host *host = priv;
907         struct mmc_data *data = host->data;
908
909         /* If we got to the end of DMA, assume everything went well */
910         data->bytes_xfered += data->blocks * data->blksz;
911
912         mmc_omap_dma_done(host, data);
913 }
914
915 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
916 {
917         u16 reg;
918
919         reg = OMAP_MMC_READ(host, SDIO);
920         reg &= ~(1 << 5);
921         OMAP_MMC_WRITE(host, SDIO, reg);
922         /* Set maximum timeout */
923         OMAP_MMC_WRITE(host, CTO, 0xff);
924 }
925
926 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
927 {
928         unsigned int timeout, cycle_ns;
929         u16 reg;
930
931         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
932         timeout = req->data->timeout_ns / cycle_ns;
933         timeout += req->data->timeout_clks;
934
935         /* Check if we need to use timeout multiplier register */
936         reg = OMAP_MMC_READ(host, SDIO);
937         if (timeout > 0xffff) {
938                 reg |= (1 << 5);
939                 timeout /= 1024;
940         } else
941                 reg &= ~(1 << 5);
942         OMAP_MMC_WRITE(host, SDIO, reg);
943         OMAP_MMC_WRITE(host, DTO, timeout);
944 }
945
946 static void
947 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
948 {
949         struct mmc_data *data = req->data;
950         int i, use_dma, block_size;
951         unsigned sg_len;
952
953         host->data = data;
954         if (data == NULL) {
955                 OMAP_MMC_WRITE(host, BLEN, 0);
956                 OMAP_MMC_WRITE(host, NBLK, 0);
957                 OMAP_MMC_WRITE(host, BUF, 0);
958                 host->dma_in_use = 0;
959                 set_cmd_timeout(host, req);
960                 return;
961         }
962
963         block_size = data->blksz;
964
965         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
966         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
967         set_data_timeout(host, req);
968
969         /* cope with calling layer confusion; it issues "single
970          * block" writes using multi-block scatterlists.
971          */
972         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
973
974         /* Only do DMA for entire blocks */
975         use_dma = host->use_dma;
976         if (use_dma) {
977                 for (i = 0; i < sg_len; i++) {
978                         if ((data->sg[i].length % block_size) != 0) {
979                                 use_dma = 0;
980                                 break;
981                         }
982                 }
983         }
984
985         host->sg_idx = 0;
986         if (use_dma) {
987                 enum dma_data_direction dma_data_dir;
988                 struct dma_async_tx_descriptor *tx;
989                 struct dma_chan *c;
990                 u32 burst, *bp;
991                 u16 buf;
992
993                 /*
994                  * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
995                  * and 24xx. Use 16 or 32 word frames when the
996                  * blocksize is at least that large. Blocksize is
997                  * usually 512 bytes; but not for some SD reads.
998                  */
999                 burst = mmc_omap15xx() ? 32 : 64;
1000                 if (burst > data->blksz)
1001                         burst = data->blksz;
1002
1003                 burst >>= 1;
1004
1005                 if (data->flags & MMC_DATA_WRITE) {
1006                         c = host->dma_tx;
1007                         bp = &host->dma_tx_burst;
1008                         buf = 0x0f80 | (burst - 1) << 0;
1009                         dma_data_dir = DMA_TO_DEVICE;
1010                 } else {
1011                         c = host->dma_rx;
1012                         bp = &host->dma_rx_burst;
1013                         buf = 0x800f | (burst - 1) << 8;
1014                         dma_data_dir = DMA_FROM_DEVICE;
1015                 }
1016
1017                 if (!c)
1018                         goto use_pio;
1019
1020                 /* Only reconfigure if we have a different burst size */
1021                 if (*bp != burst) {
1022                         struct dma_slave_config cfg;
1023
1024                         cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1025                         cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1026                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1027                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1028                         cfg.src_maxburst = burst;
1029                         cfg.dst_maxburst = burst;
1030
1031                         if (dmaengine_slave_config(c, &cfg))
1032                                 goto use_pio;
1033
1034                         *bp = burst;
1035                 }
1036
1037                 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1038                                           dma_data_dir);
1039                 if (host->sg_len == 0)
1040                         goto use_pio;
1041
1042                 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1043                         data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1044                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1045                 if (!tx)
1046                         goto use_pio;
1047
1048                 OMAP_MMC_WRITE(host, BUF, buf);
1049
1050                 tx->callback = mmc_omap_dma_callback;
1051                 tx->callback_param = host;
1052                 dmaengine_submit(tx);
1053                 host->brs_received = 0;
1054                 host->dma_done = 0;
1055                 host->dma_in_use = 1;
1056                 return;
1057         }
1058  use_pio:
1059
1060         /* Revert to PIO? */
1061         OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1062         host->total_bytes_left = data->blocks * block_size;
1063         host->sg_len = sg_len;
1064         mmc_omap_sg_to_buf(host);
1065         host->dma_in_use = 0;
1066 }
1067
1068 static void mmc_omap_start_request(struct mmc_omap_host *host,
1069                                    struct mmc_request *req)
1070 {
1071         BUG_ON(host->mrq != NULL);
1072
1073         host->mrq = req;
1074
1075         /* only touch fifo AFTER the controller readies it */
1076         mmc_omap_prepare_data(host, req);
1077         mmc_omap_start_command(host, req->cmd);
1078         if (host->dma_in_use) {
1079                 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1080                                 host->dma_tx : host->dma_rx;
1081
1082                 dma_async_issue_pending(c);
1083         }
1084 }
1085
1086 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1087 {
1088         struct mmc_omap_slot *slot = mmc_priv(mmc);
1089         struct mmc_omap_host *host = slot->host;
1090         unsigned long flags;
1091
1092         spin_lock_irqsave(&host->slot_lock, flags);
1093         if (host->mmc != NULL) {
1094                 BUG_ON(slot->mrq != NULL);
1095                 slot->mrq = req;
1096                 spin_unlock_irqrestore(&host->slot_lock, flags);
1097                 return;
1098         } else
1099                 host->mmc = mmc;
1100         spin_unlock_irqrestore(&host->slot_lock, flags);
1101         mmc_omap_select_slot(slot, 1);
1102         mmc_omap_start_request(host, req);
1103 }
1104
1105 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1106                                 int vdd)
1107 {
1108         struct mmc_omap_host *host;
1109
1110         host = slot->host;
1111
1112         if (slot->pdata->set_power != NULL)
1113                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1114                                         vdd);
1115         if (mmc_omap2()) {
1116                 u16 w;
1117
1118                 if (power_on) {
1119                         w = OMAP_MMC_READ(host, CON);
1120                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1121                 } else {
1122                         w = OMAP_MMC_READ(host, CON);
1123                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1124                 }
1125         }
1126 }
1127
1128 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1129 {
1130         struct mmc_omap_slot *slot = mmc_priv(mmc);
1131         struct mmc_omap_host *host = slot->host;
1132         int func_clk_rate = clk_get_rate(host->fclk);
1133         int dsor;
1134
1135         if (ios->clock == 0)
1136                 return 0;
1137
1138         dsor = func_clk_rate / ios->clock;
1139         if (dsor < 1)
1140                 dsor = 1;
1141
1142         if (func_clk_rate / dsor > ios->clock)
1143                 dsor++;
1144
1145         if (dsor > 250)
1146                 dsor = 250;
1147
1148         slot->fclk_freq = func_clk_rate / dsor;
1149
1150         if (ios->bus_width == MMC_BUS_WIDTH_4)
1151                 dsor |= 1 << 15;
1152
1153         return dsor;
1154 }
1155
1156 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1157 {
1158         struct mmc_omap_slot *slot = mmc_priv(mmc);
1159         struct mmc_omap_host *host = slot->host;
1160         int i, dsor;
1161         int clk_enabled;
1162
1163         mmc_omap_select_slot(slot, 0);
1164
1165         dsor = mmc_omap_calc_divisor(mmc, ios);
1166
1167         if (ios->vdd != slot->vdd)
1168                 slot->vdd = ios->vdd;
1169
1170         clk_enabled = 0;
1171         switch (ios->power_mode) {
1172         case MMC_POWER_OFF:
1173                 mmc_omap_set_power(slot, 0, ios->vdd);
1174                 break;
1175         case MMC_POWER_UP:
1176                 /* Cannot touch dsor yet, just power up MMC */
1177                 mmc_omap_set_power(slot, 1, ios->vdd);
1178                 goto exit;
1179         case MMC_POWER_ON:
1180                 mmc_omap_fclk_enable(host, 1);
1181                 clk_enabled = 1;
1182                 dsor |= 1 << 11;
1183                 break;
1184         }
1185
1186         if (slot->bus_mode != ios->bus_mode) {
1187                 if (slot->pdata->set_bus_mode != NULL)
1188                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1189                                                   ios->bus_mode);
1190                 slot->bus_mode = ios->bus_mode;
1191         }
1192
1193         /* On insanely high arm_per frequencies something sometimes
1194          * goes somehow out of sync, and the POW bit is not being set,
1195          * which results in the while loop below getting stuck.
1196          * Writing to the CON register twice seems to do the trick. */
1197         for (i = 0; i < 2; i++)
1198                 OMAP_MMC_WRITE(host, CON, dsor);
1199         slot->saved_con = dsor;
1200         if (ios->power_mode == MMC_POWER_ON) {
1201                 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1202                 int usecs = 250;
1203
1204                 /* Send clock cycles, poll completion */
1205                 OMAP_MMC_WRITE(host, IE, 0);
1206                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1207                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1208                 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1209                         udelay(1);
1210                         usecs--;
1211                 }
1212                 OMAP_MMC_WRITE(host, STAT, 1);
1213         }
1214
1215 exit:
1216         mmc_omap_release_slot(slot, clk_enabled);
1217 }
1218
1219 static const struct mmc_host_ops mmc_omap_ops = {
1220         .request        = mmc_omap_request,
1221         .set_ios        = mmc_omap_set_ios,
1222 };
1223
1224 static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1225 {
1226         struct mmc_omap_slot *slot = NULL;
1227         struct mmc_host *mmc;
1228         int r;
1229
1230         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1231         if (mmc == NULL)
1232                 return -ENOMEM;
1233
1234         slot = mmc_priv(mmc);
1235         slot->host = host;
1236         slot->mmc = mmc;
1237         slot->id = id;
1238         slot->pdata = &host->pdata->slots[id];
1239
1240         host->slots[id] = slot;
1241
1242         mmc->caps = 0;
1243         if (host->pdata->slots[id].wires >= 4)
1244                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1245
1246         mmc->ops = &mmc_omap_ops;
1247         mmc->f_min = 400000;
1248
1249         if (mmc_omap2())
1250                 mmc->f_max = 48000000;
1251         else
1252                 mmc->f_max = 24000000;
1253         if (host->pdata->max_freq)
1254                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1255         mmc->ocr_avail = slot->pdata->ocr_mask;
1256
1257         /* Use scatterlist DMA to reduce per-transfer costs.
1258          * NOTE max_seg_size assumption that small blocks aren't
1259          * normally used (except e.g. for reading SD registers).
1260          */
1261         mmc->max_segs = 32;
1262         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1263         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1264         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1265         mmc->max_seg_size = mmc->max_req_size;
1266
1267         r = mmc_add_host(mmc);
1268         if (r < 0)
1269                 goto err_remove_host;
1270
1271         if (slot->pdata->name != NULL) {
1272                 r = device_create_file(&mmc->class_dev,
1273                                         &dev_attr_slot_name);
1274                 if (r < 0)
1275                         goto err_remove_host;
1276         }
1277
1278         if (slot->pdata->get_cover_state != NULL) {
1279                 r = device_create_file(&mmc->class_dev,
1280                                         &dev_attr_cover_switch);
1281                 if (r < 0)
1282                         goto err_remove_slot_name;
1283
1284                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1285                             (unsigned long)slot);
1286                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1287                              (unsigned long)slot);
1288                 tasklet_schedule(&slot->cover_tasklet);
1289         }
1290
1291         return 0;
1292
1293 err_remove_slot_name:
1294         if (slot->pdata->name != NULL)
1295                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1296 err_remove_host:
1297         mmc_remove_host(mmc);
1298         mmc_free_host(mmc);
1299         return r;
1300 }
1301
1302 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1303 {
1304         struct mmc_host *mmc = slot->mmc;
1305
1306         if (slot->pdata->name != NULL)
1307                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1308         if (slot->pdata->get_cover_state != NULL)
1309                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1310
1311         tasklet_kill(&slot->cover_tasklet);
1312         del_timer_sync(&slot->cover_timer);
1313         flush_workqueue(slot->host->mmc_omap_wq);
1314
1315         mmc_remove_host(mmc);
1316         mmc_free_host(mmc);
1317 }
1318
1319 static int __devinit mmc_omap_probe(struct platform_device *pdev)
1320 {
1321         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1322         struct mmc_omap_host *host = NULL;
1323         struct resource *res;
1324         dma_cap_mask_t mask;
1325         unsigned sig;
1326         int i, ret = 0;
1327         int irq;
1328
1329         if (pdata == NULL) {
1330                 dev_err(&pdev->dev, "platform data missing\n");
1331                 return -ENXIO;
1332         }
1333         if (pdata->nr_slots == 0) {
1334                 dev_err(&pdev->dev, "no slots\n");
1335                 return -ENXIO;
1336         }
1337
1338         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339         irq = platform_get_irq(pdev, 0);
1340         if (res == NULL || irq < 0)
1341                 return -ENXIO;
1342
1343         res = request_mem_region(res->start, resource_size(res),
1344                                  pdev->name);
1345         if (res == NULL)
1346                 return -EBUSY;
1347
1348         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1349         if (host == NULL) {
1350                 ret = -ENOMEM;
1351                 goto err_free_mem_region;
1352         }
1353
1354         INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1355         INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1356
1357         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1358         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1359                     (unsigned long) host);
1360
1361         spin_lock_init(&host->clk_lock);
1362         setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1363
1364         spin_lock_init(&host->dma_lock);
1365         spin_lock_init(&host->slot_lock);
1366         init_waitqueue_head(&host->slot_wq);
1367
1368         host->pdata = pdata;
1369         host->features = host->pdata->slots[0].features;
1370         host->dev = &pdev->dev;
1371         platform_set_drvdata(pdev, host);
1372
1373         host->id = pdev->id;
1374         host->mem_res = res;
1375         host->irq = irq;
1376         host->use_dma = 1;
1377         host->irq = irq;
1378         host->phys_base = host->mem_res->start;
1379         host->virt_base = ioremap(res->start, resource_size(res));
1380         if (!host->virt_base)
1381                 goto err_ioremap;
1382
1383         host->iclk = clk_get(&pdev->dev, "ick");
1384         if (IS_ERR(host->iclk)) {
1385                 ret = PTR_ERR(host->iclk);
1386                 goto err_free_mmc_host;
1387         }
1388         clk_enable(host->iclk);
1389
1390         host->fclk = clk_get(&pdev->dev, "fck");
1391         if (IS_ERR(host->fclk)) {
1392                 ret = PTR_ERR(host->fclk);
1393                 goto err_free_iclk;
1394         }
1395
1396         dma_cap_zero(mask);
1397         dma_cap_set(DMA_SLAVE, mask);
1398
1399         host->dma_tx_burst = -1;
1400         host->dma_rx_burst = -1;
1401
1402         if (mmc_omap2())
1403                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
1404         else
1405                 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
1406         host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1407 #if 0
1408         if (!host->dma_tx) {
1409                 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
1410                         sig);
1411                 goto err_dma;
1412         }
1413 #else
1414         if (!host->dma_tx)
1415                 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1416                         sig);
1417 #endif
1418         if (mmc_omap2())
1419                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
1420         else
1421                 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
1422         host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1423 #if 0
1424         if (!host->dma_rx) {
1425                 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
1426                         sig);
1427                 goto err_dma;
1428         }
1429 #else
1430         if (!host->dma_rx)
1431                 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1432                         sig);
1433 #endif
1434
1435         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1436         if (ret)
1437                 goto err_free_dma;
1438
1439         if (pdata->init != NULL) {
1440                 ret = pdata->init(&pdev->dev);
1441                 if (ret < 0)
1442                         goto err_free_irq;
1443         }
1444
1445         host->nr_slots = pdata->nr_slots;
1446         host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1447
1448         host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1449         if (!host->mmc_omap_wq)
1450                 goto err_plat_cleanup;
1451
1452         for (i = 0; i < pdata->nr_slots; i++) {
1453                 ret = mmc_omap_new_slot(host, i);
1454                 if (ret < 0) {
1455                         while (--i >= 0)
1456                                 mmc_omap_remove_slot(host->slots[i]);
1457
1458                         goto err_destroy_wq;
1459                 }
1460         }
1461
1462         return 0;
1463
1464 err_destroy_wq:
1465         destroy_workqueue(host->mmc_omap_wq);
1466 err_plat_cleanup:
1467         if (pdata->cleanup)
1468                 pdata->cleanup(&pdev->dev);
1469 err_free_irq:
1470         free_irq(host->irq, host);
1471 err_free_dma:
1472         if (host->dma_tx)
1473                 dma_release_channel(host->dma_tx);
1474         if (host->dma_rx)
1475                 dma_release_channel(host->dma_rx);
1476         clk_put(host->fclk);
1477 err_free_iclk:
1478         clk_disable(host->iclk);
1479         clk_put(host->iclk);
1480 err_free_mmc_host:
1481         iounmap(host->virt_base);
1482 err_ioremap:
1483         kfree(host);
1484 err_free_mem_region:
1485         release_mem_region(res->start, resource_size(res));
1486         return ret;
1487 }
1488
1489 static int __devexit mmc_omap_remove(struct platform_device *pdev)
1490 {
1491         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1492         int i;
1493
1494         platform_set_drvdata(pdev, NULL);
1495
1496         BUG_ON(host == NULL);
1497
1498         for (i = 0; i < host->nr_slots; i++)
1499                 mmc_omap_remove_slot(host->slots[i]);
1500
1501         if (host->pdata->cleanup)
1502                 host->pdata->cleanup(&pdev->dev);
1503
1504         mmc_omap_fclk_enable(host, 0);
1505         free_irq(host->irq, host);
1506         clk_put(host->fclk);
1507         clk_disable(host->iclk);
1508         clk_put(host->iclk);
1509
1510         if (host->dma_tx)
1511                 dma_release_channel(host->dma_tx);
1512         if (host->dma_rx)
1513                 dma_release_channel(host->dma_rx);
1514
1515         iounmap(host->virt_base);
1516         release_mem_region(pdev->resource[0].start,
1517                            pdev->resource[0].end - pdev->resource[0].start + 1);
1518         destroy_workqueue(host->mmc_omap_wq);
1519
1520         kfree(host);
1521
1522         return 0;
1523 }
1524
1525 #ifdef CONFIG_PM
1526 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1527 {
1528         int i, ret = 0;
1529         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1530
1531         if (host == NULL || host->suspended)
1532                 return 0;
1533
1534         for (i = 0; i < host->nr_slots; i++) {
1535                 struct mmc_omap_slot *slot;
1536
1537                 slot = host->slots[i];
1538                 ret = mmc_suspend_host(slot->mmc);
1539                 if (ret < 0) {
1540                         while (--i >= 0) {
1541                                 slot = host->slots[i];
1542                                 mmc_resume_host(slot->mmc);
1543                         }
1544                         return ret;
1545                 }
1546         }
1547         host->suspended = 1;
1548         return 0;
1549 }
1550
1551 static int mmc_omap_resume(struct platform_device *pdev)
1552 {
1553         int i, ret = 0;
1554         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1555
1556         if (host == NULL || !host->suspended)
1557                 return 0;
1558
1559         for (i = 0; i < host->nr_slots; i++) {
1560                 struct mmc_omap_slot *slot;
1561                 slot = host->slots[i];
1562                 ret = mmc_resume_host(slot->mmc);
1563                 if (ret < 0)
1564                         return ret;
1565
1566                 host->suspended = 0;
1567         }
1568         return 0;
1569 }
1570 #else
1571 #define mmc_omap_suspend        NULL
1572 #define mmc_omap_resume         NULL
1573 #endif
1574
1575 static struct platform_driver mmc_omap_driver = {
1576         .probe          = mmc_omap_probe,
1577         .remove         = __devexit_p(mmc_omap_remove),
1578         .suspend        = mmc_omap_suspend,
1579         .resume         = mmc_omap_resume,
1580         .driver         = {
1581                 .name   = DRIVER_NAME,
1582                 .owner  = THIS_MODULE,
1583         },
1584 };
1585
1586 module_platform_driver(mmc_omap_driver);
1587 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1588 MODULE_LICENSE("GPL");
1589 MODULE_ALIAS("platform:" DRIVER_NAME);
1590 MODULE_AUTHOR("Juha Yrjölä");