e7c61b9b044cd9285c9606c78bba70863c2ec76f
[muen/linux.git] / drivers / mmc / host / omap.c
1 /*
2  *  linux/drivers/mmc/host/omap.c
3  *
4  *  Copyright (C) 2004 Nokia Corporation
5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7  *  Other hacks (DMA, SD, etc) by David Brownell
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/omap-dma.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/card.h>
28 #include <linux/clk.h>
29 #include <linux/scatterlist.h>
30 #include <linux/slab.h>
31 #include <linux/platform_data/mmc-omap.h>
32
33 #include <plat/cpu.h>
34 #include <plat/dma.h>
35
36 #define OMAP_MMC_REG_CMD        0x00
37 #define OMAP_MMC_REG_ARGL       0x01
38 #define OMAP_MMC_REG_ARGH       0x02
39 #define OMAP_MMC_REG_CON        0x03
40 #define OMAP_MMC_REG_STAT       0x04
41 #define OMAP_MMC_REG_IE         0x05
42 #define OMAP_MMC_REG_CTO        0x06
43 #define OMAP_MMC_REG_DTO        0x07
44 #define OMAP_MMC_REG_DATA       0x08
45 #define OMAP_MMC_REG_BLEN       0x09
46 #define OMAP_MMC_REG_NBLK       0x0a
47 #define OMAP_MMC_REG_BUF        0x0b
48 #define OMAP_MMC_REG_SDIO       0x0d
49 #define OMAP_MMC_REG_REV        0x0f
50 #define OMAP_MMC_REG_RSP0       0x10
51 #define OMAP_MMC_REG_RSP1       0x11
52 #define OMAP_MMC_REG_RSP2       0x12
53 #define OMAP_MMC_REG_RSP3       0x13
54 #define OMAP_MMC_REG_RSP4       0x14
55 #define OMAP_MMC_REG_RSP5       0x15
56 #define OMAP_MMC_REG_RSP6       0x16
57 #define OMAP_MMC_REG_RSP7       0x17
58 #define OMAP_MMC_REG_IOSR       0x18
59 #define OMAP_MMC_REG_SYSC       0x19
60 #define OMAP_MMC_REG_SYSS       0x1a
61
62 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
63 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
64 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
65 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
66 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
67 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
68 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
69 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
70 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
71 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
72 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
73 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
74 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
75
76 #define OMAP_MMC_REG(host, reg)         (OMAP_MMC_REG_##reg << (host)->reg_shift)
77 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
78 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
79
80 /*
81  * Command types
82  */
83 #define OMAP_MMC_CMDTYPE_BC     0
84 #define OMAP_MMC_CMDTYPE_BCR    1
85 #define OMAP_MMC_CMDTYPE_AC     2
86 #define OMAP_MMC_CMDTYPE_ADTC   3
87
88
89 #define DRIVER_NAME "mmci-omap"
90
91 /* Specifies how often in millisecs to poll for card status changes
92  * when the cover switch is open */
93 #define OMAP_MMC_COVER_POLL_DELAY       500
94
95 struct mmc_omap_host;
96
97 struct mmc_omap_slot {
98         int                     id;
99         unsigned int            vdd;
100         u16                     saved_con;
101         u16                     bus_mode;
102         unsigned int            fclk_freq;
103
104         struct tasklet_struct   cover_tasklet;
105         struct timer_list       cover_timer;
106         unsigned                cover_open;
107
108         struct mmc_request      *mrq;
109         struct mmc_omap_host    *host;
110         struct mmc_host         *mmc;
111         struct omap_mmc_slot_data *pdata;
112 };
113
114 struct mmc_omap_host {
115         int                     initialized;
116         int                     suspended;
117         struct mmc_request *    mrq;
118         struct mmc_command *    cmd;
119         struct mmc_data *       data;
120         struct mmc_host *       mmc;
121         struct device *         dev;
122         unsigned char           id; /* 16xx chips have 2 MMC blocks */
123         struct clk *            iclk;
124         struct clk *            fclk;
125         struct dma_chan         *dma_rx;
126         u32                     dma_rx_burst;
127         struct dma_chan         *dma_tx;
128         u32                     dma_tx_burst;
129         struct resource         *mem_res;
130         void __iomem            *virt_base;
131         unsigned int            phys_base;
132         int                     irq;
133         unsigned char           bus_mode;
134         unsigned int            reg_shift;
135
136         struct work_struct      cmd_abort_work;
137         unsigned                abort:1;
138         struct timer_list       cmd_abort_timer;
139
140         struct work_struct      slot_release_work;
141         struct mmc_omap_slot    *next_slot;
142         struct work_struct      send_stop_work;
143         struct mmc_data         *stop_data;
144
145         unsigned int            sg_len;
146         int                     sg_idx;
147         u16 *                   buffer;
148         u32                     buffer_bytes_left;
149         u32                     total_bytes_left;
150
151         unsigned                use_dma:1;
152         unsigned                brs_received:1, dma_done:1;
153         unsigned                dma_in_use:1;
154         spinlock_t              dma_lock;
155
156         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
157         struct mmc_omap_slot    *current_slot;
158         spinlock_t              slot_lock;
159         wait_queue_head_t       slot_wq;
160         int                     nr_slots;
161
162         struct timer_list       clk_timer;
163         spinlock_t              clk_lock;     /* for changing enabled state */
164         unsigned int            fclk_enabled:1;
165         struct workqueue_struct *mmc_omap_wq;
166
167         struct omap_mmc_platform_data *pdata;
168 };
169
170
171 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
172 {
173         unsigned long tick_ns;
174
175         if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
176                 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
177                 ndelay(8 * tick_ns);
178         }
179 }
180
181 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
182 {
183         unsigned long flags;
184
185         spin_lock_irqsave(&host->clk_lock, flags);
186         if (host->fclk_enabled != enable) {
187                 host->fclk_enabled = enable;
188                 if (enable)
189                         clk_enable(host->fclk);
190                 else
191                         clk_disable(host->fclk);
192         }
193         spin_unlock_irqrestore(&host->clk_lock, flags);
194 }
195
196 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
197 {
198         struct mmc_omap_host *host = slot->host;
199         unsigned long flags;
200
201         if (claimed)
202                 goto no_claim;
203         spin_lock_irqsave(&host->slot_lock, flags);
204         while (host->mmc != NULL) {
205                 spin_unlock_irqrestore(&host->slot_lock, flags);
206                 wait_event(host->slot_wq, host->mmc == NULL);
207                 spin_lock_irqsave(&host->slot_lock, flags);
208         }
209         host->mmc = slot->mmc;
210         spin_unlock_irqrestore(&host->slot_lock, flags);
211 no_claim:
212         del_timer(&host->clk_timer);
213         if (host->current_slot != slot || !claimed)
214                 mmc_omap_fclk_offdelay(host->current_slot);
215
216         if (host->current_slot != slot) {
217                 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
218                 if (host->pdata->switch_slot != NULL)
219                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
220                 host->current_slot = slot;
221         }
222
223         if (claimed) {
224                 mmc_omap_fclk_enable(host, 1);
225
226                 /* Doing the dummy read here seems to work around some bug
227                  * at least in OMAP24xx silicon where the command would not
228                  * start after writing the CMD register. Sigh. */
229                 OMAP_MMC_READ(host, CON);
230
231                 OMAP_MMC_WRITE(host, CON, slot->saved_con);
232         } else
233                 mmc_omap_fclk_enable(host, 0);
234 }
235
236 static void mmc_omap_start_request(struct mmc_omap_host *host,
237                                    struct mmc_request *req);
238
239 static void mmc_omap_slot_release_work(struct work_struct *work)
240 {
241         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
242                                                   slot_release_work);
243         struct mmc_omap_slot *next_slot = host->next_slot;
244         struct mmc_request *rq;
245
246         host->next_slot = NULL;
247         mmc_omap_select_slot(next_slot, 1);
248
249         rq = next_slot->mrq;
250         next_slot->mrq = NULL;
251         mmc_omap_start_request(host, rq);
252 }
253
254 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
255 {
256         struct mmc_omap_host *host = slot->host;
257         unsigned long flags;
258         int i;
259
260         BUG_ON(slot == NULL || host->mmc == NULL);
261
262         if (clk_enabled)
263                 /* Keeps clock running for at least 8 cycles on valid freq */
264                 mod_timer(&host->clk_timer, jiffies  + HZ/10);
265         else {
266                 del_timer(&host->clk_timer);
267                 mmc_omap_fclk_offdelay(slot);
268                 mmc_omap_fclk_enable(host, 0);
269         }
270
271         spin_lock_irqsave(&host->slot_lock, flags);
272         /* Check for any pending requests */
273         for (i = 0; i < host->nr_slots; i++) {
274                 struct mmc_omap_slot *new_slot;
275
276                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
277                         continue;
278
279                 BUG_ON(host->next_slot != NULL);
280                 new_slot = host->slots[i];
281                 /* The current slot should not have a request in queue */
282                 BUG_ON(new_slot == host->current_slot);
283
284                 host->next_slot = new_slot;
285                 host->mmc = new_slot->mmc;
286                 spin_unlock_irqrestore(&host->slot_lock, flags);
287                 queue_work(host->mmc_omap_wq, &host->slot_release_work);
288                 return;
289         }
290
291         host->mmc = NULL;
292         wake_up(&host->slot_wq);
293         spin_unlock_irqrestore(&host->slot_lock, flags);
294 }
295
296 static inline
297 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
298 {
299         if (slot->pdata->get_cover_state)
300                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
301                                                     slot->id);
302         return 0;
303 }
304
305 static ssize_t
306 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
307                            char *buf)
308 {
309         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
310         struct mmc_omap_slot *slot = mmc_priv(mmc);
311
312         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
313                        "closed");
314 }
315
316 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
317
318 static ssize_t
319 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
320                         char *buf)
321 {
322         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
323         struct mmc_omap_slot *slot = mmc_priv(mmc);
324
325         return sprintf(buf, "%s\n", slot->pdata->name);
326 }
327
328 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
329
330 static void
331 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
332 {
333         u32 cmdreg;
334         u32 resptype;
335         u32 cmdtype;
336
337         host->cmd = cmd;
338
339         resptype = 0;
340         cmdtype = 0;
341
342         /* Our hardware needs to know exact type */
343         switch (mmc_resp_type(cmd)) {
344         case MMC_RSP_NONE:
345                 break;
346         case MMC_RSP_R1:
347         case MMC_RSP_R1B:
348                 /* resp 1, 1b, 6, 7 */
349                 resptype = 1;
350                 break;
351         case MMC_RSP_R2:
352                 resptype = 2;
353                 break;
354         case MMC_RSP_R3:
355                 resptype = 3;
356                 break;
357         default:
358                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
359                 break;
360         }
361
362         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
363                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
364         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
365                 cmdtype = OMAP_MMC_CMDTYPE_BC;
366         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
367                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
368         } else {
369                 cmdtype = OMAP_MMC_CMDTYPE_AC;
370         }
371
372         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
373
374         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
375                 cmdreg |= 1 << 6;
376
377         if (cmd->flags & MMC_RSP_BUSY)
378                 cmdreg |= 1 << 11;
379
380         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
381                 cmdreg |= 1 << 15;
382
383         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
384
385         OMAP_MMC_WRITE(host, CTO, 200);
386         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
387         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
388         OMAP_MMC_WRITE(host, IE,
389                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
390                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
391                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
392                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
393                        OMAP_MMC_STAT_END_OF_DATA);
394         OMAP_MMC_WRITE(host, CMD, cmdreg);
395 }
396
397 static void
398 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
399                      int abort)
400 {
401         enum dma_data_direction dma_data_dir;
402         struct device *dev = mmc_dev(host->mmc);
403         struct dma_chan *c;
404
405         if (data->flags & MMC_DATA_WRITE) {
406                 dma_data_dir = DMA_TO_DEVICE;
407                 c = host->dma_tx;
408         } else {
409                 dma_data_dir = DMA_FROM_DEVICE;
410                 c = host->dma_rx;
411         }
412         if (c) {
413                 if (data->error) {
414                         dmaengine_terminate_all(c);
415                         /* Claim nothing transferred on error... */
416                         data->bytes_xfered = 0;
417                 }
418                 dev = c->device->dev;
419         }
420         dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
421 }
422
423 static void mmc_omap_send_stop_work(struct work_struct *work)
424 {
425         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
426                                                   send_stop_work);
427         struct mmc_omap_slot *slot = host->current_slot;
428         struct mmc_data *data = host->stop_data;
429         unsigned long tick_ns;
430
431         tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
432         ndelay(8*tick_ns);
433
434         mmc_omap_start_command(host, data->stop);
435 }
436
437 static void
438 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
439 {
440         if (host->dma_in_use)
441                 mmc_omap_release_dma(host, data, data->error);
442
443         host->data = NULL;
444         host->sg_len = 0;
445
446         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
447          * dozens of requests until the card finishes writing data.
448          * It'd be cheaper to just wait till an EOFB interrupt arrives...
449          */
450
451         if (!data->stop) {
452                 struct mmc_host *mmc;
453
454                 host->mrq = NULL;
455                 mmc = host->mmc;
456                 mmc_omap_release_slot(host->current_slot, 1);
457                 mmc_request_done(mmc, data->mrq);
458                 return;
459         }
460
461         host->stop_data = data;
462         queue_work(host->mmc_omap_wq, &host->send_stop_work);
463 }
464
465 static void
466 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
467 {
468         struct mmc_omap_slot *slot = host->current_slot;
469         unsigned int restarts, passes, timeout;
470         u16 stat = 0;
471
472         /* Sending abort takes 80 clocks. Have some extra and round up */
473         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
474         restarts = 0;
475         while (restarts < maxloops) {
476                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
477                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
478
479                 passes = 0;
480                 while (passes < timeout) {
481                         stat = OMAP_MMC_READ(host, STAT);
482                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
483                                 goto out;
484                         udelay(1);
485                         passes++;
486                 }
487
488                 restarts++;
489         }
490 out:
491         OMAP_MMC_WRITE(host, STAT, stat);
492 }
493
494 static void
495 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
496 {
497         if (host->dma_in_use)
498                 mmc_omap_release_dma(host, data, 1);
499
500         host->data = NULL;
501         host->sg_len = 0;
502
503         mmc_omap_send_abort(host, 10000);
504 }
505
506 static void
507 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
508 {
509         unsigned long flags;
510         int done;
511
512         if (!host->dma_in_use) {
513                 mmc_omap_xfer_done(host, data);
514                 return;
515         }
516         done = 0;
517         spin_lock_irqsave(&host->dma_lock, flags);
518         if (host->dma_done)
519                 done = 1;
520         else
521                 host->brs_received = 1;
522         spin_unlock_irqrestore(&host->dma_lock, flags);
523         if (done)
524                 mmc_omap_xfer_done(host, data);
525 }
526
527 static void
528 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
529 {
530         unsigned long flags;
531         int done;
532
533         done = 0;
534         spin_lock_irqsave(&host->dma_lock, flags);
535         if (host->brs_received)
536                 done = 1;
537         else
538                 host->dma_done = 1;
539         spin_unlock_irqrestore(&host->dma_lock, flags);
540         if (done)
541                 mmc_omap_xfer_done(host, data);
542 }
543
544 static void
545 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
546 {
547         host->cmd = NULL;
548
549         del_timer(&host->cmd_abort_timer);
550
551         if (cmd->flags & MMC_RSP_PRESENT) {
552                 if (cmd->flags & MMC_RSP_136) {
553                         /* response type 2 */
554                         cmd->resp[3] =
555                                 OMAP_MMC_READ(host, RSP0) |
556                                 (OMAP_MMC_READ(host, RSP1) << 16);
557                         cmd->resp[2] =
558                                 OMAP_MMC_READ(host, RSP2) |
559                                 (OMAP_MMC_READ(host, RSP3) << 16);
560                         cmd->resp[1] =
561                                 OMAP_MMC_READ(host, RSP4) |
562                                 (OMAP_MMC_READ(host, RSP5) << 16);
563                         cmd->resp[0] =
564                                 OMAP_MMC_READ(host, RSP6) |
565                                 (OMAP_MMC_READ(host, RSP7) << 16);
566                 } else {
567                         /* response types 1, 1b, 3, 4, 5, 6 */
568                         cmd->resp[0] =
569                                 OMAP_MMC_READ(host, RSP6) |
570                                 (OMAP_MMC_READ(host, RSP7) << 16);
571                 }
572         }
573
574         if (host->data == NULL || cmd->error) {
575                 struct mmc_host *mmc;
576
577                 if (host->data != NULL)
578                         mmc_omap_abort_xfer(host, host->data);
579                 host->mrq = NULL;
580                 mmc = host->mmc;
581                 mmc_omap_release_slot(host->current_slot, 1);
582                 mmc_request_done(mmc, cmd->mrq);
583         }
584 }
585
586 /*
587  * Abort stuck command. Can occur when card is removed while it is being
588  * read.
589  */
590 static void mmc_omap_abort_command(struct work_struct *work)
591 {
592         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
593                                                   cmd_abort_work);
594         BUG_ON(!host->cmd);
595
596         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
597                 host->cmd->opcode);
598
599         if (host->cmd->error == 0)
600                 host->cmd->error = -ETIMEDOUT;
601
602         if (host->data == NULL) {
603                 struct mmc_command *cmd;
604                 struct mmc_host    *mmc;
605
606                 cmd = host->cmd;
607                 host->cmd = NULL;
608                 mmc_omap_send_abort(host, 10000);
609
610                 host->mrq = NULL;
611                 mmc = host->mmc;
612                 mmc_omap_release_slot(host->current_slot, 1);
613                 mmc_request_done(mmc, cmd->mrq);
614         } else
615                 mmc_omap_cmd_done(host, host->cmd);
616
617         host->abort = 0;
618         enable_irq(host->irq);
619 }
620
621 static void
622 mmc_omap_cmd_timer(unsigned long data)
623 {
624         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
625         unsigned long flags;
626
627         spin_lock_irqsave(&host->slot_lock, flags);
628         if (host->cmd != NULL && !host->abort) {
629                 OMAP_MMC_WRITE(host, IE, 0);
630                 disable_irq(host->irq);
631                 host->abort = 1;
632                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
633         }
634         spin_unlock_irqrestore(&host->slot_lock, flags);
635 }
636
637 /* PIO only */
638 static void
639 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
640 {
641         struct scatterlist *sg;
642
643         sg = host->data->sg + host->sg_idx;
644         host->buffer_bytes_left = sg->length;
645         host->buffer = sg_virt(sg);
646         if (host->buffer_bytes_left > host->total_bytes_left)
647                 host->buffer_bytes_left = host->total_bytes_left;
648 }
649
650 static void
651 mmc_omap_clk_timer(unsigned long data)
652 {
653         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
654
655         mmc_omap_fclk_enable(host, 0);
656 }
657
658 /* PIO only */
659 static void
660 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
661 {
662         int n, nwords;
663
664         if (host->buffer_bytes_left == 0) {
665                 host->sg_idx++;
666                 BUG_ON(host->sg_idx == host->sg_len);
667                 mmc_omap_sg_to_buf(host);
668         }
669         n = 64;
670         if (n > host->buffer_bytes_left)
671                 n = host->buffer_bytes_left;
672
673         nwords = n / 2;
674         nwords += n & 1; /* handle odd number of bytes to transfer */
675
676         host->buffer_bytes_left -= n;
677         host->total_bytes_left -= n;
678         host->data->bytes_xfered += n;
679
680         if (write) {
681                 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
682                               host->buffer, nwords);
683         } else {
684                 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
685                              host->buffer, nwords);
686         }
687
688         host->buffer += nwords;
689 }
690
691 #ifdef CONFIG_MMC_DEBUG
692 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
693 {
694         static const char *mmc_omap_status_bits[] = {
695                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
696                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
697         };
698         int i;
699         char res[64], *buf = res;
700
701         buf += sprintf(buf, "MMC IRQ 0x%x:", status);
702
703         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
704                 if (status & (1 << i))
705                         buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
706         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
707 }
708 #else
709 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
710 {
711 }
712 #endif
713
714
715 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
716 {
717         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
718         u16 status;
719         int end_command;
720         int end_transfer;
721         int transfer_error, cmd_error;
722
723         if (host->cmd == NULL && host->data == NULL) {
724                 status = OMAP_MMC_READ(host, STAT);
725                 dev_info(mmc_dev(host->slots[0]->mmc),
726                          "Spurious IRQ 0x%04x\n", status);
727                 if (status != 0) {
728                         OMAP_MMC_WRITE(host, STAT, status);
729                         OMAP_MMC_WRITE(host, IE, 0);
730                 }
731                 return IRQ_HANDLED;
732         }
733
734         end_command = 0;
735         end_transfer = 0;
736         transfer_error = 0;
737         cmd_error = 0;
738
739         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
740                 int cmd;
741
742                 OMAP_MMC_WRITE(host, STAT, status);
743                 if (host->cmd != NULL)
744                         cmd = host->cmd->opcode;
745                 else
746                         cmd = -1;
747                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
748                         status, cmd);
749                 mmc_omap_report_irq(host, status);
750
751                 if (host->total_bytes_left) {
752                         if ((status & OMAP_MMC_STAT_A_FULL) ||
753                             (status & OMAP_MMC_STAT_END_OF_DATA))
754                                 mmc_omap_xfer_data(host, 0);
755                         if (status & OMAP_MMC_STAT_A_EMPTY)
756                                 mmc_omap_xfer_data(host, 1);
757                 }
758
759                 if (status & OMAP_MMC_STAT_END_OF_DATA)
760                         end_transfer = 1;
761
762                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
763                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
764                                 cmd);
765                         if (host->data) {
766                                 host->data->error = -ETIMEDOUT;
767                                 transfer_error = 1;
768                         }
769                 }
770
771                 if (status & OMAP_MMC_STAT_DATA_CRC) {
772                         if (host->data) {
773                                 host->data->error = -EILSEQ;
774                                 dev_dbg(mmc_dev(host->mmc),
775                                          "data CRC error, bytes left %d\n",
776                                         host->total_bytes_left);
777                                 transfer_error = 1;
778                         } else {
779                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
780                         }
781                 }
782
783                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
784                         /* Timeouts are routine with some commands */
785                         if (host->cmd) {
786                                 struct mmc_omap_slot *slot =
787                                         host->current_slot;
788                                 if (slot == NULL ||
789                                     !mmc_omap_cover_is_open(slot))
790                                         dev_err(mmc_dev(host->mmc),
791                                                 "command timeout (CMD%d)\n",
792                                                 cmd);
793                                 host->cmd->error = -ETIMEDOUT;
794                                 end_command = 1;
795                                 cmd_error = 1;
796                         }
797                 }
798
799                 if (status & OMAP_MMC_STAT_CMD_CRC) {
800                         if (host->cmd) {
801                                 dev_err(mmc_dev(host->mmc),
802                                         "command CRC error (CMD%d, arg 0x%08x)\n",
803                                         cmd, host->cmd->arg);
804                                 host->cmd->error = -EILSEQ;
805                                 end_command = 1;
806                                 cmd_error = 1;
807                         } else
808                                 dev_err(mmc_dev(host->mmc),
809                                         "command CRC error without cmd?\n");
810                 }
811
812                 if (status & OMAP_MMC_STAT_CARD_ERR) {
813                         dev_dbg(mmc_dev(host->mmc),
814                                 "ignoring card status error (CMD%d)\n",
815                                 cmd);
816                         end_command = 1;
817                 }
818
819                 /*
820                  * NOTE: On 1610 the END_OF_CMD may come too early when
821                  * starting a write
822                  */
823                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
824                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
825                         end_command = 1;
826                 }
827         }
828
829         if (cmd_error && host->data) {
830                 del_timer(&host->cmd_abort_timer);
831                 host->abort = 1;
832                 OMAP_MMC_WRITE(host, IE, 0);
833                 disable_irq_nosync(host->irq);
834                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
835                 return IRQ_HANDLED;
836         }
837
838         if (end_command && host->cmd)
839                 mmc_omap_cmd_done(host, host->cmd);
840         if (host->data != NULL) {
841                 if (transfer_error)
842                         mmc_omap_xfer_done(host, host->data);
843                 else if (end_transfer)
844                         mmc_omap_end_of_data(host, host->data);
845         }
846
847         return IRQ_HANDLED;
848 }
849
850 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
851 {
852         int cover_open;
853         struct mmc_omap_host *host = dev_get_drvdata(dev);
854         struct mmc_omap_slot *slot = host->slots[num];
855
856         BUG_ON(num >= host->nr_slots);
857
858         /* Other subsystems can call in here before we're initialised. */
859         if (host->nr_slots == 0 || !host->slots[num])
860                 return;
861
862         cover_open = mmc_omap_cover_is_open(slot);
863         if (cover_open != slot->cover_open) {
864                 slot->cover_open = cover_open;
865                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
866         }
867
868         tasklet_hi_schedule(&slot->cover_tasklet);
869 }
870
871 static void mmc_omap_cover_timer(unsigned long arg)
872 {
873         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
874         tasklet_schedule(&slot->cover_tasklet);
875 }
876
877 static void mmc_omap_cover_handler(unsigned long param)
878 {
879         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
880         int cover_open = mmc_omap_cover_is_open(slot);
881
882         mmc_detect_change(slot->mmc, 0);
883         if (!cover_open)
884                 return;
885
886         /*
887          * If no card is inserted, we postpone polling until
888          * the cover has been closed.
889          */
890         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
891                 return;
892
893         mod_timer(&slot->cover_timer,
894                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
895 }
896
897 static void mmc_omap_dma_callback(void *priv)
898 {
899         struct mmc_omap_host *host = priv;
900         struct mmc_data *data = host->data;
901
902         /* If we got to the end of DMA, assume everything went well */
903         data->bytes_xfered += data->blocks * data->blksz;
904
905         mmc_omap_dma_done(host, data);
906 }
907
908 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
909 {
910         u16 reg;
911
912         reg = OMAP_MMC_READ(host, SDIO);
913         reg &= ~(1 << 5);
914         OMAP_MMC_WRITE(host, SDIO, reg);
915         /* Set maximum timeout */
916         OMAP_MMC_WRITE(host, CTO, 0xff);
917 }
918
919 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
920 {
921         unsigned int timeout, cycle_ns;
922         u16 reg;
923
924         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
925         timeout = req->data->timeout_ns / cycle_ns;
926         timeout += req->data->timeout_clks;
927
928         /* Check if we need to use timeout multiplier register */
929         reg = OMAP_MMC_READ(host, SDIO);
930         if (timeout > 0xffff) {
931                 reg |= (1 << 5);
932                 timeout /= 1024;
933         } else
934                 reg &= ~(1 << 5);
935         OMAP_MMC_WRITE(host, SDIO, reg);
936         OMAP_MMC_WRITE(host, DTO, timeout);
937 }
938
939 static void
940 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
941 {
942         struct mmc_data *data = req->data;
943         int i, use_dma, block_size;
944         unsigned sg_len;
945
946         host->data = data;
947         if (data == NULL) {
948                 OMAP_MMC_WRITE(host, BLEN, 0);
949                 OMAP_MMC_WRITE(host, NBLK, 0);
950                 OMAP_MMC_WRITE(host, BUF, 0);
951                 host->dma_in_use = 0;
952                 set_cmd_timeout(host, req);
953                 return;
954         }
955
956         block_size = data->blksz;
957
958         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
959         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
960         set_data_timeout(host, req);
961
962         /* cope with calling layer confusion; it issues "single
963          * block" writes using multi-block scatterlists.
964          */
965         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
966
967         /* Only do DMA for entire blocks */
968         use_dma = host->use_dma;
969         if (use_dma) {
970                 for (i = 0; i < sg_len; i++) {
971                         if ((data->sg[i].length % block_size) != 0) {
972                                 use_dma = 0;
973                                 break;
974                         }
975                 }
976         }
977
978         host->sg_idx = 0;
979         if (use_dma) {
980                 enum dma_data_direction dma_data_dir;
981                 struct dma_async_tx_descriptor *tx;
982                 struct dma_chan *c;
983                 u32 burst, *bp;
984                 u16 buf;
985
986                 /*
987                  * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
988                  * and 24xx. Use 16 or 32 word frames when the
989                  * blocksize is at least that large. Blocksize is
990                  * usually 512 bytes; but not for some SD reads.
991                  */
992                 burst = cpu_is_omap15xx() ? 32 : 64;
993                 if (burst > data->blksz)
994                         burst = data->blksz;
995
996                 burst >>= 1;
997
998                 if (data->flags & MMC_DATA_WRITE) {
999                         c = host->dma_tx;
1000                         bp = &host->dma_tx_burst;
1001                         buf = 0x0f80 | (burst - 1) << 0;
1002                         dma_data_dir = DMA_TO_DEVICE;
1003                 } else {
1004                         c = host->dma_rx;
1005                         bp = &host->dma_rx_burst;
1006                         buf = 0x800f | (burst - 1) << 8;
1007                         dma_data_dir = DMA_FROM_DEVICE;
1008                 }
1009
1010                 if (!c)
1011                         goto use_pio;
1012
1013                 /* Only reconfigure if we have a different burst size */
1014                 if (*bp != burst) {
1015                         struct dma_slave_config cfg;
1016
1017                         cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1018                         cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1019                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1020                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1021                         cfg.src_maxburst = burst;
1022                         cfg.dst_maxburst = burst;
1023
1024                         if (dmaengine_slave_config(c, &cfg))
1025                                 goto use_pio;
1026
1027                         *bp = burst;
1028                 }
1029
1030                 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1031                                           dma_data_dir);
1032                 if (host->sg_len == 0)
1033                         goto use_pio;
1034
1035                 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1036                         data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1037                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1038                 if (!tx)
1039                         goto use_pio;
1040
1041                 OMAP_MMC_WRITE(host, BUF, buf);
1042
1043                 tx->callback = mmc_omap_dma_callback;
1044                 tx->callback_param = host;
1045                 dmaengine_submit(tx);
1046                 host->brs_received = 0;
1047                 host->dma_done = 0;
1048                 host->dma_in_use = 1;
1049                 return;
1050         }
1051  use_pio:
1052
1053         /* Revert to PIO? */
1054         OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1055         host->total_bytes_left = data->blocks * block_size;
1056         host->sg_len = sg_len;
1057         mmc_omap_sg_to_buf(host);
1058         host->dma_in_use = 0;
1059 }
1060
1061 static void mmc_omap_start_request(struct mmc_omap_host *host,
1062                                    struct mmc_request *req)
1063 {
1064         BUG_ON(host->mrq != NULL);
1065
1066         host->mrq = req;
1067
1068         /* only touch fifo AFTER the controller readies it */
1069         mmc_omap_prepare_data(host, req);
1070         mmc_omap_start_command(host, req->cmd);
1071         if (host->dma_in_use) {
1072                 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1073                                 host->dma_tx : host->dma_rx;
1074
1075                 dma_async_issue_pending(c);
1076         }
1077 }
1078
1079 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1080 {
1081         struct mmc_omap_slot *slot = mmc_priv(mmc);
1082         struct mmc_omap_host *host = slot->host;
1083         unsigned long flags;
1084
1085         spin_lock_irqsave(&host->slot_lock, flags);
1086         if (host->mmc != NULL) {
1087                 BUG_ON(slot->mrq != NULL);
1088                 slot->mrq = req;
1089                 spin_unlock_irqrestore(&host->slot_lock, flags);
1090                 return;
1091         } else
1092                 host->mmc = mmc;
1093         spin_unlock_irqrestore(&host->slot_lock, flags);
1094         mmc_omap_select_slot(slot, 1);
1095         mmc_omap_start_request(host, req);
1096 }
1097
1098 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1099                                 int vdd)
1100 {
1101         struct mmc_omap_host *host;
1102
1103         host = slot->host;
1104
1105         if (slot->pdata->set_power != NULL)
1106                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1107                                         vdd);
1108
1109         if (cpu_is_omap24xx()) {
1110                 u16 w;
1111
1112                 if (power_on) {
1113                         w = OMAP_MMC_READ(host, CON);
1114                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1115                 } else {
1116                         w = OMAP_MMC_READ(host, CON);
1117                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1118                 }
1119         }
1120 }
1121
1122 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1123 {
1124         struct mmc_omap_slot *slot = mmc_priv(mmc);
1125         struct mmc_omap_host *host = slot->host;
1126         int func_clk_rate = clk_get_rate(host->fclk);
1127         int dsor;
1128
1129         if (ios->clock == 0)
1130                 return 0;
1131
1132         dsor = func_clk_rate / ios->clock;
1133         if (dsor < 1)
1134                 dsor = 1;
1135
1136         if (func_clk_rate / dsor > ios->clock)
1137                 dsor++;
1138
1139         if (dsor > 250)
1140                 dsor = 250;
1141
1142         slot->fclk_freq = func_clk_rate / dsor;
1143
1144         if (ios->bus_width == MMC_BUS_WIDTH_4)
1145                 dsor |= 1 << 15;
1146
1147         return dsor;
1148 }
1149
1150 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1151 {
1152         struct mmc_omap_slot *slot = mmc_priv(mmc);
1153         struct mmc_omap_host *host = slot->host;
1154         int i, dsor;
1155         int clk_enabled;
1156
1157         mmc_omap_select_slot(slot, 0);
1158
1159         dsor = mmc_omap_calc_divisor(mmc, ios);
1160
1161         if (ios->vdd != slot->vdd)
1162                 slot->vdd = ios->vdd;
1163
1164         clk_enabled = 0;
1165         switch (ios->power_mode) {
1166         case MMC_POWER_OFF:
1167                 mmc_omap_set_power(slot, 0, ios->vdd);
1168                 break;
1169         case MMC_POWER_UP:
1170                 /* Cannot touch dsor yet, just power up MMC */
1171                 mmc_omap_set_power(slot, 1, ios->vdd);
1172                 goto exit;
1173         case MMC_POWER_ON:
1174                 mmc_omap_fclk_enable(host, 1);
1175                 clk_enabled = 1;
1176                 dsor |= 1 << 11;
1177                 break;
1178         }
1179
1180         if (slot->bus_mode != ios->bus_mode) {
1181                 if (slot->pdata->set_bus_mode != NULL)
1182                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1183                                                   ios->bus_mode);
1184                 slot->bus_mode = ios->bus_mode;
1185         }
1186
1187         /* On insanely high arm_per frequencies something sometimes
1188          * goes somehow out of sync, and the POW bit is not being set,
1189          * which results in the while loop below getting stuck.
1190          * Writing to the CON register twice seems to do the trick. */
1191         for (i = 0; i < 2; i++)
1192                 OMAP_MMC_WRITE(host, CON, dsor);
1193         slot->saved_con = dsor;
1194         if (ios->power_mode == MMC_POWER_ON) {
1195                 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1196                 int usecs = 250;
1197
1198                 /* Send clock cycles, poll completion */
1199                 OMAP_MMC_WRITE(host, IE, 0);
1200                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1201                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1202                 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1203                         udelay(1);
1204                         usecs--;
1205                 }
1206                 OMAP_MMC_WRITE(host, STAT, 1);
1207         }
1208
1209 exit:
1210         mmc_omap_release_slot(slot, clk_enabled);
1211 }
1212
1213 static const struct mmc_host_ops mmc_omap_ops = {
1214         .request        = mmc_omap_request,
1215         .set_ios        = mmc_omap_set_ios,
1216 };
1217
1218 static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1219 {
1220         struct mmc_omap_slot *slot = NULL;
1221         struct mmc_host *mmc;
1222         int r;
1223
1224         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1225         if (mmc == NULL)
1226                 return -ENOMEM;
1227
1228         slot = mmc_priv(mmc);
1229         slot->host = host;
1230         slot->mmc = mmc;
1231         slot->id = id;
1232         slot->pdata = &host->pdata->slots[id];
1233
1234         host->slots[id] = slot;
1235
1236         mmc->caps = 0;
1237         if (host->pdata->slots[id].wires >= 4)
1238                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1239
1240         mmc->ops = &mmc_omap_ops;
1241         mmc->f_min = 400000;
1242
1243         if (cpu_class_is_omap2())
1244                 mmc->f_max = 48000000;
1245         else
1246                 mmc->f_max = 24000000;
1247         if (host->pdata->max_freq)
1248                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1249         mmc->ocr_avail = slot->pdata->ocr_mask;
1250
1251         /* Use scatterlist DMA to reduce per-transfer costs.
1252          * NOTE max_seg_size assumption that small blocks aren't
1253          * normally used (except e.g. for reading SD registers).
1254          */
1255         mmc->max_segs = 32;
1256         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1257         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1258         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1259         mmc->max_seg_size = mmc->max_req_size;
1260
1261         r = mmc_add_host(mmc);
1262         if (r < 0)
1263                 goto err_remove_host;
1264
1265         if (slot->pdata->name != NULL) {
1266                 r = device_create_file(&mmc->class_dev,
1267                                         &dev_attr_slot_name);
1268                 if (r < 0)
1269                         goto err_remove_host;
1270         }
1271
1272         if (slot->pdata->get_cover_state != NULL) {
1273                 r = device_create_file(&mmc->class_dev,
1274                                         &dev_attr_cover_switch);
1275                 if (r < 0)
1276                         goto err_remove_slot_name;
1277
1278                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1279                             (unsigned long)slot);
1280                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1281                              (unsigned long)slot);
1282                 tasklet_schedule(&slot->cover_tasklet);
1283         }
1284
1285         return 0;
1286
1287 err_remove_slot_name:
1288         if (slot->pdata->name != NULL)
1289                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1290 err_remove_host:
1291         mmc_remove_host(mmc);
1292         mmc_free_host(mmc);
1293         return r;
1294 }
1295
1296 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1297 {
1298         struct mmc_host *mmc = slot->mmc;
1299
1300         if (slot->pdata->name != NULL)
1301                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1302         if (slot->pdata->get_cover_state != NULL)
1303                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1304
1305         tasklet_kill(&slot->cover_tasklet);
1306         del_timer_sync(&slot->cover_timer);
1307         flush_workqueue(slot->host->mmc_omap_wq);
1308
1309         mmc_remove_host(mmc);
1310         mmc_free_host(mmc);
1311 }
1312
1313 static int __devinit mmc_omap_probe(struct platform_device *pdev)
1314 {
1315         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1316         struct mmc_omap_host *host = NULL;
1317         struct resource *res;
1318         dma_cap_mask_t mask;
1319         unsigned sig;
1320         int i, ret = 0;
1321         int irq;
1322
1323         if (pdata == NULL) {
1324                 dev_err(&pdev->dev, "platform data missing\n");
1325                 return -ENXIO;
1326         }
1327         if (pdata->nr_slots == 0) {
1328                 dev_err(&pdev->dev, "no slots\n");
1329                 return -ENXIO;
1330         }
1331
1332         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1333         irq = platform_get_irq(pdev, 0);
1334         if (res == NULL || irq < 0)
1335                 return -ENXIO;
1336
1337         res = request_mem_region(res->start, resource_size(res),
1338                                  pdev->name);
1339         if (res == NULL)
1340                 return -EBUSY;
1341
1342         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1343         if (host == NULL) {
1344                 ret = -ENOMEM;
1345                 goto err_free_mem_region;
1346         }
1347
1348         INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1349         INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1350
1351         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1352         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1353                     (unsigned long) host);
1354
1355         spin_lock_init(&host->clk_lock);
1356         setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1357
1358         spin_lock_init(&host->dma_lock);
1359         spin_lock_init(&host->slot_lock);
1360         init_waitqueue_head(&host->slot_wq);
1361
1362         host->pdata = pdata;
1363         host->dev = &pdev->dev;
1364         platform_set_drvdata(pdev, host);
1365
1366         host->id = pdev->id;
1367         host->mem_res = res;
1368         host->irq = irq;
1369         host->use_dma = 1;
1370         host->irq = irq;
1371         host->phys_base = host->mem_res->start;
1372         host->virt_base = ioremap(res->start, resource_size(res));
1373         if (!host->virt_base)
1374                 goto err_ioremap;
1375
1376         host->iclk = clk_get(&pdev->dev, "ick");
1377         if (IS_ERR(host->iclk)) {
1378                 ret = PTR_ERR(host->iclk);
1379                 goto err_free_mmc_host;
1380         }
1381         clk_enable(host->iclk);
1382
1383         host->fclk = clk_get(&pdev->dev, "fck");
1384         if (IS_ERR(host->fclk)) {
1385                 ret = PTR_ERR(host->fclk);
1386                 goto err_free_iclk;
1387         }
1388
1389         dma_cap_zero(mask);
1390         dma_cap_set(DMA_SLAVE, mask);
1391
1392         host->dma_tx_burst = -1;
1393         host->dma_rx_burst = -1;
1394
1395         if (cpu_is_omap24xx())
1396                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
1397         else
1398                 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
1399         host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1400 #if 0
1401         if (!host->dma_tx) {
1402                 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
1403                         sig);
1404                 goto err_dma;
1405         }
1406 #else
1407         if (!host->dma_tx)
1408                 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1409                         sig);
1410 #endif
1411         if (cpu_is_omap24xx())
1412                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
1413         else
1414                 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
1415         host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1416 #if 0
1417         if (!host->dma_rx) {
1418                 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
1419                         sig);
1420                 goto err_dma;
1421         }
1422 #else
1423         if (!host->dma_rx)
1424                 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1425                         sig);
1426 #endif
1427
1428         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1429         if (ret)
1430                 goto err_free_dma;
1431
1432         if (pdata->init != NULL) {
1433                 ret = pdata->init(&pdev->dev);
1434                 if (ret < 0)
1435                         goto err_free_irq;
1436         }
1437
1438         host->nr_slots = pdata->nr_slots;
1439         host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
1440
1441         host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1442         if (!host->mmc_omap_wq)
1443                 goto err_plat_cleanup;
1444
1445         for (i = 0; i < pdata->nr_slots; i++) {
1446                 ret = mmc_omap_new_slot(host, i);
1447                 if (ret < 0) {
1448                         while (--i >= 0)
1449                                 mmc_omap_remove_slot(host->slots[i]);
1450
1451                         goto err_destroy_wq;
1452                 }
1453         }
1454
1455         return 0;
1456
1457 err_destroy_wq:
1458         destroy_workqueue(host->mmc_omap_wq);
1459 err_plat_cleanup:
1460         if (pdata->cleanup)
1461                 pdata->cleanup(&pdev->dev);
1462 err_free_irq:
1463         free_irq(host->irq, host);
1464 err_free_dma:
1465         if (host->dma_tx)
1466                 dma_release_channel(host->dma_tx);
1467         if (host->dma_rx)
1468                 dma_release_channel(host->dma_rx);
1469         clk_put(host->fclk);
1470 err_free_iclk:
1471         clk_disable(host->iclk);
1472         clk_put(host->iclk);
1473 err_free_mmc_host:
1474         iounmap(host->virt_base);
1475 err_ioremap:
1476         kfree(host);
1477 err_free_mem_region:
1478         release_mem_region(res->start, resource_size(res));
1479         return ret;
1480 }
1481
1482 static int __devexit mmc_omap_remove(struct platform_device *pdev)
1483 {
1484         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1485         int i;
1486
1487         platform_set_drvdata(pdev, NULL);
1488
1489         BUG_ON(host == NULL);
1490
1491         for (i = 0; i < host->nr_slots; i++)
1492                 mmc_omap_remove_slot(host->slots[i]);
1493
1494         if (host->pdata->cleanup)
1495                 host->pdata->cleanup(&pdev->dev);
1496
1497         mmc_omap_fclk_enable(host, 0);
1498         free_irq(host->irq, host);
1499         clk_put(host->fclk);
1500         clk_disable(host->iclk);
1501         clk_put(host->iclk);
1502
1503         if (host->dma_tx)
1504                 dma_release_channel(host->dma_tx);
1505         if (host->dma_rx)
1506                 dma_release_channel(host->dma_rx);
1507
1508         iounmap(host->virt_base);
1509         release_mem_region(pdev->resource[0].start,
1510                            pdev->resource[0].end - pdev->resource[0].start + 1);
1511         destroy_workqueue(host->mmc_omap_wq);
1512
1513         kfree(host);
1514
1515         return 0;
1516 }
1517
1518 #ifdef CONFIG_PM
1519 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1520 {
1521         int i, ret = 0;
1522         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1523
1524         if (host == NULL || host->suspended)
1525                 return 0;
1526
1527         for (i = 0; i < host->nr_slots; i++) {
1528                 struct mmc_omap_slot *slot;
1529
1530                 slot = host->slots[i];
1531                 ret = mmc_suspend_host(slot->mmc);
1532                 if (ret < 0) {
1533                         while (--i >= 0) {
1534                                 slot = host->slots[i];
1535                                 mmc_resume_host(slot->mmc);
1536                         }
1537                         return ret;
1538                 }
1539         }
1540         host->suspended = 1;
1541         return 0;
1542 }
1543
1544 static int mmc_omap_resume(struct platform_device *pdev)
1545 {
1546         int i, ret = 0;
1547         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1548
1549         if (host == NULL || !host->suspended)
1550                 return 0;
1551
1552         for (i = 0; i < host->nr_slots; i++) {
1553                 struct mmc_omap_slot *slot;
1554                 slot = host->slots[i];
1555                 ret = mmc_resume_host(slot->mmc);
1556                 if (ret < 0)
1557                         return ret;
1558
1559                 host->suspended = 0;
1560         }
1561         return 0;
1562 }
1563 #else
1564 #define mmc_omap_suspend        NULL
1565 #define mmc_omap_resume         NULL
1566 #endif
1567
1568 static struct platform_driver mmc_omap_driver = {
1569         .probe          = mmc_omap_probe,
1570         .remove         = __devexit_p(mmc_omap_remove),
1571         .suspend        = mmc_omap_suspend,
1572         .resume         = mmc_omap_resume,
1573         .driver         = {
1574                 .name   = DRIVER_NAME,
1575                 .owner  = THIS_MODULE,
1576         },
1577 };
1578
1579 module_platform_driver(mmc_omap_driver);
1580 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1581 MODULE_LICENSE("GPL");
1582 MODULE_ALIAS("platform:" DRIVER_NAME);
1583 MODULE_AUTHOR("Juha Yrjölä");