Merge tag 'nand/for-4.17' of git://git.infradead.org/linux-mtd into mtd/next
[muen/linux.git] / drivers / mtd / nand / raw / fsl_ifc_nand.c
1 /*
2  * Freescale Integrated Flash Controller NAND driver
3  *
4  * Copyright 2011-2012 Freescale Semiconductor, Inc
5  *
6  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21  */
22
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/rawnand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mtd/nand_ecc.h>
32 #include <linux/fsl_ifc.h>
33
34 #define ERR_BYTE                0xFF /* Value returned for read
35                                         bytes when read failed  */
36 #define IFC_TIMEOUT_MSECS       500  /* Maximum number of mSecs to wait
37                                         for IFC NAND Machine    */
38
39 struct fsl_ifc_ctrl;
40
41 /* mtd information per set */
42 struct fsl_ifc_mtd {
43         struct nand_chip chip;
44         struct fsl_ifc_ctrl *ctrl;
45
46         struct device *dev;
47         int bank;               /* Chip select bank number              */
48         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
49         u8 __iomem *vbase;      /* Chip select base virtual address     */
50 };
51
52 /* overview of the fsl ifc controller */
53 struct fsl_ifc_nand_ctrl {
54         struct nand_hw_control controller;
55         struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
56
57         void __iomem *addr;     /* Address of assigned IFC buffer       */
58         unsigned int page;      /* Last page written to / read from     */
59         unsigned int read_bytes;/* Number of bytes read during command  */
60         unsigned int column;    /* Saved column from SEQIN              */
61         unsigned int index;     /* Pointer to next byte to 'read'       */
62         unsigned int oob;       /* Non zero if operating on OOB data    */
63         unsigned int eccread;   /* Non zero for a full-page ECC read    */
64         unsigned int counter;   /* counter for the initializations      */
65         unsigned int max_bitflips;  /* Saved during READ0 cmd           */
66 };
67
68 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
69
70 /*
71  * Generic flash bbt descriptors
72  */
73 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
74 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
75
76 static struct nand_bbt_descr bbt_main_descr = {
77         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
78                    NAND_BBT_2BIT | NAND_BBT_VERSION,
79         .offs = 2, /* 0 on 8-bit small page */
80         .len = 4,
81         .veroffs = 6,
82         .maxblocks = 4,
83         .pattern = bbt_pattern,
84 };
85
86 static struct nand_bbt_descr bbt_mirror_descr = {
87         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
88                    NAND_BBT_2BIT | NAND_BBT_VERSION,
89         .offs = 2, /* 0 on 8-bit small page */
90         .len = 4,
91         .veroffs = 6,
92         .maxblocks = 4,
93         .pattern = mirror_pattern,
94 };
95
96 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
97                                  struct mtd_oob_region *oobregion)
98 {
99         struct nand_chip *chip = mtd_to_nand(mtd);
100
101         if (section)
102                 return -ERANGE;
103
104         oobregion->offset = 8;
105         oobregion->length = chip->ecc.total;
106
107         return 0;
108 }
109
110 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
111                                   struct mtd_oob_region *oobregion)
112 {
113         struct nand_chip *chip = mtd_to_nand(mtd);
114
115         if (section > 1)
116                 return -ERANGE;
117
118         if (mtd->writesize == 512 &&
119             !(chip->options & NAND_BUSWIDTH_16)) {
120                 if (!section) {
121                         oobregion->offset = 0;
122                         oobregion->length = 5;
123                 } else {
124                         oobregion->offset = 6;
125                         oobregion->length = 2;
126                 }
127
128                 return 0;
129         }
130
131         if (!section) {
132                 oobregion->offset = 2;
133                 oobregion->length = 6;
134         } else {
135                 oobregion->offset = chip->ecc.total + 8;
136                 oobregion->length = mtd->oobsize - oobregion->offset;
137         }
138
139         return 0;
140 }
141
142 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
143         .ecc = fsl_ifc_ooblayout_ecc,
144         .free = fsl_ifc_ooblayout_free,
145 };
146
147 /*
148  * Set up the IFC hardware block and page address fields, and the ifc nand
149  * structure addr field to point to the correct IFC buffer in memory
150  */
151 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
152 {
153         struct nand_chip *chip = mtd_to_nand(mtd);
154         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
155         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
156         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
157         int buf_num;
158
159         ifc_nand_ctrl->page = page_addr;
160         /* Program ROW0/COL0 */
161         ifc_out32(page_addr, &ifc->ifc_nand.row0);
162         ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
163
164         buf_num = page_addr & priv->bufnum_mask;
165
166         ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
167         ifc_nand_ctrl->index = column;
168
169         /* for OOB data point to the second half of the buffer */
170         if (oob)
171                 ifc_nand_ctrl->index += mtd->writesize;
172 }
173
174 /* returns nonzero if entire page is blank */
175 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
176                           u32 *eccstat, unsigned int bufnum)
177 {
178         u32 reg = eccstat[bufnum / 4];
179         int errors;
180
181         errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
182
183         return errors;
184 }
185
186 /*
187  * execute IFC NAND command and wait for it to complete
188  */
189 static void fsl_ifc_run_command(struct mtd_info *mtd)
190 {
191         struct nand_chip *chip = mtd_to_nand(mtd);
192         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
193         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
194         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
195         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
196         u32 eccstat[4];
197         int i;
198
199         /* set the chip select for NAND Transaction */
200         ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
201                   &ifc->ifc_nand.nand_csel);
202
203         dev_vdbg(priv->dev,
204                         "%s: fir0=%08x fcr0=%08x\n",
205                         __func__,
206                         ifc_in32(&ifc->ifc_nand.nand_fir0),
207                         ifc_in32(&ifc->ifc_nand.nand_fcr0));
208
209         ctrl->nand_stat = 0;
210
211         /* start read/write seq */
212         ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
213
214         /* wait for command complete flag or timeout */
215         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
216                            msecs_to_jiffies(IFC_TIMEOUT_MSECS));
217
218         /* ctrl->nand_stat will be updated from IRQ context */
219         if (!ctrl->nand_stat)
220                 dev_err(priv->dev, "Controller is not responding\n");
221         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
222                 dev_err(priv->dev, "NAND Flash Timeout Error\n");
223         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
224                 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
225
226         nctrl->max_bitflips = 0;
227
228         if (nctrl->eccread) {
229                 int errors;
230                 int bufnum = nctrl->page & priv->bufnum_mask;
231                 int sector = bufnum * chip->ecc.steps;
232                 int sector_end = sector + chip->ecc.steps - 1;
233                 __be32 *eccstat_regs;
234
235                 if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
236                         eccstat_regs = ifc->ifc_nand.v2_nand_eccstat;
237                 else
238                         eccstat_regs = ifc->ifc_nand.v1_nand_eccstat;
239
240                 for (i = sector / 4; i <= sector_end / 4; i++)
241                         eccstat[i] = ifc_in32(&eccstat_regs[i]);
242
243                 for (i = sector; i <= sector_end; i++) {
244                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
245
246                         if (errors == 15) {
247                                 /*
248                                  * Uncorrectable error.
249                                  * We'll check for blank pages later.
250                                  *
251                                  * We disable ECCER reporting due to...
252                                  * erratum IFC-A002770 -- so report it now if we
253                                  * see an uncorrectable error in ECCSTAT.
254                                  */
255                                 ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
256                                 continue;
257                         }
258
259                         mtd->ecc_stats.corrected += errors;
260                         nctrl->max_bitflips = max_t(unsigned int,
261                                                     nctrl->max_bitflips,
262                                                     errors);
263                 }
264
265                 nctrl->eccread = 0;
266         }
267 }
268
269 static void fsl_ifc_do_read(struct nand_chip *chip,
270                             int oob,
271                             struct mtd_info *mtd)
272 {
273         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
274         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
275         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
276
277         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
278         if (mtd->writesize > 512) {
279                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
280                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
281                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
282                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
283                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
284                           &ifc->ifc_nand.nand_fir0);
285                 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
286
287                 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
288                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
289                           &ifc->ifc_nand.nand_fcr0);
290         } else {
291                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
292                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
293                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
294                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
295                           &ifc->ifc_nand.nand_fir0);
296                 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
297
298                 if (oob)
299                         ifc_out32(NAND_CMD_READOOB <<
300                                   IFC_NAND_FCR0_CMD0_SHIFT,
301                                   &ifc->ifc_nand.nand_fcr0);
302                 else
303                         ifc_out32(NAND_CMD_READ0 <<
304                                   IFC_NAND_FCR0_CMD0_SHIFT,
305                                   &ifc->ifc_nand.nand_fcr0);
306         }
307 }
308
309 /* cmdfunc send commands to the IFC NAND Machine */
310 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
311                              int column, int page_addr) {
312         struct nand_chip *chip = mtd_to_nand(mtd);
313         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
314         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
315         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
316
317         /* clear the read buffer */
318         ifc_nand_ctrl->read_bytes = 0;
319         if (command != NAND_CMD_PAGEPROG)
320                 ifc_nand_ctrl->index = 0;
321
322         switch (command) {
323         /* READ0 read the entire buffer to use hardware ECC. */
324         case NAND_CMD_READ0:
325                 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
326                 set_addr(mtd, 0, page_addr, 0);
327
328                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
329                 ifc_nand_ctrl->index += column;
330
331                 if (chip->ecc.mode == NAND_ECC_HW)
332                         ifc_nand_ctrl->eccread = 1;
333
334                 fsl_ifc_do_read(chip, 0, mtd);
335                 fsl_ifc_run_command(mtd);
336                 return;
337
338         /* READOOB reads only the OOB because no ECC is performed. */
339         case NAND_CMD_READOOB:
340                 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
341                 set_addr(mtd, column, page_addr, 1);
342
343                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
344
345                 fsl_ifc_do_read(chip, 1, mtd);
346                 fsl_ifc_run_command(mtd);
347
348                 return;
349
350         case NAND_CMD_READID:
351         case NAND_CMD_PARAM: {
352                 int timing = IFC_FIR_OP_RB;
353                 if (command == NAND_CMD_PARAM)
354                         timing = IFC_FIR_OP_RBCD;
355
356                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
357                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
358                           (timing << IFC_NAND_FIR0_OP2_SHIFT),
359                           &ifc->ifc_nand.nand_fir0);
360                 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
361                           &ifc->ifc_nand.nand_fcr0);
362                 ifc_out32(column, &ifc->ifc_nand.row3);
363
364                 /*
365                  * although currently it's 8 bytes for READID, we always read
366                  * the maximum 256 bytes(for PARAM)
367                  */
368                 ifc_out32(256, &ifc->ifc_nand.nand_fbcr);
369                 ifc_nand_ctrl->read_bytes = 256;
370
371                 set_addr(mtd, 0, 0, 0);
372                 fsl_ifc_run_command(mtd);
373                 return;
374         }
375
376         /* ERASE1 stores the block and page address */
377         case NAND_CMD_ERASE1:
378                 set_addr(mtd, 0, page_addr, 0);
379                 return;
380
381         /* ERASE2 uses the block and page address from ERASE1 */
382         case NAND_CMD_ERASE2:
383                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
384                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
385                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
386                           &ifc->ifc_nand.nand_fir0);
387
388                 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
389                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
390                           &ifc->ifc_nand.nand_fcr0);
391
392                 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
393                 ifc_nand_ctrl->read_bytes = 0;
394                 fsl_ifc_run_command(mtd);
395                 return;
396
397         /* SEQIN sets up the addr buffer and all registers except the length */
398         case NAND_CMD_SEQIN: {
399                 u32 nand_fcr0;
400                 ifc_nand_ctrl->column = column;
401                 ifc_nand_ctrl->oob = 0;
402
403                 if (mtd->writesize > 512) {
404                         nand_fcr0 =
405                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
406                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
407                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
408
409                         ifc_out32(
410                                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
411                                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
412                                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
413                                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
414                                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
415                                 &ifc->ifc_nand.nand_fir0);
416                         ifc_out32(
417                                 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
418                                 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
419                                 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
420                                 &ifc->ifc_nand.nand_fir1);
421                 } else {
422                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
423                                         IFC_NAND_FCR0_CMD1_SHIFT) |
424                                     (NAND_CMD_SEQIN <<
425                                         IFC_NAND_FCR0_CMD2_SHIFT) |
426                                     (NAND_CMD_STATUS <<
427                                         IFC_NAND_FCR0_CMD3_SHIFT));
428
429                         ifc_out32(
430                                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
431                                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
432                                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
433                                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
434                                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
435                                 &ifc->ifc_nand.nand_fir0);
436                         ifc_out32(
437                                 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
438                                 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
439                                 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
440                                 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
441                                 &ifc->ifc_nand.nand_fir1);
442
443                         if (column >= mtd->writesize)
444                                 nand_fcr0 |=
445                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
446                         else
447                                 nand_fcr0 |=
448                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
449                 }
450
451                 if (column >= mtd->writesize) {
452                         /* OOB area --> READOOB */
453                         column -= mtd->writesize;
454                         ifc_nand_ctrl->oob = 1;
455                 }
456                 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
457                 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
458                 return;
459         }
460
461         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
462         case NAND_CMD_PAGEPROG: {
463                 if (ifc_nand_ctrl->oob) {
464                         ifc_out32(ifc_nand_ctrl->index -
465                                   ifc_nand_ctrl->column,
466                                   &ifc->ifc_nand.nand_fbcr);
467                 } else {
468                         ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
469                 }
470
471                 fsl_ifc_run_command(mtd);
472                 return;
473         }
474
475         case NAND_CMD_STATUS: {
476                 void __iomem *addr;
477
478                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
479                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
480                           &ifc->ifc_nand.nand_fir0);
481                 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
482                           &ifc->ifc_nand.nand_fcr0);
483                 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
484                 set_addr(mtd, 0, 0, 0);
485                 ifc_nand_ctrl->read_bytes = 1;
486
487                 fsl_ifc_run_command(mtd);
488
489                 /*
490                  * The chip always seems to report that it is
491                  * write-protected, even when it is not.
492                  */
493                 addr = ifc_nand_ctrl->addr;
494                 if (chip->options & NAND_BUSWIDTH_16)
495                         ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
496                 else
497                         ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
498                 return;
499         }
500
501         case NAND_CMD_RESET:
502                 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
503                           &ifc->ifc_nand.nand_fir0);
504                 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
505                           &ifc->ifc_nand.nand_fcr0);
506                 fsl_ifc_run_command(mtd);
507                 return;
508
509         default:
510                 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
511                                         __func__, command);
512         }
513 }
514
515 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
516 {
517         /* The hardware does not seem to support multiple
518          * chips per bank.
519          */
520 }
521
522 /*
523  * Write buf to the IFC NAND Controller Data Buffer
524  */
525 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
526 {
527         struct nand_chip *chip = mtd_to_nand(mtd);
528         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
529         unsigned int bufsize = mtd->writesize + mtd->oobsize;
530
531         if (len <= 0) {
532                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
533                 return;
534         }
535
536         if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
537                 dev_err(priv->dev,
538                         "%s: beyond end of buffer (%d requested, %u available)\n",
539                         __func__, len, bufsize - ifc_nand_ctrl->index);
540                 len = bufsize - ifc_nand_ctrl->index;
541         }
542
543         memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
544         ifc_nand_ctrl->index += len;
545 }
546
547 /*
548  * Read a byte from either the IFC hardware buffer
549  * read function for 8-bit buswidth
550  */
551 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
552 {
553         struct nand_chip *chip = mtd_to_nand(mtd);
554         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
555         unsigned int offset;
556
557         /*
558          * If there are still bytes in the IFC buffer, then use the
559          * next byte.
560          */
561         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
562                 offset = ifc_nand_ctrl->index++;
563                 return ifc_in8(ifc_nand_ctrl->addr + offset);
564         }
565
566         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
567         return ERR_BYTE;
568 }
569
570 /*
571  * Read two bytes from the IFC hardware buffer
572  * read function for 16-bit buswith
573  */
574 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
575 {
576         struct nand_chip *chip = mtd_to_nand(mtd);
577         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
578         uint16_t data;
579
580         /*
581          * If there are still bytes in the IFC buffer, then use the
582          * next byte.
583          */
584         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
585                 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
586                 ifc_nand_ctrl->index += 2;
587                 return (uint8_t) data;
588         }
589
590         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
591         return ERR_BYTE;
592 }
593
594 /*
595  * Read from the IFC Controller Data Buffer
596  */
597 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
598 {
599         struct nand_chip *chip = mtd_to_nand(mtd);
600         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
601         int avail;
602
603         if (len < 0) {
604                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
605                 return;
606         }
607
608         avail = min((unsigned int)len,
609                         ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
610         memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
611         ifc_nand_ctrl->index += avail;
612
613         if (len > avail)
614                 dev_err(priv->dev,
615                         "%s: beyond end of buffer (%d requested, %d available)\n",
616                         __func__, len, avail);
617 }
618
619 /*
620  * This function is called after Program and Erase Operations to
621  * check for success or failure.
622  */
623 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
624 {
625         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
626         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
627         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
628         u32 nand_fsr;
629
630         /* Use READ_STATUS command, but wait for the device to be ready */
631         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
632                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
633                   &ifc->ifc_nand.nand_fir0);
634         ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
635                   &ifc->ifc_nand.nand_fcr0);
636         ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
637         set_addr(mtd, 0, 0, 0);
638         ifc_nand_ctrl->read_bytes = 1;
639
640         fsl_ifc_run_command(mtd);
641
642         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
643
644         /*
645          * The chip always seems to report that it is
646          * write-protected, even when it is not.
647          */
648         return nand_fsr | NAND_STATUS_WP;
649 }
650
651 /*
652  * The controller does not check for bitflips in erased pages,
653  * therefore software must check instead.
654  */
655 static int check_erased_page(struct nand_chip *chip, u8 *buf)
656 {
657         struct mtd_info *mtd = nand_to_mtd(chip);
658         u8 *ecc = chip->oob_poi;
659         const int ecc_size = chip->ecc.bytes;
660         const int pkt_size = chip->ecc.size;
661         int i, res, bitflips = 0;
662         struct mtd_oob_region oobregion = { };
663
664         mtd_ooblayout_ecc(mtd, 0, &oobregion);
665         ecc += oobregion.offset;
666
667         for (i = 0; i < chip->ecc.steps; ++i) {
668                 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
669                                                   NULL, 0,
670                                                   chip->ecc.strength);
671                 if (res < 0)
672                         mtd->ecc_stats.failed++;
673                 else
674                         mtd->ecc_stats.corrected += res;
675
676                 bitflips = max(res, bitflips);
677                 buf += pkt_size;
678                 ecc += ecc_size;
679         }
680
681         return bitflips;
682 }
683
684 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
685                              uint8_t *buf, int oob_required, int page)
686 {
687         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
688         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
689         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
690
691         nand_read_page_op(chip, page, 0, buf, mtd->writesize);
692         if (oob_required)
693                 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
694
695         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
696                 if (!oob_required)
697                         fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
698
699                 return check_erased_page(chip, buf);
700         }
701
702         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
703                 mtd->ecc_stats.failed++;
704
705         return nctrl->max_bitflips;
706 }
707
708 /* ECC will be calculated automatically, and errors will be detected in
709  * waitfunc.
710  */
711 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
712                                const uint8_t *buf, int oob_required, int page)
713 {
714         nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
715         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
716
717         return nand_prog_page_end_op(chip);
718 }
719
720 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
721 {
722         struct nand_chip *chip = mtd_to_nand(mtd);
723         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
724
725         dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
726                                                         chip->numchips);
727         dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
728                                                         chip->chipsize);
729         dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
730                                                         chip->pagemask);
731         dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
732                                                         chip->chip_delay);
733         dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
734                                                         chip->badblockpos);
735         dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
736                                                         chip->chip_shift);
737         dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
738                                                         chip->page_shift);
739         dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
740                                                         chip->phys_erase_shift);
741         dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
742                                                         chip->ecc.mode);
743         dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
744                                                         chip->ecc.steps);
745         dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
746                                                         chip->ecc.bytes);
747         dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
748                                                         chip->ecc.total);
749         dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
750                                                         mtd->ooblayout);
751         dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
752         dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
753         dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
754                                                         mtd->erasesize);
755         dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
756                                                         mtd->writesize);
757         dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
758                                                         mtd->oobsize);
759
760         return 0;
761 }
762
763 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
764 {
765         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
766         struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
767         struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
768         uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
769         uint32_t cs = priv->bank;
770
771         /* Save CSOR and CSOR_ext */
772         csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
773         csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
774
775         /* chage PageSize 8K and SpareSize 1K*/
776         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
777         ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
778         ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
779
780         /* READID */
781         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
782                     (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
783                     (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
784                     &ifc_runtime->ifc_nand.nand_fir0);
785         ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
786                     &ifc_runtime->ifc_nand.nand_fcr0);
787         ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
788
789         ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
790
791         /* Program ROW0/COL0 */
792         ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
793         ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
794
795         /* set the chip select for NAND Transaction */
796         ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
797                 &ifc_runtime->ifc_nand.nand_csel);
798
799         /* start read seq */
800         ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
801                 &ifc_runtime->ifc_nand.nandseq_strt);
802
803         /* wait for command complete flag or timeout */
804         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
805                            msecs_to_jiffies(IFC_TIMEOUT_MSECS));
806
807         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
808                 pr_err("fsl-ifc: Failed to Initialise SRAM\n");
809
810         /* Restore CSOR and CSOR_ext */
811         ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
812         ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
813 }
814
815 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
816 {
817         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
818         struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
819         struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
820         struct nand_chip *chip = &priv->chip;
821         struct mtd_info *mtd = nand_to_mtd(&priv->chip);
822         u32 csor;
823
824         /* Fill in fsl_ifc_mtd structure */
825         mtd->dev.parent = priv->dev;
826         nand_set_flash_node(chip, priv->dev->of_node);
827
828         /* fill in nand_chip structure */
829         /* set up function call table */
830         if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
831                 & CSPR_PORT_SIZE_16)
832                 chip->read_byte = fsl_ifc_read_byte16;
833         else
834                 chip->read_byte = fsl_ifc_read_byte;
835
836         chip->write_buf = fsl_ifc_write_buf;
837         chip->read_buf = fsl_ifc_read_buf;
838         chip->select_chip = fsl_ifc_select_chip;
839         chip->cmdfunc = fsl_ifc_cmdfunc;
840         chip->waitfunc = fsl_ifc_wait;
841         chip->set_features = nand_get_set_features_notsupp;
842         chip->get_features = nand_get_set_features_notsupp;
843
844         chip->bbt_td = &bbt_main_descr;
845         chip->bbt_md = &bbt_mirror_descr;
846
847         ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
848
849         /* set up nand options */
850         chip->bbt_options = NAND_BBT_USE_FLASH;
851         chip->options = NAND_NO_SUBPAGE_WRITE;
852
853         if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
854                 & CSPR_PORT_SIZE_16) {
855                 chip->read_byte = fsl_ifc_read_byte16;
856                 chip->options |= NAND_BUSWIDTH_16;
857         } else {
858                 chip->read_byte = fsl_ifc_read_byte;
859         }
860
861         chip->controller = &ifc_nand_ctrl->controller;
862         nand_set_controller_data(chip, priv);
863
864         chip->ecc.read_page = fsl_ifc_read_page;
865         chip->ecc.write_page = fsl_ifc_write_page;
866
867         csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
868
869         switch (csor & CSOR_NAND_PGS_MASK) {
870         case CSOR_NAND_PGS_512:
871                 if (!(chip->options & NAND_BUSWIDTH_16)) {
872                         /* Avoid conflict with bad block marker */
873                         bbt_main_descr.offs = 0;
874                         bbt_mirror_descr.offs = 0;
875                 }
876
877                 priv->bufnum_mask = 15;
878                 break;
879
880         case CSOR_NAND_PGS_2K:
881                 priv->bufnum_mask = 3;
882                 break;
883
884         case CSOR_NAND_PGS_4K:
885                 priv->bufnum_mask = 1;
886                 break;
887
888         case CSOR_NAND_PGS_8K:
889                 priv->bufnum_mask = 0;
890                 break;
891
892         default:
893                 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
894                 return -ENODEV;
895         }
896
897         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
898         if (csor & CSOR_NAND_ECC_DEC_EN) {
899                 chip->ecc.mode = NAND_ECC_HW;
900                 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
901
902                 /* Hardware generates ECC per 512 Bytes */
903                 chip->ecc.size = 512;
904                 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
905                         chip->ecc.bytes = 8;
906                         chip->ecc.strength = 4;
907                 } else {
908                         chip->ecc.bytes = 16;
909                         chip->ecc.strength = 8;
910                 }
911         } else {
912                 chip->ecc.mode = NAND_ECC_SOFT;
913                 chip->ecc.algo = NAND_ECC_HAMMING;
914         }
915
916         if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
917                 fsl_ifc_sram_init(priv);
918
919         /*
920          * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
921          * versions which had 8KB. Hence bufnum mask needs to be updated.
922          */
923         if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
924                 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
925
926         return 0;
927 }
928
929 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
930 {
931         struct mtd_info *mtd = nand_to_mtd(&priv->chip);
932
933         nand_release(mtd);
934
935         kfree(mtd->name);
936
937         if (priv->vbase)
938                 iounmap(priv->vbase);
939
940         ifc_nand_ctrl->chips[priv->bank] = NULL;
941
942         return 0;
943 }
944
945 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
946                       phys_addr_t addr)
947 {
948         u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
949
950         if (!(cspr & CSPR_V))
951                 return 0;
952         if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
953                 return 0;
954
955         return (cspr & CSPR_BA) == convert_ifc_address(addr);
956 }
957
958 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
959
960 static int fsl_ifc_nand_probe(struct platform_device *dev)
961 {
962         struct fsl_ifc_runtime __iomem *ifc;
963         struct fsl_ifc_mtd *priv;
964         struct resource res;
965         static const char *part_probe_types[]
966                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
967         int ret;
968         int bank;
969         struct device_node *node = dev->dev.of_node;
970         struct mtd_info *mtd;
971
972         if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
973                 return -ENODEV;
974         ifc = fsl_ifc_ctrl_dev->rregs;
975
976         /* get, allocate and map the memory resource */
977         ret = of_address_to_resource(node, 0, &res);
978         if (ret) {
979                 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
980                 return ret;
981         }
982
983         /* find which chip select it is connected to */
984         for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
985                 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
986                         break;
987         }
988
989         if (bank >= fsl_ifc_ctrl_dev->banks) {
990                 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
991                         __func__);
992                 return -ENODEV;
993         }
994
995         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
996         if (!priv)
997                 return -ENOMEM;
998
999         mutex_lock(&fsl_ifc_nand_mutex);
1000         if (!fsl_ifc_ctrl_dev->nand) {
1001                 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1002                 if (!ifc_nand_ctrl) {
1003                         mutex_unlock(&fsl_ifc_nand_mutex);
1004                         return -ENOMEM;
1005                 }
1006
1007                 ifc_nand_ctrl->read_bytes = 0;
1008                 ifc_nand_ctrl->index = 0;
1009                 ifc_nand_ctrl->addr = NULL;
1010                 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1011
1012                 nand_hw_control_init(&ifc_nand_ctrl->controller);
1013         } else {
1014                 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1015         }
1016         mutex_unlock(&fsl_ifc_nand_mutex);
1017
1018         ifc_nand_ctrl->chips[bank] = priv;
1019         priv->bank = bank;
1020         priv->ctrl = fsl_ifc_ctrl_dev;
1021         priv->dev = &dev->dev;
1022
1023         priv->vbase = ioremap(res.start, resource_size(&res));
1024         if (!priv->vbase) {
1025                 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1026                 ret = -ENOMEM;
1027                 goto err;
1028         }
1029
1030         dev_set_drvdata(priv->dev, priv);
1031
1032         ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1033                   IFC_NAND_EVTER_EN_FTOER_EN |
1034                   IFC_NAND_EVTER_EN_WPER_EN,
1035                   &ifc->ifc_nand.nand_evter_en);
1036
1037         /* enable NAND Machine Interrupts */
1038         ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1039                   IFC_NAND_EVTER_INTR_FTOERIR_EN |
1040                   IFC_NAND_EVTER_INTR_WPERIR_EN,
1041                   &ifc->ifc_nand.nand_evter_intr_en);
1042
1043         mtd = nand_to_mtd(&priv->chip);
1044         mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1045         if (!mtd->name) {
1046                 ret = -ENOMEM;
1047                 goto err;
1048         }
1049
1050         ret = fsl_ifc_chip_init(priv);
1051         if (ret)
1052                 goto err;
1053
1054         ret = nand_scan_ident(mtd, 1, NULL);
1055         if (ret)
1056                 goto err;
1057
1058         ret = fsl_ifc_chip_init_tail(mtd);
1059         if (ret)
1060                 goto err;
1061
1062         ret = nand_scan_tail(mtd);
1063         if (ret)
1064                 goto err;
1065
1066         /* First look for RedBoot table or partitions on the command
1067          * line, these take precedence over device tree information */
1068         mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1069
1070         dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1071                  (unsigned long long)res.start, priv->bank);
1072         return 0;
1073
1074 err:
1075         fsl_ifc_chip_remove(priv);
1076         return ret;
1077 }
1078
1079 static int fsl_ifc_nand_remove(struct platform_device *dev)
1080 {
1081         struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1082
1083         fsl_ifc_chip_remove(priv);
1084
1085         mutex_lock(&fsl_ifc_nand_mutex);
1086         ifc_nand_ctrl->counter--;
1087         if (!ifc_nand_ctrl->counter) {
1088                 fsl_ifc_ctrl_dev->nand = NULL;
1089                 kfree(ifc_nand_ctrl);
1090         }
1091         mutex_unlock(&fsl_ifc_nand_mutex);
1092
1093         return 0;
1094 }
1095
1096 static const struct of_device_id fsl_ifc_nand_match[] = {
1097         {
1098                 .compatible = "fsl,ifc-nand",
1099         },
1100         {}
1101 };
1102 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1103
1104 static struct platform_driver fsl_ifc_nand_driver = {
1105         .driver = {
1106                 .name   = "fsl,ifc-nand",
1107                 .of_match_table = fsl_ifc_nand_match,
1108         },
1109         .probe       = fsl_ifc_nand_probe,
1110         .remove      = fsl_ifc_nand_remove,
1111 };
1112
1113 module_platform_driver(fsl_ifc_nand_driver);
1114
1115 MODULE_LICENSE("GPL");
1116 MODULE_AUTHOR("Freescale");
1117 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");