Merge tag 'mtd/for-4.19' of git://git.infradead.org/linux-mtd
[muen/linux.git] / drivers / mtd / spi-nor / cadence-quadspi.c
1 /*
2  * Driver for Cadence QSPI Controller
3  *
4  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dmaengine.h>
23 #include <linux/err.h>
24 #include <linux/errno.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/jiffies.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/mtd/spi-nor.h>
33 #include <linux/of_device.h>
34 #include <linux/of.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/sched.h>
38 #include <linux/spi/spi.h>
39 #include <linux/timer.h>
40
41 #define CQSPI_NAME                      "cadence-qspi"
42 #define CQSPI_MAX_CHIPSELECT            16
43
44 /* Quirks */
45 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
46
47 struct cqspi_st;
48
49 struct cqspi_flash_pdata {
50         struct spi_nor  nor;
51         struct cqspi_st *cqspi;
52         u32             clk_rate;
53         u32             read_delay;
54         u32             tshsl_ns;
55         u32             tsd2d_ns;
56         u32             tchsh_ns;
57         u32             tslch_ns;
58         u8              inst_width;
59         u8              addr_width;
60         u8              data_width;
61         u8              cs;
62         bool            registered;
63         bool            use_direct_mode;
64 };
65
66 struct cqspi_st {
67         struct platform_device  *pdev;
68
69         struct clk              *clk;
70         unsigned int            sclk;
71
72         void __iomem            *iobase;
73         void __iomem            *ahb_base;
74         resource_size_t         ahb_size;
75         struct completion       transfer_complete;
76         struct mutex            bus_mutex;
77
78         struct dma_chan         *rx_chan;
79         struct completion       rx_dma_complete;
80         dma_addr_t              mmap_phys_base;
81
82         int                     current_cs;
83         int                     current_page_size;
84         int                     current_erase_size;
85         int                     current_addr_width;
86         unsigned long           master_ref_clk_hz;
87         bool                    is_decoded_cs;
88         u32                     fifo_depth;
89         u32                     fifo_width;
90         bool                    rclk_en;
91         u32                     trigger_address;
92         u32                     wr_delay;
93         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
94 };
95
96 /* Operation timeout value */
97 #define CQSPI_TIMEOUT_MS                        500
98 #define CQSPI_READ_TIMEOUT_MS                   10
99
100 /* Instruction type */
101 #define CQSPI_INST_TYPE_SINGLE                  0
102 #define CQSPI_INST_TYPE_DUAL                    1
103 #define CQSPI_INST_TYPE_QUAD                    2
104
105 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
106 #define CQSPI_DUMMY_BYTES_MAX                   4
107 #define CQSPI_DUMMY_CLKS_MAX                    31
108
109 #define CQSPI_STIG_DATA_LEN_MAX                 8
110
111 /* Register map */
112 #define CQSPI_REG_CONFIG                        0x00
113 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
114 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
115 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
116 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
117 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
118 #define CQSPI_REG_CONFIG_BAUD_LSB               19
119 #define CQSPI_REG_CONFIG_IDLE_LSB               31
120 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
121 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
122
123 #define CQSPI_REG_RD_INSTR                      0x04
124 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
125 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
126 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
127 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
128 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
129 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
130 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
131 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
132 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
133 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
134
135 #define CQSPI_REG_WR_INSTR                      0x08
136 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
137 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
138 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
139
140 #define CQSPI_REG_DELAY                         0x0C
141 #define CQSPI_REG_DELAY_TSLCH_LSB               0
142 #define CQSPI_REG_DELAY_TCHSH_LSB               8
143 #define CQSPI_REG_DELAY_TSD2D_LSB               16
144 #define CQSPI_REG_DELAY_TSHSL_LSB               24
145 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
146 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
147 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
148 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
149
150 #define CQSPI_REG_READCAPTURE                   0x10
151 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
152 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
153 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
154
155 #define CQSPI_REG_SIZE                          0x14
156 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
157 #define CQSPI_REG_SIZE_PAGE_LSB                 4
158 #define CQSPI_REG_SIZE_BLOCK_LSB                16
159 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
160 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
161 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
162
163 #define CQSPI_REG_SRAMPARTITION                 0x18
164 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
165
166 #define CQSPI_REG_DMA                           0x20
167 #define CQSPI_REG_DMA_SINGLE_LSB                0
168 #define CQSPI_REG_DMA_BURST_LSB                 8
169 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
170 #define CQSPI_REG_DMA_BURST_MASK                0xFF
171
172 #define CQSPI_REG_REMAP                         0x24
173 #define CQSPI_REG_MODE_BIT                      0x28
174
175 #define CQSPI_REG_SDRAMLEVEL                    0x2C
176 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
177 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
178 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
179 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
180
181 #define CQSPI_REG_IRQSTATUS                     0x40
182 #define CQSPI_REG_IRQMASK                       0x44
183
184 #define CQSPI_REG_INDIRECTRD                    0x60
185 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
186 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
187 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
188
189 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
190 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
191 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
192
193 #define CQSPI_REG_CMDCTRL                       0x90
194 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
195 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
196 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
197 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
198 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
199 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
200 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
201 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
202 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
203 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
204 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
205 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
206
207 #define CQSPI_REG_INDIRECTWR                    0x70
208 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
209 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
210 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
211
212 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
213 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
214 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
215
216 #define CQSPI_REG_CMDADDRESS                    0x94
217 #define CQSPI_REG_CMDREADDATALOWER              0xA0
218 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
219 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
220 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
221
222 /* Interrupt status bits */
223 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
224 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
225 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
226 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
227 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
228 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
229 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
230 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
231
232 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
233                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
234                                          CQSPI_REG_IRQ_IND_COMP)
235
236 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
237                                          CQSPI_REG_IRQ_WATERMARK        | \
238                                          CQSPI_REG_IRQ_UNDERFLOW)
239
240 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
241
242 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
243 {
244         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
245         u32 val;
246
247         while (1) {
248                 val = readl(reg);
249                 if (clear)
250                         val = ~val;
251                 val &= mask;
252
253                 if (val == mask)
254                         return 0;
255
256                 if (time_after(jiffies, end))
257                         return -ETIMEDOUT;
258         }
259 }
260
261 static bool cqspi_is_idle(struct cqspi_st *cqspi)
262 {
263         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
264
265         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
266 }
267
268 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
269 {
270         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
271
272         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
273         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
274 }
275
276 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
277 {
278         struct cqspi_st *cqspi = dev;
279         unsigned int irq_status;
280
281         /* Read interrupt status */
282         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
283
284         /* Clear interrupt */
285         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
286
287         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
288
289         if (irq_status)
290                 complete(&cqspi->transfer_complete);
291
292         return IRQ_HANDLED;
293 }
294
295 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
296 {
297         struct cqspi_flash_pdata *f_pdata = nor->priv;
298         u32 rdreg = 0;
299
300         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
301         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
302         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
303
304         return rdreg;
305 }
306
307 static int cqspi_wait_idle(struct cqspi_st *cqspi)
308 {
309         const unsigned int poll_idle_retry = 3;
310         unsigned int count = 0;
311         unsigned long timeout;
312
313         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
314         while (1) {
315                 /*
316                  * Read few times in succession to ensure the controller
317                  * is indeed idle, that is, the bit does not transition
318                  * low again.
319                  */
320                 if (cqspi_is_idle(cqspi))
321                         count++;
322                 else
323                         count = 0;
324
325                 if (count >= poll_idle_retry)
326                         return 0;
327
328                 if (time_after(jiffies, timeout)) {
329                         /* Timeout, in busy mode. */
330                         dev_err(&cqspi->pdev->dev,
331                                 "QSPI is still busy after %dms timeout.\n",
332                                 CQSPI_TIMEOUT_MS);
333                         return -ETIMEDOUT;
334                 }
335
336                 cpu_relax();
337         }
338 }
339
340 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
341 {
342         void __iomem *reg_base = cqspi->iobase;
343         int ret;
344
345         /* Write the CMDCTRL without start execution. */
346         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
347         /* Start execute */
348         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
349         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
350
351         /* Polling for completion. */
352         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
353                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
354         if (ret) {
355                 dev_err(&cqspi->pdev->dev,
356                         "Flash command execution timed out.\n");
357                 return ret;
358         }
359
360         /* Polling QSPI idle status. */
361         return cqspi_wait_idle(cqspi);
362 }
363
364 static int cqspi_command_read(struct spi_nor *nor,
365                               const u8 *txbuf, const unsigned n_tx,
366                               u8 *rxbuf, const unsigned n_rx)
367 {
368         struct cqspi_flash_pdata *f_pdata = nor->priv;
369         struct cqspi_st *cqspi = f_pdata->cqspi;
370         void __iomem *reg_base = cqspi->iobase;
371         unsigned int rdreg;
372         unsigned int reg;
373         unsigned int read_len;
374         int status;
375
376         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
377                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
378                         n_rx, rxbuf);
379                 return -EINVAL;
380         }
381
382         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
383
384         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
385         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
386
387         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
388
389         /* 0 means 1 byte. */
390         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
391                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
392         status = cqspi_exec_flash_cmd(cqspi, reg);
393         if (status)
394                 return status;
395
396         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
397
398         /* Put the read value into rx_buf */
399         read_len = (n_rx > 4) ? 4 : n_rx;
400         memcpy(rxbuf, &reg, read_len);
401         rxbuf += read_len;
402
403         if (n_rx > 4) {
404                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
405
406                 read_len = n_rx - read_len;
407                 memcpy(rxbuf, &reg, read_len);
408         }
409
410         return 0;
411 }
412
413 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
414                                const u8 *txbuf, const unsigned n_tx)
415 {
416         struct cqspi_flash_pdata *f_pdata = nor->priv;
417         struct cqspi_st *cqspi = f_pdata->cqspi;
418         void __iomem *reg_base = cqspi->iobase;
419         unsigned int reg;
420         unsigned int data;
421         int ret;
422
423         if (n_tx > 4 || (n_tx && !txbuf)) {
424                 dev_err(nor->dev,
425                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
426                         n_tx, txbuf);
427                 return -EINVAL;
428         }
429
430         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
431         if (n_tx) {
432                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
433                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
434                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
435                 data = 0;
436                 memcpy(&data, txbuf, n_tx);
437                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
438         }
439
440         ret = cqspi_exec_flash_cmd(cqspi, reg);
441         return ret;
442 }
443
444 static int cqspi_command_write_addr(struct spi_nor *nor,
445                                     const u8 opcode, const unsigned int addr)
446 {
447         struct cqspi_flash_pdata *f_pdata = nor->priv;
448         struct cqspi_st *cqspi = f_pdata->cqspi;
449         void __iomem *reg_base = cqspi->iobase;
450         unsigned int reg;
451
452         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
453         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
454         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
455                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
456
457         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
458
459         return cqspi_exec_flash_cmd(cqspi, reg);
460 }
461
462 static int cqspi_read_setup(struct spi_nor *nor)
463 {
464         struct cqspi_flash_pdata *f_pdata = nor->priv;
465         struct cqspi_st *cqspi = f_pdata->cqspi;
466         void __iomem *reg_base = cqspi->iobase;
467         unsigned int dummy_clk = 0;
468         unsigned int reg;
469
470         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
471         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
472
473         /* Setup dummy clock cycles */
474         dummy_clk = nor->read_dummy;
475         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
476                 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
477
478         if (dummy_clk / 8) {
479                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
480                 /* Set mode bits high to ensure chip doesn't enter XIP */
481                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
482
483                 /* Need to subtract the mode byte (8 clocks). */
484                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
485                         dummy_clk -= 8;
486
487                 if (dummy_clk)
488                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
489                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
490         }
491
492         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
493
494         /* Set address width */
495         reg = readl(reg_base + CQSPI_REG_SIZE);
496         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
497         reg |= (nor->addr_width - 1);
498         writel(reg, reg_base + CQSPI_REG_SIZE);
499         return 0;
500 }
501
502 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
503                                        loff_t from_addr, const size_t n_rx)
504 {
505         struct cqspi_flash_pdata *f_pdata = nor->priv;
506         struct cqspi_st *cqspi = f_pdata->cqspi;
507         void __iomem *reg_base = cqspi->iobase;
508         void __iomem *ahb_base = cqspi->ahb_base;
509         unsigned int remaining = n_rx;
510         unsigned int mod_bytes = n_rx % 4;
511         unsigned int bytes_to_read = 0;
512         u8 *rxbuf_end = rxbuf + n_rx;
513         int ret = 0;
514
515         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
516         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
517
518         /* Clear all interrupts. */
519         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
520
521         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
522
523         reinit_completion(&cqspi->transfer_complete);
524         writel(CQSPI_REG_INDIRECTRD_START_MASK,
525                reg_base + CQSPI_REG_INDIRECTRD);
526
527         while (remaining > 0) {
528                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
529                                 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
530                         ret = -ETIMEDOUT;
531
532                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
533
534                 if (ret && bytes_to_read == 0) {
535                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
536                         goto failrd;
537                 }
538
539                 while (bytes_to_read != 0) {
540                         unsigned int word_remain = round_down(remaining, 4);
541
542                         bytes_to_read *= cqspi->fifo_width;
543                         bytes_to_read = bytes_to_read > remaining ?
544                                         remaining : bytes_to_read;
545                         bytes_to_read = round_down(bytes_to_read, 4);
546                         /* Read 4 byte word chunks then single bytes */
547                         if (bytes_to_read) {
548                                 ioread32_rep(ahb_base, rxbuf,
549                                              (bytes_to_read / 4));
550                         } else if (!word_remain && mod_bytes) {
551                                 unsigned int temp = ioread32(ahb_base);
552
553                                 bytes_to_read = mod_bytes;
554                                 memcpy(rxbuf, &temp, min((unsigned int)
555                                                          (rxbuf_end - rxbuf),
556                                                          bytes_to_read));
557                         }
558                         rxbuf += bytes_to_read;
559                         remaining -= bytes_to_read;
560                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
561                 }
562
563                 if (remaining > 0)
564                         reinit_completion(&cqspi->transfer_complete);
565         }
566
567         /* Check indirect done status */
568         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
569                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
570         if (ret) {
571                 dev_err(nor->dev,
572                         "Indirect read completion error (%i)\n", ret);
573                 goto failrd;
574         }
575
576         /* Disable interrupt */
577         writel(0, reg_base + CQSPI_REG_IRQMASK);
578
579         /* Clear indirect completion status */
580         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
581
582         return 0;
583
584 failrd:
585         /* Disable interrupt */
586         writel(0, reg_base + CQSPI_REG_IRQMASK);
587
588         /* Cancel the indirect read */
589         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
590                reg_base + CQSPI_REG_INDIRECTRD);
591         return ret;
592 }
593
594 static int cqspi_write_setup(struct spi_nor *nor)
595 {
596         unsigned int reg;
597         struct cqspi_flash_pdata *f_pdata = nor->priv;
598         struct cqspi_st *cqspi = f_pdata->cqspi;
599         void __iomem *reg_base = cqspi->iobase;
600
601         /* Set opcode. */
602         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
603         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
604         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
605         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
606
607         reg = readl(reg_base + CQSPI_REG_SIZE);
608         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
609         reg |= (nor->addr_width - 1);
610         writel(reg, reg_base + CQSPI_REG_SIZE);
611         return 0;
612 }
613
614 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
615                                         const u8 *txbuf, const size_t n_tx)
616 {
617         const unsigned int page_size = nor->page_size;
618         struct cqspi_flash_pdata *f_pdata = nor->priv;
619         struct cqspi_st *cqspi = f_pdata->cqspi;
620         void __iomem *reg_base = cqspi->iobase;
621         unsigned int remaining = n_tx;
622         unsigned int write_bytes;
623         int ret;
624
625         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
626         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
627
628         /* Clear all interrupts. */
629         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
630
631         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
632
633         reinit_completion(&cqspi->transfer_complete);
634         writel(CQSPI_REG_INDIRECTWR_START_MASK,
635                reg_base + CQSPI_REG_INDIRECTWR);
636         /*
637          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
638          * Controller programming sequence, couple of cycles of
639          * QSPI_REF_CLK delay is required for the above bit to
640          * be internally synchronized by the QSPI module. Provide 5
641          * cycles of delay.
642          */
643         if (cqspi->wr_delay)
644                 ndelay(cqspi->wr_delay);
645
646         while (remaining > 0) {
647                 write_bytes = remaining > page_size ? page_size : remaining;
648                 iowrite32_rep(cqspi->ahb_base, txbuf,
649                               DIV_ROUND_UP(write_bytes, 4));
650
651                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
652                                         msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
653                         dev_err(nor->dev, "Indirect write timeout\n");
654                         ret = -ETIMEDOUT;
655                         goto failwr;
656                 }
657
658                 txbuf += write_bytes;
659                 remaining -= write_bytes;
660
661                 if (remaining > 0)
662                         reinit_completion(&cqspi->transfer_complete);
663         }
664
665         /* Check indirect done status */
666         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
667                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
668         if (ret) {
669                 dev_err(nor->dev,
670                         "Indirect write completion error (%i)\n", ret);
671                 goto failwr;
672         }
673
674         /* Disable interrupt. */
675         writel(0, reg_base + CQSPI_REG_IRQMASK);
676
677         /* Clear indirect completion status */
678         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
679
680         cqspi_wait_idle(cqspi);
681
682         return 0;
683
684 failwr:
685         /* Disable interrupt. */
686         writel(0, reg_base + CQSPI_REG_IRQMASK);
687
688         /* Cancel the indirect write */
689         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
690                reg_base + CQSPI_REG_INDIRECTWR);
691         return ret;
692 }
693
694 static void cqspi_chipselect(struct spi_nor *nor)
695 {
696         struct cqspi_flash_pdata *f_pdata = nor->priv;
697         struct cqspi_st *cqspi = f_pdata->cqspi;
698         void __iomem *reg_base = cqspi->iobase;
699         unsigned int chip_select = f_pdata->cs;
700         unsigned int reg;
701
702         reg = readl(reg_base + CQSPI_REG_CONFIG);
703         if (cqspi->is_decoded_cs) {
704                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
705         } else {
706                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
707
708                 /* Convert CS if without decoder.
709                  * CS0 to 4b'1110
710                  * CS1 to 4b'1101
711                  * CS2 to 4b'1011
712                  * CS3 to 4b'0111
713                  */
714                 chip_select = 0xF & ~(1 << chip_select);
715         }
716
717         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
718                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
719         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
720             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
721         writel(reg, reg_base + CQSPI_REG_CONFIG);
722 }
723
724 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
725 {
726         struct cqspi_flash_pdata *f_pdata = nor->priv;
727         struct cqspi_st *cqspi = f_pdata->cqspi;
728         void __iomem *iobase = cqspi->iobase;
729         unsigned int reg;
730
731         /* configure page size and block size. */
732         reg = readl(iobase + CQSPI_REG_SIZE);
733         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
734         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
735         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
736         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
737         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
738         reg |= (nor->addr_width - 1);
739         writel(reg, iobase + CQSPI_REG_SIZE);
740
741         /* configure the chip select */
742         cqspi_chipselect(nor);
743
744         /* Store the new configuration of the controller */
745         cqspi->current_page_size = nor->page_size;
746         cqspi->current_erase_size = nor->mtd.erasesize;
747         cqspi->current_addr_width = nor->addr_width;
748 }
749
750 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
751                                            const unsigned int ns_val)
752 {
753         unsigned int ticks;
754
755         ticks = ref_clk_hz / 1000;      /* kHz */
756         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
757
758         return ticks;
759 }
760
761 static void cqspi_delay(struct spi_nor *nor)
762 {
763         struct cqspi_flash_pdata *f_pdata = nor->priv;
764         struct cqspi_st *cqspi = f_pdata->cqspi;
765         void __iomem *iobase = cqspi->iobase;
766         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
767         unsigned int tshsl, tchsh, tslch, tsd2d;
768         unsigned int reg;
769         unsigned int tsclk;
770
771         /* calculate the number of ref ticks for one sclk tick */
772         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
773
774         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
775         /* this particular value must be at least one sclk */
776         if (tshsl < tsclk)
777                 tshsl = tsclk;
778
779         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
780         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
781         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
782
783         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
784                << CQSPI_REG_DELAY_TSHSL_LSB;
785         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
786                 << CQSPI_REG_DELAY_TCHSH_LSB;
787         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
788                 << CQSPI_REG_DELAY_TSLCH_LSB;
789         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
790                 << CQSPI_REG_DELAY_TSD2D_LSB;
791         writel(reg, iobase + CQSPI_REG_DELAY);
792 }
793
794 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
795 {
796         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
797         void __iomem *reg_base = cqspi->iobase;
798         u32 reg, div;
799
800         /* Recalculate the baudrate divisor based on QSPI specification. */
801         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
802
803         reg = readl(reg_base + CQSPI_REG_CONFIG);
804         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
805         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
806         writel(reg, reg_base + CQSPI_REG_CONFIG);
807 }
808
809 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
810                                    const bool bypass,
811                                    const unsigned int delay)
812 {
813         void __iomem *reg_base = cqspi->iobase;
814         unsigned int reg;
815
816         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
817
818         if (bypass)
819                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
820         else
821                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
822
823         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
824                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
825
826         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
827                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
828
829         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
830 }
831
832 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
833 {
834         void __iomem *reg_base = cqspi->iobase;
835         unsigned int reg;
836
837         reg = readl(reg_base + CQSPI_REG_CONFIG);
838
839         if (enable)
840                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
841         else
842                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
843
844         writel(reg, reg_base + CQSPI_REG_CONFIG);
845 }
846
847 static void cqspi_configure(struct spi_nor *nor)
848 {
849         struct cqspi_flash_pdata *f_pdata = nor->priv;
850         struct cqspi_st *cqspi = f_pdata->cqspi;
851         const unsigned int sclk = f_pdata->clk_rate;
852         int switch_cs = (cqspi->current_cs != f_pdata->cs);
853         int switch_ck = (cqspi->sclk != sclk);
854
855         if ((cqspi->current_page_size != nor->page_size) ||
856             (cqspi->current_erase_size != nor->mtd.erasesize) ||
857             (cqspi->current_addr_width != nor->addr_width))
858                 switch_cs = 1;
859
860         if (switch_cs || switch_ck)
861                 cqspi_controller_enable(cqspi, 0);
862
863         /* Switch chip select. */
864         if (switch_cs) {
865                 cqspi->current_cs = f_pdata->cs;
866                 cqspi_configure_cs_and_sizes(nor);
867         }
868
869         /* Setup baudrate divisor and delays */
870         if (switch_ck) {
871                 cqspi->sclk = sclk;
872                 cqspi_config_baudrate_div(cqspi);
873                 cqspi_delay(nor);
874                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
875                                        f_pdata->read_delay);
876         }
877
878         if (switch_cs || switch_ck)
879                 cqspi_controller_enable(cqspi, 1);
880 }
881
882 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
883 {
884         struct cqspi_flash_pdata *f_pdata = nor->priv;
885
886         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
887         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
888         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
889
890         if (read) {
891                 switch (nor->read_proto) {
892                 case SNOR_PROTO_1_1_1:
893                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
894                         break;
895                 case SNOR_PROTO_1_1_2:
896                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
897                         break;
898                 case SNOR_PROTO_1_1_4:
899                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
900                         break;
901                 default:
902                         return -EINVAL;
903                 }
904         }
905
906         cqspi_configure(nor);
907
908         return 0;
909 }
910
911 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
912                            size_t len, const u_char *buf)
913 {
914         struct cqspi_flash_pdata *f_pdata = nor->priv;
915         struct cqspi_st *cqspi = f_pdata->cqspi;
916         int ret;
917
918         ret = cqspi_set_protocol(nor, 0);
919         if (ret)
920                 return ret;
921
922         ret = cqspi_write_setup(nor);
923         if (ret)
924                 return ret;
925
926         if (f_pdata->use_direct_mode) {
927                 memcpy_toio(cqspi->ahb_base + to, buf, len);
928                 ret = cqspi_wait_idle(cqspi);
929         } else {
930                 ret = cqspi_indirect_write_execute(nor, to, buf, len);
931         }
932         if (ret)
933                 return ret;
934
935         return len;
936 }
937
938 static void cqspi_rx_dma_callback(void *param)
939 {
940         struct cqspi_st *cqspi = param;
941
942         complete(&cqspi->rx_dma_complete);
943 }
944
945 static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
946                                      loff_t from, size_t len)
947 {
948         struct cqspi_flash_pdata *f_pdata = nor->priv;
949         struct cqspi_st *cqspi = f_pdata->cqspi;
950         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
951         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
952         int ret = 0;
953         struct dma_async_tx_descriptor *tx;
954         dma_cookie_t cookie;
955         dma_addr_t dma_dst;
956
957         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
958                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
959                 return 0;
960         }
961
962         dma_dst = dma_map_single(nor->dev, buf, len, DMA_DEV_TO_MEM);
963         if (dma_mapping_error(nor->dev, dma_dst)) {
964                 dev_err(nor->dev, "dma mapping failed\n");
965                 return -ENOMEM;
966         }
967         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
968                                        len, flags);
969         if (!tx) {
970                 dev_err(nor->dev, "device_prep_dma_memcpy error\n");
971                 ret = -EIO;
972                 goto err_unmap;
973         }
974
975         tx->callback = cqspi_rx_dma_callback;
976         tx->callback_param = cqspi;
977         cookie = tx->tx_submit(tx);
978         reinit_completion(&cqspi->rx_dma_complete);
979
980         ret = dma_submit_error(cookie);
981         if (ret) {
982                 dev_err(nor->dev, "dma_submit_error %d\n", cookie);
983                 ret = -EIO;
984                 goto err_unmap;
985         }
986
987         dma_async_issue_pending(cqspi->rx_chan);
988         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
989                                          msecs_to_jiffies(len))) {
990                 dmaengine_terminate_sync(cqspi->rx_chan);
991                 dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
992                 ret = -ETIMEDOUT;
993                 goto err_unmap;
994         }
995
996 err_unmap:
997         dma_unmap_single(nor->dev, dma_dst, len, DMA_DEV_TO_MEM);
998
999         return 0;
1000 }
1001
1002 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
1003                           size_t len, u_char *buf)
1004 {
1005         struct cqspi_flash_pdata *f_pdata = nor->priv;
1006         int ret;
1007
1008         ret = cqspi_set_protocol(nor, 1);
1009         if (ret)
1010                 return ret;
1011
1012         ret = cqspi_read_setup(nor);
1013         if (ret)
1014                 return ret;
1015
1016         if (f_pdata->use_direct_mode)
1017                 ret = cqspi_direct_read_execute(nor, buf, from, len);
1018         else
1019                 ret = cqspi_indirect_read_execute(nor, buf, from, len);
1020         if (ret)
1021                 return ret;
1022
1023         return len;
1024 }
1025
1026 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
1027 {
1028         int ret;
1029
1030         ret = cqspi_set_protocol(nor, 0);
1031         if (ret)
1032                 return ret;
1033
1034         /* Send write enable, then erase commands. */
1035         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
1036         if (ret)
1037                 return ret;
1038
1039         /* Set up command buffer. */
1040         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
1041         if (ret)
1042                 return ret;
1043
1044         return 0;
1045 }
1046
1047 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1048 {
1049         struct cqspi_flash_pdata *f_pdata = nor->priv;
1050         struct cqspi_st *cqspi = f_pdata->cqspi;
1051
1052         mutex_lock(&cqspi->bus_mutex);
1053
1054         return 0;
1055 }
1056
1057 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1058 {
1059         struct cqspi_flash_pdata *f_pdata = nor->priv;
1060         struct cqspi_st *cqspi = f_pdata->cqspi;
1061
1062         mutex_unlock(&cqspi->bus_mutex);
1063 }
1064
1065 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1066 {
1067         int ret;
1068
1069         ret = cqspi_set_protocol(nor, 0);
1070         if (!ret)
1071                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1072
1073         return ret;
1074 }
1075
1076 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1077 {
1078         int ret;
1079
1080         ret = cqspi_set_protocol(nor, 0);
1081         if (!ret)
1082                 ret = cqspi_command_write(nor, opcode, buf, len);
1083
1084         return ret;
1085 }
1086
1087 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1088                                     struct cqspi_flash_pdata *f_pdata,
1089                                     struct device_node *np)
1090 {
1091         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1092                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1093                 return -ENXIO;
1094         }
1095
1096         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1097                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1098                 return -ENXIO;
1099         }
1100
1101         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1102                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1103                 return -ENXIO;
1104         }
1105
1106         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1107                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1108                 return -ENXIO;
1109         }
1110
1111         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1112                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1113                 return -ENXIO;
1114         }
1115
1116         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1117                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1118                 return -ENXIO;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static int cqspi_of_get_pdata(struct platform_device *pdev)
1125 {
1126         struct device_node *np = pdev->dev.of_node;
1127         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1128
1129         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1130
1131         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1132                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1133                 return -ENXIO;
1134         }
1135
1136         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1137                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1138                 return -ENXIO;
1139         }
1140
1141         if (of_property_read_u32(np, "cdns,trigger-address",
1142                                  &cqspi->trigger_address)) {
1143                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1144                 return -ENXIO;
1145         }
1146
1147         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1148
1149         return 0;
1150 }
1151
1152 static void cqspi_controller_init(struct cqspi_st *cqspi)
1153 {
1154         u32 reg;
1155
1156         cqspi_controller_enable(cqspi, 0);
1157
1158         /* Configure the remap address register, no remap */
1159         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1160
1161         /* Disable all interrupts. */
1162         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1163
1164         /* Configure the SRAM split to 1:1 . */
1165         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1166
1167         /* Load indirect trigger address. */
1168         writel(cqspi->trigger_address,
1169                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1170
1171         /* Program read watermark -- 1/2 of the FIFO. */
1172         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1173                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1174         /* Program write watermark -- 1/8 of the FIFO. */
1175         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1176                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1177
1178         /* Enable Direct Access Controller */
1179         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1180         reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1181         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1182
1183         cqspi_controller_enable(cqspi, 1);
1184 }
1185
1186 static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1187 {
1188         dma_cap_mask_t mask;
1189
1190         dma_cap_zero(mask);
1191         dma_cap_set(DMA_MEMCPY, mask);
1192
1193         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1194         if (IS_ERR(cqspi->rx_chan)) {
1195                 dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
1196                 cqspi->rx_chan = NULL;
1197         }
1198         init_completion(&cqspi->rx_dma_complete);
1199 }
1200
1201 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1202 {
1203         const struct spi_nor_hwcaps hwcaps = {
1204                 .mask = SNOR_HWCAPS_READ |
1205                         SNOR_HWCAPS_READ_FAST |
1206                         SNOR_HWCAPS_READ_1_1_2 |
1207                         SNOR_HWCAPS_READ_1_1_4 |
1208                         SNOR_HWCAPS_PP,
1209         };
1210         struct platform_device *pdev = cqspi->pdev;
1211         struct device *dev = &pdev->dev;
1212         struct cqspi_flash_pdata *f_pdata;
1213         struct spi_nor *nor;
1214         struct mtd_info *mtd;
1215         unsigned int cs;
1216         int i, ret;
1217
1218         /* Get flash device data */
1219         for_each_available_child_of_node(dev->of_node, np) {
1220                 ret = of_property_read_u32(np, "reg", &cs);
1221                 if (ret) {
1222                         dev_err(dev, "Couldn't determine chip select.\n");
1223                         goto err;
1224                 }
1225
1226                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1227                         ret = -EINVAL;
1228                         dev_err(dev, "Chip select %d out of range.\n", cs);
1229                         goto err;
1230                 }
1231
1232                 f_pdata = &cqspi->f_pdata[cs];
1233                 f_pdata->cqspi = cqspi;
1234                 f_pdata->cs = cs;
1235
1236                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1237                 if (ret)
1238                         goto err;
1239
1240                 nor = &f_pdata->nor;
1241                 mtd = &nor->mtd;
1242
1243                 mtd->priv = nor;
1244
1245                 nor->dev = dev;
1246                 spi_nor_set_flash_node(nor, np);
1247                 nor->priv = f_pdata;
1248
1249                 nor->read_reg = cqspi_read_reg;
1250                 nor->write_reg = cqspi_write_reg;
1251                 nor->read = cqspi_read;
1252                 nor->write = cqspi_write;
1253                 nor->erase = cqspi_erase;
1254                 nor->prepare = cqspi_prep;
1255                 nor->unprepare = cqspi_unprep;
1256
1257                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1258                                            dev_name(dev), cs);
1259                 if (!mtd->name) {
1260                         ret = -ENOMEM;
1261                         goto err;
1262                 }
1263
1264                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1265                 if (ret)
1266                         goto err;
1267
1268                 ret = mtd_device_register(mtd, NULL, 0);
1269                 if (ret)
1270                         goto err;
1271
1272                 f_pdata->registered = true;
1273
1274                 if (mtd->size <= cqspi->ahb_size) {
1275                         f_pdata->use_direct_mode = true;
1276                         dev_dbg(nor->dev, "using direct mode for %s\n",
1277                                 mtd->name);
1278
1279                         if (!cqspi->rx_chan)
1280                                 cqspi_request_mmap_dma(cqspi);
1281                 }
1282         }
1283
1284         return 0;
1285
1286 err:
1287         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1288                 if (cqspi->f_pdata[i].registered)
1289                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1290         return ret;
1291 }
1292
1293 static int cqspi_probe(struct platform_device *pdev)
1294 {
1295         struct device_node *np = pdev->dev.of_node;
1296         struct device *dev = &pdev->dev;
1297         struct cqspi_st *cqspi;
1298         struct resource *res;
1299         struct resource *res_ahb;
1300         unsigned long data;
1301         int ret;
1302         int irq;
1303
1304         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1305         if (!cqspi)
1306                 return -ENOMEM;
1307
1308         mutex_init(&cqspi->bus_mutex);
1309         cqspi->pdev = pdev;
1310         platform_set_drvdata(pdev, cqspi);
1311
1312         /* Obtain configuration from OF. */
1313         ret = cqspi_of_get_pdata(pdev);
1314         if (ret) {
1315                 dev_err(dev, "Cannot get mandatory OF data.\n");
1316                 return -ENODEV;
1317         }
1318
1319         /* Obtain QSPI clock. */
1320         cqspi->clk = devm_clk_get(dev, NULL);
1321         if (IS_ERR(cqspi->clk)) {
1322                 dev_err(dev, "Cannot claim QSPI clock.\n");
1323                 return PTR_ERR(cqspi->clk);
1324         }
1325
1326         /* Obtain and remap controller address. */
1327         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1328         cqspi->iobase = devm_ioremap_resource(dev, res);
1329         if (IS_ERR(cqspi->iobase)) {
1330                 dev_err(dev, "Cannot remap controller address.\n");
1331                 return PTR_ERR(cqspi->iobase);
1332         }
1333
1334         /* Obtain and remap AHB address. */
1335         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1336         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1337         if (IS_ERR(cqspi->ahb_base)) {
1338                 dev_err(dev, "Cannot remap AHB address.\n");
1339                 return PTR_ERR(cqspi->ahb_base);
1340         }
1341         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1342         cqspi->ahb_size = resource_size(res_ahb);
1343
1344         init_completion(&cqspi->transfer_complete);
1345
1346         /* Obtain IRQ line. */
1347         irq = platform_get_irq(pdev, 0);
1348         if (irq < 0) {
1349                 dev_err(dev, "Cannot obtain IRQ.\n");
1350                 return -ENXIO;
1351         }
1352
1353         pm_runtime_enable(dev);
1354         ret = pm_runtime_get_sync(dev);
1355         if (ret < 0) {
1356                 pm_runtime_put_noidle(dev);
1357                 return ret;
1358         }
1359
1360         ret = clk_prepare_enable(cqspi->clk);
1361         if (ret) {
1362                 dev_err(dev, "Cannot enable QSPI clock.\n");
1363                 goto probe_clk_failed;
1364         }
1365
1366         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1367         data  = (unsigned long)of_device_get_match_data(dev);
1368         if (data & CQSPI_NEEDS_WR_DELAY)
1369                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1370                                                    cqspi->master_ref_clk_hz);
1371
1372         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1373                                pdev->name, cqspi);
1374         if (ret) {
1375                 dev_err(dev, "Cannot request IRQ.\n");
1376                 goto probe_irq_failed;
1377         }
1378
1379         cqspi_wait_idle(cqspi);
1380         cqspi_controller_init(cqspi);
1381         cqspi->current_cs = -1;
1382         cqspi->sclk = 0;
1383
1384         ret = cqspi_setup_flash(cqspi, np);
1385         if (ret) {
1386                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1387                 goto probe_setup_failed;
1388         }
1389
1390         return ret;
1391 probe_setup_failed:
1392         cqspi_controller_enable(cqspi, 0);
1393 probe_irq_failed:
1394         clk_disable_unprepare(cqspi->clk);
1395 probe_clk_failed:
1396         pm_runtime_put_sync(dev);
1397         pm_runtime_disable(dev);
1398         return ret;
1399 }
1400
1401 static int cqspi_remove(struct platform_device *pdev)
1402 {
1403         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1404         int i;
1405
1406         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1407                 if (cqspi->f_pdata[i].registered)
1408                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1409
1410         cqspi_controller_enable(cqspi, 0);
1411
1412         if (cqspi->rx_chan)
1413                 dma_release_channel(cqspi->rx_chan);
1414
1415         clk_disable_unprepare(cqspi->clk);
1416
1417         pm_runtime_put_sync(&pdev->dev);
1418         pm_runtime_disable(&pdev->dev);
1419
1420         return 0;
1421 }
1422
1423 #ifdef CONFIG_PM_SLEEP
1424 static int cqspi_suspend(struct device *dev)
1425 {
1426         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1427
1428         cqspi_controller_enable(cqspi, 0);
1429         return 0;
1430 }
1431
1432 static int cqspi_resume(struct device *dev)
1433 {
1434         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1435
1436         cqspi_controller_enable(cqspi, 1);
1437         return 0;
1438 }
1439
1440 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1441         .suspend = cqspi_suspend,
1442         .resume = cqspi_resume,
1443 };
1444
1445 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1446 #else
1447 #define CQSPI_DEV_PM_OPS        NULL
1448 #endif
1449
1450 static const struct of_device_id cqspi_dt_ids[] = {
1451         {
1452                 .compatible = "cdns,qspi-nor",
1453                 .data = (void *)0,
1454         },
1455         {
1456                 .compatible = "ti,k2g-qspi",
1457                 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1458         },
1459         { /* end of table */ }
1460 };
1461
1462 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1463
1464 static struct platform_driver cqspi_platform_driver = {
1465         .probe = cqspi_probe,
1466         .remove = cqspi_remove,
1467         .driver = {
1468                 .name = CQSPI_NAME,
1469                 .pm = CQSPI_DEV_PM_OPS,
1470                 .of_match_table = cqspi_dt_ids,
1471         },
1472 };
1473
1474 module_platform_driver(cqspi_platform_driver);
1475
1476 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1477 MODULE_LICENSE("GPL v2");
1478 MODULE_ALIAS("platform:" CQSPI_NAME);
1479 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1480 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");