tg3: Enable PHY reset in MTU change path for 5720
[muen/linux.git] / drivers / net / ethernet / broadcom / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2016 Broadcom Corporation.
8  * Copyright (C) 2016-2017 Broadcom Limited.
9  *
10  * Firmware is:
11  *      Derived from proprietary unpublished source code,
12  *      Copyright (C) 2000-2016 Broadcom Corporation.
13  *      Copyright (C) 2016-2017 Broadcom Ltd.
14  *
15  *      Permission is hereby granted for the distribution of this firmware
16  *      data in hexadecimal or equivalent format, provided this copyright
17  *      notice is accompanying it.
18  */
19
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/stringify.h>
24 #include <linux/kernel.h>
25 #include <linux/sched/signal.h>
26 #include <linux/types.h>
27 #include <linux/compiler.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/in.h>
31 #include <linux/interrupt.h>
32 #include <linux/ioport.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/mdio.h>
39 #include <linux/mii.h>
40 #include <linux/phy.h>
41 #include <linux/brcmphy.h>
42 #include <linux/if.h>
43 #include <linux/if_vlan.h>
44 #include <linux/ip.h>
45 #include <linux/tcp.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/firmware.h>
50 #include <linux/ssb/ssb_driver_gige.h>
51 #include <linux/hwmon.h>
52 #include <linux/hwmon-sysfs.h>
53
54 #include <net/checksum.h>
55 #include <net/ip.h>
56
57 #include <linux/io.h>
58 #include <asm/byteorder.h>
59 #include <linux/uaccess.h>
60
61 #include <uapi/linux/net_tstamp.h>
62 #include <linux/ptp_clock_kernel.h>
63
64 #ifdef CONFIG_SPARC
65 #include <asm/idprom.h>
66 #include <asm/prom.h>
67 #endif
68
69 #define BAR_0   0
70 #define BAR_2   2
71
72 #include "tg3.h"
73
74 /* Functions & macros to verify TG3_FLAGS types */
75
76 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
77 {
78         return test_bit(flag, bits);
79 }
80
81 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
82 {
83         set_bit(flag, bits);
84 }
85
86 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
87 {
88         clear_bit(flag, bits);
89 }
90
91 #define tg3_flag(tp, flag)                              \
92         _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
93 #define tg3_flag_set(tp, flag)                          \
94         _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define tg3_flag_clear(tp, flag)                        \
96         _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
97
98 #define DRV_MODULE_NAME         "tg3"
99 #define TG3_MAJ_NUM                     3
100 #define TG3_MIN_NUM                     137
101 #define DRV_MODULE_VERSION      \
102         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
103 #define DRV_MODULE_RELDATE      "May 11, 2014"
104
105 #define RESET_KIND_SHUTDOWN     0
106 #define RESET_KIND_INIT         1
107 #define RESET_KIND_SUSPEND      2
108
109 #define TG3_DEF_RX_MODE         0
110 #define TG3_DEF_TX_MODE         0
111 #define TG3_DEF_MSG_ENABLE        \
112         (NETIF_MSG_DRV          | \
113          NETIF_MSG_PROBE        | \
114          NETIF_MSG_LINK         | \
115          NETIF_MSG_TIMER        | \
116          NETIF_MSG_IFDOWN       | \
117          NETIF_MSG_IFUP         | \
118          NETIF_MSG_RX_ERR       | \
119          NETIF_MSG_TX_ERR)
120
121 #define TG3_GRC_LCLCTL_PWRSW_DELAY      100
122
123 /* length of time before we decide the hardware is borked,
124  * and dev->tx_timeout() should be called to fix the problem
125  */
126
127 #define TG3_TX_TIMEOUT                  (5 * HZ)
128
129 /* hardware minimum and maximum for a single frame's data payload */
130 #define TG3_MIN_MTU                     ETH_ZLEN
131 #define TG3_MAX_MTU(tp) \
132         (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
133
134 /* These numbers seem to be hard coded in the NIC firmware somehow.
135  * You can't change the ring sizes, but you can change where you place
136  * them in the NIC onboard memory.
137  */
138 #define TG3_RX_STD_RING_SIZE(tp) \
139         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
140          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
141 #define TG3_DEF_RX_RING_PENDING         200
142 #define TG3_RX_JMB_RING_SIZE(tp) \
143         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
144          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
145 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
146
147 /* Do not place this n-ring entries value into the tp struct itself,
148  * we really want to expose these constants to GCC so that modulo et
149  * al.  operations are done with shifts and masks instead of with
150  * hw multiply/modulo instructions.  Another solution would be to
151  * replace things like '% foo' with '& (foo - 1)'.
152  */
153
154 #define TG3_TX_RING_SIZE                512
155 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
156
157 #define TG3_RX_STD_RING_BYTES(tp) \
158         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
159 #define TG3_RX_JMB_RING_BYTES(tp) \
160         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
161 #define TG3_RX_RCB_RING_BYTES(tp) \
162         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
163 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
164                                  TG3_TX_RING_SIZE)
165 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
166
167 #define TG3_DMA_BYTE_ENAB               64
168
169 #define TG3_RX_STD_DMA_SZ               1536
170 #define TG3_RX_JMB_DMA_SZ               9046
171
172 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
173
174 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
175 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
176
177 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
178         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
179
180 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
181         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
182
183 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
184  * that are at least dword aligned when used in PCIX mode.  The driver
185  * works around this bug by double copying the packet.  This workaround
186  * is built into the normal double copy length check for efficiency.
187  *
188  * However, the double copy is only necessary on those architectures
189  * where unaligned memory accesses are inefficient.  For those architectures
190  * where unaligned memory accesses incur little penalty, we can reintegrate
191  * the 5701 in the normal rx path.  Doing so saves a device structure
192  * dereference by hardcoding the double copy threshold in place.
193  */
194 #define TG3_RX_COPY_THRESHOLD           256
195 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
196         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
197 #else
198         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
199 #endif
200
201 #if (NET_IP_ALIGN != 0)
202 #define TG3_RX_OFFSET(tp)       ((tp)->rx_offset)
203 #else
204 #define TG3_RX_OFFSET(tp)       (NET_SKB_PAD)
205 #endif
206
207 /* minimum number of free TX descriptors required to wake up TX process */
208 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
209 #define TG3_TX_BD_DMA_MAX_2K            2048
210 #define TG3_TX_BD_DMA_MAX_4K            4096
211
212 #define TG3_RAW_IP_ALIGN 2
213
214 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
215 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
216
217 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
218 #define TG3_FW_UPDATE_FREQ_SEC          (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
219
220 #define FIRMWARE_TG3            "tigon/tg3.bin"
221 #define FIRMWARE_TG357766       "tigon/tg357766.bin"
222 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
223 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
224
225 static char version[] =
226         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
227
228 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
229 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
230 MODULE_LICENSE("GPL");
231 MODULE_VERSION(DRV_MODULE_VERSION);
232 MODULE_FIRMWARE(FIRMWARE_TG3);
233 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
234 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
235
236 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
237 module_param(tg3_debug, int, 0);
238 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
239
240 #define TG3_DRV_DATA_FLAG_10_100_ONLY   0x0001
241 #define TG3_DRV_DATA_FLAG_5705_10_100   0x0002
242
243 static const struct pci_device_id tg3_pci_tbl[] = {
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
263          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264                         TG3_DRV_DATA_FLAG_5705_10_100},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
266          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
267                         TG3_DRV_DATA_FLAG_5705_10_100},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
270          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
271                         TG3_DRV_DATA_FLAG_5705_10_100},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
278          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
279         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
280         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
281         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
282         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
283         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
284          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
285         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
286         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
287         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
288         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
289         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
290         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
291         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
292         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
293                         PCI_VENDOR_ID_LENOVO,
294                         TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
295          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
297         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
298          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
299         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
300         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
301         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
302         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
303         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
304         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
305         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
306         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
307         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
308         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
309         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
310         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
311         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
312         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
313         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
314         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
315         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
316         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
317         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318                         PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
319          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
321                         PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
322          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
323         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
324         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
325         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
326          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
327         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
328         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
329         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
330         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
331         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
332         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
333         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
334         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
335         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
336          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
337         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
338          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
339         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
340         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
341         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
342         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
343         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
344         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
345         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
346         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
347         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
348         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
349         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
350         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
351         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
352         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
353         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
354         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
355         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
356         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
357         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
358         {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359         {}
360 };
361
362 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
363
364 static const struct {
365         const char string[ETH_GSTRING_LEN];
366 } ethtool_stats_keys[] = {
367         { "rx_octets" },
368         { "rx_fragments" },
369         { "rx_ucast_packets" },
370         { "rx_mcast_packets" },
371         { "rx_bcast_packets" },
372         { "rx_fcs_errors" },
373         { "rx_align_errors" },
374         { "rx_xon_pause_rcvd" },
375         { "rx_xoff_pause_rcvd" },
376         { "rx_mac_ctrl_rcvd" },
377         { "rx_xoff_entered" },
378         { "rx_frame_too_long_errors" },
379         { "rx_jabbers" },
380         { "rx_undersize_packets" },
381         { "rx_in_length_errors" },
382         { "rx_out_length_errors" },
383         { "rx_64_or_less_octet_packets" },
384         { "rx_65_to_127_octet_packets" },
385         { "rx_128_to_255_octet_packets" },
386         { "rx_256_to_511_octet_packets" },
387         { "rx_512_to_1023_octet_packets" },
388         { "rx_1024_to_1522_octet_packets" },
389         { "rx_1523_to_2047_octet_packets" },
390         { "rx_2048_to_4095_octet_packets" },
391         { "rx_4096_to_8191_octet_packets" },
392         { "rx_8192_to_9022_octet_packets" },
393
394         { "tx_octets" },
395         { "tx_collisions" },
396
397         { "tx_xon_sent" },
398         { "tx_xoff_sent" },
399         { "tx_flow_control" },
400         { "tx_mac_errors" },
401         { "tx_single_collisions" },
402         { "tx_mult_collisions" },
403         { "tx_deferred" },
404         { "tx_excessive_collisions" },
405         { "tx_late_collisions" },
406         { "tx_collide_2times" },
407         { "tx_collide_3times" },
408         { "tx_collide_4times" },
409         { "tx_collide_5times" },
410         { "tx_collide_6times" },
411         { "tx_collide_7times" },
412         { "tx_collide_8times" },
413         { "tx_collide_9times" },
414         { "tx_collide_10times" },
415         { "tx_collide_11times" },
416         { "tx_collide_12times" },
417         { "tx_collide_13times" },
418         { "tx_collide_14times" },
419         { "tx_collide_15times" },
420         { "tx_ucast_packets" },
421         { "tx_mcast_packets" },
422         { "tx_bcast_packets" },
423         { "tx_carrier_sense_errors" },
424         { "tx_discards" },
425         { "tx_errors" },
426
427         { "dma_writeq_full" },
428         { "dma_write_prioq_full" },
429         { "rxbds_empty" },
430         { "rx_discards" },
431         { "rx_errors" },
432         { "rx_threshold_hit" },
433
434         { "dma_readq_full" },
435         { "dma_read_prioq_full" },
436         { "tx_comp_queue_full" },
437
438         { "ring_set_send_prod_index" },
439         { "ring_status_update" },
440         { "nic_irqs" },
441         { "nic_avoided_irqs" },
442         { "nic_tx_threshold_hit" },
443
444         { "mbuf_lwm_thresh_hit" },
445 };
446
447 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
448 #define TG3_NVRAM_TEST          0
449 #define TG3_LINK_TEST           1
450 #define TG3_REGISTER_TEST       2
451 #define TG3_MEMORY_TEST         3
452 #define TG3_MAC_LOOPB_TEST      4
453 #define TG3_PHY_LOOPB_TEST      5
454 #define TG3_EXT_LOOPB_TEST      6
455 #define TG3_INTERRUPT_TEST      7
456
457
458 static const struct {
459         const char string[ETH_GSTRING_LEN];
460 } ethtool_test_keys[] = {
461         [TG3_NVRAM_TEST]        = { "nvram test        (online) " },
462         [TG3_LINK_TEST]         = { "link test         (online) " },
463         [TG3_REGISTER_TEST]     = { "register test     (offline)" },
464         [TG3_MEMORY_TEST]       = { "memory test       (offline)" },
465         [TG3_MAC_LOOPB_TEST]    = { "mac loopback test (offline)" },
466         [TG3_PHY_LOOPB_TEST]    = { "phy loopback test (offline)" },
467         [TG3_EXT_LOOPB_TEST]    = { "ext loopback test (offline)" },
468         [TG3_INTERRUPT_TEST]    = { "interrupt test    (offline)" },
469 };
470
471 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
472
473
474 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
475 {
476         writel(val, tp->regs + off);
477 }
478
479 static u32 tg3_read32(struct tg3 *tp, u32 off)
480 {
481         return readl(tp->regs + off);
482 }
483
484 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
485 {
486         writel(val, tp->aperegs + off);
487 }
488
489 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
490 {
491         return readl(tp->aperegs + off);
492 }
493
494 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 {
496         unsigned long flags;
497
498         spin_lock_irqsave(&tp->indirect_lock, flags);
499         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
500         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
501         spin_unlock_irqrestore(&tp->indirect_lock, flags);
502 }
503
504 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
505 {
506         writel(val, tp->regs + off);
507         readl(tp->regs + off);
508 }
509
510 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
511 {
512         unsigned long flags;
513         u32 val;
514
515         spin_lock_irqsave(&tp->indirect_lock, flags);
516         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
517         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
519         return val;
520 }
521
522 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 {
524         unsigned long flags;
525
526         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
527                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
528                                        TG3_64BIT_REG_LOW, val);
529                 return;
530         }
531         if (off == TG3_RX_STD_PROD_IDX_REG) {
532                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
533                                        TG3_64BIT_REG_LOW, val);
534                 return;
535         }
536
537         spin_lock_irqsave(&tp->indirect_lock, flags);
538         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
539         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
540         spin_unlock_irqrestore(&tp->indirect_lock, flags);
541
542         /* In indirect mode when disabling interrupts, we also need
543          * to clear the interrupt bit in the GRC local ctrl register.
544          */
545         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
546             (val == 0x1)) {
547                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
548                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549         }
550 }
551
552 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
553 {
554         unsigned long flags;
555         u32 val;
556
557         spin_lock_irqsave(&tp->indirect_lock, flags);
558         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
559         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
560         spin_unlock_irqrestore(&tp->indirect_lock, flags);
561         return val;
562 }
563
564 /* usec_wait specifies the wait time in usec when writing to certain registers
565  * where it is unsafe to read back the register without some delay.
566  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
567  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
568  */
569 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
570 {
571         if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
572                 /* Non-posted methods */
573                 tp->write32(tp, off, val);
574         else {
575                 /* Posted method */
576                 tg3_write32(tp, off, val);
577                 if (usec_wait)
578                         udelay(usec_wait);
579                 tp->read32(tp, off);
580         }
581         /* Wait again after the read for the posted method to guarantee that
582          * the wait time is met.
583          */
584         if (usec_wait)
585                 udelay(usec_wait);
586 }
587
588 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
589 {
590         tp->write32_mbox(tp, off, val);
591         if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
592             (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
593              !tg3_flag(tp, ICH_WORKAROUND)))
594                 tp->read32_mbox(tp, off);
595 }
596
597 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
598 {
599         void __iomem *mbox = tp->regs + off;
600         writel(val, mbox);
601         if (tg3_flag(tp, TXD_MBOX_HWBUG))
602                 writel(val, mbox);
603         if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
604             tg3_flag(tp, FLUSH_POSTED_WRITES))
605                 readl(mbox);
606 }
607
608 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
609 {
610         return readl(tp->regs + off + GRCMBOX_BASE);
611 }
612
613 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
614 {
615         writel(val, tp->regs + off + GRCMBOX_BASE);
616 }
617
618 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
619 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
620 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
621 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
622 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
623
624 #define tw32(reg, val)                  tp->write32(tp, reg, val)
625 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
626 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
627 #define tr32(reg)                       tp->read32(tp, reg)
628
629 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 {
631         unsigned long flags;
632
633         if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
634             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
635                 return;
636
637         spin_lock_irqsave(&tp->indirect_lock, flags);
638         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
639                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
640                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
641
642                 /* Always leave this as zero. */
643                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
644         } else {
645                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
646                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
647
648                 /* Always leave this as zero. */
649                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
650         }
651         spin_unlock_irqrestore(&tp->indirect_lock, flags);
652 }
653
654 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 {
656         unsigned long flags;
657
658         if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
659             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
660                 *val = 0;
661                 return;
662         }
663
664         spin_lock_irqsave(&tp->indirect_lock, flags);
665         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
666                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
667                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
668
669                 /* Always leave this as zero. */
670                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
671         } else {
672                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
673                 *val = tr32(TG3PCI_MEM_WIN_DATA);
674
675                 /* Always leave this as zero. */
676                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
677         }
678         spin_unlock_irqrestore(&tp->indirect_lock, flags);
679 }
680
681 static void tg3_ape_lock_init(struct tg3 *tp)
682 {
683         int i;
684         u32 regbase, bit;
685
686         if (tg3_asic_rev(tp) == ASIC_REV_5761)
687                 regbase = TG3_APE_LOCK_GRANT;
688         else
689                 regbase = TG3_APE_PER_LOCK_GRANT;
690
691         /* Make sure the driver hasn't any stale locks. */
692         for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
693                 switch (i) {
694                 case TG3_APE_LOCK_PHY0:
695                 case TG3_APE_LOCK_PHY1:
696                 case TG3_APE_LOCK_PHY2:
697                 case TG3_APE_LOCK_PHY3:
698                         bit = APE_LOCK_GRANT_DRIVER;
699                         break;
700                 default:
701                         if (!tp->pci_fn)
702                                 bit = APE_LOCK_GRANT_DRIVER;
703                         else
704                                 bit = 1 << tp->pci_fn;
705                 }
706                 tg3_ape_write32(tp, regbase + 4 * i, bit);
707         }
708
709 }
710
711 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 {
713         int i, off;
714         int ret = 0;
715         u32 status, req, gnt, bit;
716
717         if (!tg3_flag(tp, ENABLE_APE))
718                 return 0;
719
720         switch (locknum) {
721         case TG3_APE_LOCK_GPIO:
722                 if (tg3_asic_rev(tp) == ASIC_REV_5761)
723                         return 0;
724         case TG3_APE_LOCK_GRC:
725         case TG3_APE_LOCK_MEM:
726                 if (!tp->pci_fn)
727                         bit = APE_LOCK_REQ_DRIVER;
728                 else
729                         bit = 1 << tp->pci_fn;
730                 break;
731         case TG3_APE_LOCK_PHY0:
732         case TG3_APE_LOCK_PHY1:
733         case TG3_APE_LOCK_PHY2:
734         case TG3_APE_LOCK_PHY3:
735                 bit = APE_LOCK_REQ_DRIVER;
736                 break;
737         default:
738                 return -EINVAL;
739         }
740
741         if (tg3_asic_rev(tp) == ASIC_REV_5761) {
742                 req = TG3_APE_LOCK_REQ;
743                 gnt = TG3_APE_LOCK_GRANT;
744         } else {
745                 req = TG3_APE_PER_LOCK_REQ;
746                 gnt = TG3_APE_PER_LOCK_GRANT;
747         }
748
749         off = 4 * locknum;
750
751         tg3_ape_write32(tp, req + off, bit);
752
753         /* Wait for up to 1 millisecond to acquire lock. */
754         for (i = 0; i < 100; i++) {
755                 status = tg3_ape_read32(tp, gnt + off);
756                 if (status == bit)
757                         break;
758                 if (pci_channel_offline(tp->pdev))
759                         break;
760
761                 udelay(10);
762         }
763
764         if (status != bit) {
765                 /* Revoke the lock request. */
766                 tg3_ape_write32(tp, gnt + off, bit);
767                 ret = -EBUSY;
768         }
769
770         return ret;
771 }
772
773 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 {
775         u32 gnt, bit;
776
777         if (!tg3_flag(tp, ENABLE_APE))
778                 return;
779
780         switch (locknum) {
781         case TG3_APE_LOCK_GPIO:
782                 if (tg3_asic_rev(tp) == ASIC_REV_5761)
783                         return;
784         case TG3_APE_LOCK_GRC:
785         case TG3_APE_LOCK_MEM:
786                 if (!tp->pci_fn)
787                         bit = APE_LOCK_GRANT_DRIVER;
788                 else
789                         bit = 1 << tp->pci_fn;
790                 break;
791         case TG3_APE_LOCK_PHY0:
792         case TG3_APE_LOCK_PHY1:
793         case TG3_APE_LOCK_PHY2:
794         case TG3_APE_LOCK_PHY3:
795                 bit = APE_LOCK_GRANT_DRIVER;
796                 break;
797         default:
798                 return;
799         }
800
801         if (tg3_asic_rev(tp) == ASIC_REV_5761)
802                 gnt = TG3_APE_LOCK_GRANT;
803         else
804                 gnt = TG3_APE_PER_LOCK_GRANT;
805
806         tg3_ape_write32(tp, gnt + 4 * locknum, bit);
807 }
808
809 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
810 {
811         u32 apedata;
812
813         while (timeout_us) {
814                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
815                         return -EBUSY;
816
817                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
818                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
819                         break;
820
821                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
822
823                 udelay(10);
824                 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
825         }
826
827         return timeout_us ? 0 : -EBUSY;
828 }
829
830 #ifdef CONFIG_TIGON3_HWMON
831 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
832 {
833         u32 i, apedata;
834
835         for (i = 0; i < timeout_us / 10; i++) {
836                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
837
838                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
839                         break;
840
841                 udelay(10);
842         }
843
844         return i == timeout_us / 10;
845 }
846
847 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
848                                    u32 len)
849 {
850         int err;
851         u32 i, bufoff, msgoff, maxlen, apedata;
852
853         if (!tg3_flag(tp, APE_HAS_NCSI))
854                 return 0;
855
856         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
857         if (apedata != APE_SEG_SIG_MAGIC)
858                 return -ENODEV;
859
860         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
861         if (!(apedata & APE_FW_STATUS_READY))
862                 return -EAGAIN;
863
864         bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
865                  TG3_APE_SHMEM_BASE;
866         msgoff = bufoff + 2 * sizeof(u32);
867         maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868
869         while (len) {
870                 u32 length;
871
872                 /* Cap xfer sizes to scratchpad limits. */
873                 length = (len > maxlen) ? maxlen : len;
874                 len -= length;
875
876                 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
877                 if (!(apedata & APE_FW_STATUS_READY))
878                         return -EAGAIN;
879
880                 /* Wait for up to 1 msec for APE to service previous event. */
881                 err = tg3_ape_event_lock(tp, 1000);
882                 if (err)
883                         return err;
884
885                 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
886                           APE_EVENT_STATUS_SCRTCHPD_READ |
887                           APE_EVENT_STATUS_EVENT_PENDING;
888                 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
889
890                 tg3_ape_write32(tp, bufoff, base_off);
891                 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
892
893                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
894                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
895
896                 base_off += length;
897
898                 if (tg3_ape_wait_for_event(tp, 30000))
899                         return -EAGAIN;
900
901                 for (i = 0; length; i += 4, length -= 4) {
902                         u32 val = tg3_ape_read32(tp, msgoff + i);
903                         memcpy(data, &val, sizeof(u32));
904                         data++;
905                 }
906         }
907
908         return 0;
909 }
910 #endif
911
912 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
913 {
914         int err;
915         u32 apedata;
916
917         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
918         if (apedata != APE_SEG_SIG_MAGIC)
919                 return -EAGAIN;
920
921         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
922         if (!(apedata & APE_FW_STATUS_READY))
923                 return -EAGAIN;
924
925         /* Wait for up to 1 millisecond for APE to service previous event. */
926         err = tg3_ape_event_lock(tp, 1000);
927         if (err)
928                 return err;
929
930         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
931                         event | APE_EVENT_STATUS_EVENT_PENDING);
932
933         tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
934         tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
935
936         return 0;
937 }
938
939 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
940 {
941         u32 event;
942         u32 apedata;
943
944         if (!tg3_flag(tp, ENABLE_APE))
945                 return;
946
947         switch (kind) {
948         case RESET_KIND_INIT:
949                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
950                                 APE_HOST_SEG_SIG_MAGIC);
951                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
952                                 APE_HOST_SEG_LEN_MAGIC);
953                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
954                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
955                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
956                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
957                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
958                                 APE_HOST_BEHAV_NO_PHYLOCK);
959                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
960                                     TG3_APE_HOST_DRVR_STATE_START);
961
962                 event = APE_EVENT_STATUS_STATE_START;
963                 break;
964         case RESET_KIND_SHUTDOWN:
965                 /* With the interface we are currently using,
966                  * APE does not track driver state.  Wiping
967                  * out the HOST SEGMENT SIGNATURE forces
968                  * the APE to assume OS absent status.
969                  */
970                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
971
972                 if (device_may_wakeup(&tp->pdev->dev) &&
973                     tg3_flag(tp, WOL_ENABLE)) {
974                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
975                                             TG3_APE_HOST_WOL_SPEED_AUTO);
976                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
977                 } else
978                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
979
980                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
981
982                 event = APE_EVENT_STATUS_STATE_UNLOAD;
983                 break;
984         default:
985                 return;
986         }
987
988         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
989
990         tg3_ape_send_event(tp, event);
991 }
992
993 static void tg3_disable_ints(struct tg3 *tp)
994 {
995         int i;
996
997         tw32(TG3PCI_MISC_HOST_CTRL,
998              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
999         for (i = 0; i < tp->irq_max; i++)
1000                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1001 }
1002
1003 static void tg3_enable_ints(struct tg3 *tp)
1004 {
1005         int i;
1006
1007         tp->irq_sync = 0;
1008         wmb();
1009
1010         tw32(TG3PCI_MISC_HOST_CTRL,
1011              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1012
1013         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1014         for (i = 0; i < tp->irq_cnt; i++) {
1015                 struct tg3_napi *tnapi = &tp->napi[i];
1016
1017                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1018                 if (tg3_flag(tp, 1SHOT_MSI))
1019                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1020
1021                 tp->coal_now |= tnapi->coal_now;
1022         }
1023
1024         /* Force an initial interrupt */
1025         if (!tg3_flag(tp, TAGGED_STATUS) &&
1026             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1027                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1028         else
1029                 tw32(HOSTCC_MODE, tp->coal_now);
1030
1031         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1032 }
1033
1034 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1035 {
1036         struct tg3 *tp = tnapi->tp;
1037         struct tg3_hw_status *sblk = tnapi->hw_status;
1038         unsigned int work_exists = 0;
1039
1040         /* check for phy events */
1041         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1042                 if (sblk->status & SD_STATUS_LINK_CHG)
1043                         work_exists = 1;
1044         }
1045
1046         /* check for TX work to do */
1047         if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1048                 work_exists = 1;
1049
1050         /* check for RX work to do */
1051         if (tnapi->rx_rcb_prod_idx &&
1052             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1053                 work_exists = 1;
1054
1055         return work_exists;
1056 }
1057
1058 /* tg3_int_reenable
1059  *  similar to tg3_enable_ints, but it accurately determines whether there
1060  *  is new work pending and can return without flushing the PIO write
1061  *  which reenables interrupts
1062  */
1063 static void tg3_int_reenable(struct tg3_napi *tnapi)
1064 {
1065         struct tg3 *tp = tnapi->tp;
1066
1067         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1068         mmiowb();
1069
1070         /* When doing tagged status, this work check is unnecessary.
1071          * The last_tag we write above tells the chip which piece of
1072          * work we've completed.
1073          */
1074         if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1075                 tw32(HOSTCC_MODE, tp->coalesce_mode |
1076                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
1077 }
1078
1079 static void tg3_switch_clocks(struct tg3 *tp)
1080 {
1081         u32 clock_ctrl;
1082         u32 orig_clock_ctrl;
1083
1084         if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1085                 return;
1086
1087         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1088
1089         orig_clock_ctrl = clock_ctrl;
1090         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1091                        CLOCK_CTRL_CLKRUN_OENABLE |
1092                        0x1f);
1093         tp->pci_clock_ctrl = clock_ctrl;
1094
1095         if (tg3_flag(tp, 5705_PLUS)) {
1096                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1097                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1099                 }
1100         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1101                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1102                             clock_ctrl |
1103                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1104                             40);
1105                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1106                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
1107                             40);
1108         }
1109         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1110 }
1111
1112 #define PHY_BUSY_LOOPS  5000
1113
1114 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1115                          u32 *val)
1116 {
1117         u32 frame_val;
1118         unsigned int loops;
1119         int ret;
1120
1121         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1122                 tw32_f(MAC_MI_MODE,
1123                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1124                 udelay(80);
1125         }
1126
1127         tg3_ape_lock(tp, tp->phy_ape_lock);
1128
1129         *val = 0x0;
1130
1131         frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1132                       MI_COM_PHY_ADDR_MASK);
1133         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1134                       MI_COM_REG_ADDR_MASK);
1135         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1136
1137         tw32_f(MAC_MI_COM, frame_val);
1138
1139         loops = PHY_BUSY_LOOPS;
1140         while (loops != 0) {
1141                 udelay(10);
1142                 frame_val = tr32(MAC_MI_COM);
1143
1144                 if ((frame_val & MI_COM_BUSY) == 0) {
1145                         udelay(5);
1146                         frame_val = tr32(MAC_MI_COM);
1147                         break;
1148                 }
1149                 loops -= 1;
1150         }
1151
1152         ret = -EBUSY;
1153         if (loops != 0) {
1154                 *val = frame_val & MI_COM_DATA_MASK;
1155                 ret = 0;
1156         }
1157
1158         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1159                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1160                 udelay(80);
1161         }
1162
1163         tg3_ape_unlock(tp, tp->phy_ape_lock);
1164
1165         return ret;
1166 }
1167
1168 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1169 {
1170         return __tg3_readphy(tp, tp->phy_addr, reg, val);
1171 }
1172
1173 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1174                           u32 val)
1175 {
1176         u32 frame_val;
1177         unsigned int loops;
1178         int ret;
1179
1180         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1181             (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1182                 return 0;
1183
1184         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1185                 tw32_f(MAC_MI_MODE,
1186                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1187                 udelay(80);
1188         }
1189
1190         tg3_ape_lock(tp, tp->phy_ape_lock);
1191
1192         frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1193                       MI_COM_PHY_ADDR_MASK);
1194         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1195                       MI_COM_REG_ADDR_MASK);
1196         frame_val |= (val & MI_COM_DATA_MASK);
1197         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1198
1199         tw32_f(MAC_MI_COM, frame_val);
1200
1201         loops = PHY_BUSY_LOOPS;
1202         while (loops != 0) {
1203                 udelay(10);
1204                 frame_val = tr32(MAC_MI_COM);
1205                 if ((frame_val & MI_COM_BUSY) == 0) {
1206                         udelay(5);
1207                         frame_val = tr32(MAC_MI_COM);
1208                         break;
1209                 }
1210                 loops -= 1;
1211         }
1212
1213         ret = -EBUSY;
1214         if (loops != 0)
1215                 ret = 0;
1216
1217         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1218                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1219                 udelay(80);
1220         }
1221
1222         tg3_ape_unlock(tp, tp->phy_ape_lock);
1223
1224         return ret;
1225 }
1226
1227 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1228 {
1229         return __tg3_writephy(tp, tp->phy_addr, reg, val);
1230 }
1231
1232 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1233 {
1234         int err;
1235
1236         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1237         if (err)
1238                 goto done;
1239
1240         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1241         if (err)
1242                 goto done;
1243
1244         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1245                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1246         if (err)
1247                 goto done;
1248
1249         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250
1251 done:
1252         return err;
1253 }
1254
1255 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1256 {
1257         int err;
1258
1259         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1260         if (err)
1261                 goto done;
1262
1263         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1264         if (err)
1265                 goto done;
1266
1267         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1268                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1269         if (err)
1270                 goto done;
1271
1272         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273
1274 done:
1275         return err;
1276 }
1277
1278 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1279 {
1280         int err;
1281
1282         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1283         if (!err)
1284                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1285
1286         return err;
1287 }
1288
1289 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1290 {
1291         int err;
1292
1293         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1294         if (!err)
1295                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1296
1297         return err;
1298 }
1299
1300 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1301 {
1302         int err;
1303
1304         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1305                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1306                            MII_TG3_AUXCTL_SHDWSEL_MISC);
1307         if (!err)
1308                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1309
1310         return err;
1311 }
1312
1313 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1314 {
1315         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1316                 set |= MII_TG3_AUXCTL_MISC_WREN;
1317
1318         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1319 }
1320
1321 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1322 {
1323         u32 val;
1324         int err;
1325
1326         err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327
1328         if (err)
1329                 return err;
1330
1331         if (enable)
1332                 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1333         else
1334                 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1335
1336         err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1337                                    val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1338
1339         return err;
1340 }
1341
1342 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1343 {
1344         return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1345                             reg | val | MII_TG3_MISC_SHDW_WREN);
1346 }
1347
1348 static int tg3_bmcr_reset(struct tg3 *tp)
1349 {
1350         u32 phy_control;
1351         int limit, err;
1352
1353         /* OK, reset it, and poll the BMCR_RESET bit until it
1354          * clears or we time out.
1355          */
1356         phy_control = BMCR_RESET;
1357         err = tg3_writephy(tp, MII_BMCR, phy_control);
1358         if (err != 0)
1359                 return -EBUSY;
1360
1361         limit = 5000;
1362         while (limit--) {
1363                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1364                 if (err != 0)
1365                         return -EBUSY;
1366
1367                 if ((phy_control & BMCR_RESET) == 0) {
1368                         udelay(40);
1369                         break;
1370                 }
1371                 udelay(10);
1372         }
1373         if (limit < 0)
1374                 return -EBUSY;
1375
1376         return 0;
1377 }
1378
1379 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1380 {
1381         struct tg3 *tp = bp->priv;
1382         u32 val;
1383
1384         spin_lock_bh(&tp->lock);
1385
1386         if (__tg3_readphy(tp, mii_id, reg, &val))
1387                 val = -EIO;
1388
1389         spin_unlock_bh(&tp->lock);
1390
1391         return val;
1392 }
1393
1394 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1395 {
1396         struct tg3 *tp = bp->priv;
1397         u32 ret = 0;
1398
1399         spin_lock_bh(&tp->lock);
1400
1401         if (__tg3_writephy(tp, mii_id, reg, val))
1402                 ret = -EIO;
1403
1404         spin_unlock_bh(&tp->lock);
1405
1406         return ret;
1407 }
1408
1409 static void tg3_mdio_config_5785(struct tg3 *tp)
1410 {
1411         u32 val;
1412         struct phy_device *phydev;
1413
1414         phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1415         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1416         case PHY_ID_BCM50610:
1417         case PHY_ID_BCM50610M:
1418                 val = MAC_PHYCFG2_50610_LED_MODES;
1419                 break;
1420         case PHY_ID_BCMAC131:
1421                 val = MAC_PHYCFG2_AC131_LED_MODES;
1422                 break;
1423         case PHY_ID_RTL8211C:
1424                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1425                 break;
1426         case PHY_ID_RTL8201E:
1427                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428                 break;
1429         default:
1430                 return;
1431         }
1432
1433         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1434                 tw32(MAC_PHYCFG2, val);
1435
1436                 val = tr32(MAC_PHYCFG1);
1437                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1438                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1439                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1440                 tw32(MAC_PHYCFG1, val);
1441
1442                 return;
1443         }
1444
1445         if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1446                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1447                        MAC_PHYCFG2_FMODE_MASK_MASK |
1448                        MAC_PHYCFG2_GMODE_MASK_MASK |
1449                        MAC_PHYCFG2_ACT_MASK_MASK   |
1450                        MAC_PHYCFG2_QUAL_MASK_MASK |
1451                        MAC_PHYCFG2_INBAND_ENABLE;
1452
1453         tw32(MAC_PHYCFG2, val);
1454
1455         val = tr32(MAC_PHYCFG1);
1456         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1457                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1458         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1459                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1460                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1461                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1462                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1463         }
1464         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1465                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1466         tw32(MAC_PHYCFG1, val);
1467
1468         val = tr32(MAC_EXT_RGMII_MODE);
1469         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1470                  MAC_RGMII_MODE_RX_QUALITY |
1471                  MAC_RGMII_MODE_RX_ACTIVITY |
1472                  MAC_RGMII_MODE_RX_ENG_DET |
1473                  MAC_RGMII_MODE_TX_ENABLE |
1474                  MAC_RGMII_MODE_TX_LOWPWR |
1475                  MAC_RGMII_MODE_TX_RESET);
1476         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1477                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1478                         val |= MAC_RGMII_MODE_RX_INT_B |
1479                                MAC_RGMII_MODE_RX_QUALITY |
1480                                MAC_RGMII_MODE_RX_ACTIVITY |
1481                                MAC_RGMII_MODE_RX_ENG_DET;
1482                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1483                         val |= MAC_RGMII_MODE_TX_ENABLE |
1484                                MAC_RGMII_MODE_TX_LOWPWR |
1485                                MAC_RGMII_MODE_TX_RESET;
1486         }
1487         tw32(MAC_EXT_RGMII_MODE, val);
1488 }
1489
1490 static void tg3_mdio_start(struct tg3 *tp)
1491 {
1492         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1493         tw32_f(MAC_MI_MODE, tp->mi_mode);
1494         udelay(80);
1495
1496         if (tg3_flag(tp, MDIOBUS_INITED) &&
1497             tg3_asic_rev(tp) == ASIC_REV_5785)
1498                 tg3_mdio_config_5785(tp);
1499 }
1500
1501 static int tg3_mdio_init(struct tg3 *tp)
1502 {
1503         int i;
1504         u32 reg;
1505         struct phy_device *phydev;
1506
1507         if (tg3_flag(tp, 5717_PLUS)) {
1508                 u32 is_serdes;
1509
1510                 tp->phy_addr = tp->pci_fn + 1;
1511
1512                 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1513                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1514                 else
1515                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1516                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1517                 if (is_serdes)
1518                         tp->phy_addr += 7;
1519         } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1520                 int addr;
1521
1522                 addr = ssb_gige_get_phyaddr(tp->pdev);
1523                 if (addr < 0)
1524                         return addr;
1525                 tp->phy_addr = addr;
1526         } else
1527                 tp->phy_addr = TG3_PHY_MII_ADDR;
1528
1529         tg3_mdio_start(tp);
1530
1531         if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1532                 return 0;
1533
1534         tp->mdio_bus = mdiobus_alloc();
1535         if (tp->mdio_bus == NULL)
1536                 return -ENOMEM;
1537
1538         tp->mdio_bus->name     = "tg3 mdio bus";
1539         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1540                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1541         tp->mdio_bus->priv     = tp;
1542         tp->mdio_bus->parent   = &tp->pdev->dev;
1543         tp->mdio_bus->read     = &tg3_mdio_read;
1544         tp->mdio_bus->write    = &tg3_mdio_write;
1545         tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1546
1547         /* The bus registration will look for all the PHYs on the mdio bus.
1548          * Unfortunately, it does not ensure the PHY is powered up before
1549          * accessing the PHY ID registers.  A chip reset is the
1550          * quickest way to bring the device back to an operational state..
1551          */
1552         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1553                 tg3_bmcr_reset(tp);
1554
1555         i = mdiobus_register(tp->mdio_bus);
1556         if (i) {
1557                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1558                 mdiobus_free(tp->mdio_bus);
1559                 return i;
1560         }
1561
1562         phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1563
1564         if (!phydev || !phydev->drv) {
1565                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1566                 mdiobus_unregister(tp->mdio_bus);
1567                 mdiobus_free(tp->mdio_bus);
1568                 return -ENODEV;
1569         }
1570
1571         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1572         case PHY_ID_BCM57780:
1573                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1574                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1575                 break;
1576         case PHY_ID_BCM50610:
1577         case PHY_ID_BCM50610M:
1578                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1579                                      PHY_BRCM_RX_REFCLK_UNUSED |
1580                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1581                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1582                 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1583                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1584                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1585                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1586                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1587                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1588                 /* fallthru */
1589         case PHY_ID_RTL8211C:
1590                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1591                 break;
1592         case PHY_ID_RTL8201E:
1593         case PHY_ID_BCMAC131:
1594                 phydev->interface = PHY_INTERFACE_MODE_MII;
1595                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1596                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1597                 break;
1598         }
1599
1600         tg3_flag_set(tp, MDIOBUS_INITED);
1601
1602         if (tg3_asic_rev(tp) == ASIC_REV_5785)
1603                 tg3_mdio_config_5785(tp);
1604
1605         return 0;
1606 }
1607
1608 static void tg3_mdio_fini(struct tg3 *tp)
1609 {
1610         if (tg3_flag(tp, MDIOBUS_INITED)) {
1611                 tg3_flag_clear(tp, MDIOBUS_INITED);
1612                 mdiobus_unregister(tp->mdio_bus);
1613                 mdiobus_free(tp->mdio_bus);
1614         }
1615 }
1616
1617 /* tp->lock is held. */
1618 static inline void tg3_generate_fw_event(struct tg3 *tp)
1619 {
1620         u32 val;
1621
1622         val = tr32(GRC_RX_CPU_EVENT);
1623         val |= GRC_RX_CPU_DRIVER_EVENT;
1624         tw32_f(GRC_RX_CPU_EVENT, val);
1625
1626         tp->last_event_jiffies = jiffies;
1627 }
1628
1629 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1630
1631 /* tp->lock is held. */
1632 static void tg3_wait_for_event_ack(struct tg3 *tp)
1633 {
1634         int i;
1635         unsigned int delay_cnt;
1636         long time_remain;
1637
1638         /* If enough time has passed, no wait is necessary. */
1639         time_remain = (long)(tp->last_event_jiffies + 1 +
1640                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1641                       (long)jiffies;
1642         if (time_remain < 0)
1643                 return;
1644
1645         /* Check if we can shorten the wait time. */
1646         delay_cnt = jiffies_to_usecs(time_remain);
1647         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1648                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1649         delay_cnt = (delay_cnt >> 3) + 1;
1650
1651         for (i = 0; i < delay_cnt; i++) {
1652                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1653                         break;
1654                 if (pci_channel_offline(tp->pdev))
1655                         break;
1656
1657                 udelay(8);
1658         }
1659 }
1660
1661 /* tp->lock is held. */
1662 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1663 {
1664         u32 reg, val;
1665
1666         val = 0;
1667         if (!tg3_readphy(tp, MII_BMCR, &reg))
1668                 val = reg << 16;
1669         if (!tg3_readphy(tp, MII_BMSR, &reg))
1670                 val |= (reg & 0xffff);
1671         *data++ = val;
1672
1673         val = 0;
1674         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1675                 val = reg << 16;
1676         if (!tg3_readphy(tp, MII_LPA, &reg))
1677                 val |= (reg & 0xffff);
1678         *data++ = val;
1679
1680         val = 0;
1681         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1682                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1683                         val = reg << 16;
1684                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1685                         val |= (reg & 0xffff);
1686         }
1687         *data++ = val;
1688
1689         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1690                 val = reg << 16;
1691         else
1692                 val = 0;
1693         *data++ = val;
1694 }
1695
1696 /* tp->lock is held. */
1697 static void tg3_ump_link_report(struct tg3 *tp)
1698 {
1699         u32 data[4];
1700
1701         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1702                 return;
1703
1704         tg3_phy_gather_ump_data(tp, data);
1705
1706         tg3_wait_for_event_ack(tp);
1707
1708         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1709         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1710         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1711         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1712         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1713         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1714
1715         tg3_generate_fw_event(tp);
1716 }
1717
1718 /* tp->lock is held. */
1719 static void tg3_stop_fw(struct tg3 *tp)
1720 {
1721         if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1722                 /* Wait for RX cpu to ACK the previous event. */
1723                 tg3_wait_for_event_ack(tp);
1724
1725                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1726
1727                 tg3_generate_fw_event(tp);
1728
1729                 /* Wait for RX cpu to ACK this event. */
1730                 tg3_wait_for_event_ack(tp);
1731         }
1732 }
1733
1734 /* tp->lock is held. */
1735 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1736 {
1737         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1738                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1739
1740         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1741                 switch (kind) {
1742                 case RESET_KIND_INIT:
1743                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1744                                       DRV_STATE_START);
1745                         break;
1746
1747                 case RESET_KIND_SHUTDOWN:
1748                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749                                       DRV_STATE_UNLOAD);
1750                         break;
1751
1752                 case RESET_KIND_SUSPEND:
1753                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1754                                       DRV_STATE_SUSPEND);
1755                         break;
1756
1757                 default:
1758                         break;
1759                 }
1760         }
1761 }
1762
1763 /* tp->lock is held. */
1764 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1765 {
1766         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1767                 switch (kind) {
1768                 case RESET_KIND_INIT:
1769                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1770                                       DRV_STATE_START_DONE);
1771                         break;
1772
1773                 case RESET_KIND_SHUTDOWN:
1774                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1775                                       DRV_STATE_UNLOAD_DONE);
1776                         break;
1777
1778                 default:
1779                         break;
1780                 }
1781         }
1782 }
1783
1784 /* tp->lock is held. */
1785 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1786 {
1787         if (tg3_flag(tp, ENABLE_ASF)) {
1788                 switch (kind) {
1789                 case RESET_KIND_INIT:
1790                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1791                                       DRV_STATE_START);
1792                         break;
1793
1794                 case RESET_KIND_SHUTDOWN:
1795                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796                                       DRV_STATE_UNLOAD);
1797                         break;
1798
1799                 case RESET_KIND_SUSPEND:
1800                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1801                                       DRV_STATE_SUSPEND);
1802                         break;
1803
1804                 default:
1805                         break;
1806                 }
1807         }
1808 }
1809
1810 static int tg3_poll_fw(struct tg3 *tp)
1811 {
1812         int i;
1813         u32 val;
1814
1815         if (tg3_flag(tp, NO_FWARE_REPORTED))
1816                 return 0;
1817
1818         if (tg3_flag(tp, IS_SSB_CORE)) {
1819                 /* We don't use firmware. */
1820                 return 0;
1821         }
1822
1823         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1824                 /* Wait up to 20ms for init done. */
1825                 for (i = 0; i < 200; i++) {
1826                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1827                                 return 0;
1828                         if (pci_channel_offline(tp->pdev))
1829                                 return -ENODEV;
1830
1831                         udelay(100);
1832                 }
1833                 return -ENODEV;
1834         }
1835
1836         /* Wait for firmware initialization to complete. */
1837         for (i = 0; i < 100000; i++) {
1838                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1839                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1840                         break;
1841                 if (pci_channel_offline(tp->pdev)) {
1842                         if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1843                                 tg3_flag_set(tp, NO_FWARE_REPORTED);
1844                                 netdev_info(tp->dev, "No firmware running\n");
1845                         }
1846
1847                         break;
1848                 }
1849
1850                 udelay(10);
1851         }
1852
1853         /* Chip might not be fitted with firmware.  Some Sun onboard
1854          * parts are configured like that.  So don't signal the timeout
1855          * of the above loop as an error, but do report the lack of
1856          * running firmware once.
1857          */
1858         if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1859                 tg3_flag_set(tp, NO_FWARE_REPORTED);
1860
1861                 netdev_info(tp->dev, "No firmware running\n");
1862         }
1863
1864         if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1865                 /* The 57765 A0 needs a little more
1866                  * time to do some important work.
1867                  */
1868                 mdelay(10);
1869         }
1870
1871         return 0;
1872 }
1873
1874 static void tg3_link_report(struct tg3 *tp)
1875 {
1876         if (!netif_carrier_ok(tp->dev)) {
1877                 netif_info(tp, link, tp->dev, "Link is down\n");
1878                 tg3_ump_link_report(tp);
1879         } else if (netif_msg_link(tp)) {
1880                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1881                             (tp->link_config.active_speed == SPEED_1000 ?
1882                              1000 :
1883                              (tp->link_config.active_speed == SPEED_100 ?
1884                               100 : 10)),
1885                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1886                              "full" : "half"));
1887
1888                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1889                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1890                             "on" : "off",
1891                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1892                             "on" : "off");
1893
1894                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1895                         netdev_info(tp->dev, "EEE is %s\n",
1896                                     tp->setlpicnt ? "enabled" : "disabled");
1897
1898                 tg3_ump_link_report(tp);
1899         }
1900
1901         tp->link_up = netif_carrier_ok(tp->dev);
1902 }
1903
1904 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1905 {
1906         u32 flowctrl = 0;
1907
1908         if (adv & ADVERTISE_PAUSE_CAP) {
1909                 flowctrl |= FLOW_CTRL_RX;
1910                 if (!(adv & ADVERTISE_PAUSE_ASYM))
1911                         flowctrl |= FLOW_CTRL_TX;
1912         } else if (adv & ADVERTISE_PAUSE_ASYM)
1913                 flowctrl |= FLOW_CTRL_TX;
1914
1915         return flowctrl;
1916 }
1917
1918 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1919 {
1920         u16 miireg;
1921
1922         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1923                 miireg = ADVERTISE_1000XPAUSE;
1924         else if (flow_ctrl & FLOW_CTRL_TX)
1925                 miireg = ADVERTISE_1000XPSE_ASYM;
1926         else if (flow_ctrl & FLOW_CTRL_RX)
1927                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1928         else
1929                 miireg = 0;
1930
1931         return miireg;
1932 }
1933
1934 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1935 {
1936         u32 flowctrl = 0;
1937
1938         if (adv & ADVERTISE_1000XPAUSE) {
1939                 flowctrl |= FLOW_CTRL_RX;
1940                 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1941                         flowctrl |= FLOW_CTRL_TX;
1942         } else if (adv & ADVERTISE_1000XPSE_ASYM)
1943                 flowctrl |= FLOW_CTRL_TX;
1944
1945         return flowctrl;
1946 }
1947
1948 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1949 {
1950         u8 cap = 0;
1951
1952         if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1953                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1954         } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1955                 if (lcladv & ADVERTISE_1000XPAUSE)
1956                         cap = FLOW_CTRL_RX;
1957                 if (rmtadv & ADVERTISE_1000XPAUSE)
1958                         cap = FLOW_CTRL_TX;
1959         }
1960
1961         return cap;
1962 }
1963
1964 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1965 {
1966         u8 autoneg;
1967         u8 flowctrl = 0;
1968         u32 old_rx_mode = tp->rx_mode;
1969         u32 old_tx_mode = tp->tx_mode;
1970
1971         if (tg3_flag(tp, USE_PHYLIB))
1972                 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1973         else
1974                 autoneg = tp->link_config.autoneg;
1975
1976         if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1977                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1978                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1979                 else
1980                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1981         } else
1982                 flowctrl = tp->link_config.flowctrl;
1983
1984         tp->link_config.active_flowctrl = flowctrl;
1985
1986         if (flowctrl & FLOW_CTRL_RX)
1987                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1988         else
1989                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1990
1991         if (old_rx_mode != tp->rx_mode)
1992                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1993
1994         if (flowctrl & FLOW_CTRL_TX)
1995                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1996         else
1997                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1998
1999         if (old_tx_mode != tp->tx_mode)
2000                 tw32_f(MAC_TX_MODE, tp->tx_mode);
2001 }
2002
2003 static void tg3_adjust_link(struct net_device *dev)
2004 {
2005         u8 oldflowctrl, linkmesg = 0;
2006         u32 mac_mode, lcl_adv, rmt_adv;
2007         struct tg3 *tp = netdev_priv(dev);
2008         struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2009
2010         spin_lock_bh(&tp->lock);
2011
2012         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2013                                     MAC_MODE_HALF_DUPLEX);
2014
2015         oldflowctrl = tp->link_config.active_flowctrl;
2016
2017         if (phydev->link) {
2018                 lcl_adv = 0;
2019                 rmt_adv = 0;
2020
2021                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2022                         mac_mode |= MAC_MODE_PORT_MODE_MII;
2023                 else if (phydev->speed == SPEED_1000 ||
2024                          tg3_asic_rev(tp) != ASIC_REV_5785)
2025                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
2026                 else
2027                         mac_mode |= MAC_MODE_PORT_MODE_MII;
2028
2029                 if (phydev->duplex == DUPLEX_HALF)
2030                         mac_mode |= MAC_MODE_HALF_DUPLEX;
2031                 else {
2032                         lcl_adv = mii_advertise_flowctrl(
2033                                   tp->link_config.flowctrl);
2034
2035                         if (phydev->pause)
2036                                 rmt_adv = LPA_PAUSE_CAP;
2037                         if (phydev->asym_pause)
2038                                 rmt_adv |= LPA_PAUSE_ASYM;
2039                 }
2040
2041                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2042         } else
2043                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2044
2045         if (mac_mode != tp->mac_mode) {
2046                 tp->mac_mode = mac_mode;
2047                 tw32_f(MAC_MODE, tp->mac_mode);
2048                 udelay(40);
2049         }
2050
2051         if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2052                 if (phydev->speed == SPEED_10)
2053                         tw32(MAC_MI_STAT,
2054                              MAC_MI_STAT_10MBPS_MODE |
2055                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2056                 else
2057                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2058         }
2059
2060         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2061                 tw32(MAC_TX_LENGTHS,
2062                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2063                       (6 << TX_LENGTHS_IPG_SHIFT) |
2064                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065         else
2066                 tw32(MAC_TX_LENGTHS,
2067                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2068                       (6 << TX_LENGTHS_IPG_SHIFT) |
2069                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070
2071         if (phydev->link != tp->old_link ||
2072             phydev->speed != tp->link_config.active_speed ||
2073             phydev->duplex != tp->link_config.active_duplex ||
2074             oldflowctrl != tp->link_config.active_flowctrl)
2075                 linkmesg = 1;
2076
2077         tp->old_link = phydev->link;
2078         tp->link_config.active_speed = phydev->speed;
2079         tp->link_config.active_duplex = phydev->duplex;
2080
2081         spin_unlock_bh(&tp->lock);
2082
2083         if (linkmesg)
2084                 tg3_link_report(tp);
2085 }
2086
2087 static int tg3_phy_init(struct tg3 *tp)
2088 {
2089         struct phy_device *phydev;
2090
2091         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2092                 return 0;
2093
2094         /* Bring the PHY back to a known state. */
2095         tg3_bmcr_reset(tp);
2096
2097         phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2098
2099         /* Attach the MAC to the PHY. */
2100         phydev = phy_connect(tp->dev, phydev_name(phydev),
2101                              tg3_adjust_link, phydev->interface);
2102         if (IS_ERR(phydev)) {
2103                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2104                 return PTR_ERR(phydev);
2105         }
2106
2107         /* Mask with MAC supported features. */
2108         switch (phydev->interface) {
2109         case PHY_INTERFACE_MODE_GMII:
2110         case PHY_INTERFACE_MODE_RGMII:
2111                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2112                         phydev->supported &= (PHY_GBIT_FEATURES |
2113                                               SUPPORTED_Pause |
2114                                               SUPPORTED_Asym_Pause);
2115                         break;
2116                 }
2117                 /* fallthru */
2118         case PHY_INTERFACE_MODE_MII:
2119                 phydev->supported &= (PHY_BASIC_FEATURES |
2120                                       SUPPORTED_Pause |
2121                                       SUPPORTED_Asym_Pause);
2122                 break;
2123         default:
2124                 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2125                 return -EINVAL;
2126         }
2127
2128         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2129
2130         phydev->advertising = phydev->supported;
2131
2132         phy_attached_info(phydev);
2133
2134         return 0;
2135 }
2136
2137 static void tg3_phy_start(struct tg3 *tp)
2138 {
2139         struct phy_device *phydev;
2140
2141         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2142                 return;
2143
2144         phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2145
2146         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2147                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2148                 phydev->speed = tp->link_config.speed;
2149                 phydev->duplex = tp->link_config.duplex;
2150                 phydev->autoneg = tp->link_config.autoneg;
2151                 phydev->advertising = tp->link_config.advertising;
2152         }
2153
2154         phy_start(phydev);
2155
2156         phy_start_aneg(phydev);
2157 }
2158
2159 static void tg3_phy_stop(struct tg3 *tp)
2160 {
2161         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2162                 return;
2163
2164         phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2165 }
2166
2167 static void tg3_phy_fini(struct tg3 *tp)
2168 {
2169         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2170                 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2171                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2172         }
2173 }
2174
2175 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2176 {
2177         int err;
2178         u32 val;
2179
2180         if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2181                 return 0;
2182
2183         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2184                 /* Cannot do read-modify-write on 5401 */
2185                 err = tg3_phy_auxctl_write(tp,
2186                                            MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2187                                            MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2188                                            0x4c20);
2189                 goto done;
2190         }
2191
2192         err = tg3_phy_auxctl_read(tp,
2193                                   MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2194         if (err)
2195                 return err;
2196
2197         val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2198         err = tg3_phy_auxctl_write(tp,
2199                                    MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2200
2201 done:
2202         return err;
2203 }
2204
2205 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2206 {
2207         u32 phytest;
2208
2209         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2210                 u32 phy;
2211
2212                 tg3_writephy(tp, MII_TG3_FET_TEST,
2213                              phytest | MII_TG3_FET_SHADOW_EN);
2214                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2215                         if (enable)
2216                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2217                         else
2218                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2219                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2220                 }
2221                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2222         }
2223 }
2224
2225 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2226 {
2227         u32 reg;
2228
2229         if (!tg3_flag(tp, 5705_PLUS) ||
2230             (tg3_flag(tp, 5717_PLUS) &&
2231              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2232                 return;
2233
2234         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2235                 tg3_phy_fet_toggle_apd(tp, enable);
2236                 return;
2237         }
2238
2239         reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2240               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2241               MII_TG3_MISC_SHDW_SCR5_SDTL |
2242               MII_TG3_MISC_SHDW_SCR5_C125OE;
2243         if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2244                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2245
2246         tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2247
2248
2249         reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2250         if (enable)
2251                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2252
2253         tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2254 }
2255
2256 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2257 {
2258         u32 phy;
2259
2260         if (!tg3_flag(tp, 5705_PLUS) ||
2261             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2262                 return;
2263
2264         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2265                 u32 ephy;
2266
2267                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2268                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2269
2270                         tg3_writephy(tp, MII_TG3_FET_TEST,
2271                                      ephy | MII_TG3_FET_SHADOW_EN);
2272                         if (!tg3_readphy(tp, reg, &phy)) {
2273                                 if (enable)
2274                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2275                                 else
2276                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2277                                 tg3_writephy(tp, reg, phy);
2278                         }
2279                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2280                 }
2281         } else {
2282                 int ret;
2283
2284                 ret = tg3_phy_auxctl_read(tp,
2285                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2286                 if (!ret) {
2287                         if (enable)
2288                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2289                         else
2290                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2291                         tg3_phy_auxctl_write(tp,
2292                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2293                 }
2294         }
2295 }
2296
2297 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2298 {
2299         int ret;
2300         u32 val;
2301
2302         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2303                 return;
2304
2305         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2306         if (!ret)
2307                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2308                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2309 }
2310
2311 static void tg3_phy_apply_otp(struct tg3 *tp)
2312 {
2313         u32 otp, phy;
2314
2315         if (!tp->phy_otp)
2316                 return;
2317
2318         otp = tp->phy_otp;
2319
2320         if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2321                 return;
2322
2323         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2324         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2325         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2326
2327         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2328               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2329         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2330
2331         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2332         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2333         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2334
2335         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2336         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2337
2338         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2339         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2340
2341         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2342               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2343         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2344
2345         tg3_phy_toggle_auxctl_smdsp(tp, false);
2346 }
2347
2348 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2349 {
2350         u32 val;
2351         struct ethtool_eee *dest = &tp->eee;
2352
2353         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2354                 return;
2355
2356         if (eee)
2357                 dest = eee;
2358
2359         if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2360                 return;
2361
2362         /* Pull eee_active */
2363         if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2364             val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2365                 dest->eee_active = 1;
2366         } else
2367                 dest->eee_active = 0;
2368
2369         /* Pull lp advertised settings */
2370         if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2371                 return;
2372         dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2373
2374         /* Pull advertised and eee_enabled settings */
2375         if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2376                 return;
2377         dest->eee_enabled = !!val;
2378         dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2379
2380         /* Pull tx_lpi_enabled */
2381         val = tr32(TG3_CPMU_EEE_MODE);
2382         dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2383
2384         /* Pull lpi timer value */
2385         dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2386 }
2387
2388 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2389 {
2390         u32 val;
2391
2392         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2393                 return;
2394
2395         tp->setlpicnt = 0;
2396
2397         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2398             current_link_up &&
2399             tp->link_config.active_duplex == DUPLEX_FULL &&
2400             (tp->link_config.active_speed == SPEED_100 ||
2401              tp->link_config.active_speed == SPEED_1000)) {
2402                 u32 eeectl;
2403
2404                 if (tp->link_config.active_speed == SPEED_1000)
2405                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2406                 else
2407                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2408
2409                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2410
2411                 tg3_eee_pull_config(tp, NULL);
2412                 if (tp->eee.eee_active)
2413                         tp->setlpicnt = 2;
2414         }
2415
2416         if (!tp->setlpicnt) {
2417                 if (current_link_up &&
2418                    !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2419                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2420                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2421                 }
2422
2423                 val = tr32(TG3_CPMU_EEE_MODE);
2424                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2425         }
2426 }
2427
2428 static void tg3_phy_eee_enable(struct tg3 *tp)
2429 {
2430         u32 val;
2431
2432         if (tp->link_config.active_speed == SPEED_1000 &&
2433             (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2434              tg3_asic_rev(tp) == ASIC_REV_5719 ||
2435              tg3_flag(tp, 57765_CLASS)) &&
2436             !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2437                 val = MII_TG3_DSP_TAP26_ALNOKO |
2438                       MII_TG3_DSP_TAP26_RMRXSTO;
2439                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2440                 tg3_phy_toggle_auxctl_smdsp(tp, false);
2441         }
2442
2443         val = tr32(TG3_CPMU_EEE_MODE);
2444         tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2445 }
2446
2447 static int tg3_wait_macro_done(struct tg3 *tp)
2448 {
2449         int limit = 100;
2450
2451         while (limit--) {
2452                 u32 tmp32;
2453
2454                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2455                         if ((tmp32 & 0x1000) == 0)
2456                                 break;
2457                 }
2458         }
2459         if (limit < 0)
2460                 return -EBUSY;
2461
2462         return 0;
2463 }
2464
2465 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2466 {
2467         static const u32 test_pat[4][6] = {
2468         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2469         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2470         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2471         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2472         };
2473         int chan;
2474
2475         for (chan = 0; chan < 4; chan++) {
2476                 int i;
2477
2478                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2479                              (chan * 0x2000) | 0x0200);
2480                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2481
2482                 for (i = 0; i < 6; i++)
2483                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2484                                      test_pat[chan][i]);
2485
2486                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2487                 if (tg3_wait_macro_done(tp)) {
2488                         *resetp = 1;
2489                         return -EBUSY;
2490                 }
2491
2492                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2493                              (chan * 0x2000) | 0x0200);
2494                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2495                 if (tg3_wait_macro_done(tp)) {
2496                         *resetp = 1;
2497                         return -EBUSY;
2498                 }
2499
2500                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2501                 if (tg3_wait_macro_done(tp)) {
2502                         *resetp = 1;
2503                         return -EBUSY;
2504                 }
2505
2506                 for (i = 0; i < 6; i += 2) {
2507                         u32 low, high;
2508
2509                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2510                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2511                             tg3_wait_macro_done(tp)) {
2512                                 *resetp = 1;
2513                                 return -EBUSY;
2514                         }
2515                         low &= 0x7fff;
2516                         high &= 0x000f;
2517                         if (low != test_pat[chan][i] ||
2518                             high != test_pat[chan][i+1]) {
2519                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2520                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2521                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2522
2523                                 return -EBUSY;
2524                         }
2525                 }
2526         }
2527
2528         return 0;
2529 }
2530
2531 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2532 {
2533         int chan;
2534
2535         for (chan = 0; chan < 4; chan++) {
2536                 int i;
2537
2538                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2539                              (chan * 0x2000) | 0x0200);
2540                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2541                 for (i = 0; i < 6; i++)
2542                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2543                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2544                 if (tg3_wait_macro_done(tp))
2545                         return -EBUSY;
2546         }
2547
2548         return 0;
2549 }
2550
2551 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2552 {
2553         u32 reg32, phy9_orig;
2554         int retries, do_phy_reset, err;
2555
2556         retries = 10;
2557         do_phy_reset = 1;
2558         do {
2559                 if (do_phy_reset) {
2560                         err = tg3_bmcr_reset(tp);
2561                         if (err)
2562                                 return err;
2563                         do_phy_reset = 0;
2564                 }
2565
2566                 /* Disable transmitter and interrupt.  */
2567                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2568                         continue;
2569
2570                 reg32 |= 0x3000;
2571                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2572
2573                 /* Set full-duplex, 1000 mbps.  */
2574                 tg3_writephy(tp, MII_BMCR,
2575                              BMCR_FULLDPLX | BMCR_SPEED1000);
2576
2577                 /* Set to master mode.  */
2578                 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2579                         continue;
2580
2581                 tg3_writephy(tp, MII_CTRL1000,
2582                              CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2583
2584                 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2585                 if (err)
2586                         return err;
2587
2588                 /* Block the PHY control access.  */
2589                 tg3_phydsp_write(tp, 0x8005, 0x0800);
2590
2591                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2592                 if (!err)
2593                         break;
2594         } while (--retries);
2595
2596         err = tg3_phy_reset_chanpat(tp);
2597         if (err)
2598                 return err;
2599
2600         tg3_phydsp_write(tp, 0x8005, 0x0000);
2601
2602         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2603         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2604
2605         tg3_phy_toggle_auxctl_smdsp(tp, false);
2606
2607         tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2608
2609         err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
2610         if (err)
2611                 return err;
2612
2613         reg32 &= ~0x3000;
2614         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2615
2616         return 0;
2617 }
2618
2619 static void tg3_carrier_off(struct tg3 *tp)
2620 {
2621         netif_carrier_off(tp->dev);
2622         tp->link_up = false;
2623 }
2624
2625 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2626 {
2627         if (tg3_flag(tp, ENABLE_ASF))
2628                 netdev_warn(tp->dev,
2629                             "Management side-band traffic will be interrupted during phy settings change\n");
2630 }
2631
2632 /* This will reset the tigon3 PHY if there is no valid
2633  * link unless the FORCE argument is non-zero.
2634  */
2635 static int tg3_phy_reset(struct tg3 *tp)
2636 {
2637         u32 val, cpmuctrl;
2638         int err;
2639
2640         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2641                 val = tr32(GRC_MISC_CFG);
2642                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2643                 udelay(40);
2644         }
2645         err  = tg3_readphy(tp, MII_BMSR, &val);
2646         err |= tg3_readphy(tp, MII_BMSR, &val);
2647         if (err != 0)
2648                 return -EBUSY;
2649
2650         if (netif_running(tp->dev) && tp->link_up) {
2651                 netif_carrier_off(tp->dev);
2652                 tg3_link_report(tp);
2653         }
2654
2655         if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2656             tg3_asic_rev(tp) == ASIC_REV_5704 ||
2657             tg3_asic_rev(tp) == ASIC_REV_5705) {
2658                 err = tg3_phy_reset_5703_4_5(tp);
2659                 if (err)
2660                         return err;
2661                 goto out;
2662         }
2663
2664         cpmuctrl = 0;
2665         if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2666             tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2667                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2668                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2669                         tw32(TG3_CPMU_CTRL,
2670                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2671         }
2672
2673         err = tg3_bmcr_reset(tp);
2674         if (err)
2675                 return err;
2676
2677         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2678                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2679                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2680
2681                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2682         }
2683
2684         if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2685             tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2686                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2687                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2688                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2689                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2690                         udelay(40);
2691                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2692                 }
2693         }
2694
2695         if (tg3_flag(tp, 5717_PLUS) &&
2696             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2697                 return 0;
2698
2699         tg3_phy_apply_otp(tp);
2700
2701         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2702                 tg3_phy_toggle_apd(tp, true);
2703         else
2704                 tg3_phy_toggle_apd(tp, false);
2705
2706 out:
2707         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2708             !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2709                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2710                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2711                 tg3_phy_toggle_auxctl_smdsp(tp, false);
2712         }
2713
2714         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2715                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2716                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2717         }
2718
2719         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2720                 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2721                         tg3_phydsp_write(tp, 0x000a, 0x310b);
2722                         tg3_phydsp_write(tp, 0x201f, 0x9506);
2723                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
2724                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2725                 }
2726         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2727                 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2728                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2729                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2730                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2731                                 tg3_writephy(tp, MII_TG3_TEST1,
2732                                              MII_TG3_TEST1_TRIM_EN | 0x4);
2733                         } else
2734                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2735
2736                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2737                 }
2738         }
2739
2740         /* Set Extended packet length bit (bit 14) on all chips that */
2741         /* support jumbo frames */
2742         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2743                 /* Cannot do read-modify-write on 5401 */
2744                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2745         } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2746                 /* Set bit 14 with read-modify-write to preserve other bits */
2747                 err = tg3_phy_auxctl_read(tp,
2748                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2749                 if (!err)
2750                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2751                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2752         }
2753
2754         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2755          * jumbo frames transmission.
2756          */
2757         if (tg3_flag(tp, JUMBO_CAPABLE)) {
2758                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2759                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2760                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2761         }
2762
2763         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2764                 /* adjust output voltage */
2765                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2766         }
2767
2768         if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2769                 tg3_phydsp_write(tp, 0xffb, 0x4000);
2770
2771         tg3_phy_toggle_automdix(tp, true);
2772         tg3_phy_set_wirespeed(tp);
2773         return 0;
2774 }
2775
2776 #define TG3_GPIO_MSG_DRVR_PRES           0x00000001
2777 #define TG3_GPIO_MSG_NEED_VAUX           0x00000002
2778 #define TG3_GPIO_MSG_MASK                (TG3_GPIO_MSG_DRVR_PRES | \
2779                                           TG3_GPIO_MSG_NEED_VAUX)
2780 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2781         ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2782          (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2783          (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2784          (TG3_GPIO_MSG_DRVR_PRES << 12))
2785
2786 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2787         ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2788          (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2789          (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2790          (TG3_GPIO_MSG_NEED_VAUX << 12))
2791
2792 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2793 {
2794         u32 status, shift;
2795
2796         if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2797             tg3_asic_rev(tp) == ASIC_REV_5719)
2798                 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2799         else
2800                 status = tr32(TG3_CPMU_DRV_STATUS);
2801
2802         shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2803         status &= ~(TG3_GPIO_MSG_MASK << shift);
2804         status |= (newstat << shift);
2805
2806         if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2807             tg3_asic_rev(tp) == ASIC_REV_5719)
2808                 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2809         else
2810                 tw32(TG3_CPMU_DRV_STATUS, status);
2811
2812         return status >> TG3_APE_GPIO_MSG_SHIFT;
2813 }
2814
2815 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2816 {
2817         if (!tg3_flag(tp, IS_NIC))
2818                 return 0;
2819
2820         if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2821             tg3_asic_rev(tp) == ASIC_REV_5719 ||
2822             tg3_asic_rev(tp) == ASIC_REV_5720) {
2823                 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2824                         return -EIO;
2825
2826                 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2827
2828                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2829                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2830
2831                 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2832         } else {
2833                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2834                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2835         }
2836
2837         return 0;
2838 }
2839
2840 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2841 {
2842         u32 grc_local_ctrl;
2843
2844         if (!tg3_flag(tp, IS_NIC) ||
2845             tg3_asic_rev(tp) == ASIC_REV_5700 ||
2846             tg3_asic_rev(tp) == ASIC_REV_5701)
2847                 return;
2848
2849         grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2850
2851         tw32_wait_f(GRC_LOCAL_CTRL,
2852                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2853                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2854
2855         tw32_wait_f(GRC_LOCAL_CTRL,
2856                     grc_local_ctrl,
2857                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2858
2859         tw32_wait_f(GRC_LOCAL_CTRL,
2860                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2861                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2862 }
2863
2864 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2865 {
2866         if (!tg3_flag(tp, IS_NIC))
2867                 return;
2868
2869         if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2870             tg3_asic_rev(tp) == ASIC_REV_5701) {
2871                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2872                             (GRC_LCLCTRL_GPIO_OE0 |
2873                              GRC_LCLCTRL_GPIO_OE1 |
2874                              GRC_LCLCTRL_GPIO_OE2 |
2875                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2876                              GRC_LCLCTRL_GPIO_OUTPUT1),
2877                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2878         } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2879                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2880                 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2881                 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2882                                      GRC_LCLCTRL_GPIO_OE1 |
2883                                      GRC_LCLCTRL_GPIO_OE2 |
2884                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2885                                      GRC_LCLCTRL_GPIO_OUTPUT1 |
2886                                      tp->grc_local_ctrl;
2887                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2888                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2889
2890                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2891                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2892                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2893
2894                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2895                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2896                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2897         } else {
2898                 u32 no_gpio2;
2899                 u32 grc_local_ctrl = 0;
2900
2901                 /* Workaround to prevent overdrawing Amps. */
2902                 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2903                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2904                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2905                                     grc_local_ctrl,
2906                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2907                 }
2908
2909                 /* On 5753 and variants, GPIO2 cannot be used. */
2910                 no_gpio2 = tp->nic_sram_data_cfg &
2911                            NIC_SRAM_DATA_CFG_NO_GPIO2;
2912
2913                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2914                                   GRC_LCLCTRL_GPIO_OE1 |
2915                                   GRC_LCLCTRL_GPIO_OE2 |
2916                                   GRC_LCLCTRL_GPIO_OUTPUT1 |
2917                                   GRC_LCLCTRL_GPIO_OUTPUT2;
2918                 if (no_gpio2) {
2919                         grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2920                                             GRC_LCLCTRL_GPIO_OUTPUT2);
2921                 }
2922                 tw32_wait_f(GRC_LOCAL_CTRL,
2923                             tp->grc_local_ctrl | grc_local_ctrl,
2924                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2925
2926                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2927
2928                 tw32_wait_f(GRC_LOCAL_CTRL,
2929                             tp->grc_local_ctrl | grc_local_ctrl,
2930                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2931
2932                 if (!no_gpio2) {
2933                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2934                         tw32_wait_f(GRC_LOCAL_CTRL,
2935                                     tp->grc_local_ctrl | grc_local_ctrl,
2936                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2937                 }
2938         }
2939 }
2940
2941 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2942 {
2943         u32 msg = 0;
2944
2945         /* Serialize power state transitions */
2946         if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2947                 return;
2948
2949         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2950                 msg = TG3_GPIO_MSG_NEED_VAUX;
2951
2952         msg = tg3_set_function_status(tp, msg);
2953
2954         if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2955                 goto done;
2956
2957         if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2958                 tg3_pwrsrc_switch_to_vaux(tp);
2959         else
2960                 tg3_pwrsrc_die_with_vmain(tp);
2961
2962 done:
2963         tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2964 }
2965
2966 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2967 {
2968         bool need_vaux = false;
2969
2970         /* The GPIOs do something completely different on 57765. */
2971         if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2972                 return;
2973
2974         if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2975             tg3_asic_rev(tp) == ASIC_REV_5719 ||
2976             tg3_asic_rev(tp) == ASIC_REV_5720) {
2977                 tg3_frob_aux_power_5717(tp, include_wol ?
2978                                         tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2979                 return;
2980         }
2981
2982         if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2983                 struct net_device *dev_peer;
2984
2985                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2986
2987                 /* remove_one() may have been run on the peer. */
2988                 if (dev_peer) {
2989                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2990
2991                         if (tg3_flag(tp_peer, INIT_COMPLETE))
2992                                 return;
2993
2994                         if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2995                             tg3_flag(tp_peer, ENABLE_ASF))
2996                                 need_vaux = true;
2997                 }
2998         }
2999
3000         if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3001             tg3_flag(tp, ENABLE_ASF))
3002                 need_vaux = true;
3003
3004         if (need_vaux)
3005                 tg3_pwrsrc_switch_to_vaux(tp);
3006         else
3007                 tg3_pwrsrc_die_with_vmain(tp);
3008 }
3009
3010 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3011 {
3012         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3013                 return 1;
3014         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3015                 if (speed != SPEED_10)
3016                         return 1;
3017         } else if (speed == SPEED_10)
3018                 return 1;
3019
3020         return 0;
3021 }
3022
3023 static bool tg3_phy_power_bug(struct tg3 *tp)
3024 {
3025         switch (tg3_asic_rev(tp)) {
3026         case ASIC_REV_5700:
3027         case ASIC_REV_5704:
3028                 return true;
3029         case ASIC_REV_5780:
3030                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3031                         return true;
3032                 return false;
3033         case ASIC_REV_5717:
3034                 if (!tp->pci_fn)
3035                         return true;
3036                 return false;
3037         case ASIC_REV_5719:
3038         case ASIC_REV_5720:
3039                 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3040                     !tp->pci_fn)
3041                         return true;
3042                 return false;
3043         }
3044
3045         return false;
3046 }
3047
3048 static bool tg3_phy_led_bug(struct tg3 *tp)
3049 {
3050         switch (tg3_asic_rev(tp)) {
3051         case ASIC_REV_5719:
3052         case ASIC_REV_5720:
3053                 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3054                     !tp->pci_fn)
3055                         return true;
3056                 return false;
3057         }
3058
3059         return false;
3060 }
3061
3062 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3063 {
3064         u32 val;
3065
3066         if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3067                 return;
3068
3069         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3070                 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3071                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3072                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3073
3074                         sg_dig_ctrl |=
3075                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3076                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
3077                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3078                 }
3079                 return;
3080         }
3081
3082         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3083                 tg3_bmcr_reset(tp);
3084                 val = tr32(GRC_MISC_CFG);
3085                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3086                 udelay(40);
3087                 return;
3088         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3089                 u32 phytest;
3090                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3091                         u32 phy;
3092
3093                         tg3_writephy(tp, MII_ADVERTISE, 0);
3094                         tg3_writephy(tp, MII_BMCR,
3095                                      BMCR_ANENABLE | BMCR_ANRESTART);
3096
3097                         tg3_writephy(tp, MII_TG3_FET_TEST,
3098                                      phytest | MII_TG3_FET_SHADOW_EN);
3099                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3100                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3101                                 tg3_writephy(tp,
3102                                              MII_TG3_FET_SHDW_AUXMODE4,
3103                                              phy);
3104                         }
3105                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3106                 }
3107                 return;
3108         } else if (do_low_power) {
3109                 if (!tg3_phy_led_bug(tp))
3110                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3111                                      MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3112
3113                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3114                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3115                       MII_TG3_AUXCTL_PCTL_VREG_11V;
3116                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3117         }
3118
3119         /* The PHY should not be powered down on some chips because
3120          * of bugs.
3121          */
3122         if (tg3_phy_power_bug(tp))
3123                 return;
3124
3125         if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3126             tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3127                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3128                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3129                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3130                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3131         }
3132
3133         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3134 }
3135
3136 /* tp->lock is held. */
3137 static int tg3_nvram_lock(struct tg3 *tp)
3138 {
3139         if (tg3_flag(tp, NVRAM)) {
3140                 int i;
3141
3142                 if (tp->nvram_lock_cnt == 0) {
3143                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3144                         for (i = 0; i < 8000; i++) {
3145                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3146                                         break;
3147                                 udelay(20);
3148                         }
3149                         if (i == 8000) {
3150                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3151                                 return -ENODEV;
3152                         }
3153                 }
3154                 tp->nvram_lock_cnt++;
3155         }
3156         return 0;
3157 }
3158
3159 /* tp->lock is held. */
3160 static void tg3_nvram_unlock(struct tg3 *tp)
3161 {
3162         if (tg3_flag(tp, NVRAM)) {
3163                 if (tp->nvram_lock_cnt > 0)
3164                         tp->nvram_lock_cnt--;
3165                 if (tp->nvram_lock_cnt == 0)
3166                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3167         }
3168 }
3169
3170 /* tp->lock is held. */
3171 static void tg3_enable_nvram_access(struct tg3 *tp)
3172 {
3173         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3174                 u32 nvaccess = tr32(NVRAM_ACCESS);
3175
3176                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3177         }
3178 }
3179
3180 /* tp->lock is held. */
3181 static void tg3_disable_nvram_access(struct tg3 *tp)
3182 {
3183         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3184                 u32 nvaccess = tr32(NVRAM_ACCESS);
3185
3186                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3187         }
3188 }
3189
3190 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3191                                         u32 offset, u32 *val)
3192 {
3193         u32 tmp;
3194         int i;
3195
3196         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3197                 return -EINVAL;
3198
3199         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3200                                         EEPROM_ADDR_DEVID_MASK |
3201                                         EEPROM_ADDR_READ);
3202         tw32(GRC_EEPROM_ADDR,
3203              tmp |
3204              (0 << EEPROM_ADDR_DEVID_SHIFT) |
3205              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3206               EEPROM_ADDR_ADDR_MASK) |
3207              EEPROM_ADDR_READ | EEPROM_ADDR_START);
3208
3209         for (i = 0; i < 1000; i++) {
3210                 tmp = tr32(GRC_EEPROM_ADDR);
3211
3212                 if (tmp & EEPROM_ADDR_COMPLETE)
3213                         break;
3214                 msleep(1);
3215         }
3216         if (!(tmp & EEPROM_ADDR_COMPLETE))
3217                 return -EBUSY;
3218
3219         tmp = tr32(GRC_EEPROM_DATA);
3220
3221         /*
3222          * The data will always be opposite the native endian
3223          * format.  Perform a blind byteswap to compensate.
3224          */
3225         *val = swab32(tmp);
3226
3227         return 0;
3228 }
3229
3230 #define NVRAM_CMD_TIMEOUT 5000
3231
3232 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3233 {
3234         int i;
3235
3236         tw32(NVRAM_CMD, nvram_cmd);
3237         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3238                 usleep_range(10, 40);
3239                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3240                         udelay(10);
3241                         break;
3242                 }
3243         }
3244
3245         if (i == NVRAM_CMD_TIMEOUT)
3246                 return -EBUSY;
3247
3248         return 0;
3249 }
3250
3251 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3252 {
3253         if (tg3_flag(tp, NVRAM) &&
3254             tg3_flag(tp, NVRAM_BUFFERED) &&
3255             tg3_flag(tp, FLASH) &&
3256             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3257             (tp->nvram_jedecnum == JEDEC_ATMEL))
3258
3259                 addr = ((addr / tp->nvram_pagesize) <<
3260                         ATMEL_AT45DB0X1B_PAGE_POS) +
3261                        (addr % tp->nvram_pagesize);
3262
3263         return addr;
3264 }
3265
3266 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3267 {
3268         if (tg3_flag(tp, NVRAM) &&
3269             tg3_flag(tp, NVRAM_BUFFERED) &&
3270             tg3_flag(tp, FLASH) &&
3271             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3272             (tp->nvram_jedecnum == JEDEC_ATMEL))
3273
3274                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3275                         tp->nvram_pagesize) +
3276                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3277
3278         return addr;
3279 }
3280
3281 /* NOTE: Data read in from NVRAM is byteswapped according to
3282  * the byteswapping settings for all other register accesses.
3283  * tg3 devices are BE devices, so on a BE machine, the data
3284  * returned will be exactly as it is seen in NVRAM.  On a LE
3285  * machine, the 32-bit value will be byteswapped.
3286  */
3287 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3288 {
3289         int ret;
3290
3291         if (!tg3_flag(tp, NVRAM))
3292                 return tg3_nvram_read_using_eeprom(tp, offset, val);
3293
3294         offset = tg3_nvram_phys_addr(tp, offset);
3295
3296         if (offset > NVRAM_ADDR_MSK)
3297                 return -EINVAL;
3298
3299         ret = tg3_nvram_lock(tp);
3300         if (ret)