cxgb4: fix thermal configuration dependencies
[muen/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
1 /*
2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3  *
4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <linux/uaccess.h>
66 #include <linux/crash_dump.h>
67 #include <net/udp_tunnel.h>
68
69 #include "cxgb4.h"
70 #include "cxgb4_filter.h"
71 #include "t4_regs.h"
72 #include "t4_values.h"
73 #include "t4_msg.h"
74 #include "t4fw_api.h"
75 #include "t4fw_version.h"
76 #include "cxgb4_dcb.h"
77 #include "srq.h"
78 #include "cxgb4_debugfs.h"
79 #include "clip_tbl.h"
80 #include "l2t.h"
81 #include "smt.h"
82 #include "sched.h"
83 #include "cxgb4_tc_u32.h"
84 #include "cxgb4_tc_flower.h"
85 #include "cxgb4_ptp.h"
86 #include "cxgb4_cudbg.h"
87
88 char cxgb4_driver_name[] = KBUILD_MODNAME;
89
90 #ifdef DRV_VERSION
91 #undef DRV_VERSION
92 #endif
93 #define DRV_VERSION "2.0.0-ko"
94 const char cxgb4_driver_version[] = DRV_VERSION;
95 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
96
97 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
98                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
99                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
100
101 /* Macros needed to support the PCI Device ID Table ...
102  */
103 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
104         static const struct pci_device_id cxgb4_pci_tbl[] = {
105 #define CXGB4_UNIFIED_PF 0x4
106
107 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
108
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
110  * called for both.
111  */
112 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
113
114 #define CH_PCI_ID_TABLE_ENTRY(devid) \
115                 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
116
117 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
118                 { 0, } \
119         }
120
121 #include "t4_pci_id_tbl.h"
122
123 #define FW4_FNAME "cxgb4/t4fw.bin"
124 #define FW5_FNAME "cxgb4/t5fw.bin"
125 #define FW6_FNAME "cxgb4/t6fw.bin"
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
129 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
130 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
131 #define PHY_AQ1202_DEVICEID 0x4409
132 #define PHY_BCM84834_DEVICEID 0x4486
133
134 MODULE_DESCRIPTION(DRV_DESC);
135 MODULE_AUTHOR("Chelsio Communications");
136 MODULE_LICENSE("Dual BSD/GPL");
137 MODULE_VERSION(DRV_VERSION);
138 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
139 MODULE_FIRMWARE(FW4_FNAME);
140 MODULE_FIRMWARE(FW5_FNAME);
141 MODULE_FIRMWARE(FW6_FNAME);
142
143 /*
144  * The driver uses the best interrupt scheme available on a platform in the
145  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
146  * of these schemes the driver may consider as follows:
147  *
148  * msi = 2: choose from among all three options
149  * msi = 1: only consider MSI and INTx interrupts
150  * msi = 0: force INTx interrupts
151  */
152 static int msi = 2;
153
154 module_param(msi, int, 0644);
155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
156
157 /*
158  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
159  * offset by 2 bytes in order to have the IP headers line up on 4-byte
160  * boundaries.  This is a requirement for many architectures which will throw
161  * a machine check fault if an attempt is made to access one of the 4-byte IP
162  * header fields on a non-4-byte boundary.  And it's a major performance issue
163  * even on some architectures which allow it like some implementations of the
164  * x86 ISA.  However, some architectures don't mind this and for some very
165  * edge-case performance sensitive applications (like forwarding large volumes
166  * of small packets), setting this DMA offset to 0 will decrease the number of
167  * PCI-E Bus transfers enough to measurably affect performance.
168  */
169 static int rx_dma_offset = 2;
170
171 /* TX Queue select used to determine what algorithm to use for selecting TX
172  * queue. Select between the kernel provided function (select_queue=0) or user
173  * cxgb_select_queue function (select_queue=1)
174  *
175  * Default: select_queue=0
176  */
177 static int select_queue;
178 module_param(select_queue, int, 0644);
179 MODULE_PARM_DESC(select_queue,
180                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
181
182 static struct dentry *cxgb4_debugfs_root;
183
184 LIST_HEAD(adapter_list);
185 DEFINE_MUTEX(uld_mutex);
186
187 static void link_report(struct net_device *dev)
188 {
189         if (!netif_carrier_ok(dev))
190                 netdev_info(dev, "link down\n");
191         else {
192                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
193
194                 const char *s;
195                 const struct port_info *p = netdev_priv(dev);
196
197                 switch (p->link_cfg.speed) {
198                 case 100:
199                         s = "100Mbps";
200                         break;
201                 case 1000:
202                         s = "1Gbps";
203                         break;
204                 case 10000:
205                         s = "10Gbps";
206                         break;
207                 case 25000:
208                         s = "25Gbps";
209                         break;
210                 case 40000:
211                         s = "40Gbps";
212                         break;
213                 case 50000:
214                         s = "50Gbps";
215                         break;
216                 case 100000:
217                         s = "100Gbps";
218                         break;
219                 default:
220                         pr_info("%s: unsupported speed: %d\n",
221                                 dev->name, p->link_cfg.speed);
222                         return;
223                 }
224
225                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
226                             fc[p->link_cfg.fc]);
227         }
228 }
229
230 #ifdef CONFIG_CHELSIO_T4_DCB
231 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
232 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
233 {
234         struct port_info *pi = netdev_priv(dev);
235         struct adapter *adap = pi->adapter;
236         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
237         int i;
238
239         /* We use a simple mapping of Port TX Queue Index to DCB
240          * Priority when we're enabling DCB.
241          */
242         for (i = 0; i < pi->nqsets; i++, txq++) {
243                 u32 name, value;
244                 int err;
245
246                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
247                         FW_PARAMS_PARAM_X_V(
248                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
249                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
250                 value = enable ? i : 0xffffffff;
251
252                 /* Since we can be called while atomic (from "interrupt
253                  * level") we need to issue the Set Parameters Commannd
254                  * without sleeping (timeout < 0).
255                  */
256                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
257                                             &name, &value,
258                                             -FW_CMD_MAX_TIMEOUT);
259
260                 if (err)
261                         dev_err(adap->pdev_dev,
262                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
263                                 enable ? "set" : "unset", pi->port_id, i, -err);
264                 else
265                         txq->dcb_prio = enable ? value : 0;
266         }
267 }
268
269 int cxgb4_dcb_enabled(const struct net_device *dev)
270 {
271         struct port_info *pi = netdev_priv(dev);
272
273         if (!pi->dcb.enabled)
274                 return 0;
275
276         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
277                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
278 }
279 #endif /* CONFIG_CHELSIO_T4_DCB */
280
281 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
282 {
283         struct net_device *dev = adapter->port[port_id];
284
285         /* Skip changes from disabled ports. */
286         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
287                 if (link_stat)
288                         netif_carrier_on(dev);
289                 else {
290 #ifdef CONFIG_CHELSIO_T4_DCB
291                         if (cxgb4_dcb_enabled(dev)) {
292                                 cxgb4_dcb_reset(dev);
293                                 dcb_tx_queue_prio_enable(dev, false);
294                         }
295 #endif /* CONFIG_CHELSIO_T4_DCB */
296                         netif_carrier_off(dev);
297                 }
298
299                 link_report(dev);
300         }
301 }
302
303 void t4_os_portmod_changed(struct adapter *adap, int port_id)
304 {
305         static const char *mod_str[] = {
306                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
307         };
308
309         struct net_device *dev = adap->port[port_id];
310         struct port_info *pi = netdev_priv(dev);
311
312         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
313                 netdev_info(dev, "port module unplugged\n");
314         else if (pi->mod_type < ARRAY_SIZE(mod_str))
315                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
316         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
317                 netdev_info(dev, "%s: unsupported port module inserted\n",
318                             dev->name);
319         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
320                 netdev_info(dev, "%s: unknown port module inserted\n",
321                             dev->name);
322         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
323                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
324         else
325                 netdev_info(dev, "%s: unknown module type %d inserted\n",
326                             dev->name, pi->mod_type);
327
328         /* If the interface is running, then we'll need any "sticky" Link
329          * Parameters redone with a new Transceiver Module.
330          */
331         pi->link_cfg.redo_l1cfg = netif_running(dev);
332 }
333
334 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
335 module_param(dbfifo_int_thresh, int, 0644);
336 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
337
338 /*
339  * usecs to sleep while draining the dbfifo
340  */
341 static int dbfifo_drain_delay = 1000;
342 module_param(dbfifo_drain_delay, int, 0644);
343 MODULE_PARM_DESC(dbfifo_drain_delay,
344                  "usecs to sleep while draining the dbfifo");
345
346 static inline int cxgb4_set_addr_hash(struct port_info *pi)
347 {
348         struct adapter *adap = pi->adapter;
349         u64 vec = 0;
350         bool ucast = false;
351         struct hash_mac_addr *entry;
352
353         /* Calculate the hash vector for the updated list and program it */
354         list_for_each_entry(entry, &adap->mac_hlist, list) {
355                 ucast |= is_unicast_ether_addr(entry->addr);
356                 vec |= (1ULL << hash_mac_addr(entry->addr));
357         }
358         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
359                                 vec, false);
360 }
361
362 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
363 {
364         struct port_info *pi = netdev_priv(netdev);
365         struct adapter *adap = pi->adapter;
366         int ret;
367         u64 mhash = 0;
368         u64 uhash = 0;
369         bool free = false;
370         bool ucast = is_unicast_ether_addr(mac_addr);
371         const u8 *maclist[1] = {mac_addr};
372         struct hash_mac_addr *new_entry;
373
374         ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
375                                 NULL, ucast ? &uhash : &mhash, false);
376         if (ret < 0)
377                 goto out;
378         /* if hash != 0, then add the addr to hash addr list
379          * so on the end we will calculate the hash for the
380          * list and program it
381          */
382         if (uhash || mhash) {
383                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
384                 if (!new_entry)
385                         return -ENOMEM;
386                 ether_addr_copy(new_entry->addr, mac_addr);
387                 list_add_tail(&new_entry->list, &adap->mac_hlist);
388                 ret = cxgb4_set_addr_hash(pi);
389         }
390 out:
391         return ret < 0 ? ret : 0;
392 }
393
394 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
395 {
396         struct port_info *pi = netdev_priv(netdev);
397         struct adapter *adap = pi->adapter;
398         int ret;
399         const u8 *maclist[1] = {mac_addr};
400         struct hash_mac_addr *entry, *tmp;
401
402         /* If the MAC address to be removed is in the hash addr
403          * list, delete it from the list and update hash vector
404          */
405         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
406                 if (ether_addr_equal(entry->addr, mac_addr)) {
407                         list_del(&entry->list);
408                         kfree(entry);
409                         return cxgb4_set_addr_hash(pi);
410                 }
411         }
412
413         ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
414         return ret < 0 ? -EINVAL : 0;
415 }
416
417 /*
418  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
419  * If @mtu is -1 it is left unchanged.
420  */
421 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
422 {
423         struct port_info *pi = netdev_priv(dev);
424         struct adapter *adapter = pi->adapter;
425
426         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
427         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
428
429         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
430                              (dev->flags & IFF_PROMISC) ? 1 : 0,
431                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
432                              sleep_ok);
433 }
434
435 /**
436  *      link_start - enable a port
437  *      @dev: the port to enable
438  *
439  *      Performs the MAC and PHY actions needed to enable a port.
440  */
441 static int link_start(struct net_device *dev)
442 {
443         int ret;
444         struct port_info *pi = netdev_priv(dev);
445         unsigned int mb = pi->adapter->pf;
446
447         /*
448          * We do not set address filters and promiscuity here, the stack does
449          * that step explicitly.
450          */
451         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
452                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
453         if (ret == 0) {
454                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
455                                     pi->xact_addr_filt, dev->dev_addr, true,
456                                     true);
457                 if (ret >= 0) {
458                         pi->xact_addr_filt = ret;
459                         ret = 0;
460                 }
461         }
462         if (ret == 0)
463                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
464                                     &pi->link_cfg);
465         if (ret == 0) {
466                 local_bh_disable();
467                 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
468                                           true, CXGB4_DCB_ENABLED);
469                 local_bh_enable();
470         }
471
472         return ret;
473 }
474
475 #ifdef CONFIG_CHELSIO_T4_DCB
476 /* Handle a Data Center Bridging update message from the firmware. */
477 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
478 {
479         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
480         struct net_device *dev = adap->port[adap->chan_map[port]];
481         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
482         int new_dcb_enabled;
483
484         cxgb4_dcb_handle_fw_update(adap, pcmd);
485         new_dcb_enabled = cxgb4_dcb_enabled(dev);
486
487         /* If the DCB has become enabled or disabled on the port then we're
488          * going to need to set up/tear down DCB Priority parameters for the
489          * TX Queues associated with the port.
490          */
491         if (new_dcb_enabled != old_dcb_enabled)
492                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
493 }
494 #endif /* CONFIG_CHELSIO_T4_DCB */
495
496 /* Response queue handler for the FW event queue.
497  */
498 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
499                           const struct pkt_gl *gl)
500 {
501         u8 opcode = ((const struct rss_header *)rsp)->opcode;
502
503         rsp++;                                          /* skip RSS header */
504
505         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
506          */
507         if (unlikely(opcode == CPL_FW4_MSG &&
508            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
509                 rsp++;
510                 opcode = ((const struct rss_header *)rsp)->opcode;
511                 rsp++;
512                 if (opcode != CPL_SGE_EGR_UPDATE) {
513                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
514                                 , opcode);
515                         goto out;
516                 }
517         }
518
519         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
520                 const struct cpl_sge_egr_update *p = (void *)rsp;
521                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
522                 struct sge_txq *txq;
523
524                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
525                 txq->restarts++;
526                 if (txq->q_type == CXGB4_TXQ_ETH) {
527                         struct sge_eth_txq *eq;
528
529                         eq = container_of(txq, struct sge_eth_txq, q);
530                         netif_tx_wake_queue(eq->txq);
531                 } else {
532                         struct sge_uld_txq *oq;
533
534                         oq = container_of(txq, struct sge_uld_txq, q);
535                         tasklet_schedule(&oq->qresume_tsk);
536                 }
537         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
538                 const struct cpl_fw6_msg *p = (void *)rsp;
539
540 #ifdef CONFIG_CHELSIO_T4_DCB
541                 const struct fw_port_cmd *pcmd = (const void *)p->data;
542                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
543                 unsigned int action =
544                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
545
546                 if (cmd == FW_PORT_CMD &&
547                     (action == FW_PORT_ACTION_GET_PORT_INFO ||
548                      action == FW_PORT_ACTION_GET_PORT_INFO32)) {
549                         int port = FW_PORT_CMD_PORTID_G(
550                                         be32_to_cpu(pcmd->op_to_portid));
551                         struct net_device *dev;
552                         int dcbxdis, state_input;
553
554                         dev = q->adap->port[q->adap->chan_map[port]];
555                         dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
556                           ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
557                           : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
558                                & FW_PORT_CMD_DCBXDIS32_F));
559                         state_input = (dcbxdis
560                                        ? CXGB4_DCB_INPUT_FW_DISABLED
561                                        : CXGB4_DCB_INPUT_FW_ENABLED);
562
563                         cxgb4_dcb_state_fsm(dev, state_input);
564                 }
565
566                 if (cmd == FW_PORT_CMD &&
567                     action == FW_PORT_ACTION_L2_DCB_CFG)
568                         dcb_rpl(q->adap, pcmd);
569                 else
570 #endif
571                         if (p->type == 0)
572                                 t4_handle_fw_rpl(q->adap, p->data);
573         } else if (opcode == CPL_L2T_WRITE_RPL) {
574                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
575
576                 do_l2t_write_rpl(q->adap, p);
577         } else if (opcode == CPL_SMT_WRITE_RPL) {
578                 const struct cpl_smt_write_rpl *p = (void *)rsp;
579
580                 do_smt_write_rpl(q->adap, p);
581         } else if (opcode == CPL_SET_TCB_RPL) {
582                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
583
584                 filter_rpl(q->adap, p);
585         } else if (opcode == CPL_ACT_OPEN_RPL) {
586                 const struct cpl_act_open_rpl *p = (void *)rsp;
587
588                 hash_filter_rpl(q->adap, p);
589         } else if (opcode == CPL_ABORT_RPL_RSS) {
590                 const struct cpl_abort_rpl_rss *p = (void *)rsp;
591
592                 hash_del_filter_rpl(q->adap, p);
593         } else if (opcode == CPL_SRQ_TABLE_RPL) {
594                 const struct cpl_srq_table_rpl *p = (void *)rsp;
595
596                 do_srq_table_rpl(q->adap, p);
597         } else
598                 dev_err(q->adap->pdev_dev,
599                         "unexpected CPL %#x on FW event queue\n", opcode);
600 out:
601         return 0;
602 }
603
604 static void disable_msi(struct adapter *adapter)
605 {
606         if (adapter->flags & USING_MSIX) {
607                 pci_disable_msix(adapter->pdev);
608                 adapter->flags &= ~USING_MSIX;
609         } else if (adapter->flags & USING_MSI) {
610                 pci_disable_msi(adapter->pdev);
611                 adapter->flags &= ~USING_MSI;
612         }
613 }
614
615 /*
616  * Interrupt handler for non-data events used with MSI-X.
617  */
618 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
619 {
620         struct adapter *adap = cookie;
621         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
622
623         if (v & PFSW_F) {
624                 adap->swintr = 1;
625                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
626         }
627         if (adap->flags & MASTER_PF)
628                 t4_slow_intr_handler(adap);
629         return IRQ_HANDLED;
630 }
631
632 /*
633  * Name the MSI-X interrupts.
634  */
635 static void name_msix_vecs(struct adapter *adap)
636 {
637         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
638
639         /* non-data interrupts */
640         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
641
642         /* FW events */
643         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
644                  adap->port[0]->name);
645
646         /* Ethernet queues */
647         for_each_port(adap, j) {
648                 struct net_device *d = adap->port[j];
649                 const struct port_info *pi = netdev_priv(d);
650
651                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
652                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
653                                  d->name, i);
654         }
655 }
656
657 static int request_msix_queue_irqs(struct adapter *adap)
658 {
659         struct sge *s = &adap->sge;
660         int err, ethqidx;
661         int msi_index = 2;
662
663         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
664                           adap->msix_info[1].desc, &s->fw_evtq);
665         if (err)
666                 return err;
667
668         for_each_ethrxq(s, ethqidx) {
669                 err = request_irq(adap->msix_info[msi_index].vec,
670                                   t4_sge_intr_msix, 0,
671                                   adap->msix_info[msi_index].desc,
672                                   &s->ethrxq[ethqidx].rspq);
673                 if (err)
674                         goto unwind;
675                 msi_index++;
676         }
677         return 0;
678
679 unwind:
680         while (--ethqidx >= 0)
681                 free_irq(adap->msix_info[--msi_index].vec,
682                          &s->ethrxq[ethqidx].rspq);
683         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
684         return err;
685 }
686
687 static void free_msix_queue_irqs(struct adapter *adap)
688 {
689         int i, msi_index = 2;
690         struct sge *s = &adap->sge;
691
692         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
693         for_each_ethrxq(s, i)
694                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
695 }
696
697 /**
698  *      cxgb4_write_rss - write the RSS table for a given port
699  *      @pi: the port
700  *      @queues: array of queue indices for RSS
701  *
702  *      Sets up the portion of the HW RSS table for the port's VI to distribute
703  *      packets to the Rx queues in @queues.
704  *      Should never be called before setting up sge eth rx queues
705  */
706 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
707 {
708         u16 *rss;
709         int i, err;
710         struct adapter *adapter = pi->adapter;
711         const struct sge_eth_rxq *rxq;
712
713         rxq = &adapter->sge.ethrxq[pi->first_qset];
714         rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
715         if (!rss)
716                 return -ENOMEM;
717
718         /* map the queue indices to queue ids */
719         for (i = 0; i < pi->rss_size; i++, queues++)
720                 rss[i] = rxq[*queues].rspq.abs_id;
721
722         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
723                                   pi->rss_size, rss, pi->rss_size);
724         /* If Tunnel All Lookup isn't specified in the global RSS
725          * Configuration, then we need to specify a default Ingress
726          * Queue for any ingress packets which aren't hashed.  We'll
727          * use our first ingress queue ...
728          */
729         if (!err)
730                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
731                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
732                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
733                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
734                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
735                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
736                                        rss[0]);
737         kfree(rss);
738         return err;
739 }
740
741 /**
742  *      setup_rss - configure RSS
743  *      @adap: the adapter
744  *
745  *      Sets up RSS for each port.
746  */
747 static int setup_rss(struct adapter *adap)
748 {
749         int i, j, err;
750
751         for_each_port(adap, i) {
752                 const struct port_info *pi = adap2pinfo(adap, i);
753
754                 /* Fill default values with equal distribution */
755                 for (j = 0; j < pi->rss_size; j++)
756                         pi->rss[j] = j % pi->nqsets;
757
758                 err = cxgb4_write_rss(pi, pi->rss);
759                 if (err)
760                         return err;
761         }
762         return 0;
763 }
764
765 /*
766  * Return the channel of the ingress queue with the given qid.
767  */
768 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
769 {
770         qid -= p->ingr_start;
771         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
772 }
773
774 /*
775  * Wait until all NAPI handlers are descheduled.
776  */
777 static void quiesce_rx(struct adapter *adap)
778 {
779         int i;
780
781         for (i = 0; i < adap->sge.ingr_sz; i++) {
782                 struct sge_rspq *q = adap->sge.ingr_map[i];
783
784                 if (q && q->handler)
785                         napi_disable(&q->napi);
786         }
787 }
788
789 /* Disable interrupt and napi handler */
790 static void disable_interrupts(struct adapter *adap)
791 {
792         if (adap->flags & FULL_INIT_DONE) {
793                 t4_intr_disable(adap);
794                 if (adap->flags & USING_MSIX) {
795                         free_msix_queue_irqs(adap);
796                         free_irq(adap->msix_info[0].vec, adap);
797                 } else {
798                         free_irq(adap->pdev->irq, adap);
799                 }
800                 quiesce_rx(adap);
801         }
802 }
803
804 /*
805  * Enable NAPI scheduling and interrupt generation for all Rx queues.
806  */
807 static void enable_rx(struct adapter *adap)
808 {
809         int i;
810
811         for (i = 0; i < adap->sge.ingr_sz; i++) {
812                 struct sge_rspq *q = adap->sge.ingr_map[i];
813
814                 if (!q)
815                         continue;
816                 if (q->handler)
817                         napi_enable(&q->napi);
818
819                 /* 0-increment GTS to start the timer and enable interrupts */
820                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
821                              SEINTARM_V(q->intr_params) |
822                              INGRESSQID_V(q->cntxt_id));
823         }
824 }
825
826
827 static int setup_fw_sge_queues(struct adapter *adap)
828 {
829         struct sge *s = &adap->sge;
830         int err = 0;
831
832         bitmap_zero(s->starving_fl, s->egr_sz);
833         bitmap_zero(s->txq_maperr, s->egr_sz);
834
835         if (adap->flags & USING_MSIX)
836                 adap->msi_idx = 1;         /* vector 0 is for non-queue interrupts */
837         else {
838                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
839                                        NULL, NULL, NULL, -1);
840                 if (err)
841                         return err;
842                 adap->msi_idx = -((int)s->intrq.abs_id + 1);
843         }
844
845         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
846                                adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
847         return err;
848 }
849
850 /**
851  *      setup_sge_queues - configure SGE Tx/Rx/response queues
852  *      @adap: the adapter
853  *
854  *      Determines how many sets of SGE queues to use and initializes them.
855  *      We support multiple queue sets per port if we have MSI-X, otherwise
856  *      just one queue set per port.
857  */
858 static int setup_sge_queues(struct adapter *adap)
859 {
860         int err, i, j;
861         struct sge *s = &adap->sge;
862         struct sge_uld_rxq_info *rxq_info = NULL;
863         unsigned int cmplqid = 0;
864
865         if (is_uld(adap))
866                 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
867
868         for_each_port(adap, i) {
869                 struct net_device *dev = adap->port[i];
870                 struct port_info *pi = netdev_priv(dev);
871                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
872                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
873
874                 for (j = 0; j < pi->nqsets; j++, q++) {
875                         if (adap->msi_idx > 0)
876                                 adap->msi_idx++;
877                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
878                                                adap->msi_idx, &q->fl,
879                                                t4_ethrx_handler,
880                                                NULL,
881                                                t4_get_tp_ch_map(adap,
882                                                                 pi->tx_chan));
883                         if (err)
884                                 goto freeout;
885                         q->rspq.idx = j;
886                         memset(&q->stats, 0, sizeof(q->stats));
887                 }
888                 for (j = 0; j < pi->nqsets; j++, t++) {
889                         err = t4_sge_alloc_eth_txq(adap, t, dev,
890                                         netdev_get_tx_queue(dev, j),
891                                         s->fw_evtq.cntxt_id);
892                         if (err)
893                                 goto freeout;
894                 }
895         }
896
897         for_each_port(adap, i) {
898                 /* Note that cmplqid below is 0 if we don't
899                  * have RDMA queues, and that's the right value.
900                  */
901                 if (rxq_info)
902                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
903
904                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
905                                             s->fw_evtq.cntxt_id, cmplqid);
906                 if (err)
907                         goto freeout;
908         }
909
910         if (!is_t4(adap->params.chip)) {
911                 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
912                                            netdev_get_tx_queue(adap->port[0], 0)
913                                            , s->fw_evtq.cntxt_id);
914                 if (err)
915                         goto freeout;
916         }
917
918         t4_write_reg(adap, is_t4(adap->params.chip) ?
919                                 MPS_TRC_RSS_CONTROL_A :
920                                 MPS_T5_TRC_RSS_CONTROL_A,
921                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
922                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
923         return 0;
924 freeout:
925         dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
926         t4_free_sge_resources(adap);
927         return err;
928 }
929
930 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
931                              struct net_device *sb_dev,
932                              select_queue_fallback_t fallback)
933 {
934         int txq;
935
936 #ifdef CONFIG_CHELSIO_T4_DCB
937         /* If a Data Center Bridging has been successfully negotiated on this
938          * link then we'll use the skb's priority to map it to a TX Queue.
939          * The skb's priority is determined via the VLAN Tag Priority Code
940          * Point field.
941          */
942         if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
943                 u16 vlan_tci;
944                 int err;
945
946                 err = vlan_get_tag(skb, &vlan_tci);
947                 if (unlikely(err)) {
948                         if (net_ratelimit())
949                                 netdev_warn(dev,
950                                             "TX Packet without VLAN Tag on DCB Link\n");
951                         txq = 0;
952                 } else {
953                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
954 #ifdef CONFIG_CHELSIO_T4_FCOE
955                         if (skb->protocol == htons(ETH_P_FCOE))
956                                 txq = skb->priority & 0x7;
957 #endif /* CONFIG_CHELSIO_T4_FCOE */
958                 }
959                 return txq;
960         }
961 #endif /* CONFIG_CHELSIO_T4_DCB */
962
963         if (select_queue) {
964                 txq = (skb_rx_queue_recorded(skb)
965                         ? skb_get_rx_queue(skb)
966                         : smp_processor_id());
967
968                 while (unlikely(txq >= dev->real_num_tx_queues))
969                         txq -= dev->real_num_tx_queues;
970
971                 return txq;
972         }
973
974         return fallback(dev, skb, NULL) % dev->real_num_tx_queues;
975 }
976
977 static int closest_timer(const struct sge *s, int time)
978 {
979         int i, delta, match = 0, min_delta = INT_MAX;
980
981         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
982                 delta = time - s->timer_val[i];
983                 if (delta < 0)
984                         delta = -delta;
985                 if (delta < min_delta) {
986                         min_delta = delta;
987                         match = i;
988                 }
989         }
990         return match;
991 }
992
993 static int closest_thres(const struct sge *s, int thres)
994 {
995         int i, delta, match = 0, min_delta = INT_MAX;
996
997         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
998                 delta = thres - s->counter_val[i];
999                 if (delta < 0)
1000                         delta = -delta;
1001                 if (delta < min_delta) {
1002                         min_delta = delta;
1003                         match = i;
1004                 }
1005         }
1006         return match;
1007 }
1008
1009 /**
1010  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1011  *      @q: the Rx queue
1012  *      @us: the hold-off time in us, or 0 to disable timer
1013  *      @cnt: the hold-off packet count, or 0 to disable counter
1014  *
1015  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
1016  *      one of the two needs to be enabled for the queue to generate interrupts.
1017  */
1018 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1019                                unsigned int us, unsigned int cnt)
1020 {
1021         struct adapter *adap = q->adap;
1022
1023         if ((us | cnt) == 0)
1024                 cnt = 1;
1025
1026         if (cnt) {
1027                 int err;
1028                 u32 v, new_idx;
1029
1030                 new_idx = closest_thres(&adap->sge, cnt);
1031                 if (q->desc && q->pktcnt_idx != new_idx) {
1032                         /* the queue has already been created, update it */
1033                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1034                             FW_PARAMS_PARAM_X_V(
1035                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1036                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1037                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1038                                             &v, &new_idx);
1039                         if (err)
1040                                 return err;
1041                 }
1042                 q->pktcnt_idx = new_idx;
1043         }
1044
1045         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1046         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1047         return 0;
1048 }
1049
1050 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1051 {
1052         const struct port_info *pi = netdev_priv(dev);
1053         netdev_features_t changed = dev->features ^ features;
1054         int err;
1055
1056         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1057                 return 0;
1058
1059         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1060                             -1, -1, -1,
1061                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1062         if (unlikely(err))
1063                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1064         return err;
1065 }
1066
1067 static int setup_debugfs(struct adapter *adap)
1068 {
1069         if (IS_ERR_OR_NULL(adap->debugfs_root))
1070                 return -1;
1071
1072 #ifdef CONFIG_DEBUG_FS
1073         t4_setup_debugfs(adap);
1074 #endif
1075         return 0;
1076 }
1077
1078 /*
1079  * upper-layer driver support
1080  */
1081
1082 /*
1083  * Allocate an active-open TID and set it to the supplied value.
1084  */
1085 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1086 {
1087         int atid = -1;
1088
1089         spin_lock_bh(&t->atid_lock);
1090         if (t->afree) {
1091                 union aopen_entry *p = t->afree;
1092
1093                 atid = (p - t->atid_tab) + t->atid_base;
1094                 t->afree = p->next;
1095                 p->data = data;
1096                 t->atids_in_use++;
1097         }
1098         spin_unlock_bh(&t->atid_lock);
1099         return atid;
1100 }
1101 EXPORT_SYMBOL(cxgb4_alloc_atid);
1102
1103 /*
1104  * Release an active-open TID.
1105  */
1106 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1107 {
1108         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1109
1110         spin_lock_bh(&t->atid_lock);
1111         p->next = t->afree;
1112         t->afree = p;
1113         t->atids_in_use--;
1114         spin_unlock_bh(&t->atid_lock);
1115 }
1116 EXPORT_SYMBOL(cxgb4_free_atid);
1117
1118 /*
1119  * Allocate a server TID and set it to the supplied value.
1120  */
1121 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1122 {
1123         int stid;
1124
1125         spin_lock_bh(&t->stid_lock);
1126         if (family == PF_INET) {
1127                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1128                 if (stid < t->nstids)
1129                         __set_bit(stid, t->stid_bmap);
1130                 else
1131                         stid = -1;
1132         } else {
1133                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1134                 if (stid < 0)
1135                         stid = -1;
1136         }
1137         if (stid >= 0) {
1138                 t->stid_tab[stid].data = data;
1139                 stid += t->stid_base;
1140                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1141                  * This is equivalent to 4 TIDs. With CLIP enabled it
1142                  * needs 2 TIDs.
1143                  */
1144                 if (family == PF_INET6) {
1145                         t->stids_in_use += 2;
1146                         t->v6_stids_in_use += 2;
1147                 } else {
1148                         t->stids_in_use++;
1149                 }
1150         }
1151         spin_unlock_bh(&t->stid_lock);
1152         return stid;
1153 }
1154 EXPORT_SYMBOL(cxgb4_alloc_stid);
1155
1156 /* Allocate a server filter TID and set it to the supplied value.
1157  */
1158 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1159 {
1160         int stid;
1161
1162         spin_lock_bh(&t->stid_lock);
1163         if (family == PF_INET) {
1164                 stid = find_next_zero_bit(t->stid_bmap,
1165                                 t->nstids + t->nsftids, t->nstids);
1166                 if (stid < (t->nstids + t->nsftids))
1167                         __set_bit(stid, t->stid_bmap);
1168                 else
1169                         stid = -1;
1170         } else {
1171                 stid = -1;
1172         }
1173         if (stid >= 0) {
1174                 t->stid_tab[stid].data = data;
1175                 stid -= t->nstids;
1176                 stid += t->sftid_base;
1177                 t->sftids_in_use++;
1178         }
1179         spin_unlock_bh(&t->stid_lock);
1180         return stid;
1181 }
1182 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1183
1184 /* Release a server TID.
1185  */
1186 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1187 {
1188         /* Is it a server filter TID? */
1189         if (t->nsftids && (stid >= t->sftid_base)) {
1190                 stid -= t->sftid_base;
1191                 stid += t->nstids;
1192         } else {
1193                 stid -= t->stid_base;
1194         }
1195
1196         spin_lock_bh(&t->stid_lock);
1197         if (family == PF_INET)
1198                 __clear_bit(stid, t->stid_bmap);
1199         else
1200                 bitmap_release_region(t->stid_bmap, stid, 1);
1201         t->stid_tab[stid].data = NULL;
1202         if (stid < t->nstids) {
1203                 if (family == PF_INET6) {
1204                         t->stids_in_use -= 2;
1205                         t->v6_stids_in_use -= 2;
1206                 } else {
1207                         t->stids_in_use--;
1208                 }
1209         } else {
1210                 t->sftids_in_use--;
1211         }
1212
1213         spin_unlock_bh(&t->stid_lock);
1214 }
1215 EXPORT_SYMBOL(cxgb4_free_stid);
1216
1217 /*
1218  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1219  */
1220 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1221                            unsigned int tid)
1222 {
1223         struct cpl_tid_release *req;
1224
1225         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1226         req = __skb_put(skb, sizeof(*req));
1227         INIT_TP_WR(req, tid);
1228         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1229 }
1230
1231 /*
1232  * Queue a TID release request and if necessary schedule a work queue to
1233  * process it.
1234  */
1235 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1236                                     unsigned int tid)
1237 {
1238         void **p = &t->tid_tab[tid];
1239         struct adapter *adap = container_of(t, struct adapter, tids);
1240
1241         spin_lock_bh(&adap->tid_release_lock);
1242         *p = adap->tid_release_head;
1243         /* Low 2 bits encode the Tx channel number */
1244         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1245         if (!adap->tid_release_task_busy) {
1246                 adap->tid_release_task_busy = true;
1247                 queue_work(adap->workq, &adap->tid_release_task);
1248         }
1249         spin_unlock_bh(&adap->tid_release_lock);
1250 }
1251
1252 /*
1253  * Process the list of pending TID release requests.
1254  */
1255 static void process_tid_release_list(struct work_struct *work)
1256 {
1257         struct sk_buff *skb;
1258         struct adapter *adap;
1259
1260         adap = container_of(work, struct adapter, tid_release_task);
1261
1262         spin_lock_bh(&adap->tid_release_lock);
1263         while (adap->tid_release_head) {
1264                 void **p = adap->tid_release_head;
1265                 unsigned int chan = (uintptr_t)p & 3;
1266                 p = (void *)p - chan;
1267
1268                 adap->tid_release_head = *p;
1269                 *p = NULL;
1270                 spin_unlock_bh(&adap->tid_release_lock);
1271
1272                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1273                                          GFP_KERNEL)))
1274                         schedule_timeout_uninterruptible(1);
1275
1276                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1277                 t4_ofld_send(adap, skb);
1278                 spin_lock_bh(&adap->tid_release_lock);
1279         }
1280         adap->tid_release_task_busy = false;
1281         spin_unlock_bh(&adap->tid_release_lock);
1282 }
1283
1284 /*
1285  * Release a TID and inform HW.  If we are unable to allocate the release
1286  * message we defer to a work queue.
1287  */
1288 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1289                       unsigned short family)
1290 {
1291         struct sk_buff *skb;
1292         struct adapter *adap = container_of(t, struct adapter, tids);
1293
1294         WARN_ON(tid >= t->ntids);
1295
1296         if (t->tid_tab[tid]) {
1297                 t->tid_tab[tid] = NULL;
1298                 atomic_dec(&t->conns_in_use);
1299                 if (t->hash_base && (tid >= t->hash_base)) {
1300                         if (family == AF_INET6)
1301                                 atomic_sub(2, &t->hash_tids_in_use);
1302                         else
1303                                 atomic_dec(&t->hash_tids_in_use);
1304                 } else {
1305                         if (family == AF_INET6)
1306                                 atomic_sub(2, &t->tids_in_use);
1307                         else
1308                                 atomic_dec(&t->tids_in_use);
1309                 }
1310         }
1311
1312         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1313         if (likely(skb)) {
1314                 mk_tid_release(skb, chan, tid);
1315                 t4_ofld_send(adap, skb);
1316         } else
1317                 cxgb4_queue_tid_release(t, chan, tid);
1318 }
1319 EXPORT_SYMBOL(cxgb4_remove_tid);
1320
1321 /*
1322  * Allocate and initialize the TID tables.  Returns 0 on success.
1323  */
1324 static int tid_init(struct tid_info *t)
1325 {
1326         struct adapter *adap = container_of(t, struct adapter, tids);
1327         unsigned int max_ftids = t->nftids + t->nsftids;
1328         unsigned int natids = t->natids;
1329         unsigned int stid_bmap_size;
1330         unsigned int ftid_bmap_size;
1331         size_t size;
1332
1333         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1334         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1335         size = t->ntids * sizeof(*t->tid_tab) +
1336                natids * sizeof(*t->atid_tab) +
1337                t->nstids * sizeof(*t->stid_tab) +
1338                t->nsftids * sizeof(*t->stid_tab) +
1339                stid_bmap_size * sizeof(long) +
1340                max_ftids * sizeof(*t->ftid_tab) +
1341                ftid_bmap_size * sizeof(long);
1342
1343         t->tid_tab = kvzalloc(size, GFP_KERNEL);
1344         if (!t->tid_tab)
1345                 return -ENOMEM;
1346
1347         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1348         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1349         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1350         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1351         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1352         spin_lock_init(&t->stid_lock);
1353         spin_lock_init(&t->atid_lock);
1354         spin_lock_init(&t->ftid_lock);
1355
1356         t->stids_in_use = 0;
1357         t->v6_stids_in_use = 0;
1358         t->sftids_in_use = 0;
1359         t->afree = NULL;
1360         t->atids_in_use = 0;
1361         atomic_set(&t->tids_in_use, 0);
1362         atomic_set(&t->conns_in_use, 0);
1363         atomic_set(&t->hash_tids_in_use, 0);
1364
1365         /* Setup the free list for atid_tab and clear the stid bitmap. */
1366         if (natids) {
1367                 while (--natids)
1368                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1369                 t->afree = t->atid_tab;
1370         }
1371
1372         if (is_offload(adap)) {
1373                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1374                 /* Reserve stid 0 for T4/T5 adapters */
1375                 if (!t->stid_base &&
1376                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1377                         __set_bit(0, t->stid_bmap);
1378         }
1379
1380         bitmap_zero(t->ftid_bmap, t->nftids);
1381         return 0;
1382 }
1383
1384 /**
1385  *      cxgb4_create_server - create an IP server
1386  *      @dev: the device
1387  *      @stid: the server TID
1388  *      @sip: local IP address to bind server to
1389  *      @sport: the server's TCP port
1390  *      @queue: queue to direct messages from this server to
1391  *
1392  *      Create an IP server for the given port and address.
1393  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1394  */
1395 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1396                         __be32 sip, __be16 sport, __be16 vlan,
1397                         unsigned int queue)
1398 {
1399         unsigned int chan;
1400         struct sk_buff *skb;
1401         struct adapter *adap;
1402         struct cpl_pass_open_req *req;
1403         int ret;
1404
1405         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1406         if (!skb)
1407                 return -ENOMEM;
1408
1409         adap = netdev2adap(dev);
1410         req = __skb_put(skb, sizeof(*req));
1411         INIT_TP_WR(req, 0);
1412         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1413         req->local_port = sport;
1414         req->peer_port = htons(0);
1415         req->local_ip = sip;
1416         req->peer_ip = htonl(0);
1417         chan = rxq_to_chan(&adap->sge, queue);
1418         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1419         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1420                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1421         ret = t4_mgmt_tx(adap, skb);
1422         return net_xmit_eval(ret);
1423 }
1424 EXPORT_SYMBOL(cxgb4_create_server);
1425
1426 /*      cxgb4_create_server6 - create an IPv6 server
1427  *      @dev: the device
1428  *      @stid: the server TID
1429  *      @sip: local IPv6 address to bind server to
1430  *      @sport: the server's TCP port
1431  *      @queue: queue to direct messages from this server to
1432  *
1433  *      Create an IPv6 server for the given port and address.
1434  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1435  */
1436 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1437                          const struct in6_addr *sip, __be16 sport,
1438                          unsigned int queue)
1439 {
1440         unsigned int chan;
1441         struct sk_buff *skb;
1442         struct adapter *adap;
1443         struct cpl_pass_open_req6 *req;
1444         int ret;
1445
1446         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1447         if (!skb)
1448                 return -ENOMEM;
1449
1450         adap = netdev2adap(dev);
1451         req = __skb_put(skb, sizeof(*req));
1452         INIT_TP_WR(req, 0);
1453         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1454         req->local_port = sport;
1455         req->peer_port = htons(0);
1456         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1457         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1458         req->peer_ip_hi = cpu_to_be64(0);
1459         req->peer_ip_lo = cpu_to_be64(0);
1460         chan = rxq_to_chan(&adap->sge, queue);
1461         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1462         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1463                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1464         ret = t4_mgmt_tx(adap, skb);
1465         return net_xmit_eval(ret);
1466 }
1467 EXPORT_SYMBOL(cxgb4_create_server6);
1468
1469 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1470                         unsigned int queue, bool ipv6)
1471 {
1472         struct sk_buff *skb;
1473         struct adapter *adap;
1474         struct cpl_close_listsvr_req *req;
1475         int ret;
1476
1477         adap = netdev2adap(dev);
1478
1479         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1480         if (!skb)
1481                 return -ENOMEM;
1482
1483         req = __skb_put(skb, sizeof(*req));
1484         INIT_TP_WR(req, 0);
1485         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1486         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1487                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1488         ret = t4_mgmt_tx(adap, skb);
1489         return net_xmit_eval(ret);
1490 }
1491 EXPORT_SYMBOL(cxgb4_remove_server);
1492
1493 /**
1494  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1495  *      @mtus: the HW MTU table
1496  *      @mtu: the target MTU
1497  *      @idx: index of selected entry in the MTU table
1498  *
1499  *      Returns the index and the value in the HW MTU table that is closest to
1500  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1501  *      table, in which case that smallest available value is selected.
1502  */
1503 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1504                             unsigned int *idx)
1505 {
1506         unsigned int i = 0;
1507
1508         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1509                 ++i;
1510         if (idx)
1511                 *idx = i;
1512         return mtus[i];
1513 }
1514 EXPORT_SYMBOL(cxgb4_best_mtu);
1515
1516 /**
1517  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1518  *     @mtus: the HW MTU table
1519  *     @header_size: Header Size
1520  *     @data_size_max: maximum Data Segment Size
1521  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1522  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1523  *
1524  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1525  *     MTU Table based solely on a Maximum MTU parameter, we break that
1526  *     parameter up into a Header Size and Maximum Data Segment Size, and
1527  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1528  *     the Hardware MTU Table which will result in a Data Segment Size with
1529  *     the requested alignment _and_ that MTU isn't "too far" from the
1530  *     closest MTU, then we'll return that rather than the closest MTU.
1531  */
1532 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1533                                     unsigned short header_size,
1534                                     unsigned short data_size_max,
1535                                     unsigned short data_size_align,
1536                                     unsigned int *mtu_idxp)
1537 {
1538         unsigned short max_mtu = header_size + data_size_max;
1539         unsigned short data_size_align_mask = data_size_align - 1;
1540         int mtu_idx, aligned_mtu_idx;
1541
1542         /* Scan the MTU Table till we find an MTU which is larger than our
1543          * Maximum MTU or we reach the end of the table.  Along the way,
1544          * record the last MTU found, if any, which will result in a Data
1545          * Segment Length matching the requested alignment.
1546          */
1547         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1548                 unsigned short data_size = mtus[mtu_idx] - header_size;
1549
1550                 /* If this MTU minus the Header Size would result in a
1551                  * Data Segment Size of the desired alignment, remember it.
1552                  */
1553                 if ((data_size & data_size_align_mask) == 0)
1554                         aligned_mtu_idx = mtu_idx;
1555
1556                 /* If we're not at the end of the Hardware MTU Table and the
1557                  * next element is larger than our Maximum MTU, drop out of
1558                  * the loop.
1559                  */
1560                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1561                         break;
1562         }
1563
1564         /* If we fell out of the loop because we ran to the end of the table,
1565          * then we just have to use the last [largest] entry.
1566          */
1567         if (mtu_idx == NMTUS)
1568                 mtu_idx--;
1569
1570         /* If we found an MTU which resulted in the requested Data Segment
1571          * Length alignment and that's "not far" from the largest MTU which is
1572          * less than or equal to the maximum MTU, then use that.
1573          */
1574         if (aligned_mtu_idx >= 0 &&
1575             mtu_idx - aligned_mtu_idx <= 1)
1576                 mtu_idx = aligned_mtu_idx;
1577
1578         /* If the caller has passed in an MTU Index pointer, pass the
1579          * MTU Index back.  Return the MTU value.
1580          */
1581         if (mtu_idxp)
1582                 *mtu_idxp = mtu_idx;
1583         return mtus[mtu_idx];
1584 }
1585 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1586
1587 /**
1588  *      cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1589  *      @chip: chip type
1590  *      @viid: VI id of the given port
1591  *
1592  *      Return the SMT index for this VI.
1593  */
1594 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1595 {
1596         /* In T4/T5, SMT contains 256 SMAC entries organized in
1597          * 128 rows of 2 entries each.
1598          * In T6, SMT contains 256 SMAC entries in 256 rows.
1599          * TODO: The below code needs to be updated when we add support
1600          * for 256 VFs.
1601          */
1602         if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1603                 return ((viid & 0x7f) << 1);
1604         else
1605                 return (viid & 0x7f);
1606 }
1607 EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1608
1609 /**
1610  *      cxgb4_port_chan - get the HW channel of a port
1611  *      @dev: the net device for the port
1612  *
1613  *      Return the HW Tx channel of the given port.
1614  */
1615 unsigned int cxgb4_port_chan(const struct net_device *dev)
1616 {
1617         return netdev2pinfo(dev)->tx_chan;
1618 }
1619 EXPORT_SYMBOL(cxgb4_port_chan);
1620
1621 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1622 {
1623         struct adapter *adap = netdev2adap(dev);
1624         u32 v1, v2, lp_count, hp_count;
1625
1626         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1627         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1628         if (is_t4(adap->params.chip)) {
1629                 lp_count = LP_COUNT_G(v1);
1630                 hp_count = HP_COUNT_G(v1);
1631         } else {
1632                 lp_count = LP_COUNT_T5_G(v1);
1633                 hp_count = HP_COUNT_T5_G(v2);
1634         }
1635         return lpfifo ? lp_count : hp_count;
1636 }
1637 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1638
1639 /**
1640  *      cxgb4_port_viid - get the VI id of a port
1641  *      @dev: the net device for the port
1642  *
1643  *      Return the VI id of the given port.
1644  */
1645 unsigned int cxgb4_port_viid(const struct net_device *dev)
1646 {
1647         return netdev2pinfo(dev)->viid;
1648 }
1649 EXPORT_SYMBOL(cxgb4_port_viid);
1650
1651 /**
1652  *      cxgb4_port_idx - get the index of a port
1653  *      @dev: the net device for the port
1654  *
1655  *      Return the index of the given port.
1656  */
1657 unsigned int cxgb4_port_idx(const struct net_device *dev)
1658 {
1659         return netdev2pinfo(dev)->port_id;
1660 }
1661 EXPORT_SYMBOL(cxgb4_port_idx);
1662
1663 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1664                          struct tp_tcp_stats *v6)
1665 {
1666         struct adapter *adap = pci_get_drvdata(pdev);
1667
1668         spin_lock(&adap->stats_lock);
1669         t4_tp_get_tcp_stats(adap, v4, v6, false);
1670         spin_unlock(&adap->stats_lock);
1671 }
1672 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1673
1674 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1675                       const unsigned int *pgsz_order)
1676 {
1677         struct adapter *adap = netdev2adap(dev);
1678
1679         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1680         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1681                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1682                      HPZ3_V(pgsz_order[3]));
1683 }
1684 EXPORT_SYMBOL(cxgb4_iscsi_init);
1685
1686 int cxgb4_flush_eq_cache(struct net_device *dev)
1687 {
1688         struct adapter *adap = netdev2adap(dev);
1689
1690         return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1691 }
1692 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1693
1694 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1695 {
1696         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1697         __be64 indices;
1698         int ret;
1699
1700         spin_lock(&adap->win0_lock);
1701         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1702                            sizeof(indices), (__be32 *)&indices,
1703                            T4_MEMORY_READ);
1704         spin_unlock(&adap->win0_lock);
1705         if (!ret) {
1706                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1707                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1708         }
1709         return ret;
1710 }
1711
1712 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1713                         u16 size)
1714 {
1715         struct adapter *adap = netdev2adap(dev);
1716         u16 hw_pidx, hw_cidx;
1717         int ret;
1718
1719         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1720         if (ret)
1721                 goto out;
1722
1723         if (pidx != hw_pidx) {
1724                 u16 delta;
1725                 u32 val;
1726
1727                 if (pidx >= hw_pidx)
1728                         delta = pidx - hw_pidx;
1729                 else
1730                         delta = size - hw_pidx + pidx;
1731
1732                 if (is_t4(adap->params.chip))
1733                         val = PIDX_V(delta);
1734                 else
1735                         val = PIDX_T5_V(delta);
1736                 wmb();
1737                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1738                              QID_V(qid) | val);
1739         }
1740 out:
1741         return ret;
1742 }
1743 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1744
1745 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1746 {
1747         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1748         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1749         u32 offset, memtype, memaddr;
1750         struct adapter *adap;
1751         u32 hma_size = 0;
1752         int ret;
1753
1754         adap = netdev2adap(dev);
1755
1756         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1757
1758         /* Figure out where the offset lands in the Memory Type/Address scheme.
1759          * This code assumes that the memory is laid out starting at offset 0
1760          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1761          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1762          * MC0, and some have both MC0 and MC1.
1763          */
1764         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1765         edc0_size = EDRAM0_SIZE_G(size) << 20;
1766         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1767         edc1_size = EDRAM1_SIZE_G(size) << 20;
1768         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1769         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1770
1771         if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1772                 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1773                 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1774         }
1775         edc0_end = edc0_size;
1776         edc1_end = edc0_end + edc1_size;
1777         mc0_end = edc1_end + mc0_size;
1778
1779         if (offset < edc0_end) {
1780                 memtype = MEM_EDC0;
1781                 memaddr = offset;
1782         } else if (offset < edc1_end) {
1783                 memtype = MEM_EDC1;
1784                 memaddr = offset - edc0_end;
1785         } else {
1786                 if (hma_size && (offset < (edc1_end + hma_size))) {
1787                         memtype = MEM_HMA;
1788                         memaddr = offset - edc1_end;
1789                 } else if (offset < mc0_end) {
1790                         memtype = MEM_MC0;
1791                         memaddr = offset - edc1_end;
1792                 } else if (is_t5(adap->params.chip)) {
1793                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1794                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1795                         mc1_end = mc0_end + mc1_size;
1796                         if (offset < mc1_end) {
1797                                 memtype = MEM_MC1;
1798                                 memaddr = offset - mc0_end;
1799                         } else {
1800                                 /* offset beyond the end of any memory */
1801                                 goto err;
1802                         }
1803                 } else {
1804                         /* T4/T6 only has a single memory channel */
1805                         goto err;
1806                 }
1807         }
1808
1809         spin_lock(&adap->win0_lock);
1810         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1811         spin_unlock(&adap->win0_lock);
1812         return ret;
1813
1814 err:
1815         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1816                 stag, offset);
1817         return -EINVAL;
1818 }
1819 EXPORT_SYMBOL(cxgb4_read_tpte);
1820
1821 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1822 {
1823         u32 hi, lo;
1824         struct adapter *adap;
1825
1826         adap = netdev2adap(dev);
1827         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1828         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1829
1830         return ((u64)hi << 32) | (u64)lo;
1831 }
1832 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1833
1834 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1835                          unsigned int qid,
1836                          enum cxgb4_bar2_qtype qtype,
1837                          int user,
1838                          u64 *pbar2_qoffset,
1839                          unsigned int *pbar2_qid)
1840 {
1841         return t4_bar2_sge_qregs(netdev2adap(dev),
1842                                  qid,
1843                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
1844                                   ? T4_BAR2_QTYPE_EGRESS
1845                                   : T4_BAR2_QTYPE_INGRESS),
1846                                  user,
1847                                  pbar2_qoffset,
1848                                  pbar2_qid);
1849 }
1850 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1851
1852 static struct pci_driver cxgb4_driver;
1853
1854 static void check_neigh_update(struct neighbour *neigh)
1855 {
1856         const struct device *parent;
1857         const struct net_device *netdev = neigh->dev;
1858
1859         if (is_vlan_dev(netdev))
1860                 netdev = vlan_dev_real_dev(netdev);
1861         parent = netdev->dev.parent;
1862         if (parent && parent->driver == &cxgb4_driver.driver)
1863                 t4_l2t_update(dev_get_drvdata(parent), neigh);
1864 }
1865
1866 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1867                        void *data)
1868 {
1869         switch (event) {
1870         case NETEVENT_NEIGH_UPDATE:
1871                 check_neigh_update(data);
1872                 break;
1873         case NETEVENT_REDIRECT:
1874         default:
1875                 break;
1876         }
1877         return 0;
1878 }
1879
1880 static bool netevent_registered;
1881 static struct notifier_block cxgb4_netevent_nb = {
1882         .notifier_call = netevent_cb
1883 };
1884
1885 static void drain_db_fifo(struct adapter *adap, int usecs)
1886 {
1887         u32 v1, v2, lp_count, hp_count;
1888
1889         do {
1890                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1891                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1892                 if (is_t4(adap->params.chip)) {
1893                         lp_count = LP_COUNT_G(v1);
1894                         hp_count = HP_COUNT_G(v1);
1895                 } else {
1896                         lp_count = LP_COUNT_T5_G(v1);
1897                         hp_count = HP_COUNT_T5_G(v2);
1898                 }
1899
1900                 if (lp_count == 0 && hp_count == 0)
1901                         break;
1902                 set_current_state(TASK_UNINTERRUPTIBLE);
1903                 schedule_timeout(usecs_to_jiffies(usecs));
1904         } while (1);
1905 }
1906
1907 static void disable_txq_db(struct sge_txq *q)
1908 {
1909         unsigned long flags;
1910
1911         spin_lock_irqsave(&q->db_lock, flags);
1912         q->db_disabled = 1;
1913         spin_unlock_irqrestore(&q->db_lock, flags);
1914 }
1915
1916 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
1917 {
1918         spin_lock_irq(&q->db_lock);
1919         if (q->db_pidx_inc) {
1920                 /* Make sure that all writes to the TX descriptors
1921                  * are committed before we tell HW about them.
1922                  */
1923                 wmb();
1924                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1925                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
1926                 q->db_pidx_inc = 0;
1927         }
1928         q->db_disabled = 0;
1929         spin_unlock_irq(&q->db_lock);
1930 }
1931
1932 static void disable_dbs(struct adapter *adap)
1933 {
1934         int i;
1935
1936         for_each_ethrxq(&adap->sge, i)
1937                 disable_txq_db(&adap->sge.ethtxq[i].q);
1938         if (is_offload(adap)) {
1939                 struct sge_uld_txq_info *txq_info =
1940                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1941
1942                 if (txq_info) {
1943                         for_each_ofldtxq(&adap->sge, i) {
1944                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1945
1946                                 disable_txq_db(&txq->q);
1947                         }
1948                 }
1949         }
1950         for_each_port(adap, i)
1951                 disable_txq_db(&adap->sge.ctrlq[i].q);
1952 }
1953
1954 static void enable_dbs(struct adapter *adap)
1955 {
1956         int i;
1957
1958         for_each_ethrxq(&adap->sge, i)
1959                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
1960         if (is_offload(adap)) {
1961                 struct sge_uld_txq_info *txq_info =
1962                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1963
1964                 if (txq_info) {
1965                         for_each_ofldtxq(&adap->sge, i) {
1966                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1967
1968                                 enable_txq_db(adap, &txq->q);
1969                         }
1970                 }
1971         }
1972         for_each_port(adap, i)
1973                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
1974 }
1975
1976 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
1977 {
1978         enum cxgb4_uld type = CXGB4_ULD_RDMA;
1979
1980         if (adap->uld && adap->uld[type].handle)
1981                 adap->uld[type].control(adap->uld[type].handle, cmd);
1982 }
1983
1984 static void process_db_full(struct work_struct *work)
1985 {
1986         struct adapter *adap;
1987
1988         adap = container_of(work, struct adapter, db_full_task);
1989
1990         drain_db_fifo(adap, dbfifo_drain_delay);
1991         enable_dbs(adap);
1992         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
1993         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1994                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1995                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
1996                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
1997         else
1998                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1999                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2000 }
2001
2002 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2003 {
2004         u16 hw_pidx, hw_cidx;
2005         int ret;
2006
2007         spin_lock_irq(&q->db_lock);
2008         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2009         if (ret)
2010                 goto out;
2011         if (q->db_pidx != hw_pidx) {
2012                 u16 delta;
2013                 u32 val;
2014
2015                 if (q->db_pidx >= hw_pidx)
2016                         delta = q->db_pidx - hw_pidx;
2017                 else
2018                         delta = q->size - hw_pidx + q->db_pidx;
2019
2020                 if (is_t4(adap->params.chip))
2021                         val = PIDX_V(delta);
2022                 else
2023                         val = PIDX_T5_V(delta);
2024                 wmb();
2025                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2026                              QID_V(q->cntxt_id) | val);
2027         }
2028 out:
2029         q->db_disabled = 0;
2030         q->db_pidx_inc = 0;
2031         spin_unlock_irq(&q->db_lock);
2032         if (ret)
2033                 CH_WARN(adap, "DB drop recovery failed.\n");
2034 }
2035
2036 static void recover_all_queues(struct adapter *adap)
2037 {
2038         int i;
2039
2040         for_each_ethrxq(&adap->sge, i)
2041                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2042         if (is_offload(adap)) {
2043                 struct sge_uld_txq_info *txq_info =
2044                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2045                 if (txq_info) {
2046                         for_each_ofldtxq(&adap->sge, i) {
2047                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2048
2049                                 sync_txq_pidx(adap, &txq->q);
2050                         }
2051                 }
2052         }
2053         for_each_port(adap, i)
2054                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2055 }
2056
2057 static void process_db_drop(struct work_struct *work)
2058 {
2059         struct adapter *adap;
2060
2061         adap = container_of(work, struct adapter, db_drop_task);
2062
2063         if (is_t4(adap->params.chip)) {
2064                 drain_db_fifo(adap, dbfifo_drain_delay);
2065                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2066                 drain_db_fifo(adap, dbfifo_drain_delay);
2067                 recover_all_queues(adap);
2068                 drain_db_fifo(adap, dbfifo_drain_delay);
2069                 enable_dbs(adap);
2070                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2071         } else if (is_t5(adap->params.chip)) {
2072                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2073                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2074                 u16 pidx_inc = dropped_db & 0x1fff;
2075                 u64 bar2_qoffset;
2076                 unsigned int bar2_qid;
2077                 int ret;
2078
2079                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2080                                         0, &bar2_qoffset, &bar2_qid);
2081                 if (ret)
2082                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2083                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2084                 else
2085                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2086                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2087
2088                 /* Re-enable BAR2 WC */
2089                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2090         }
2091
2092         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2093                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2094 }
2095
2096 void t4_db_full(struct adapter *adap)
2097 {
2098         if (is_t4(adap->params.chip)) {
2099                 disable_dbs(adap);
2100                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2101                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2102                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2103                 queue_work(adap->workq, &adap->db_full_task);
2104         }
2105 }
2106
2107 void t4_db_dropped(struct adapter *adap)
2108 {
2109         if (is_t4(adap->params.chip)) {
2110                 disable_dbs(adap);
2111                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2112         }
2113         queue_work(adap->workq, &adap->db_drop_task);
2114 }
2115
2116 void t4_register_netevent_notifier(void)
2117 {
2118         if (!netevent_registered) {
2119                 register_netevent_notifier(&cxgb4_netevent_nb);
2120                 netevent_registered = true;
2121         }
2122 }
2123
2124 static void detach_ulds(struct adapter *adap)
2125 {
2126         unsigned int i;
2127
2128         mutex_lock(&uld_mutex);
2129         list_del(&adap->list_node);
2130
2131         for (i = 0; i < CXGB4_ULD_MAX; i++)
2132                 if (adap->uld && adap->uld[i].handle)
2133                         adap->uld[i].state_change(adap->uld[i].handle,
2134                                              CXGB4_STATE_DETACH);
2135
2136         if (netevent_registered && list_empty(&adapter_list)) {
2137                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2138                 netevent_registered = false;
2139         }
2140         mutex_unlock(&uld_mutex);
2141 }
2142
2143 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2144 {
2145         unsigned int i;
2146
2147         mutex_lock(&uld_mutex);
2148         for (i = 0; i < CXGB4_ULD_MAX; i++)
2149                 if (adap->uld && adap->uld[i].handle)
2150                         adap->uld[i].state_change(adap->uld[i].handle,
2151                                                   new_state);
2152         mutex_unlock(&uld_mutex);
2153 }
2154
2155 #if IS_ENABLED(CONFIG_IPV6)
2156 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2157                                    unsigned long event, void *data)
2158 {
2159         struct inet6_ifaddr *ifa = data;
2160         struct net_device *event_dev = ifa->idev->dev;
2161         const struct device *parent = NULL;
2162 #if IS_ENABLED(CONFIG_BONDING)
2163         struct adapter *adap;
2164 #endif
2165         if (is_vlan_dev(event_dev))
2166                 event_dev = vlan_dev_real_dev(event_dev);
2167 #if IS_ENABLED(CONFIG_BONDING)
2168         if (event_dev->flags & IFF_MASTER) {
2169                 list_for_each_entry(adap, &adapter_list, list_node) {
2170                         switch (event) {
2171                         case NETDEV_UP:
2172                                 cxgb4_clip_get(adap->port[0],
2173                                                (const u32 *)ifa, 1);
2174                                 break;
2175                         case NETDEV_DOWN:
2176                                 cxgb4_clip_release(adap->port[0],
2177                                                    (const u32 *)ifa, 1);
2178                                 break;
2179                         default:
2180                                 break;
2181                         }
2182                 }
2183                 return NOTIFY_OK;
2184         }
2185 #endif
2186
2187         if (event_dev)
2188                 parent = event_dev->dev.parent;
2189
2190         if (parent && parent->driver == &cxgb4_driver.driver) {
2191                 switch (event) {
2192                 case NETDEV_UP:
2193                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2194                         break;
2195                 case NETDEV_DOWN:
2196                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2197                         break;
2198                 default:
2199                         break;
2200                 }
2201         }
2202         return NOTIFY_OK;
2203 }
2204
2205 static bool inet6addr_registered;
2206 static struct notifier_block cxgb4_inet6addr_notifier = {
2207         .notifier_call = cxgb4_inet6addr_handler
2208 };
2209
2210 static void update_clip(const struct adapter *adap)
2211 {
2212         int i;
2213         struct net_device *dev;
2214         int ret;
2215
2216         rcu_read_lock();
2217
2218         for (i = 0; i < MAX_NPORTS; i++) {
2219                 dev = adap->port[i];
2220                 ret = 0;
2221
2222                 if (dev)
2223                         ret = cxgb4_update_root_dev_clip(dev);
2224
2225                 if (ret < 0)
2226                         break;
2227         }
2228         rcu_read_unlock();
2229 }
2230 #endif /* IS_ENABLED(CONFIG_IPV6) */
2231
2232 /**
2233  *      cxgb_up - enable the adapter
2234  *      @adap: adapter being enabled
2235  *
2236  *      Called when the first port is enabled, this function performs the
2237  *      actions necessary to make an adapter operational, such as completing
2238  *      the initialization of HW modules, and enabling interrupts.
2239  *
2240  *      Must be called with the rtnl lock held.
2241  */
2242 static int cxgb_up(struct adapter *adap)
2243 {
2244         int err;
2245
2246         mutex_lock(&uld_mutex);
2247         err = setup_sge_queues(adap);
2248         if (err)
2249                 goto rel_lock;
2250         err = setup_rss(adap);
2251         if (err)
2252                 goto freeq;
2253
2254         if (adap->flags & USING_MSIX) {
2255                 name_msix_vecs(adap);
2256                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2257                                   adap->msix_info[0].desc, adap);
2258                 if (err)
2259                         goto irq_err;
2260                 err = request_msix_queue_irqs(adap);
2261                 if (err) {
2262                         free_irq(adap->msix_info[0].vec, adap);
2263                         goto irq_err;
2264                 }
2265         } else {
2266                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2267                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2268                                   adap->port[0]->name, adap);
2269                 if (err)
2270                         goto irq_err;
2271         }
2272
2273         enable_rx(adap);
2274         t4_sge_start(adap);
2275         t4_intr_enable(adap);
2276         adap->flags |= FULL_INIT_DONE;
2277         mutex_unlock(&uld_mutex);
2278
2279         notify_ulds(adap, CXGB4_STATE_UP);
2280 #if IS_ENABLED(CONFIG_IPV6)
2281         update_clip(adap);
2282 #endif
2283         /* Initialize hash mac addr list*/
2284         INIT_LIST_HEAD(&adap->mac_hlist);
2285         return err;
2286
2287  irq_err:
2288         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2289  freeq:
2290         t4_free_sge_resources(adap);
2291  rel_lock:
2292         mutex_unlock(&uld_mutex);
2293         return err;
2294 }
2295
2296 static void cxgb_down(struct adapter *adapter)
2297 {
2298         cancel_work_sync(&adapter->tid_release_task);
2299         cancel_work_sync(&adapter->db_full_task);
2300         cancel_work_sync(&adapter->db_drop_task);
2301         adapter->tid_release_task_busy = false;
2302         adapter->tid_release_head = NULL;
2303
2304         t4_sge_stop(adapter);
2305         t4_free_sge_resources(adapter);
2306         adapter->flags &= ~FULL_INIT_DONE;
2307 }
2308
2309 /*
2310  * net_device operations
2311  */
2312 static int cxgb_open(struct net_device *dev)
2313 {
2314         int err;
2315         struct port_info *pi = netdev_priv(dev);
2316         struct adapter *adapter = pi->adapter;
2317
2318         netif_carrier_off(dev);
2319
2320         if (!(adapter->flags & FULL_INIT_DONE)) {
2321                 err = cxgb_up(adapter);
2322                 if (err < 0)
2323                         return err;
2324         }
2325
2326         /* It's possible that the basic port information could have
2327          * changed since we first read it.
2328          */
2329         err = t4_update_port_info(pi);
2330         if (err < 0)
2331                 return err;
2332
2333         err = link_start(dev);
2334         if (!err)
2335                 netif_tx_start_all_queues(dev);
2336         return err;
2337 }
2338
2339 static int cxgb_close(struct net_device *dev)
2340 {
2341         struct port_info *pi = netdev_priv(dev);
2342         struct adapter *adapter = pi->adapter;
2343         int ret;
2344
2345         netif_tx_stop_all_queues(dev);
2346         netif_carrier_off(dev);
2347         ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2348                                   false, false, false);
2349 #ifdef CONFIG_CHELSIO_T4_DCB
2350         cxgb4_dcb_reset(dev);
2351         dcb_tx_queue_prio_enable(dev, false);
2352 #endif
2353         return ret;
2354 }
2355
2356 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2357                 __be32 sip, __be16 sport, __be16 vlan,
2358                 unsigned int queue, unsigned char port, unsigned char mask)
2359 {
2360         int ret;
2361         struct filter_entry *f;
2362         struct adapter *adap;
2363         int i;
2364         u8 *val;
2365
2366         adap = netdev2adap(dev);
2367
2368         /* Adjust stid to correct filter index */
2369         stid -= adap->tids.sftid_base;
2370         stid += adap->tids.nftids;
2371
2372         /* Check to make sure the filter requested is writable ...
2373          */
2374         f = &adap->tids.ftid_tab[stid];
2375         ret = writable_filter(f);
2376         if (ret)
2377                 return ret;
2378
2379         /* Clear out any old resources being used by the filter before
2380          * we start constructing the new filter.
2381          */
2382         if (f->valid)
2383                 clear_filter(adap, f);
2384
2385         /* Clear out filter specifications */
2386         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2387         f->fs.val.lport = cpu_to_be16(sport);
2388         f->fs.mask.lport  = ~0;
2389         val = (u8 *)&sip;
2390         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2391                 for (i = 0; i < 4; i++) {
2392                         f->fs.val.lip[i] = val[i];
2393                         f->fs.mask.lip[i] = ~0;
2394                 }
2395                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2396                         f->fs.val.iport = port;
2397                         f->fs.mask.iport = mask;
2398                 }
2399         }
2400
2401         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2402                 f->fs.val.proto = IPPROTO_TCP;
2403                 f->fs.mask.proto = ~0;
2404         }
2405
2406         f->fs.dirsteer = 1;
2407         f->fs.iq = queue;
2408         /* Mark filter as locked */
2409         f->locked = 1;
2410         f->fs.rpttid = 1;
2411
2412         /* Save the actual tid. We need this to get the corresponding
2413          * filter entry structure in filter_rpl.
2414          */
2415         f->tid = stid + adap->tids.ftid_base;
2416         ret = set_filter_wr(adap, stid);
2417         if (ret) {
2418                 clear_filter(adap, f);
2419                 return ret;
2420         }
2421
2422         return 0;
2423 }
2424 EXPORT_SYMBOL(cxgb4_create_server_filter);
2425
2426 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2427                 unsigned int queue, bool ipv6)
2428 {
2429         struct filter_entry *f;
2430         struct adapter *adap;
2431
2432         adap = netdev2adap(dev);
2433
2434         /* Adjust stid to correct filter index */
2435         stid -= adap->tids.sftid_base;
2436         stid += adap->tids.nftids;
2437
2438         f = &adap->tids.ftid_tab[stid];
2439         /* Unlock the filter */
2440         f->locked = 0;
2441
2442         return delete_filter(adap, stid);
2443 }
2444 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2445
2446 static void cxgb_get_stats(struct net_device *dev,
2447                            struct rtnl_link_stats64 *ns)
2448 {
2449         struct port_stats stats;
2450         struct port_info *p = netdev_priv(dev);
2451         struct adapter *adapter = p->adapter;
2452
2453         /* Block retrieving statistics during EEH error
2454          * recovery. Otherwise, the recovery might fail
2455          * and the PCI device will be removed permanently
2456          */
2457         spin_lock(&adapter->stats_lock);
2458         if (!netif_device_present(dev)) {
2459                 spin_unlock(&adapter->stats_lock);
2460                 return;
2461         }
2462         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2463                                  &p->stats_base);
2464         spin_unlock(&adapter->stats_lock);
2465
2466         ns->tx_bytes   = stats.tx_octets;
2467         ns->tx_packets = stats.tx_frames;
2468         ns->rx_bytes   = stats.rx_octets;
2469         ns->rx_packets = stats.rx_frames;
2470         ns->multicast  = stats.rx_mcast_frames;
2471
2472         /* detailed rx_errors */
2473         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2474                                stats.rx_runt;
2475         ns->rx_over_errors   = 0;
2476         ns->rx_crc_errors    = stats.rx_fcs_err;
2477         ns->rx_frame_errors  = stats.rx_symbol_err;
2478         ns->rx_dropped       = stats.rx_ovflow0 + stats.rx_ovflow1 +
2479                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2480                                stats.rx_trunc0 + stats.rx_trunc1 +
2481                                stats.rx_trunc2 + stats.rx_trunc3;
2482         ns->rx_missed_errors = 0;
2483
2484         /* detailed tx_errors */
2485         ns->tx_aborted_errors   = 0;
2486         ns->tx_carrier_errors   = 0;
2487         ns->tx_fifo_errors      = 0;
2488         ns->tx_heartbeat_errors = 0;
2489         ns->tx_window_errors    = 0;
2490
2491         ns->tx_errors = stats.tx_error_frames;
2492         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2493                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2494 }
2495
2496 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2497 {
2498         unsigned int mbox;
2499         int ret = 0, prtad, devad;
2500         struct port_info *pi = netdev_priv(dev);
2501         struct adapter *adapter = pi->adapter;
2502         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2503
2504         switch (cmd) {
2505         case SIOCGMIIPHY:
2506                 if (pi->mdio_addr < 0)
2507                         return -EOPNOTSUPP;
2508                 data->phy_id = pi->mdio_addr;
2509                 break;
2510         case SIOCGMIIREG:
2511         case SIOCSMIIREG:
2512                 if (mdio_phy_id_is_c45(data->phy_id)) {
2513                         prtad = mdio_phy_id_prtad(data->phy_id);
2514                         devad = mdio_phy_id_devad(data->phy_id);
2515                 } else if (data->phy_id < 32) {
2516                         prtad = data->phy_id;
2517                         devad = 0;
2518                         data->reg_num &= 0x1f;
2519                 } else
2520                         return -EINVAL;
2521
2522                 mbox = pi->adapter->pf;
2523                 if (cmd == SIOCGMIIREG)
2524                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2525                                          data->reg_num, &data->val_out);
2526                 else
2527                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2528                                          data->reg_num, data->val_in);
2529                 break;
2530         case SIOCGHWTSTAMP:
2531                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2532                                     sizeof(pi->tstamp_config)) ?
2533                         -EFAULT : 0;
2534         case SIOCSHWTSTAMP:
2535                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2536                                    sizeof(pi->tstamp_config)))
2537                         return -EFAULT;
2538
2539                 if (!is_t4(adapter->params.chip)) {
2540                         switch (pi->tstamp_config.tx_type) {
2541                         case HWTSTAMP_TX_OFF:
2542                         case HWTSTAMP_TX_ON:
2543                                 break;
2544                         default:
2545                                 return -ERANGE;
2546                         }
2547
2548                         switch (pi->tstamp_config.rx_filter) {
2549                         case HWTSTAMP_FILTER_NONE:
2550                                 pi->rxtstamp = false;
2551                                 break;
2552                         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2553                         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2554                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2555                                                          PTP_TS_L4);
2556                                 break;
2557                         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2558                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2559                                                          PTP_TS_L2_L4);
2560                                 break;
2561                         case HWTSTAMP_FILTER_ALL:
2562                         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2563                         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2564                         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2565                         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2566                                 pi->rxtstamp = true;
2567                                 break;
2568                         default:
2569                                 pi->tstamp_config.rx_filter =
2570                                         HWTSTAMP_FILTER_NONE;
2571                                 return -ERANGE;
2572                         }
2573
2574                         if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2575                             (pi->tstamp_config.rx_filter ==
2576                                 HWTSTAMP_FILTER_NONE)) {
2577                                 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2578                                         pi->ptp_enable = false;
2579                         }
2580
2581                         if (pi->tstamp_config.rx_filter !=
2582                                 HWTSTAMP_FILTER_NONE) {
2583                                 if (cxgb4_ptp_redirect_rx_packet(adapter,
2584                                                                  pi) >= 0)
2585                                         pi->ptp_enable = true;
2586                         }
2587                 } else {
2588                         /* For T4 Adapters */
2589                         switch (pi->tstamp_config.rx_filter) {
2590                         case HWTSTAMP_FILTER_NONE:
2591                         pi->rxtstamp = false;
2592                         break;
2593                         case HWTSTAMP_FILTER_ALL:
2594                         pi->rxtstamp = true;
2595                         break;
2596                         default:
2597                         pi->tstamp_config.rx_filter =
2598                         HWTSTAMP_FILTER_NONE;
2599                         return -ERANGE;
2600                         }
2601                 }
2602                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2603                                     sizeof(pi->tstamp_config)) ?
2604                         -EFAULT : 0;
2605         default:
2606                 return -EOPNOTSUPP;
2607         }
2608         return ret;
2609 }
2610
2611 static void cxgb_set_rxmode(struct net_device *dev)
2612 {
2613         /* unfortunately we can't return errors to the stack */
2614         set_rxmode(dev, -1, false);
2615 }
2616
2617 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2618 {
2619         int ret;
2620         struct port_info *pi = netdev_priv(dev);
2621
2622         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2623                             -1, -1, -1, true);
2624         if (!ret)
2625                 dev->mtu = new_mtu;
2626         return ret;
2627 }
2628
2629 #ifdef CONFIG_PCI_IOV
2630 static int cxgb4_mgmt_open(struct net_device *dev)
2631 {
2632         /* Turn carrier off since we don't have to transmit anything on this
2633          * interface.
2634          */
2635         netif_carrier_off(dev);
2636         return 0;
2637 }
2638
2639 /* Fill MAC address that will be assigned by the FW */
2640 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2641 {
2642         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2643         unsigned int i, vf, nvfs;
2644         u16 a, b;
2645         int err;
2646         u8 *na;
2647
2648         adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2649                                                             PCI_CAP_ID_VPD);
2650         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2651         if (err)
2652                 return;
2653
2654         na = adap->params.vpd.na;
2655         for (i = 0; i < ETH_ALEN; i++)
2656                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2657                               hex2val(na[2 * i + 1]));
2658
2659         a = (hw_addr[0] << 8) | hw_addr[1];
2660         b = (hw_addr[1] << 8) | hw_addr[2];
2661         a ^= b;
2662         a |= 0x0200;    /* locally assigned Ethernet MAC address */
2663         a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2664         macaddr[0] = a >> 8;
2665         macaddr[1] = a & 0xff;
2666
2667         for (i = 2; i < 5; i++)
2668                 macaddr[i] = hw_addr[i + 1];
2669
2670         for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2671                 vf < nvfs; vf++) {
2672                 macaddr[5] = adap->pf * 16 + vf;
2673                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2674         }
2675 }
2676
2677 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2678 {
2679         struct port_info *pi = netdev_priv(dev);
2680         struct adapter *adap = pi->adapter;
2681         int ret;
2682
2683         /* verify MAC addr is valid */
2684         if (!is_valid_ether_addr(mac)) {
2685                 dev_err(pi->adapter->pdev_dev,
2686                         "Invalid Ethernet address %pM for VF %d\n",
2687                         mac, vf);
2688                 return -EINVAL;
2689         }
2690
2691         dev_info(pi->adapter->pdev_dev,
2692                  "Setting MAC %pM on VF %d\n", mac, vf);
2693         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2694         if (!ret)
2695                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2696         return ret;
2697 }
2698
2699 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2700                                     int vf, struct ifla_vf_info *ivi)
2701 {
2702         struct port_info *pi = netdev_priv(dev);
2703         struct adapter *adap = pi->adapter;
2704         struct vf_info *vfinfo;
2705
2706         if (vf >= adap->num_vfs)
2707                 return -EINVAL;
2708         vfinfo = &adap->vfinfo[vf];
2709
2710         ivi->vf = vf;
2711         ivi->max_tx_rate = vfinfo->tx_rate;
2712         ivi->min_tx_rate = 0;
2713         ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2714         ivi->vlan = vfinfo->vlan;
2715         return 0;
2716 }
2717
2718 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2719                                        struct netdev_phys_item_id *ppid)
2720 {
2721         struct port_info *pi = netdev_priv(dev);
2722         unsigned int phy_port_id;
2723
2724         phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2725         ppid->id_len = sizeof(phy_port_id);
2726         memcpy(ppid->id, &phy_port_id, ppid->id_len);
2727         return 0;
2728 }
2729
2730 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2731                                   int min_tx_rate, int max_tx_rate)
2732 {
2733         struct port_info *pi = netdev_priv(dev);
2734         struct adapter *adap = pi->adapter;
2735         unsigned int link_ok, speed, mtu;
2736         u32 fw_pfvf, fw_class;
2737         int class_id = vf;
2738         int ret;
2739         u16 pktsize;
2740
2741         if (vf >= adap->num_vfs)
2742                 return -EINVAL;
2743
2744         if (min_tx_rate) {
2745                 dev_err(adap->pdev_dev,
2746                         "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2747                         min_tx_rate, vf);
2748                 return -EINVAL;
2749         }
2750
2751         if (max_tx_rate == 0) {
2752                 /* unbind VF to to any Traffic Class */
2753                 fw_pfvf =
2754                     (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2755                      FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2756                 fw_class = 0xffffffff;
2757                 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2758                                     &fw_pfvf, &fw_class);
2759                 if (ret) {
2760                         dev_err(adap->pdev_dev,
2761                                 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2762                                 ret, adap->pf, vf);
2763                         return -EINVAL;
2764                 }
2765                 dev_info(adap->pdev_dev,
2766                          "PF %d VF %d is unbound from TX Rate Limiting\n",
2767                          adap->pf, vf);
2768                 adap->vfinfo[vf].tx_rate = 0;
2769                 return 0;
2770         }
2771
2772         ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2773         if (ret != FW_SUCCESS) {
2774                 dev_err(adap->pdev_dev,
2775                         "Failed to get link information for VF %d\n", vf);
2776                 return -EINVAL;
2777         }
2778
2779         if (!link_ok) {
2780                 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2781                 return -EINVAL;
2782         }
2783
2784         if (max_tx_rate > speed) {
2785                 dev_err(adap->pdev_dev,
2786                         "Max tx rate %d for VF %d can't be > link-speed %u",
2787                         max_tx_rate, vf, speed);
2788                 return -EINVAL;
2789         }
2790
2791         pktsize = mtu;
2792         /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2793         pktsize = pktsize - sizeof(struct ethhdr) - 4;
2794         /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2795         pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2796         /* configure Traffic Class for rate-limiting */
2797         ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2798                               SCHED_CLASS_LEVEL_CL_RL,
2799                               SCHED_CLASS_MODE_CLASS,
2800                               SCHED_CLASS_RATEUNIT_BITS,
2801                               SCHED_CLASS_RATEMODE_ABS,
2802                               pi->tx_chan, class_id, 0,
2803                               max_tx_rate * 1000, 0, pktsize);
2804         if (ret) {
2805                 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2806                         ret);
2807                 return -EINVAL;
2808         }
2809         dev_info(adap->pdev_dev,
2810                  "Class %d with MSS %u configured with rate %u\n",
2811                  class_id, pktsize, max_tx_rate);
2812
2813         /* bind VF to configured Traffic Class */
2814         fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2815                    FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2816         fw_class = class_id;
2817         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2818                             &fw_class);
2819         if (ret) {
2820                 dev_err(adap->pdev_dev,
2821                         "Err %d in binding PF %d VF %d to Traffic Class %d\n",
2822                         ret, adap->pf, vf, class_id);
2823                 return -EINVAL;
2824         }
2825         dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2826                  adap->pf, vf, class_id);
2827         adap->vfinfo[vf].tx_rate = max_tx_rate;
2828         return 0;
2829 }
2830
2831 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2832                                   u16 vlan, u8 qos, __be16 vlan_proto)
2833 {
2834         struct port_info *pi = netdev_priv(dev);
2835         struct adapter *adap = pi->adapter;
2836         int ret;
2837
2838         if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2839                 return -EINVAL;
2840
2841         if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2842                 return -EPROTONOSUPPORT;
2843
2844         ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2845         if (!ret) {
2846                 adap->vfinfo[vf].vlan = vlan;
2847                 return 0;
2848         }
2849
2850         dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2851                 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2852         return ret;
2853 }
2854 #endif /* CONFIG_PCI_IOV */
2855
2856 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2857 {
2858         int ret;
2859         struct sockaddr *addr = p;
2860         struct port_info *pi = netdev_priv(dev);
2861
2862         if (!is_valid_ether_addr(addr->sa_data))
2863                 return -EADDRNOTAVAIL;
2864
2865         ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
2866                             pi->xact_addr_filt, addr->sa_data, true, true);
2867         if (ret < 0)
2868                 return ret;
2869
2870         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2871         pi->xact_addr_filt = ret;
2872         return 0;
2873 }
2874
2875 #ifdef CONFIG_NET_POLL_CONTROLLER
2876 static void cxgb_netpoll(struct net_device *dev)
2877 {
2878         struct port_info *pi = netdev_priv(dev);
2879         struct adapter *adap = pi->adapter;
2880
2881         if (adap->flags & USING_MSIX) {
2882                 int i;
2883                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2884
2885                 for (i = pi->nqsets; i; i--, rx++)
2886                         t4_sge_intr_msix(0, &rx->rspq);
2887         } else
2888                 t4_intr_handler(adap)(0, adap);
2889 }
2890 #endif
2891
2892 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2893 {
2894         struct port_info *pi = netdev_priv(dev);
2895         struct adapter *adap = pi->adapter;
2896         struct sched_class *e;
2897         struct ch_sched_params p;
2898         struct ch_sched_queue qe;
2899         u32 req_rate;
2900         int err = 0;
2901
2902         if (!can_sched(dev))
2903                 return -ENOTSUPP;
2904
2905         if (index < 0 || index > pi->nqsets - 1)
2906                 return -EINVAL;
2907
2908         if (!(adap->flags & FULL_INIT_DONE)) {
2909                 dev_err(adap->pdev_dev,
2910                         "Failed to rate limit on queue %d. Link Down?\n",
2911                         index);
2912                 return -EINVAL;
2913         }
2914
2915         /* Convert from Mbps to Kbps */
2916         req_rate = rate * 1000;
2917
2918         /* Max rate is 100 Gbps */
2919         if (req_rate > SCHED_MAX_RATE_KBPS) {
2920                 dev_err(adap->pdev_dev,
2921                         "Invalid rate %u Mbps, Max rate is %u Mbps\n",
2922                         rate, SCHED_MAX_RATE_KBPS / 1000);
2923                 return -ERANGE;
2924         }
2925
2926         /* First unbind the queue from any existing class */
2927         memset(&qe, 0, sizeof(qe));
2928         qe.queue = index;
2929         qe.class = SCHED_CLS_NONE;
2930
2931         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
2932         if (err) {
2933                 dev_err(adap->pdev_dev,
2934                         "Unbinding Queue %d on port %d fail. Err: %d\n",
2935                         index, pi->port_id, err);
2936                 return err;
2937         }
2938
2939         /* Queue already unbound */
2940         if (!req_rate)
2941                 return 0;
2942
2943         /* Fetch any available unused or matching scheduling class */
2944         memset(&p, 0, sizeof(p));
2945         p.type = SCHED_CLASS_TYPE_PACKET;
2946         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
2947         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
2948         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
2949         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
2950         p.u.params.channel  = pi->tx_chan;
2951         p.u.params.class    = SCHED_CLS_NONE;
2952         p.u.params.minrate  = 0;
2953         p.u.params.maxrate  = req_rate;
2954         p.u.params.weight   = 0;
2955         p.u.params.pktsize  = dev->mtu;
2956
2957         e = cxgb4_sched_class_alloc(dev, &p);
2958         if (!e)
2959                 return -ENOMEM;
2960
2961         /* Bind the queue to a scheduling class */
2962         memset(&qe, 0, sizeof(qe));
2963         qe.queue = index;
2964         qe.class = e->idx;
2965
2966         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
2967         if (err)
2968                 dev_err(adap->pdev_dev,
2969                         "Queue rate limiting failed. Err: %d\n", err);
2970         return err;
2971 }
2972
2973 static int cxgb_setup_tc_flower(struct net_device *dev,
2974                                 struct tc_cls_flower_offload *cls_flower)
2975 {
2976         switch (cls_flower->command) {
2977         case TC_CLSFLOWER_REPLACE:
2978                 return cxgb4_tc_flower_replace(dev, cls_flower);
2979         case TC_CLSFLOWER_DESTROY:
2980                 return cxgb4_tc_flower_destroy(dev, cls_flower);
2981         case TC_CLSFLOWER_STATS:
2982                 return cxgb4_tc_flower_stats(dev, cls_flower);
2983         default:
2984                 return -EOPNOTSUPP;
2985         }
2986 }
2987
2988 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
2989                                  struct tc_cls_u32_offload *cls_u32)
2990 {
2991         switch (cls_u32->command) {
2992         case TC_CLSU32_NEW_KNODE:
2993         case TC_CLSU32_REPLACE_KNODE:
2994                 return cxgb4_config_knode(dev, cls_u32);
2995         case TC_CLSU32_DELETE_KNODE:
2996                 return cxgb4_delete_knode(dev, cls_u32);
2997         default:
2998                 return -EOPNOTSUPP;
2999         }
3000 }
3001
3002 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3003                                   void *cb_priv)
3004 {
3005         struct net_device *dev = cb_priv;
3006         struct port_info *pi = netdev2pinfo(dev);
3007         struct adapter *adap = netdev2adap(dev);
3008
3009         if (!(adap->flags & FULL_INIT_DONE)) {
3010                 dev_err(adap->pdev_dev,
3011                         "Failed to setup tc on port %d. Link Down?\n",
3012                         pi->port_id);
3013                 return -EINVAL;
3014         }
3015
3016         if (!tc_cls_can_offload_and_chain0(dev, type_data))
3017                 return -EOPNOTSUPP;
3018
3019         switch (type) {
3020         case TC_SETUP_CLSU32:
3021                 return cxgb_setup_tc_cls_u32(dev, type_data);
3022         case TC_SETUP_CLSFLOWER:
3023                 return cxgb_setup_tc_flower(dev, type_data);
3024         default:
3025                 return -EOPNOTSUPP;
3026         }
3027 }
3028
3029 static int cxgb_setup_tc_block(struct net_device *dev,
3030                                struct tc_block_offload *f)
3031 {
3032         struct port_info *pi = netdev2pinfo(dev);
3033
3034         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3035                 return -EOPNOTSUPP;
3036
3037         switch (f->command) {
3038         case TC_BLOCK_BIND:
3039                 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb,
3040                                              pi, dev, f->extack);
3041         case TC_BLOCK_UNBIND:
3042                 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi);
3043                 return 0;
3044         default:
3045                 return -EOPNOTSUPP;
3046         }
3047 }
3048
3049 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3050                          void *type_data)
3051 {
3052         switch (type) {
3053         case TC_SETUP_BLOCK:
3054                 return cxgb_setup_tc_block(dev, type_data);
3055         default:
3056                 return -EOPNOTSUPP;
3057         }
3058 }
3059
3060 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3061                                 struct udp_tunnel_info *ti)
3062 {
3063         struct port_info *pi = netdev_priv(netdev);
3064         struct adapter *adapter = pi->adapter;
3065         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3066         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3067         int ret = 0, i;
3068
3069         if (chip_ver < CHELSIO_T6)
3070                 return;
3071
3072         switch (ti->type) {
3073         case UDP_TUNNEL_TYPE_VXLAN:
3074                 if (!adapter->vxlan_port_cnt ||
3075                     adapter->vxlan_port != ti->port)
3076                         return; /* Invalid VxLAN destination port */
3077
3078                 adapter->vxlan_port_cnt--;
3079                 if (adapter->vxlan_port_cnt)
3080                         return;
3081
3082                 adapter->vxlan_port = 0;
3083                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3084                 break;
3085         case UDP_TUNNEL_TYPE_GENEVE:
3086                 if (!adapter->geneve_port_cnt ||
3087                     adapter->geneve_port != ti->port)
3088                         return; /* Invalid GENEVE destination port */
3089
3090                 adapter->geneve_port_cnt--;
3091                 if (adapter->geneve_port_cnt)
3092                         return;
3093
3094                 adapter->geneve_port = 0;
3095                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
3096                 break;
3097         default:
3098                 return;
3099         }
3100
3101         /* Matchall mac entries can be deleted only after all tunnel ports
3102          * are brought down or removed.
3103          */
3104         if (!adapter->rawf_cnt)
3105                 return;
3106         for_each_port(adapter, i) {
3107                 pi = adap2pinfo(adapter, i);
3108                 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3109                                            match_all_mac, match_all_mac,
3110                                            adapter->rawf_start +
3111                                             pi->port_id,
3112                                            1, pi->port_id, false);
3113                 if (ret < 0) {
3114                         netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3115                                     i);
3116                         return;
3117                 }
3118                 atomic_dec(&adapter->mps_encap[adapter->rawf_start +
3119                            pi->port_id].refcnt);
3120         }
3121 }
3122
3123 static void cxgb_add_udp_tunnel(struct net_device *netdev,
3124                                 struct udp_tunnel_info *ti)
3125 {
3126         struct port_info *pi = netdev_priv(netdev);
3127         struct adapter *adapter = pi->adapter;
3128         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3129         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3130         int i, ret;
3131
3132         if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
3133                 return;