cxgb4: Fix error path in cxgb4_init_module
[muen/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
1 /*
2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3  *
4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <linux/uaccess.h>
66 #include <linux/crash_dump.h>
67 #include <net/udp_tunnel.h>
68
69 #include "cxgb4.h"
70 #include "cxgb4_filter.h"
71 #include "t4_regs.h"
72 #include "t4_values.h"
73 #include "t4_msg.h"
74 #include "t4fw_api.h"
75 #include "t4fw_version.h"
76 #include "cxgb4_dcb.h"
77 #include "srq.h"
78 #include "cxgb4_debugfs.h"
79 #include "clip_tbl.h"
80 #include "l2t.h"
81 #include "smt.h"
82 #include "sched.h"
83 #include "cxgb4_tc_u32.h"
84 #include "cxgb4_tc_flower.h"
85 #include "cxgb4_ptp.h"
86 #include "cxgb4_cudbg.h"
87
88 char cxgb4_driver_name[] = KBUILD_MODNAME;
89
90 #ifdef DRV_VERSION
91 #undef DRV_VERSION
92 #endif
93 #define DRV_VERSION "2.0.0-ko"
94 const char cxgb4_driver_version[] = DRV_VERSION;
95 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
96
97 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
98                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
99                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
100
101 /* Macros needed to support the PCI Device ID Table ...
102  */
103 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
104         static const struct pci_device_id cxgb4_pci_tbl[] = {
105 #define CXGB4_UNIFIED_PF 0x4
106
107 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
108
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
110  * called for both.
111  */
112 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
113
114 #define CH_PCI_ID_TABLE_ENTRY(devid) \
115                 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
116
117 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
118                 { 0, } \
119         }
120
121 #include "t4_pci_id_tbl.h"
122
123 #define FW4_FNAME "cxgb4/t4fw.bin"
124 #define FW5_FNAME "cxgb4/t5fw.bin"
125 #define FW6_FNAME "cxgb4/t6fw.bin"
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
129 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
130 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
131 #define PHY_AQ1202_DEVICEID 0x4409
132 #define PHY_BCM84834_DEVICEID 0x4486
133
134 MODULE_DESCRIPTION(DRV_DESC);
135 MODULE_AUTHOR("Chelsio Communications");
136 MODULE_LICENSE("Dual BSD/GPL");
137 MODULE_VERSION(DRV_VERSION);
138 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
139 MODULE_FIRMWARE(FW4_FNAME);
140 MODULE_FIRMWARE(FW5_FNAME);
141 MODULE_FIRMWARE(FW6_FNAME);
142
143 /*
144  * The driver uses the best interrupt scheme available on a platform in the
145  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
146  * of these schemes the driver may consider as follows:
147  *
148  * msi = 2: choose from among all three options
149  * msi = 1: only consider MSI and INTx interrupts
150  * msi = 0: force INTx interrupts
151  */
152 static int msi = 2;
153
154 module_param(msi, int, 0644);
155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
156
157 /*
158  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
159  * offset by 2 bytes in order to have the IP headers line up on 4-byte
160  * boundaries.  This is a requirement for many architectures which will throw
161  * a machine check fault if an attempt is made to access one of the 4-byte IP
162  * header fields on a non-4-byte boundary.  And it's a major performance issue
163  * even on some architectures which allow it like some implementations of the
164  * x86 ISA.  However, some architectures don't mind this and for some very
165  * edge-case performance sensitive applications (like forwarding large volumes
166  * of small packets), setting this DMA offset to 0 will decrease the number of
167  * PCI-E Bus transfers enough to measurably affect performance.
168  */
169 static int rx_dma_offset = 2;
170
171 /* TX Queue select used to determine what algorithm to use for selecting TX
172  * queue. Select between the kernel provided function (select_queue=0) or user
173  * cxgb_select_queue function (select_queue=1)
174  *
175  * Default: select_queue=0
176  */
177 static int select_queue;
178 module_param(select_queue, int, 0644);
179 MODULE_PARM_DESC(select_queue,
180                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
181
182 static struct dentry *cxgb4_debugfs_root;
183
184 LIST_HEAD(adapter_list);
185 DEFINE_MUTEX(uld_mutex);
186
187 static void link_report(struct net_device *dev)
188 {
189         if (!netif_carrier_ok(dev))
190                 netdev_info(dev, "link down\n");
191         else {
192                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
193
194                 const char *s;
195                 const struct port_info *p = netdev_priv(dev);
196
197                 switch (p->link_cfg.speed) {
198                 case 100:
199                         s = "100Mbps";
200                         break;
201                 case 1000:
202                         s = "1Gbps";
203                         break;
204                 case 10000:
205                         s = "10Gbps";
206                         break;
207                 case 25000:
208                         s = "25Gbps";
209                         break;
210                 case 40000:
211                         s = "40Gbps";
212                         break;
213                 case 50000:
214                         s = "50Gbps";
215                         break;
216                 case 100000:
217                         s = "100Gbps";
218                         break;
219                 default:
220                         pr_info("%s: unsupported speed: %d\n",
221                                 dev->name, p->link_cfg.speed);
222                         return;
223                 }
224
225                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
226                             fc[p->link_cfg.fc]);
227         }
228 }
229
230 #ifdef CONFIG_CHELSIO_T4_DCB
231 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
232 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
233 {
234         struct port_info *pi = netdev_priv(dev);
235         struct adapter *adap = pi->adapter;
236         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
237         int i;
238
239         /* We use a simple mapping of Port TX Queue Index to DCB
240          * Priority when we're enabling DCB.
241          */
242         for (i = 0; i < pi->nqsets; i++, txq++) {
243                 u32 name, value;
244                 int err;
245
246                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
247                         FW_PARAMS_PARAM_X_V(
248                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
249                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
250                 value = enable ? i : 0xffffffff;
251
252                 /* Since we can be called while atomic (from "interrupt
253                  * level") we need to issue the Set Parameters Commannd
254                  * without sleeping (timeout < 0).
255                  */
256                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
257                                             &name, &value,
258                                             -FW_CMD_MAX_TIMEOUT);
259
260                 if (err)
261                         dev_err(adap->pdev_dev,
262                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
263                                 enable ? "set" : "unset", pi->port_id, i, -err);
264                 else
265                         txq->dcb_prio = enable ? value : 0;
266         }
267 }
268
269 int cxgb4_dcb_enabled(const struct net_device *dev)
270 {
271         struct port_info *pi = netdev_priv(dev);
272
273         if (!pi->dcb.enabled)
274                 return 0;
275
276         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
277                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
278 }
279 #endif /* CONFIG_CHELSIO_T4_DCB */
280
281 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
282 {
283         struct net_device *dev = adapter->port[port_id];
284
285         /* Skip changes from disabled ports. */
286         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
287                 if (link_stat)
288                         netif_carrier_on(dev);
289                 else {
290 #ifdef CONFIG_CHELSIO_T4_DCB
291                         if (cxgb4_dcb_enabled(dev)) {
292                                 cxgb4_dcb_reset(dev);
293                                 dcb_tx_queue_prio_enable(dev, false);
294                         }
295 #endif /* CONFIG_CHELSIO_T4_DCB */
296                         netif_carrier_off(dev);
297                 }
298
299                 link_report(dev);
300         }
301 }
302
303 void t4_os_portmod_changed(struct adapter *adap, int port_id)
304 {
305         static const char *mod_str[] = {
306                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
307         };
308
309         struct net_device *dev = adap->port[port_id];
310         struct port_info *pi = netdev_priv(dev);
311
312         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
313                 netdev_info(dev, "port module unplugged\n");
314         else if (pi->mod_type < ARRAY_SIZE(mod_str))
315                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
316         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
317                 netdev_info(dev, "%s: unsupported port module inserted\n",
318                             dev->name);
319         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
320                 netdev_info(dev, "%s: unknown port module inserted\n",
321                             dev->name);
322         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
323                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
324         else
325                 netdev_info(dev, "%s: unknown module type %d inserted\n",
326                             dev->name, pi->mod_type);
327
328         /* If the interface is running, then we'll need any "sticky" Link
329          * Parameters redone with a new Transceiver Module.
330          */
331         pi->link_cfg.redo_l1cfg = netif_running(dev);
332 }
333
334 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
335 module_param(dbfifo_int_thresh, int, 0644);
336 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
337
338 /*
339  * usecs to sleep while draining the dbfifo
340  */
341 static int dbfifo_drain_delay = 1000;
342 module_param(dbfifo_drain_delay, int, 0644);
343 MODULE_PARM_DESC(dbfifo_drain_delay,
344                  "usecs to sleep while draining the dbfifo");
345
346 static inline int cxgb4_set_addr_hash(struct port_info *pi)
347 {
348         struct adapter *adap = pi->adapter;
349         u64 vec = 0;
350         bool ucast = false;
351         struct hash_mac_addr *entry;
352
353         /* Calculate the hash vector for the updated list and program it */
354         list_for_each_entry(entry, &adap->mac_hlist, list) {
355                 ucast |= is_unicast_ether_addr(entry->addr);
356                 vec |= (1ULL << hash_mac_addr(entry->addr));
357         }
358         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
359                                 vec, false);
360 }
361
362 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
363 {
364         struct port_info *pi = netdev_priv(netdev);
365         struct adapter *adap = pi->adapter;
366         int ret;
367         u64 mhash = 0;
368         u64 uhash = 0;
369         bool free = false;
370         bool ucast = is_unicast_ether_addr(mac_addr);
371         const u8 *maclist[1] = {mac_addr};
372         struct hash_mac_addr *new_entry;
373
374         ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
375                                 NULL, ucast ? &uhash : &mhash, false);
376         if (ret < 0)
377                 goto out;
378         /* if hash != 0, then add the addr to hash addr list
379          * so on the end we will calculate the hash for the
380          * list and program it
381          */
382         if (uhash || mhash) {
383                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
384                 if (!new_entry)
385                         return -ENOMEM;
386                 ether_addr_copy(new_entry->addr, mac_addr);
387                 list_add_tail(&new_entry->list, &adap->mac_hlist);
388                 ret = cxgb4_set_addr_hash(pi);
389         }
390 out:
391         return ret < 0 ? ret : 0;
392 }
393
394 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
395 {
396         struct port_info *pi = netdev_priv(netdev);
397         struct adapter *adap = pi->adapter;
398         int ret;
399         const u8 *maclist[1] = {mac_addr};
400         struct hash_mac_addr *entry, *tmp;
401
402         /* If the MAC address to be removed is in the hash addr
403          * list, delete it from the list and update hash vector
404          */
405         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
406                 if (ether_addr_equal(entry->addr, mac_addr)) {
407                         list_del(&entry->list);
408                         kfree(entry);
409                         return cxgb4_set_addr_hash(pi);
410                 }
411         }
412
413         ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
414         return ret < 0 ? -EINVAL : 0;
415 }
416
417 /*
418  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
419  * If @mtu is -1 it is left unchanged.
420  */
421 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
422 {
423         struct port_info *pi = netdev_priv(dev);
424         struct adapter *adapter = pi->adapter;
425
426         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
427         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
428
429         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
430                              (dev->flags & IFF_PROMISC) ? 1 : 0,
431                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
432                              sleep_ok);
433 }
434
435 /**
436  *      cxgb4_change_mac - Update match filter for a MAC address.
437  *      @pi: the port_info
438  *      @viid: the VI id
439  *      @tcam_idx: TCAM index of existing filter for old value of MAC address,
440  *                 or -1
441  *      @addr: the new MAC address value
442  *      @persist: whether a new MAC allocation should be persistent
443  *      @add_smt: if true also add the address to the HW SMT
444  *
445  *      Modifies an MPS filter and sets it to the new MAC address if
446  *      @tcam_idx >= 0, or adds the MAC address to a new filter if
447  *      @tcam_idx < 0. In the latter case the address is added persistently
448  *      if @persist is %true.
449  *      Addresses are programmed to hash region, if tcam runs out of entries.
450  *
451  */
452 static int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
453                             int *tcam_idx, const u8 *addr, bool persist,
454                             u8 *smt_idx)
455 {
456         struct adapter *adapter = pi->adapter;
457         struct hash_mac_addr *entry, *new_entry;
458         int ret;
459
460         ret = t4_change_mac(adapter, adapter->mbox, viid,
461                             *tcam_idx, addr, persist, smt_idx);
462         /* We ran out of TCAM entries. try programming hash region. */
463         if (ret == -ENOMEM) {
464                 /* If the MAC address to be updated is in the hash addr
465                  * list, update it from the list
466                  */
467                 list_for_each_entry(entry, &adapter->mac_hlist, list) {
468                         if (entry->iface_mac) {
469                                 ether_addr_copy(entry->addr, addr);
470                                 goto set_hash;
471                         }
472                 }
473                 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
474                 if (!new_entry)
475                         return -ENOMEM;
476                 ether_addr_copy(new_entry->addr, addr);
477                 new_entry->iface_mac = true;
478                 list_add_tail(&new_entry->list, &adapter->mac_hlist);
479 set_hash:
480                 ret = cxgb4_set_addr_hash(pi);
481         } else if (ret >= 0) {
482                 *tcam_idx = ret;
483                 ret = 0;
484         }
485
486         return ret;
487 }
488
489 /*
490  *      link_start - enable a port
491  *      @dev: the port to enable
492  *
493  *      Performs the MAC and PHY actions needed to enable a port.
494  */
495 static int link_start(struct net_device *dev)
496 {
497         int ret;
498         struct port_info *pi = netdev_priv(dev);
499         unsigned int mb = pi->adapter->pf;
500
501         /*
502          * We do not set address filters and promiscuity here, the stack does
503          * that step explicitly.
504          */
505         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
506                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
507         if (ret == 0)
508                 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
509                                        dev->dev_addr, true, &pi->smt_idx);
510         if (ret == 0)
511                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
512                                     &pi->link_cfg);
513         if (ret == 0) {
514                 local_bh_disable();
515                 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
516                                           true, CXGB4_DCB_ENABLED);
517                 local_bh_enable();
518         }
519
520         return ret;
521 }
522
523 #ifdef CONFIG_CHELSIO_T4_DCB
524 /* Handle a Data Center Bridging update message from the firmware. */
525 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
526 {
527         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
528         struct net_device *dev = adap->port[adap->chan_map[port]];
529         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
530         int new_dcb_enabled;
531
532         cxgb4_dcb_handle_fw_update(adap, pcmd);
533         new_dcb_enabled = cxgb4_dcb_enabled(dev);
534
535         /* If the DCB has become enabled or disabled on the port then we're
536          * going to need to set up/tear down DCB Priority parameters for the
537          * TX Queues associated with the port.
538          */
539         if (new_dcb_enabled != old_dcb_enabled)
540                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
541 }
542 #endif /* CONFIG_CHELSIO_T4_DCB */
543
544 /* Response queue handler for the FW event queue.
545  */
546 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
547                           const struct pkt_gl *gl)
548 {
549         u8 opcode = ((const struct rss_header *)rsp)->opcode;
550
551         rsp++;                                          /* skip RSS header */
552
553         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
554          */
555         if (unlikely(opcode == CPL_FW4_MSG &&
556            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
557                 rsp++;
558                 opcode = ((const struct rss_header *)rsp)->opcode;
559                 rsp++;
560                 if (opcode != CPL_SGE_EGR_UPDATE) {
561                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
562                                 , opcode);
563                         goto out;
564                 }
565         }
566
567         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
568                 const struct cpl_sge_egr_update *p = (void *)rsp;
569                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
570                 struct sge_txq *txq;
571
572                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
573                 txq->restarts++;
574                 if (txq->q_type == CXGB4_TXQ_ETH) {
575                         struct sge_eth_txq *eq;
576
577                         eq = container_of(txq, struct sge_eth_txq, q);
578                         t4_sge_eth_txq_egress_update(q->adap, eq, -1);
579                 } else {
580                         struct sge_uld_txq *oq;
581
582                         oq = container_of(txq, struct sge_uld_txq, q);
583                         tasklet_schedule(&oq->qresume_tsk);
584                 }
585         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
586                 const struct cpl_fw6_msg *p = (void *)rsp;
587
588 #ifdef CONFIG_CHELSIO_T4_DCB
589                 const struct fw_port_cmd *pcmd = (const void *)p->data;
590                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
591                 unsigned int action =
592                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
593
594                 if (cmd == FW_PORT_CMD &&
595                     (action == FW_PORT_ACTION_GET_PORT_INFO ||
596                      action == FW_PORT_ACTION_GET_PORT_INFO32)) {
597                         int port = FW_PORT_CMD_PORTID_G(
598                                         be32_to_cpu(pcmd->op_to_portid));
599                         struct net_device *dev;
600                         int dcbxdis, state_input;
601
602                         dev = q->adap->port[q->adap->chan_map[port]];
603                         dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
604                           ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
605                           : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
606                                & FW_PORT_CMD_DCBXDIS32_F));
607                         state_input = (dcbxdis
608                                        ? CXGB4_DCB_INPUT_FW_DISABLED
609                                        : CXGB4_DCB_INPUT_FW_ENABLED);
610
611                         cxgb4_dcb_state_fsm(dev, state_input);
612                 }
613
614                 if (cmd == FW_PORT_CMD &&
615                     action == FW_PORT_ACTION_L2_DCB_CFG)
616                         dcb_rpl(q->adap, pcmd);
617                 else
618 #endif
619                         if (p->type == 0)
620                                 t4_handle_fw_rpl(q->adap, p->data);
621         } else if (opcode == CPL_L2T_WRITE_RPL) {
622                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
623
624                 do_l2t_write_rpl(q->adap, p);
625         } else if (opcode == CPL_SMT_WRITE_RPL) {
626                 const struct cpl_smt_write_rpl *p = (void *)rsp;
627
628                 do_smt_write_rpl(q->adap, p);
629         } else if (opcode == CPL_SET_TCB_RPL) {
630                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
631
632                 filter_rpl(q->adap, p);
633         } else if (opcode == CPL_ACT_OPEN_RPL) {
634                 const struct cpl_act_open_rpl *p = (void *)rsp;
635
636                 hash_filter_rpl(q->adap, p);
637         } else if (opcode == CPL_ABORT_RPL_RSS) {
638                 const struct cpl_abort_rpl_rss *p = (void *)rsp;
639
640                 hash_del_filter_rpl(q->adap, p);
641         } else if (opcode == CPL_SRQ_TABLE_RPL) {
642                 const struct cpl_srq_table_rpl *p = (void *)rsp;
643
644                 do_srq_table_rpl(q->adap, p);
645         } else
646                 dev_err(q->adap->pdev_dev,
647                         "unexpected CPL %#x on FW event queue\n", opcode);
648 out:
649         return 0;
650 }
651
652 static void disable_msi(struct adapter *adapter)
653 {
654         if (adapter->flags & CXGB4_USING_MSIX) {
655                 pci_disable_msix(adapter->pdev);
656                 adapter->flags &= ~CXGB4_USING_MSIX;
657         } else if (adapter->flags & CXGB4_USING_MSI) {
658                 pci_disable_msi(adapter->pdev);
659                 adapter->flags &= ~CXGB4_USING_MSI;
660         }
661 }
662
663 /*
664  * Interrupt handler for non-data events used with MSI-X.
665  */
666 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
667 {
668         struct adapter *adap = cookie;
669         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
670
671         if (v & PFSW_F) {
672                 adap->swintr = 1;
673                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
674         }
675         if (adap->flags & CXGB4_MASTER_PF)
676                 t4_slow_intr_handler(adap);
677         return IRQ_HANDLED;
678 }
679
680 /*
681  * Name the MSI-X interrupts.
682  */
683 static void name_msix_vecs(struct adapter *adap)
684 {
685         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
686
687         /* non-data interrupts */
688         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
689
690         /* FW events */
691         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
692                  adap->port[0]->name);
693
694         /* Ethernet queues */
695         for_each_port(adap, j) {
696                 struct net_device *d = adap->port[j];
697                 const struct port_info *pi = netdev_priv(d);
698
699                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
700                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
701                                  d->name, i);
702         }
703 }
704
705 static int request_msix_queue_irqs(struct adapter *adap)
706 {
707         struct sge *s = &adap->sge;
708         int err, ethqidx;
709         int msi_index = 2;
710
711         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
712                           adap->msix_info[1].desc, &s->fw_evtq);
713         if (err)
714                 return err;
715
716         for_each_ethrxq(s, ethqidx) {
717                 err = request_irq(adap->msix_info[msi_index].vec,
718                                   t4_sge_intr_msix, 0,
719                                   adap->msix_info[msi_index].desc,
720                                   &s->ethrxq[ethqidx].rspq);
721                 if (err)
722                         goto unwind;
723                 msi_index++;
724         }
725         return 0;
726
727 unwind:
728         while (--ethqidx >= 0)
729                 free_irq(adap->msix_info[--msi_index].vec,
730                          &s->ethrxq[ethqidx].rspq);
731         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
732         return err;
733 }
734
735 static void free_msix_queue_irqs(struct adapter *adap)
736 {
737         int i, msi_index = 2;
738         struct sge *s = &adap->sge;
739
740         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
741         for_each_ethrxq(s, i)
742                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
743 }
744
745 /**
746  *      cxgb4_write_rss - write the RSS table for a given port
747  *      @pi: the port
748  *      @queues: array of queue indices for RSS
749  *
750  *      Sets up the portion of the HW RSS table for the port's VI to distribute
751  *      packets to the Rx queues in @queues.
752  *      Should never be called before setting up sge eth rx queues
753  */
754 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
755 {
756         u16 *rss;
757         int i, err;
758         struct adapter *adapter = pi->adapter;
759         const struct sge_eth_rxq *rxq;
760
761         rxq = &adapter->sge.ethrxq[pi->first_qset];
762         rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
763         if (!rss)
764                 return -ENOMEM;
765
766         /* map the queue indices to queue ids */
767         for (i = 0; i < pi->rss_size; i++, queues++)
768                 rss[i] = rxq[*queues].rspq.abs_id;
769
770         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
771                                   pi->rss_size, rss, pi->rss_size);
772         /* If Tunnel All Lookup isn't specified in the global RSS
773          * Configuration, then we need to specify a default Ingress
774          * Queue for any ingress packets which aren't hashed.  We'll
775          * use our first ingress queue ...
776          */
777         if (!err)
778                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
779                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
780                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
781                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
782                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
783                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
784                                        rss[0]);
785         kfree(rss);
786         return err;
787 }
788
789 /**
790  *      setup_rss - configure RSS
791  *      @adap: the adapter
792  *
793  *      Sets up RSS for each port.
794  */
795 static int setup_rss(struct adapter *adap)
796 {
797         int i, j, err;
798
799         for_each_port(adap, i) {
800                 const struct port_info *pi = adap2pinfo(adap, i);
801
802                 /* Fill default values with equal distribution */
803                 for (j = 0; j < pi->rss_size; j++)
804                         pi->rss[j] = j % pi->nqsets;
805
806                 err = cxgb4_write_rss(pi, pi->rss);
807                 if (err)
808                         return err;
809         }
810         return 0;
811 }
812
813 /*
814  * Return the channel of the ingress queue with the given qid.
815  */
816 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
817 {
818         qid -= p->ingr_start;
819         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
820 }
821
822 /*
823  * Wait until all NAPI handlers are descheduled.
824  */
825 static void quiesce_rx(struct adapter *adap)
826 {
827         int i;
828
829         for (i = 0; i < adap->sge.ingr_sz; i++) {
830                 struct sge_rspq *q = adap->sge.ingr_map[i];
831
832                 if (q && q->handler)
833                         napi_disable(&q->napi);
834         }
835 }
836
837 /* Disable interrupt and napi handler */
838 static void disable_interrupts(struct adapter *adap)
839 {
840         if (adap->flags & CXGB4_FULL_INIT_DONE) {
841                 t4_intr_disable(adap);
842                 if (adap->flags & CXGB4_USING_MSIX) {
843                         free_msix_queue_irqs(adap);
844                         free_irq(adap->msix_info[0].vec, adap);
845                 } else {
846                         free_irq(adap->pdev->irq, adap);
847                 }
848                 quiesce_rx(adap);
849         }
850 }
851
852 /*
853  * Enable NAPI scheduling and interrupt generation for all Rx queues.
854  */
855 static void enable_rx(struct adapter *adap)
856 {
857         int i;
858
859         for (i = 0; i < adap->sge.ingr_sz; i++) {
860                 struct sge_rspq *q = adap->sge.ingr_map[i];
861
862                 if (!q)
863                         continue;
864                 if (q->handler)
865                         napi_enable(&q->napi);
866
867                 /* 0-increment GTS to start the timer and enable interrupts */
868                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
869                              SEINTARM_V(q->intr_params) |
870                              INGRESSQID_V(q->cntxt_id));
871         }
872 }
873
874
875 static int setup_fw_sge_queues(struct adapter *adap)
876 {
877         struct sge *s = &adap->sge;
878         int err = 0;
879
880         bitmap_zero(s->starving_fl, s->egr_sz);
881         bitmap_zero(s->txq_maperr, s->egr_sz);
882
883         if (adap->flags & CXGB4_USING_MSIX)
884                 adap->msi_idx = 1;         /* vector 0 is for non-queue interrupts */
885         else {
886                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
887                                        NULL, NULL, NULL, -1);
888                 if (err)
889                         return err;
890                 adap->msi_idx = -((int)s->intrq.abs_id + 1);
891         }
892
893         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
894                                adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
895         return err;
896 }
897
898 /**
899  *      setup_sge_queues - configure SGE Tx/Rx/response queues
900  *      @adap: the adapter
901  *
902  *      Determines how many sets of SGE queues to use and initializes them.
903  *      We support multiple queue sets per port if we have MSI-X, otherwise
904  *      just one queue set per port.
905  */
906 static int setup_sge_queues(struct adapter *adap)
907 {
908         int err, i, j;
909         struct sge *s = &adap->sge;
910         struct sge_uld_rxq_info *rxq_info = NULL;
911         unsigned int cmplqid = 0;
912
913         if (is_uld(adap))
914                 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
915
916         for_each_port(adap, i) {
917                 struct net_device *dev = adap->port[i];
918                 struct port_info *pi = netdev_priv(dev);
919                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
920                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
921
922                 for (j = 0; j < pi->nqsets; j++, q++) {
923                         if (adap->msi_idx > 0)
924                                 adap->msi_idx++;
925                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
926                                                adap->msi_idx, &q->fl,
927                                                t4_ethrx_handler,
928                                                NULL,
929                                                t4_get_tp_ch_map(adap,
930                                                                 pi->tx_chan));
931                         if (err)
932                                 goto freeout;
933                         q->rspq.idx = j;
934                         memset(&q->stats, 0, sizeof(q->stats));
935                 }
936
937                 q = &s->ethrxq[pi->first_qset];
938                 for (j = 0; j < pi->nqsets; j++, t++, q++) {
939                         err = t4_sge_alloc_eth_txq(adap, t, dev,
940                                         netdev_get_tx_queue(dev, j),
941                                         q->rspq.cntxt_id,
942                                         !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
943                         if (err)
944                                 goto freeout;
945                 }
946         }
947
948         for_each_port(adap, i) {
949                 /* Note that cmplqid below is 0 if we don't
950                  * have RDMA queues, and that's the right value.
951                  */
952                 if (rxq_info)
953                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
954
955                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
956                                             s->fw_evtq.cntxt_id, cmplqid);
957                 if (err)
958                         goto freeout;
959         }
960
961         if (!is_t4(adap->params.chip)) {
962                 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
963                                            netdev_get_tx_queue(adap->port[0], 0)
964                                            , s->fw_evtq.cntxt_id, false);
965                 if (err)
966                         goto freeout;
967         }
968
969         t4_write_reg(adap, is_t4(adap->params.chip) ?
970                                 MPS_TRC_RSS_CONTROL_A :
971                                 MPS_T5_TRC_RSS_CONTROL_A,
972                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
973                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
974         return 0;
975 freeout:
976         dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
977         t4_free_sge_resources(adap);
978         return err;
979 }
980
981 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
982                              struct net_device *sb_dev,
983                              select_queue_fallback_t fallback)
984 {
985         int txq;
986
987 #ifdef CONFIG_CHELSIO_T4_DCB
988         /* If a Data Center Bridging has been successfully negotiated on this
989          * link then we'll use the skb's priority to map it to a TX Queue.
990          * The skb's priority is determined via the VLAN Tag Priority Code
991          * Point field.
992          */
993         if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
994                 u16 vlan_tci;
995                 int err;
996
997                 err = vlan_get_tag(skb, &vlan_tci);
998                 if (unlikely(err)) {
999                         if (net_ratelimit())
1000                                 netdev_warn(dev,
1001                                             "TX Packet without VLAN Tag on DCB Link\n");
1002                         txq = 0;
1003                 } else {
1004                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1005 #ifdef CONFIG_CHELSIO_T4_FCOE
1006                         if (skb->protocol == htons(ETH_P_FCOE))
1007                                 txq = skb->priority & 0x7;
1008 #endif /* CONFIG_CHELSIO_T4_FCOE */
1009                 }
1010                 return txq;
1011         }
1012 #endif /* CONFIG_CHELSIO_T4_DCB */
1013
1014         if (select_queue) {
1015                 txq = (skb_rx_queue_recorded(skb)
1016                         ? skb_get_rx_queue(skb)
1017                         : smp_processor_id());
1018
1019                 while (unlikely(txq >= dev->real_num_tx_queues))
1020                         txq -= dev->real_num_tx_queues;
1021
1022                 return txq;
1023         }
1024
1025         return fallback(dev, skb, NULL) % dev->real_num_tx_queues;
1026 }
1027
1028 static int closest_timer(const struct sge *s, int time)
1029 {
1030         int i, delta, match = 0, min_delta = INT_MAX;
1031
1032         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1033                 delta = time - s->timer_val[i];
1034                 if (delta < 0)
1035                         delta = -delta;
1036                 if (delta < min_delta) {
1037                         min_delta = delta;
1038                         match = i;
1039                 }
1040         }
1041         return match;
1042 }
1043
1044 static int closest_thres(const struct sge *s, int thres)
1045 {
1046         int i, delta, match = 0, min_delta = INT_MAX;
1047
1048         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1049                 delta = thres - s->counter_val[i];
1050                 if (delta < 0)
1051                         delta = -delta;
1052                 if (delta < min_delta) {
1053                         min_delta = delta;
1054                         match = i;
1055                 }
1056         }
1057         return match;
1058 }
1059
1060 /**
1061  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1062  *      @q: the Rx queue
1063  *      @us: the hold-off time in us, or 0 to disable timer
1064  *      @cnt: the hold-off packet count, or 0 to disable counter
1065  *
1066  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
1067  *      one of the two needs to be enabled for the queue to generate interrupts.
1068  */
1069 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1070                                unsigned int us, unsigned int cnt)
1071 {
1072         struct adapter *adap = q->adap;
1073
1074         if ((us | cnt) == 0)
1075                 cnt = 1;
1076
1077         if (cnt) {
1078                 int err;
1079                 u32 v, new_idx;
1080
1081                 new_idx = closest_thres(&adap->sge, cnt);
1082                 if (q->desc && q->pktcnt_idx != new_idx) {
1083                         /* the queue has already been created, update it */
1084                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1085                             FW_PARAMS_PARAM_X_V(
1086                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1087                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1088                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1089                                             &v, &new_idx);
1090                         if (err)
1091                                 return err;
1092                 }
1093                 q->pktcnt_idx = new_idx;
1094         }
1095
1096         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1097         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1098         return 0;
1099 }
1100
1101 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1102 {
1103         const struct port_info *pi = netdev_priv(dev);
1104         netdev_features_t changed = dev->features ^ features;
1105         int err;
1106
1107         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1108                 return 0;
1109
1110         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1111                             -1, -1, -1,
1112                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1113         if (unlikely(err))
1114                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1115         return err;
1116 }
1117
1118 static int setup_debugfs(struct adapter *adap)
1119 {
1120         if (IS_ERR_OR_NULL(adap->debugfs_root))
1121                 return -1;
1122
1123 #ifdef CONFIG_DEBUG_FS
1124         t4_setup_debugfs(adap);
1125 #endif
1126         return 0;
1127 }
1128
1129 /*
1130  * upper-layer driver support
1131  */
1132
1133 /*
1134  * Allocate an active-open TID and set it to the supplied value.
1135  */
1136 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1137 {
1138         int atid = -1;
1139
1140         spin_lock_bh(&t->atid_lock);
1141         if (t->afree) {
1142                 union aopen_entry *p = t->afree;
1143
1144                 atid = (p - t->atid_tab) + t->atid_base;
1145                 t->afree = p->next;
1146                 p->data = data;
1147                 t->atids_in_use++;
1148         }
1149         spin_unlock_bh(&t->atid_lock);
1150         return atid;
1151 }
1152 EXPORT_SYMBOL(cxgb4_alloc_atid);
1153
1154 /*
1155  * Release an active-open TID.
1156  */
1157 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1158 {
1159         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1160
1161         spin_lock_bh(&t->atid_lock);
1162         p->next = t->afree;
1163         t->afree = p;
1164         t->atids_in_use--;
1165         spin_unlock_bh(&t->atid_lock);
1166 }
1167 EXPORT_SYMBOL(cxgb4_free_atid);
1168
1169 /*
1170  * Allocate a server TID and set it to the supplied value.
1171  */
1172 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1173 {
1174         int stid;
1175
1176         spin_lock_bh(&t->stid_lock);
1177         if (family == PF_INET) {
1178                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1179                 if (stid < t->nstids)
1180                         __set_bit(stid, t->stid_bmap);
1181                 else
1182                         stid = -1;
1183         } else {
1184                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1185                 if (stid < 0)
1186                         stid = -1;
1187         }
1188         if (stid >= 0) {
1189                 t->stid_tab[stid].data = data;
1190                 stid += t->stid_base;
1191                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1192                  * This is equivalent to 4 TIDs. With CLIP enabled it
1193                  * needs 2 TIDs.
1194                  */
1195                 if (family == PF_INET6) {
1196                         t->stids_in_use += 2;
1197                         t->v6_stids_in_use += 2;
1198                 } else {
1199                         t->stids_in_use++;
1200                 }
1201         }
1202         spin_unlock_bh(&t->stid_lock);
1203         return stid;
1204 }
1205 EXPORT_SYMBOL(cxgb4_alloc_stid);
1206
1207 /* Allocate a server filter TID and set it to the supplied value.
1208  */
1209 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1210 {
1211         int stid;
1212
1213         spin_lock_bh(&t->stid_lock);
1214         if (family == PF_INET) {
1215                 stid = find_next_zero_bit(t->stid_bmap,
1216                                 t->nstids + t->nsftids, t->nstids);
1217                 if (stid < (t->nstids + t->nsftids))
1218                         __set_bit(stid, t->stid_bmap);
1219                 else
1220                         stid = -1;
1221         } else {
1222                 stid = -1;
1223         }
1224         if (stid >= 0) {
1225                 t->stid_tab[stid].data = data;
1226                 stid -= t->nstids;
1227                 stid += t->sftid_base;
1228                 t->sftids_in_use++;
1229         }
1230         spin_unlock_bh(&t->stid_lock);
1231         return stid;
1232 }
1233 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1234
1235 /* Release a server TID.
1236  */
1237 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1238 {
1239         /* Is it a server filter TID? */
1240         if (t->nsftids && (stid >= t->sftid_base)) {
1241                 stid -= t->sftid_base;
1242                 stid += t->nstids;
1243         } else {
1244                 stid -= t->stid_base;
1245         }
1246
1247         spin_lock_bh(&t->stid_lock);
1248         if (family == PF_INET)
1249                 __clear_bit(stid, t->stid_bmap);
1250         else
1251                 bitmap_release_region(t->stid_bmap, stid, 1);
1252         t->stid_tab[stid].data = NULL;
1253         if (stid < t->nstids) {
1254                 if (family == PF_INET6) {
1255                         t->stids_in_use -= 2;
1256                         t->v6_stids_in_use -= 2;
1257                 } else {
1258                         t->stids_in_use--;
1259                 }
1260         } else {
1261                 t->sftids_in_use--;
1262         }
1263
1264         spin_unlock_bh(&t->stid_lock);
1265 }
1266 EXPORT_SYMBOL(cxgb4_free_stid);
1267
1268 /*
1269  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1270  */
1271 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1272                            unsigned int tid)
1273 {
1274         struct cpl_tid_release *req;
1275
1276         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1277         req = __skb_put(skb, sizeof(*req));
1278         INIT_TP_WR(req, tid);
1279         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1280 }
1281
1282 /*
1283  * Queue a TID release request and if necessary schedule a work queue to
1284  * process it.
1285  */
1286 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1287                                     unsigned int tid)
1288 {
1289         void **p = &t->tid_tab[tid];
1290         struct adapter *adap = container_of(t, struct adapter, tids);
1291
1292         spin_lock_bh(&adap->tid_release_lock);
1293         *p = adap->tid_release_head;
1294         /* Low 2 bits encode the Tx channel number */
1295         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1296         if (!adap->tid_release_task_busy) {
1297                 adap->tid_release_task_busy = true;
1298                 queue_work(adap->workq, &adap->tid_release_task);
1299         }
1300         spin_unlock_bh(&adap->tid_release_lock);
1301 }
1302
1303 /*
1304  * Process the list of pending TID release requests.
1305  */
1306 static void process_tid_release_list(struct work_struct *work)
1307 {
1308         struct sk_buff *skb;
1309         struct adapter *adap;
1310
1311         adap = container_of(work, struct adapter, tid_release_task);
1312
1313         spin_lock_bh(&adap->tid_release_lock);
1314         while (adap->tid_release_head) {
1315                 void **p = adap->tid_release_head;
1316                 unsigned int chan = (uintptr_t)p & 3;
1317                 p = (void *)p - chan;
1318
1319                 adap->tid_release_head = *p;
1320                 *p = NULL;
1321                 spin_unlock_bh(&adap->tid_release_lock);
1322
1323                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1324                                          GFP_KERNEL)))
1325                         schedule_timeout_uninterruptible(1);
1326
1327                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1328                 t4_ofld_send(adap, skb);
1329                 spin_lock_bh(&adap->tid_release_lock);
1330         }
1331         adap->tid_release_task_busy = false;
1332         spin_unlock_bh(&adap->tid_release_lock);
1333 }
1334
1335 /*
1336  * Release a TID and inform HW.  If we are unable to allocate the release
1337  * message we defer to a work queue.
1338  */
1339 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1340                       unsigned short family)
1341 {
1342         struct sk_buff *skb;
1343         struct adapter *adap = container_of(t, struct adapter, tids);
1344
1345         WARN_ON(tid >= t->ntids);
1346
1347         if (t->tid_tab[tid]) {
1348                 t->tid_tab[tid] = NULL;
1349                 atomic_dec(&t->conns_in_use);
1350                 if (t->hash_base && (tid >= t->hash_base)) {
1351                         if (family == AF_INET6)
1352                                 atomic_sub(2, &t->hash_tids_in_use);
1353                         else
1354                                 atomic_dec(&t->hash_tids_in_use);
1355                 } else {
1356                         if (family == AF_INET6)
1357                                 atomic_sub(2, &t->tids_in_use);
1358                         else
1359                                 atomic_dec(&t->tids_in_use);
1360                 }
1361         }
1362
1363         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1364         if (likely(skb)) {
1365                 mk_tid_release(skb, chan, tid);
1366                 t4_ofld_send(adap, skb);
1367         } else
1368                 cxgb4_queue_tid_release(t, chan, tid);
1369 }
1370 EXPORT_SYMBOL(cxgb4_remove_tid);
1371
1372 /*
1373  * Allocate and initialize the TID tables.  Returns 0 on success.
1374  */
1375 static int tid_init(struct tid_info *t)
1376 {
1377         struct adapter *adap = container_of(t, struct adapter, tids);
1378         unsigned int max_ftids = t->nftids + t->nsftids;
1379         unsigned int natids = t->natids;
1380         unsigned int stid_bmap_size;
1381         unsigned int ftid_bmap_size;
1382         size_t size;
1383
1384         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1385         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1386         size = t->ntids * sizeof(*t->tid_tab) +
1387                natids * sizeof(*t->atid_tab) +
1388                t->nstids * sizeof(*t->stid_tab) +
1389                t->nsftids * sizeof(*t->stid_tab) +
1390                stid_bmap_size * sizeof(long) +
1391                max_ftids * sizeof(*t->ftid_tab) +
1392                ftid_bmap_size * sizeof(long);
1393
1394         t->tid_tab = kvzalloc(size, GFP_KERNEL);
1395         if (!t->tid_tab)
1396                 return -ENOMEM;
1397
1398         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1399         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1400         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1401         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1402         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1403         spin_lock_init(&t->stid_lock);
1404         spin_lock_init(&t->atid_lock);
1405         spin_lock_init(&t->ftid_lock);
1406
1407         t->stids_in_use = 0;
1408         t->v6_stids_in_use = 0;
1409         t->sftids_in_use = 0;
1410         t->afree = NULL;
1411         t->atids_in_use = 0;
1412         atomic_set(&t->tids_in_use, 0);
1413         atomic_set(&t->conns_in_use, 0);
1414         atomic_set(&t->hash_tids_in_use, 0);
1415
1416         /* Setup the free list for atid_tab and clear the stid bitmap. */
1417         if (natids) {
1418                 while (--natids)
1419                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1420                 t->afree = t->atid_tab;
1421         }
1422
1423         if (is_offload(adap)) {
1424                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1425                 /* Reserve stid 0 for T4/T5 adapters */
1426                 if (!t->stid_base &&
1427                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1428                         __set_bit(0, t->stid_bmap);
1429         }
1430
1431         bitmap_zero(t->ftid_bmap, t->nftids);
1432         return 0;
1433 }
1434
1435 /**
1436  *      cxgb4_create_server - create an IP server
1437  *      @dev: the device
1438  *      @stid: the server TID
1439  *      @sip: local IP address to bind server to
1440  *      @sport: the server's TCP port
1441  *      @queue: queue to direct messages from this server to
1442  *
1443  *      Create an IP server for the given port and address.
1444  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1445  */
1446 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1447                         __be32 sip, __be16 sport, __be16 vlan,
1448                         unsigned int queue)
1449 {
1450         unsigned int chan;
1451         struct sk_buff *skb;
1452         struct adapter *adap;
1453         struct cpl_pass_open_req *req;
1454         int ret;
1455
1456         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1457         if (!skb)
1458                 return -ENOMEM;
1459
1460         adap = netdev2adap(dev);
1461         req = __skb_put(skb, sizeof(*req));
1462         INIT_TP_WR(req, 0);
1463         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1464         req->local_port = sport;
1465         req->peer_port = htons(0);
1466         req->local_ip = sip;
1467         req->peer_ip = htonl(0);
1468         chan = rxq_to_chan(&adap->sge, queue);
1469         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1470         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1471                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1472         ret = t4_mgmt_tx(adap, skb);
1473         return net_xmit_eval(ret);
1474 }
1475 EXPORT_SYMBOL(cxgb4_create_server);
1476
1477 /*      cxgb4_create_server6 - create an IPv6 server
1478  *      @dev: the device
1479  *      @stid: the server TID
1480  *      @sip: local IPv6 address to bind server to
1481  *      @sport: the server's TCP port
1482  *      @queue: queue to direct messages from this server to
1483  *
1484  *      Create an IPv6 server for the given port and address.
1485  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1486  */
1487 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1488                          const struct in6_addr *sip, __be16 sport,
1489                          unsigned int queue)
1490 {
1491         unsigned int chan;
1492         struct sk_buff *skb;
1493         struct adapter *adap;
1494         struct cpl_pass_open_req6 *req;
1495         int ret;
1496
1497         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1498         if (!skb)
1499                 return -ENOMEM;
1500
1501         adap = netdev2adap(dev);
1502         req = __skb_put(skb, sizeof(*req));
1503         INIT_TP_WR(req, 0);
1504         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1505         req->local_port = sport;
1506         req->peer_port = htons(0);
1507         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1508         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1509         req->peer_ip_hi = cpu_to_be64(0);
1510         req->peer_ip_lo = cpu_to_be64(0);
1511         chan = rxq_to_chan(&adap->sge, queue);
1512         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1513         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1514                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1515         ret = t4_mgmt_tx(adap, skb);
1516         return net_xmit_eval(ret);
1517 }
1518 EXPORT_SYMBOL(cxgb4_create_server6);
1519
1520 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1521                         unsigned int queue, bool ipv6)
1522 {
1523         struct sk_buff *skb;
1524         struct adapter *adap;
1525         struct cpl_close_listsvr_req *req;
1526         int ret;
1527
1528         adap = netdev2adap(dev);
1529
1530         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1531         if (!skb)
1532                 return -ENOMEM;
1533
1534         req = __skb_put(skb, sizeof(*req));
1535         INIT_TP_WR(req, 0);
1536         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1537         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1538                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1539         ret = t4_mgmt_tx(adap, skb);
1540         return net_xmit_eval(ret);
1541 }
1542 EXPORT_SYMBOL(cxgb4_remove_server);
1543
1544 /**
1545  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1546  *      @mtus: the HW MTU table
1547  *      @mtu: the target MTU
1548  *      @idx: index of selected entry in the MTU table
1549  *
1550  *      Returns the index and the value in the HW MTU table that is closest to
1551  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1552  *      table, in which case that smallest available value is selected.
1553  */
1554 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1555                             unsigned int *idx)
1556 {
1557         unsigned int i = 0;
1558
1559         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1560                 ++i;
1561         if (idx)
1562                 *idx = i;
1563         return mtus[i];
1564 }
1565 EXPORT_SYMBOL(cxgb4_best_mtu);
1566
1567 /**
1568  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1569  *     @mtus: the HW MTU table
1570  *     @header_size: Header Size
1571  *     @data_size_max: maximum Data Segment Size
1572  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1573  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1574  *
1575  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1576  *     MTU Table based solely on a Maximum MTU parameter, we break that
1577  *     parameter up into a Header Size and Maximum Data Segment Size, and
1578  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1579  *     the Hardware MTU Table which will result in a Data Segment Size with
1580  *     the requested alignment _and_ that MTU isn't "too far" from the
1581  *     closest MTU, then we'll return that rather than the closest MTU.
1582  */
1583 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1584                                     unsigned short header_size,
1585                                     unsigned short data_size_max,
1586                                     unsigned short data_size_align,
1587                                     unsigned int *mtu_idxp)
1588 {
1589         unsigned short max_mtu = header_size + data_size_max;
1590         unsigned short data_size_align_mask = data_size_align - 1;
1591         int mtu_idx, aligned_mtu_idx;
1592
1593         /* Scan the MTU Table till we find an MTU which is larger than our
1594          * Maximum MTU or we reach the end of the table.  Along the way,
1595          * record the last MTU found, if any, which will result in a Data
1596          * Segment Length matching the requested alignment.
1597          */
1598         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1599                 unsigned short data_size = mtus[mtu_idx] - header_size;
1600
1601                 /* If this MTU minus the Header Size would result in a
1602                  * Data Segment Size of the desired alignment, remember it.
1603                  */
1604                 if ((data_size & data_size_align_mask) == 0)
1605                         aligned_mtu_idx = mtu_idx;
1606
1607                 /* If we're not at the end of the Hardware MTU Table and the
1608                  * next element is larger than our Maximum MTU, drop out of
1609                  * the loop.
1610                  */
1611                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1612                         break;
1613         }
1614
1615         /* If we fell out of the loop because we ran to the end of the table,
1616          * then we just have to use the last [largest] entry.
1617          */
1618         if (mtu_idx == NMTUS)
1619                 mtu_idx--;
1620
1621         /* If we found an MTU which resulted in the requested Data Segment
1622          * Length alignment and that's "not far" from the largest MTU which is
1623          * less than or equal to the maximum MTU, then use that.
1624          */
1625         if (aligned_mtu_idx >= 0 &&
1626             mtu_idx - aligned_mtu_idx <= 1)
1627                 mtu_idx = aligned_mtu_idx;
1628
1629         /* If the caller has passed in an MTU Index pointer, pass the
1630          * MTU Index back.  Return the MTU value.
1631          */
1632         if (mtu_idxp)
1633                 *mtu_idxp = mtu_idx;
1634         return mtus[mtu_idx];
1635 }
1636 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1637
1638 /**
1639  *      cxgb4_port_chan - get the HW channel of a port
1640  *      @dev: the net device for the port
1641  *
1642  *      Return the HW Tx channel of the given port.
1643  */
1644 unsigned int cxgb4_port_chan(const struct net_device *dev)
1645 {
1646         return netdev2pinfo(dev)->tx_chan;
1647 }
1648 EXPORT_SYMBOL(cxgb4_port_chan);
1649
1650 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1651 {
1652         struct adapter *adap = netdev2adap(dev);
1653         u32 v1, v2, lp_count, hp_count;
1654
1655         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1656         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1657         if (is_t4(adap->params.chip)) {
1658                 lp_count = LP_COUNT_G(v1);
1659                 hp_count = HP_COUNT_G(v1);
1660         } else {
1661                 lp_count = LP_COUNT_T5_G(v1);
1662                 hp_count = HP_COUNT_T5_G(v2);
1663         }
1664         return lpfifo ? lp_count : hp_count;
1665 }
1666 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1667
1668 /**
1669  *      cxgb4_port_viid - get the VI id of a port
1670  *      @dev: the net device for the port
1671  *
1672  *      Return the VI id of the given port.
1673  */
1674 unsigned int cxgb4_port_viid(const struct net_device *dev)
1675 {
1676         return netdev2pinfo(dev)->viid;
1677 }
1678 EXPORT_SYMBOL(cxgb4_port_viid);
1679
1680 /**
1681  *      cxgb4_port_idx - get the index of a port
1682  *      @dev: the net device for the port
1683  *
1684  *      Return the index of the given port.
1685  */
1686 unsigned int cxgb4_port_idx(const struct net_device *dev)
1687 {
1688         return netdev2pinfo(dev)->port_id;
1689 }
1690 EXPORT_SYMBOL(cxgb4_port_idx);
1691
1692 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1693                          struct tp_tcp_stats *v6)
1694 {
1695         struct adapter *adap = pci_get_drvdata(pdev);
1696
1697         spin_lock(&adap->stats_lock);
1698         t4_tp_get_tcp_stats(adap, v4, v6, false);
1699         spin_unlock(&adap->stats_lock);
1700 }
1701 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1702
1703 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1704                       const unsigned int *pgsz_order)
1705 {
1706         struct adapter *adap = netdev2adap(dev);
1707
1708         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1709         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1710                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1711                      HPZ3_V(pgsz_order[3]));
1712 }
1713 EXPORT_SYMBOL(cxgb4_iscsi_init);
1714
1715 int cxgb4_flush_eq_cache(struct net_device *dev)
1716 {
1717         struct adapter *adap = netdev2adap(dev);
1718
1719         return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1720 }
1721 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1722
1723 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1724 {
1725         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1726         __be64 indices;
1727         int ret;
1728
1729         spin_lock(&adap->win0_lock);
1730         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1731                            sizeof(indices), (__be32 *)&indices,
1732                            T4_MEMORY_READ);
1733         spin_unlock(&adap->win0_lock);
1734         if (!ret) {
1735                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1736                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1737         }
1738         return ret;
1739 }
1740
1741 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1742                         u16 size)
1743 {
1744         struct adapter *adap = netdev2adap(dev);
1745         u16 hw_pidx, hw_cidx;
1746         int ret;
1747
1748         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1749         if (ret)
1750                 goto out;
1751
1752         if (pidx != hw_pidx) {
1753                 u16 delta;
1754                 u32 val;
1755
1756                 if (pidx >= hw_pidx)
1757                         delta = pidx - hw_pidx;
1758                 else
1759                         delta = size - hw_pidx + pidx;
1760
1761                 if (is_t4(adap->params.chip))
1762                         val = PIDX_V(delta);
1763                 else
1764                         val = PIDX_T5_V(delta);
1765                 wmb();
1766                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1767                              QID_V(qid) | val);
1768         }
1769 out:
1770         return ret;
1771 }
1772 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1773
1774 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1775 {
1776         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1777         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1778         u32 offset, memtype, memaddr;
1779         struct adapter *adap;
1780         u32 hma_size = 0;
1781         int ret;
1782
1783         adap = netdev2adap(dev);
1784
1785         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1786
1787         /* Figure out where the offset lands in the Memory Type/Address scheme.
1788          * This code assumes that the memory is laid out starting at offset 0
1789          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1790          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1791          * MC0, and some have both MC0 and MC1.
1792          */
1793         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1794         edc0_size = EDRAM0_SIZE_G(size) << 20;
1795         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1796         edc1_size = EDRAM1_SIZE_G(size) << 20;
1797         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1798         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1799
1800         if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1801                 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1802                 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1803         }
1804         edc0_end = edc0_size;
1805         edc1_end = edc0_end + edc1_size;
1806         mc0_end = edc1_end + mc0_size;
1807
1808         if (offset < edc0_end) {
1809                 memtype = MEM_EDC0;
1810                 memaddr = offset;
1811         } else if (offset < edc1_end) {
1812                 memtype = MEM_EDC1;
1813                 memaddr = offset - edc0_end;
1814         } else {
1815                 if (hma_size && (offset < (edc1_end + hma_size))) {
1816                         memtype = MEM_HMA;
1817                         memaddr = offset - edc1_end;
1818                 } else if (offset < mc0_end) {
1819                         memtype = MEM_MC0;
1820                         memaddr = offset - edc1_end;
1821                 } else if (is_t5(adap->params.chip)) {
1822                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1823                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1824                         mc1_end = mc0_end + mc1_size;
1825                         if (offset < mc1_end) {
1826                                 memtype = MEM_MC1;
1827                                 memaddr = offset - mc0_end;
1828                         } else {
1829                                 /* offset beyond the end of any memory */
1830                                 goto err;
1831                         }
1832                 } else {
1833                         /* T4/T6 only has a single memory channel */
1834                         goto err;
1835                 }
1836         }
1837
1838         spin_lock(&adap->win0_lock);
1839         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1840         spin_unlock(&adap->win0_lock);
1841         return ret;
1842
1843 err:
1844         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1845                 stag, offset);
1846         return -EINVAL;
1847 }
1848 EXPORT_SYMBOL(cxgb4_read_tpte);
1849
1850 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1851 {
1852         u32 hi, lo;
1853         struct adapter *adap;
1854
1855         adap = netdev2adap(dev);
1856         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1857         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1858
1859         return ((u64)hi << 32) | (u64)lo;
1860 }
1861 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1862
1863 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1864                          unsigned int qid,
1865                          enum cxgb4_bar2_qtype qtype,
1866                          int user,
1867                          u64 *pbar2_qoffset,
1868                          unsigned int *pbar2_qid)
1869 {
1870         return t4_bar2_sge_qregs(netdev2adap(dev),
1871                                  qid,
1872                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
1873                                   ? T4_BAR2_QTYPE_EGRESS
1874                                   : T4_BAR2_QTYPE_INGRESS),
1875                                  user,
1876                                  pbar2_qoffset,
1877                                  pbar2_qid);
1878 }
1879 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1880
1881 static struct pci_driver cxgb4_driver;
1882
1883 static void check_neigh_update(struct neighbour *neigh)
1884 {
1885         const struct device *parent;
1886         const struct net_device *netdev = neigh->dev;
1887
1888         if (is_vlan_dev(netdev))
1889                 netdev = vlan_dev_real_dev(netdev);
1890         parent = netdev->dev.parent;
1891         if (parent && parent->driver == &cxgb4_driver.driver)
1892                 t4_l2t_update(dev_get_drvdata(parent), neigh);
1893 }
1894
1895 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1896                        void *data)
1897 {
1898         switch (event) {
1899         case NETEVENT_NEIGH_UPDATE:
1900                 check_neigh_update(data);
1901                 break;
1902         case NETEVENT_REDIRECT:
1903         default:
1904                 break;
1905         }
1906         return 0;
1907 }
1908
1909 static bool netevent_registered;
1910 static struct notifier_block cxgb4_netevent_nb = {
1911         .notifier_call = netevent_cb
1912 };
1913
1914 static void drain_db_fifo(struct adapter *adap, int usecs)
1915 {
1916         u32 v1, v2, lp_count, hp_count;
1917
1918         do {
1919                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1920                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1921                 if (is_t4(adap->params.chip)) {
1922                         lp_count = LP_COUNT_G(v1);
1923                         hp_count = HP_COUNT_G(v1);
1924                 } else {
1925                         lp_count = LP_COUNT_T5_G(v1);
1926                         hp_count = HP_COUNT_T5_G(v2);
1927                 }
1928
1929                 if (lp_count == 0 && hp_count == 0)
1930                         break;
1931                 set_current_state(TASK_UNINTERRUPTIBLE);
1932                 schedule_timeout(usecs_to_jiffies(usecs));
1933         } while (1);
1934 }
1935
1936 static void disable_txq_db(struct sge_txq *q)
1937 {
1938         unsigned long flags;
1939
1940         spin_lock_irqsave(&q->db_lock, flags);
1941         q->db_disabled = 1;
1942         spin_unlock_irqrestore(&q->db_lock, flags);
1943 }
1944
1945 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
1946 {
1947         spin_lock_irq(&q->db_lock);
1948         if (q->db_pidx_inc) {
1949                 /* Make sure that all writes to the TX descriptors
1950                  * are committed before we tell HW about them.
1951                  */
1952                 wmb();
1953                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1954                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
1955                 q->db_pidx_inc = 0;
1956         }
1957         q->db_disabled = 0;
1958         spin_unlock_irq(&q->db_lock);
1959 }
1960
1961 static void disable_dbs(struct adapter *adap)
1962 {
1963         int i;
1964
1965         for_each_ethrxq(&adap->sge, i)
1966                 disable_txq_db(&adap->sge.ethtxq[i].q);
1967         if (is_offload(adap)) {
1968                 struct sge_uld_txq_info *txq_info =
1969                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1970
1971                 if (txq_info) {
1972                         for_each_ofldtxq(&adap->sge, i) {
1973                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1974
1975                                 disable_txq_db(&txq->q);
1976                         }
1977                 }
1978         }
1979         for_each_port(adap, i)
1980                 disable_txq_db(&adap->sge.ctrlq[i].q);
1981 }
1982
1983 static void enable_dbs(struct adapter *adap)
1984 {
1985         int i;
1986
1987         for_each_ethrxq(&adap->sge, i)
1988                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
1989         if (is_offload(adap)) {
1990                 struct sge_uld_txq_info *txq_info =
1991                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1992
1993                 if (txq_info) {
1994                         for_each_ofldtxq(&adap->sge, i) {
1995                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1996
1997                                 enable_txq_db(adap, &txq->q);
1998                         }
1999                 }
2000         }
2001         for_each_port(adap, i)
2002                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2003 }
2004
2005 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2006 {
2007         enum cxgb4_uld type = CXGB4_ULD_RDMA;
2008
2009         if (adap->uld && adap->uld[type].handle)
2010                 adap->uld[type].control(adap->uld[type].handle, cmd);
2011 }
2012
2013 static void process_db_full(struct work_struct *work)
2014 {
2015         struct adapter *adap;
2016
2017         adap = container_of(work, struct adapter, db_full_task);
2018
2019         drain_db_fifo(adap, dbfifo_drain_delay);
2020         enable_dbs(adap);
2021         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2022         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2023                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2024                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2025                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2026         else
2027                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2028                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2029 }
2030
2031 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2032 {
2033         u16 hw_pidx, hw_cidx;
2034         int ret;
2035
2036         spin_lock_irq(&q->db_lock);
2037         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2038         if (ret)
2039                 goto out;
2040         if (q->db_pidx != hw_pidx) {
2041                 u16 delta;
2042                 u32 val;
2043
2044                 if (q->db_pidx >= hw_pidx)
2045                         delta = q->db_pidx - hw_pidx;
2046                 else
2047                         delta = q->size - hw_pidx + q->db_pidx;
2048
2049                 if (is_t4(adap->params.chip))
2050                         val = PIDX_V(delta);
2051                 else
2052                         val = PIDX_T5_V(delta);
2053                 wmb();
2054                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2055                              QID_V(q->cntxt_id) | val);
2056         }
2057 out:
2058         q->db_disabled = 0;
2059         q->db_pidx_inc = 0;
2060         spin_unlock_irq(&q->db_lock);
2061         if (ret)
2062                 CH_WARN(adap, "DB drop recovery failed.\n");
2063 }
2064
2065 static void recover_all_queues(struct adapter *adap)
2066 {
2067         int i;
2068
2069         for_each_ethrxq(&adap->sge, i)
2070                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2071         if (is_offload(adap)) {
2072                 struct sge_uld_txq_info *txq_info =
2073                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2074                 if (txq_info) {
2075                         for_each_ofldtxq(&adap->sge, i) {
2076                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2077
2078                                 sync_txq_pidx(adap, &txq->q);
2079                         }
2080                 }
2081         }
2082         for_each_port(adap, i)
2083                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2084 }
2085
2086 static void process_db_drop(struct work_struct *work)
2087 {
2088         struct adapter *adap;
2089
2090         adap = container_of(work, struct adapter, db_drop_task);
2091
2092         if (is_t4(adap->params.chip)) {
2093                 drain_db_fifo(adap, dbfifo_drain_delay);
2094                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2095                 drain_db_fifo(adap, dbfifo_drain_delay);
2096                 recover_all_queues(adap);
2097                 drain_db_fifo(adap, dbfifo_drain_delay);
2098                 enable_dbs(adap);
2099                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2100         } else if (is_t5(adap->params.chip)) {
2101                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2102                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2103                 u16 pidx_inc = dropped_db & 0x1fff;
2104                 u64 bar2_qoffset;
2105                 unsigned int bar2_qid;
2106                 int ret;
2107
2108                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2109                                         0, &bar2_qoffset, &bar2_qid);
2110                 if (ret)
2111                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2112                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2113                 else
2114                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2115                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2116
2117                 /* Re-enable BAR2 WC */
2118                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2119         }
2120
2121         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2122                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2123 }
2124
2125 void t4_db_full(struct adapter *adap)
2126 {
2127         if (is_t4(adap->params.chip)) {
2128                 disable_dbs(adap);
2129                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2130                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2131                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2132                 queue_work(adap->workq, &adap->db_full_task);
2133         }
2134 }
2135
2136 void t4_db_dropped(struct adapter *adap)
2137 {
2138         if (is_t4(adap->params.chip)) {
2139                 disable_dbs(adap);
2140                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2141         }
2142         queue_work(adap->workq, &adap->db_drop_task);
2143 }
2144
2145 void t4_register_netevent_notifier(void)
2146 {
2147         if (!netevent_registered) {
2148                 register_netevent_notifier(&cxgb4_netevent_nb);
2149                 netevent_registered = true;
2150         }
2151 }
2152
2153 static void detach_ulds(struct adapter *adap)
2154 {
2155         unsigned int i;
2156
2157         mutex_lock(&uld_mutex);
2158         list_del(&adap->list_node);
2159
2160         for (i = 0; i < CXGB4_ULD_MAX; i++)
2161                 if (adap->uld && adap->uld[i].handle)
2162                         adap->uld[i].state_change(adap->uld[i].handle,
2163                                              CXGB4_STATE_DETACH);
2164
2165         if (netevent_registered && list_empty(&adapter_list)) {
2166                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2167                 netevent_registered = false;
2168         }
2169         mutex_unlock(&uld_mutex);
2170 }
2171
2172 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2173 {
2174         unsigned int i;
2175
2176         mutex_lock(&uld_mutex);
2177         for (i = 0; i < CXGB4_ULD_MAX; i++)
2178                 if (adap->uld && adap->uld[i].handle)
2179                         adap->uld[i].state_change(adap->uld[i].handle,
2180                                                   new_state);
2181         mutex_unlock(&uld_mutex);
2182 }
2183
2184 #if IS_ENABLED(CONFIG_IPV6)
2185 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2186                                    unsigned long event, void *data)
2187 {
2188         struct inet6_ifaddr *ifa = data;
2189         struct net_device *event_dev = ifa->idev->dev;
2190         const struct device *parent = NULL;
2191 #if IS_ENABLED(CONFIG_BONDING)
2192         struct adapter *adap;
2193 #endif
2194         if (is_vlan_dev(event_dev))
2195                 event_dev = vlan_dev_real_dev(event_dev);
2196 #if IS_ENABLED(CONFIG_BONDING)
2197         if (event_dev->flags & IFF_MASTER) {
2198                 list_for_each_entry(adap, &adapter_list, list_node) {
2199                         switch (event) {
2200                         case NETDEV_UP:
2201                                 cxgb4_clip_get(adap->port[0],
2202                                                (const u32 *)ifa, 1);
2203                                 break;
2204                         case NETDEV_DOWN:
2205                                 cxgb4_clip_release(adap->port[0],
2206                                                    (const u32 *)ifa, 1);
2207                                 break;
2208                         default:
2209                                 break;
2210                         }
2211                 }
2212                 return NOTIFY_OK;
2213         }
2214 #endif
2215
2216         if (event_dev)
2217                 parent = event_dev->dev.parent;
2218
2219         if (parent && parent->driver == &cxgb4_driver.driver) {
2220                 switch (event) {
2221                 case NETDEV_UP:
2222                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2223                         break;
2224                 case NETDEV_DOWN:
2225                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2226                         break;
2227                 default:
2228                         break;
2229                 }
2230         }
2231         return NOTIFY_OK;
2232 }
2233
2234 static bool inet6addr_registered;
2235 static struct notifier_block cxgb4_inet6addr_notifier = {
2236         .notifier_call = cxgb4_inet6addr_handler
2237 };
2238
2239 static void update_clip(const struct adapter *adap)
2240 {
2241         int i;
2242         struct net_device *dev;
2243         int ret;
2244
2245         rcu_read_lock();
2246
2247         for (i = 0; i < MAX_NPORTS; i++) {
2248                 dev = adap->port[i];
2249                 ret = 0;
2250
2251                 if (dev)
2252                         ret = cxgb4_update_root_dev_clip(dev);
2253
2254                 if (ret < 0)
2255                         break;
2256         }
2257         rcu_read_unlock();
2258 }
2259 #endif /* IS_ENABLED(CONFIG_IPV6) */
2260
2261 /**
2262  *      cxgb_up - enable the adapter
2263  *      @adap: adapter being enabled
2264  *
2265  *      Called when the first port is enabled, this function performs the
2266  *      actions necessary to make an adapter operational, such as completing
2267  *      the initialization of HW modules, and enabling interrupts.
2268  *
2269  *      Must be called with the rtnl lock held.
2270  */
2271 static int cxgb_up(struct adapter *adap)
2272 {
2273         int err;
2274
2275         mutex_lock(&uld_mutex);
2276         err = setup_sge_queues(adap);
2277         if (err)
2278                 goto rel_lock;
2279         err = setup_rss(adap);
2280         if (err)
2281                 goto freeq;
2282
2283         if (adap->flags & CXGB4_USING_MSIX) {
2284                 name_msix_vecs(adap);
2285                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2286                                   adap->msix_info[0].desc, adap);
2287                 if (err)
2288                         goto irq_err;
2289                 err = request_msix_queue_irqs(adap);
2290                 if (err) {
2291                         free_irq(adap->msix_info[0].vec, adap);
2292                         goto irq_err;
2293                 }
2294         } else {
2295                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2296                                   (adap->flags & CXGB4_USING_MSI) ? 0
2297                                                                   : IRQF_SHARED,
2298                                   adap->port[0]->name, adap);
2299                 if (err)
2300                         goto irq_err;
2301         }
2302
2303         enable_rx(adap);
2304         t4_sge_start(adap);
2305         t4_intr_enable(adap);
2306         adap->flags |= CXGB4_FULL_INIT_DONE;
2307         mutex_unlock(&uld_mutex);
2308
2309         notify_ulds(adap, CXGB4_STATE_UP);
2310 #if IS_ENABLED(CONFIG_IPV6)
2311         update_clip(adap);
2312 #endif
2313         return err;
2314
2315  irq_err:
2316         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2317  freeq:
2318         t4_free_sge_resources(adap);
2319  rel_lock:
2320         mutex_unlock(&uld_mutex);
2321         return err;
2322 }
2323
2324 static void cxgb_down(struct adapter *adapter)
2325 {
2326         cancel_work_sync(&adapter->tid_release_task);
2327         cancel_work_sync(&adapter->db_full_task);
2328         cancel_work_sync(&adapter->db_drop_task);
2329         adapter->tid_release_task_busy = false;
2330         adapter->tid_release_head = NULL;
2331
2332         t4_sge_stop(adapter);
2333         t4_free_sge_resources(adapter);
2334
2335         adapter->flags &= ~CXGB4_FULL_INIT_DONE;
2336 }
2337
2338 /*
2339  * net_device operations
2340  */
2341 static int cxgb_open(struct net_device *dev)
2342 {
2343         int err;
2344         struct port_info *pi = netdev_priv(dev);
2345         struct adapter *adapter = pi->adapter;
2346
2347         netif_carrier_off(dev);
2348
2349         if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
2350                 err = cxgb_up(adapter);
2351                 if (err < 0)
2352                         return err;
2353         }
2354
2355         /* It's possible that the basic port information could have
2356          * changed since we first read it.
2357          */
2358         err = t4_update_port_info(pi);
2359         if (err < 0)
2360                 return err;
2361
2362         err = link_start(dev);
2363         if (!err)
2364                 netif_tx_start_all_queues(dev);
2365         return err;
2366 }
2367
2368 static int cxgb_close(struct net_device *dev)
2369 {
2370         struct port_info *pi = netdev_priv(dev);
2371         struct adapter *adapter = pi->adapter;
2372         int ret;
2373
2374         netif_tx_stop_all_queues(dev);
2375         netif_carrier_off(dev);
2376         ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2377                                   false, false, false);
2378 #ifdef CONFIG_CHELSIO_T4_DCB
2379         cxgb4_dcb_reset(dev);
2380         dcb_tx_queue_prio_enable(dev, false);
2381 #endif
2382         return ret;
2383 }
2384
2385 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2386                 __be32 sip, __be16 sport, __be16 vlan,
2387                 unsigned int queue, unsigned char port, unsigned char mask)
2388 {
2389         int ret;
2390         struct filter_entry *f;
2391         struct adapter *adap;
2392         int i;
2393         u8 *val;
2394
2395         adap = netdev2adap(dev);
2396
2397         /* Adjust stid to correct filter index */
2398         stid -= adap->tids.sftid_base;
2399         stid += adap->tids.nftids;
2400
2401         /* Check to make sure the filter requested is writable ...
2402          */
2403         f = &adap->tids.ftid_tab[stid];
2404         ret = writable_filter(f);
2405         if (ret)
2406                 return ret;
2407
2408         /* Clear out any old resources being used by the filter before
2409          * we start constructing the new filter.
2410          */
2411         if (f->valid)
2412                 clear_filter(adap, f);
2413
2414         /* Clear out filter specifications */
2415         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2416         f->fs.val.lport = cpu_to_be16(sport);
2417         f->fs.mask.lport  = ~0;
2418         val = (u8 *)&sip;
2419         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2420                 for (i = 0; i < 4; i++) {
2421                         f->fs.val.lip[i] = val[i];
2422                         f->fs.mask.lip[i] = ~0;
2423                 }
2424                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2425                         f->fs.val.iport = port;
2426                         f->fs.mask.iport = mask;
2427                 }
2428         }
2429
2430         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2431                 f->fs.val.proto = IPPROTO_TCP;
2432                 f->fs.mask.proto = ~0;
2433         }
2434
2435         f->fs.dirsteer = 1;
2436         f->fs.iq = queue;
2437         /* Mark filter as locked */
2438         f->locked = 1;
2439         f->fs.rpttid = 1;
2440
2441         /* Save the actual tid. We need this to get the corresponding
2442          * filter entry structure in filter_rpl.
2443          */
2444         f->tid = stid + adap->tids.ftid_base;
2445         ret = set_filter_wr(adap, stid);
2446         if (ret) {
2447                 clear_filter(adap, f);
2448                 return ret;
2449         }
2450
2451         return 0;
2452 }
2453 EXPORT_SYMBOL(cxgb4_create_server_filter);
2454
2455 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2456                 unsigned int queue, bool ipv6)
2457 {
2458         struct filter_entry *f;
2459         struct adapter *adap;
2460
2461         adap = netdev2adap(dev);
2462
2463         /* Adjust stid to correct filter index */
2464         stid -= adap->tids.sftid_base;
2465         stid += adap->tids.nftids;
2466
2467         f = &adap->tids.ftid_tab[stid];
2468         /* Unlock the filter */
2469         f->locked = 0;
2470
2471         return delete_filter(adap, stid);
2472 }
2473 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2474
2475 static void cxgb_get_stats(struct net_device *dev,
2476                            struct rtnl_link_stats64 *ns)
2477 {
2478         struct port_stats stats;
2479         struct port_info *p = netdev_priv(dev);
2480         struct adapter *adapter = p->adapter;
2481
2482         /* Block retrieving statistics during EEH error
2483          * recovery. Otherwise, the recovery might fail
2484          * and the PCI device will be removed permanently
2485          */
2486         spin_lock(&adapter->stats_lock);
2487         if (!netif_device_present(dev)) {
2488                 spin_unlock(&adapter->stats_lock);
2489                 return;
2490         }
2491         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2492                                  &p->stats_base);
2493         spin_unlock(&adapter->stats_lock);
2494
2495         ns->tx_bytes   = stats.tx_octets;
2496         ns->tx_packets = stats.tx_frames;
2497         ns->rx_bytes   = stats.rx_octets;
2498         ns->rx_packets = stats.rx_frames;
2499         ns->multicast  = stats.rx_mcast_frames;
2500
2501         /* detailed rx_errors */
2502         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2503                                stats.rx_runt;
2504         ns->rx_over_errors   = 0;
2505         ns->rx_crc_errors    = stats.rx_fcs_err;
2506         ns->rx_frame_errors  = stats.rx_symbol_err;
2507         ns->rx_dropped       = stats.rx_ovflow0 + stats.rx_ovflow1 +
2508                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2509                                stats.rx_trunc0 + stats.rx_trunc1 +
2510                                stats.rx_trunc2 + stats.rx_trunc3;
2511         ns->rx_missed_errors = 0;
2512
2513         /* detailed tx_errors */
2514         ns->tx_aborted_errors   = 0;
2515         ns->tx_carrier_errors   = 0;
2516         ns->tx_fifo_errors      = 0;
2517         ns->tx_heartbeat_errors = 0;
2518         ns->tx_window_errors    = 0;
2519
2520         ns->tx_errors = stats.tx_error_frames;
2521         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2522                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2523 }
2524
2525 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2526 {
2527         unsigned int mbox;
2528         int ret = 0, prtad, devad;
2529         struct port_info *pi = netdev_priv(dev);
2530         struct adapter *adapter = pi->adapter;
2531         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2532
2533         switch (cmd) {
2534         case SIOCGMIIPHY:
2535                 if (pi->mdio_addr < 0)
2536                         return -EOPNOTSUPP;
2537                 data->phy_id = pi->mdio_addr;
2538                 break;
2539         case SIOCGMIIREG:
2540         case SIOCSMIIREG:
2541                 if (mdio_phy_id_is_c45(data->phy_id)) {
2542                         prtad = mdio_phy_id_prtad(data->phy_id);
2543                         devad = mdio_phy_id_devad(data->phy_id);
2544                 } else if (data->phy_id < 32) {
2545                         prtad = data->phy_id;
2546                         devad = 0;
2547                         data->reg_num &= 0x1f;
2548                 } else
2549                         return -EINVAL;
2550
2551                 mbox = pi->adapter->pf;
2552                 if (cmd == SIOCGMIIREG)
2553                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2554                                          data->reg_num, &data->val_out);
2555                 else
2556                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2557                                          data->reg_num, data->val_in);
2558                 break;
2559         case SIOCGHWTSTAMP:
2560                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2561                                     sizeof(pi->tstamp_config)) ?
2562                         -EFAULT : 0;
2563         case SIOCSHWTSTAMP:
2564                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2565                                    sizeof(pi->tstamp_config)))
2566                         return -EFAULT;
2567
2568                 if (!is_t4(adapter->params.chip)) {
2569                         switch (pi->tstamp_config.tx_type) {
2570                         case HWTSTAMP_TX_OFF:
2571                         case HWTSTAMP_TX_ON:
2572                                 break;
2573                         default:
2574                                 return -ERANGE;
2575                         }
2576
2577                         switch (pi->tstamp_config.rx_filter) {
2578                         case HWTSTAMP_FILTER_NONE:
2579                                 pi->rxtstamp = false;
2580                                 break;
2581                         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2582                         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2583                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2584                                                          PTP_TS_L4);
2585                                 break;
2586                         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2587                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2588                                                          PTP_TS_L2_L4);
2589                                 break;
2590                         case HWTSTAMP_FILTER_ALL:
2591                         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2592                         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2593                         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2594                         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2595                                 pi->rxtstamp = true;
2596                                 break;
2597                         default:
2598                                 pi->tstamp_config.rx_filter =
2599                                         HWTSTAMP_FILTER_NONE;
2600                                 return -ERANGE;
2601                         }
2602
2603                         if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2604                             (pi->tstamp_config.rx_filter ==
2605                                 HWTSTAMP_FILTER_NONE)) {
2606                                 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2607                                         pi->ptp_enable = false;
2608                         }
2609
2610                         if (pi->tstamp_config.rx_filter !=
2611                                 HWTSTAMP_FILTER_NONE) {
2612                                 if (cxgb4_ptp_redirect_rx_packet(adapter,
2613                                                                  pi) >= 0)
2614                                         pi->ptp_enable = true;
2615                         }
2616                 } else {
2617                         /* For T4 Adapters */
2618                         switch (pi->tstamp_config.rx_filter) {
2619                         case HWTSTAMP_FILTER_NONE:
2620                         pi->rxtstamp = false;
2621                         break;
2622                         case HWTSTAMP_FILTER_ALL:
2623                         pi->rxtstamp = true;
2624                         break;
2625                         default:
2626                         pi->tstamp_config.rx_filter =
2627                         HWTSTAMP_FILTER_NONE;
2628                         return -ERANGE;
2629                         }
2630                 }
2631                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2632                                     sizeof(pi->tstamp_config)) ?
2633                         -EFAULT : 0;
2634         default:
2635                 return -EOPNOTSUPP;
2636         }
2637         return ret;
2638 }
2639
2640 static void cxgb_set_rxmode(struct net_device *dev)
2641 {
2642         /* unfortunately we can't return errors to the stack */
2643         set_rxmode(dev, -1, false);
2644 }
2645
2646 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2647 {
2648         int ret;
2649         struct port_info *pi = netdev_priv(dev);
2650
2651         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2652                             -1, -1, -1, true);
2653         if (!ret)
2654                 dev->mtu = new_mtu;
2655         return ret;
2656 }
2657
2658 #ifdef CONFIG_PCI_IOV
2659 static int cxgb4_mgmt_open(struct net_device *dev)
2660 {
2661         /* Turn carrier off since we don't have to transmit anything on this
2662          * interface.
2663          */
2664         netif_carrier_off(dev);
2665         return 0;
2666 }
2667
2668 /* Fill MAC address that will be assigned by the FW */
2669 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2670 {
2671         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2672         unsigned int i, vf, nvfs;
2673         u16 a, b;
2674         int err;
2675         u8 *na;
2676
2677         adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2678                                                             PCI_CAP_ID_VPD);
2679         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2680         if (err)
2681                 return;
2682
2683         na = adap->params.vpd.na;
2684         for (i = 0; i < ETH_ALEN; i++)
2685                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2686                               hex2val(na[2 * i + 1]));
2687
2688         a = (hw_addr[0] << 8) | hw_addr[1];
2689         b = (hw_addr[1] << 8) | hw_addr[2];
2690         a ^= b;
2691         a |= 0x0200;    /* locally assigned Ethernet MAC address */
2692         a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2693         macaddr[0] = a >> 8;
2694         macaddr[1] = a & 0xff;
2695
2696         for (i = 2; i < 5; i++)
2697                 macaddr[i] = hw_addr[i + 1];
2698
2699         for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2700                 vf < nvfs; vf++) {
2701                 macaddr[5] = adap->pf * nvfs + vf;
2702                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2703         }
2704 }
2705
2706 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2707 {
2708         struct port_info *pi = netdev_priv(dev);
2709         struct adapter *adap = pi->adapter;
2710         int ret;
2711
2712         /* verify MAC addr is valid */
2713         if (!is_valid_ether_addr(mac)) {
2714                 dev_err(pi->adapter->pdev_dev,
2715                         "Invalid Ethernet address %pM for VF %d\n",
2716                         mac, vf);
2717                 return -EINVAL;
2718         }
2719
2720         dev_info(pi->adapter->pdev_dev,
2721                  "Setting MAC %pM on VF %d\n", mac, vf);
2722         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2723         if (!ret)
2724                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2725         return ret;
2726 }
2727
2728 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2729                                     int vf, struct ifla_vf_info *ivi)
2730 {
2731         struct port_info *pi = netdev_priv(dev);
2732         struct adapter *adap = pi->adapter;
2733         struct vf_info *vfinfo;
2734
2735         if (vf >= adap->num_vfs)
2736                 return -EINVAL;
2737         vfinfo = &adap->vfinfo[vf];
2738
2739         ivi->vf = vf;
2740         ivi->max_tx_rate = vfinfo->tx_rate;
2741         ivi->min_tx_rate = 0;
2742         ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2743         ivi->vlan = vfinfo->vlan;
2744         ivi->linkstate = vfinfo->link_state;
2745         return 0;
2746 }
2747
2748 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2749                                        struct netdev_phys_item_id *ppid)
2750 {
2751         struct port_info *pi = netdev_priv(dev);
2752         unsigned int phy_port_id;
2753
2754         phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2755         ppid->id_len = sizeof(phy_port_id);
2756         memcpy(ppid->id, &phy_port_id, ppid->id_len);
2757         return 0;
2758 }
2759
2760 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2761                                   int min_tx_rate, int max_tx_rate)
2762 {
2763         struct port_info *pi = netdev_priv(dev);
2764         struct adapter *adap = pi->adapter;
2765         unsigned int link_ok, speed, mtu;
2766         u32 fw_pfvf, fw_class;
2767         int class_id = vf;
2768         int ret;
2769         u16 pktsize;
2770
2771         if (vf >= adap->num_vfs)
2772                 return -EINVAL;
2773
2774         if (min_tx_rate) {
2775                 dev_err(adap->pdev_dev,
2776                         "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2777                         min_tx_rate, vf);
2778                 return -EINVAL;
2779         }
2780
2781         if (max_tx_rate == 0) {
2782                 /* unbind VF to to any Traffic Class */
2783                 fw_pfvf =
2784                     (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2785                      FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2786                 fw_class = 0xffffffff;
2787                 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2788                                     &fw_pfvf, &fw_class);
2789                 if (ret) {
2790                         dev_err(adap->pdev_dev,
2791                                 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2792                                 ret, adap->pf, vf);
2793                         return -EINVAL;
2794                 }
2795                 dev_info(adap->pdev_dev,
2796                          "PF %d VF %d is unbound from TX Rate Limiting\n",
2797                          adap->pf, vf);
2798                 adap->vfinfo[vf].tx_rate = 0;
2799                 return 0;
2800         }
2801
2802         ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2803         if (ret != FW_SUCCESS) {
2804                 dev_err(adap->pdev_dev,
2805                         "Failed to get link information for VF %d\n", vf);
2806                 return -EINVAL;
2807         }
2808
2809         if (!link_ok) {
2810                 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2811                 return -EINVAL;
2812         }
2813
2814         if (max_tx_rate > speed) {
2815                 dev_err(adap->pdev_dev,
2816                         "Max tx rate %d for VF %d can't be > link-speed %u",
2817                         max_tx_rate, vf, speed);
2818                 return -EINVAL;
2819         }
2820
2821         pktsize = mtu;
2822         /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2823         pktsize = pktsize - sizeof(struct ethhdr) - 4;
2824         /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2825         pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2826         /* configure Traffic Class for rate-limiting */
2827         ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2828                               SCHED_CLASS_LEVEL_CL_RL,
2829                               SCHED_CLASS_MODE_CLASS,
2830                               SCHED_CLASS_RATEUNIT_BITS,
2831                               SCHED_CLASS_RATEMODE_ABS,
2832                               pi->tx_chan, class_id, 0,
2833                               max_tx_rate * 1000, 0, pktsize);
2834         if (ret) {
2835                 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2836                         ret);
2837                 return -EINVAL;
2838         }
2839         dev_info(adap->pdev_dev,
2840                  "Class %d with MSS %u configured with rate %u\n",
2841                  class_id, pktsize, max_tx_rate);
2842
2843         /* bind VF to configured Traffic Class */
2844         fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2845                    FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2846         fw_class = class_id;
2847         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2848                             &fw_class);
2849         if (ret) {
2850                 dev_err(adap->pdev_dev,
2851                         "Err %d in binding PF %d VF %d to Traffic Class %d\n",
2852                         ret, adap->pf, vf, class_id);
2853                 return -EINVAL;
2854         }
2855         dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2856                  adap->pf, vf, class_id);
2857         adap->vfinfo[vf].tx_rate = max_tx_rate;
2858         return 0;
2859 }
2860
2861 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2862                                   u16 vlan, u8 qos, __be16 vlan_proto)
2863 {
2864         struct port_info *pi = netdev_priv(dev);
2865         struct adapter *adap = pi->adapter;
2866         int ret;
2867
2868         if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2869                 return -EINVAL;
2870
2871         if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2872                 return -EPROTONOSUPPORT;
2873
2874         ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2875         if (!ret) {
2876                 adap->vfinfo[vf].vlan = vlan;
2877                 return 0;
2878         }
2879
2880         dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2881                 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2882         return ret;
2883 }
2884
2885 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
2886                                         int link)
2887 {
2888         struct port_info *pi = netdev_priv(dev);
2889         struct adapter *adap = pi->adapter;
2890         u32 param, val;
2891         int ret = 0;
2892
2893         if (vf >= adap->num_vfs)
2894                 return -EINVAL;
2895
2896         switch (link) {
2897         case IFLA_VF_LINK_STATE_AUTO:
2898                 val = FW_VF_LINK_STATE_AUTO;
2899                 break;
2900
2901         case IFLA_VF_LINK_STATE_ENABLE:
2902                 val = FW_VF_LINK_STATE_ENABLE;
2903                 break;
2904
2905         case IFLA_VF_LINK_STATE_DISABLE:
2906                 val = FW_VF_LINK_STATE_DISABLE;
2907                 break;
2908
2909         default:
2910                 return -EINVAL;
2911         }
2912
2913         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2914                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
2915         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2916                             &param, &val);
2917         if (ret) {
2918                 dev_err(adap->pdev_dev,
2919                         "Error %d in setting PF %d VF %d link state\n",
2920                         ret, adap->pf, vf);
2921                 return -EINVAL;
2922         }
2923
2924         adap->vfinfo[vf].link_state = link;
2925         return ret;
2926 }
2927 #endif /* CONFIG_PCI_IOV */
2928
2929 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2930 {
2931         int ret;
2932         struct sockaddr *addr = p;
2933         struct port_info *pi = netdev_priv(dev);
2934
2935         if (!is_valid_ether_addr(addr->sa_data))
2936                 return -EADDRNOTAVAIL;
2937
2938         ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
2939                                addr->sa_data, true, &pi->smt_idx);
2940         if (ret < 0)
2941                 return ret;
2942
2943         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2944         pi->xact_addr_filt = ret;
2945         return 0;
2946 }
2947
2948 #ifdef CONFIG_NET_POLL_CONTROLLER
2949 static void cxgb_netpoll(struct net_device *dev)
2950 {
2951         struct port_info *pi = netdev_priv(dev);
2952         struct adapter *adap = pi->adapter;
2953
2954         if (adap->flags & CXGB4_USING_MSIX) {
2955                 int i;
2956                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2957
2958                 for (i = pi->nqsets; i; i--, rx++)
2959                         t4_sge_intr_msix(0, &rx->rspq);
2960         } else
2961                 t4_intr_handler(adap)(0, adap);
2962 }
2963 #endif
2964
2965 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2966 {
2967         struct port_info *pi = netdev_priv(dev);
2968         struct adapter *adap = pi->adapter;
2969         struct sched_class *e;
2970         struct ch_sched_params p;
2971         struct ch_sched_queue qe;
2972         u32 req_rate;
2973         int err = 0;
2974
2975         if (!can_sched(dev))
2976                 return -ENOTSUPP;
2977
2978         if (index < 0 || index > pi->nqsets - 1)
2979                 return -EINVAL;
2980
2981         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
2982                 dev_err(adap->pdev_dev,
2983                         "Failed to rate limit on queue %d. Link Down?\n",
2984                         index);
2985                 return -EINVAL;
2986         }
2987
2988         /* Convert from Mbps to Kbps */
2989         req_rate = rate * 1000;
2990
2991         /* Max rate is 100 Gbps */
2992         if (req_rate > SCHED_MAX_RATE_KBPS) {
2993                 dev_err(adap->pdev_dev,
2994                         "Invalid rate %u Mbps, Max rate is %u Mbps\n",
2995                         rate, SCHED_MAX_RATE_KBPS / 1000);
2996                 return -ERANGE;
2997         }
2998
2999         /* First unbind the queue from any existing class */
3000         memset(&qe, 0, sizeof(qe));
3001         qe.queue = index;
3002         qe.class = SCHED_CLS_NONE;
3003
3004         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3005         if (err) {
3006                 dev_err(adap->pdev_dev,
3007                         "Unbinding Queue %d on port %d fail. Err: %d\n",
3008                         index, pi->port_id, err);
3009                 return err;
3010         }
3011
3012         /* Queue already unbound */
3013         if (!req_rate)
3014                 return 0;
3015
3016         /* Fetch any available unused or matching scheduling class */
3017         memset(&p, 0, sizeof(p));
3018         p.type = SCHED_CLASS_TYPE_PACKET;
3019         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
3020         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
3021         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3022         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3023         p.u.params.channel  = pi->tx_chan;
3024         p.u.params.class    = SCHED_CLS_NONE;
3025         p.u.params.minrate  = 0;
3026         p.u.params.maxrate  = req_rate;
3027         p.u.params.weight   = 0;
3028         p.u.params.pktsize  = dev->mtu;
3029
3030         e = cxgb4_sched_class_alloc(dev, &p);
3031         if (!e)
3032                 return -ENOMEM;
3033
3034         /* Bind the queue to a scheduling class */
3035         memset(&qe, 0, sizeof(qe));
3036         qe.queue = index;
3037         qe.class = e->idx;
3038
3039         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3040         if (err)
3041                 dev_err(adap->pdev_dev,
3042                         "Queue rate limiting failed. Err: %d\n", err);
3043         return err;
3044 }
3045
3046 static int cxgb_setup_tc_flower(struct net_device *dev,
3047                                 struct tc_cls_flower_offload *cls_flower)
3048 {
3049         switch (cls_flower->command) {
3050         case TC_CLSFLOWER_REPLACE:
3051                 return cxgb4_tc_flower_replace(dev, cls_flower);
3052         case TC_CLSFLOWER_DESTROY:
3053                 return cxgb4_tc_flower_destroy(dev, cls_flower);
3054         case TC_CLSFLOWER_STATS:
3055                 return cxgb4_tc_flower_stats(dev, cls_flower);
3056         default:
3057                 return -EOPNOTSUPP;
3058         }
3059 }
3060
3061 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
3062                                  struct tc_cls_u32_offload *cls_u32)
3063 {
3064         switch (cls_u32->command) {
3065         case TC_CLSU32_NEW_KNODE:
3066         case TC_CLSU32_REPLACE_KNODE:
3067                 return cxgb4_config_knode(dev, cls_u32);
3068         case TC_CLSU32_DELETE_KNODE:
3069                 return cxgb4_delete_knode(dev, cls_u32);
3070         default:
3071                 return -EOPNOTSUPP;
3072         }
3073 }
3074
3075 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3076                                   void *cb_priv)
3077 {
3078         struct net_device *dev = cb_priv;
3079         struct port_info *pi = netdev2pinfo(dev);
3080         struct adapter *adap = netdev2adap(dev);
3081
3082         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3083                 dev_err(adap->pdev_dev,
3084                         "Failed to setup tc on port %d. Link Down?\n",
3085                         pi->port_id);
3086                 return -EINVAL;
3087         }
3088
3089         if (!tc_cls_can_offload_and_chain0(dev, type_data))
3090                 return -EOPNOTSUPP;
3091
3092         switch (type) {
3093         case TC_SETUP_CLSU32:
3094                 return cxgb_setup_tc_cls_u32(dev, type_data);
3095         case TC_SETUP_CLSFLOWER:
3096                 return cxgb_setup_tc_flower(dev, type_data);
3097         default:
3098                 return -EOPNOTSUPP;
3099         }
3100 }
3101
3102 static int cxgb_setup_tc_block(struct net_device *dev,
3103                                struct tc_block_offload *f)
3104 {
3105         struct port_info *pi = netdev2pinfo(dev);
3106
3107         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3108                 return -EOPNOTSUPP;
3109
3110         switch (f->command) {
3111         case TC_BLOCK_BIND:
3112                 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb,
3113                                              pi, dev, f->extack);
3114         case TC_BLOCK_UNBIND:
3115                 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi);
3116                 return 0;
3117         default:
3118                 return -EOPNOTSUPP;
3119         }
3120 }
3121
3122 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3123                          void *type_data)
3124 {
3125         switch (type) {
3126         case TC_SETUP_BLOCK:
3127                 return cxgb_setup_tc_block(dev, type_data);
3128         default:
3129                 return -EOPNOTSUPP;
3130         }
3131 }
3132
3133 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3134                                 struct udp_tunnel_info *ti)