net: hns3: Add support to enable and disable hw errors
[muen/linux.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_cmd.h
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_CMD_H
5 #define __HCLGE_CMD_H
6 #include <linux/types.h>
7 #include <linux/io.h>
8
9 #define HCLGE_CMDQ_TX_TIMEOUT           30000
10
11 struct hclge_dev;
12 struct hclge_desc {
13         __le16 opcode;
14
15 #define HCLGE_CMDQ_RX_INVLD_B           0
16 #define HCLGE_CMDQ_RX_OUTVLD_B          1
17
18         __le16 flag;
19         __le16 retval;
20         __le16 rsv;
21         __le32 data[6];
22 };
23
24 struct hclge_cmq_ring {
25         dma_addr_t desc_dma_addr;
26         struct hclge_desc *desc;
27         struct hclge_dev *dev;
28         u32 head;
29         u32 tail;
30
31         u16 buf_size;
32         u16 desc_num;
33         int next_to_use;
34         int next_to_clean;
35         u8 ring_type; /* cmq ring type */
36         spinlock_t lock; /* Command queue lock */
37 };
38
39 enum hclge_cmd_return_status {
40         HCLGE_CMD_EXEC_SUCCESS  = 0,
41         HCLGE_CMD_NO_AUTH       = 1,
42         HCLGE_CMD_NOT_EXEC      = 2,
43         HCLGE_CMD_QUEUE_FULL    = 3,
44 };
45
46 enum hclge_cmd_status {
47         HCLGE_STATUS_SUCCESS    = 0,
48         HCLGE_ERR_CSQ_FULL      = -1,
49         HCLGE_ERR_CSQ_TIMEOUT   = -2,
50         HCLGE_ERR_CSQ_ERROR     = -3,
51 };
52
53 struct hclge_misc_vector {
54         u8 __iomem *addr;
55         int vector_irq;
56 };
57
58 struct hclge_cmq {
59         struct hclge_cmq_ring csq;
60         struct hclge_cmq_ring crq;
61         u16 tx_timeout;
62         enum hclge_cmd_status last_status;
63 };
64
65 #define HCLGE_CMD_FLAG_IN       BIT(0)
66 #define HCLGE_CMD_FLAG_OUT      BIT(1)
67 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
68 #define HCLGE_CMD_FLAG_WR       BIT(3)
69 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
71
72 enum hclge_opcode_type {
73         /* Generic commands */
74         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
75         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
76         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
77         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
78         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
79         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
80         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
81
82         HCLGE_OPC_STATS_64_BIT          = 0x0030,
83         HCLGE_OPC_STATS_32_BIT          = 0x0031,
84         HCLGE_OPC_STATS_MAC             = 0x0032,
85
86         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
87         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
88         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
89
90         /* MAC command */
91         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
92         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
93         HCLGE_OPC_QUERY_AN_RESULT       = 0x0306,
94         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
95         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
96         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
97         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
98
99         /* PFC/Pause commands */
100         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
101         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
102         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
103         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
104         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
105         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
106         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
107         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
108         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
109         HCLGE_OPC_QOS_MAP               = 0x070A,
110
111         /* ETS/scheduler commands */
112         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
113         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
114         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
115         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
116         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
117         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
118         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
119         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
120         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
121         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
122         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
123         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
124         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
125         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
126         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
127         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
128         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
129
130         /* Packet buffer allocate commands */
131         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
132         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
133         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
134         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
135         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
136         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
137
138         /* TQP management command */
139         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
140
141         /* TQP commands */
142         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
143         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
144         HCLGE_OPC_QUERY_TX_STATUS       = 0x0B03,
145         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
146         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
147         HCLGE_OPC_QUERY_RX_STATUS       = 0x0B13,
148         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
149         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
150         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
151         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
152
153         /* TSO command */
154         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
155
156         /* RSS commands */
157         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
158         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
159         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
160         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
161
162         /* Promisuous mode command */
163         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
164
165         /* Vlan offload commands */
166         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
167         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
168
169         /* Interrupts commands */
170         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
171         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
172
173         /* MAC commands */
174         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
175         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
176         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
177         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
178         HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
179         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
180         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
181
182         /* VLAN commands */
183         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
184         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
185         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
186
187         /* Flow Director commands */
188         HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
189         HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
190         HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
191         HCLGE_OPC_FD_TCAM_OP            = 0x1203,
192         HCLGE_OPC_FD_AD_OP              = 0x1204,
193
194         /* MDIO command */
195         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
196
197         /* QCN commands */
198         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
199         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
200         HCLGE_OPC_QCN_SHAPPING_IR_CFG   = 0x1A03,
201         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
202         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
203         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
204         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
205         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
206
207         /* Mailbox command */
208         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
209
210         /* Led command */
211         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
212 };
213
214 #define HCLGE_TQP_REG_OFFSET            0x80000
215 #define HCLGE_TQP_REG_SIZE              0x200
216
217 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
218 #define HCLGE_RCB_INIT_FLAG_EN_B        0
219 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
220 struct hclge_config_rcb_init_cmd {
221         __le16 rcb_init_flag;
222         u8 rsv[22];
223 };
224
225 struct hclge_tqp_map_cmd {
226         __le16 tqp_id;  /* Absolute tqp id for in this pf */
227         u8 tqp_vf;      /* VF id */
228 #define HCLGE_TQP_MAP_TYPE_PF           0
229 #define HCLGE_TQP_MAP_TYPE_VF           1
230 #define HCLGE_TQP_MAP_TYPE_B            0
231 #define HCLGE_TQP_MAP_EN_B              1
232         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
233         __le16 tqp_vid; /* Virtual id in this pf/vf */
234         u8 rsv[18];
235 };
236
237 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
238
239 enum hclge_int_type {
240         HCLGE_INT_TX,
241         HCLGE_INT_RX,
242         HCLGE_INT_EVENT,
243 };
244
245 struct hclge_ctrl_vector_chain_cmd {
246         u8 int_vector_id;
247         u8 int_cause_num;
248 #define HCLGE_INT_TYPE_S        0
249 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
250 #define HCLGE_TQP_ID_S          2
251 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
252 #define HCLGE_INT_GL_IDX_S      13
253 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
254         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
255         u8 vfid;
256         u8 rsv;
257 };
258
259 #define HCLGE_TC_NUM            8
260 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
261 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
262 struct hclge_tx_buff_alloc_cmd {
263         __le16 tx_pkt_buff[HCLGE_TC_NUM];
264         u8 tx_buff_rsv[8];
265 };
266
267 struct hclge_rx_priv_buff_cmd {
268         __le16 buf_num[HCLGE_TC_NUM];
269         __le16 shared_buf;
270         u8 rsv[6];
271 };
272
273 struct hclge_query_version_cmd {
274         __le32 firmware;
275         __le32 firmware_rsv[5];
276 };
277
278 #define HCLGE_RX_PRIV_EN_B      15
279 #define HCLGE_TC_NUM_ONE_DESC   4
280 struct hclge_priv_wl {
281         __le16 high;
282         __le16 low;
283 };
284
285 struct hclge_rx_priv_wl_buf {
286         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
287 };
288
289 struct hclge_rx_com_thrd {
290         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
291 };
292
293 struct hclge_rx_com_wl {
294         struct hclge_priv_wl com_wl;
295 };
296
297 struct hclge_waterline {
298         u32 low;
299         u32 high;
300 };
301
302 struct hclge_tc_thrd {
303         u32 low;
304         u32 high;
305 };
306
307 struct hclge_priv_buf {
308         struct hclge_waterline wl;      /* Waterline for low and high*/
309         u32 buf_size;   /* TC private buffer size */
310         u32 tx_buf_size;
311         u32 enable;     /* Enable TC private buffer or not */
312 };
313
314 #define HCLGE_MAX_TC_NUM        8
315 struct hclge_shared_buf {
316         struct hclge_waterline self;
317         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
318         u32 buf_size;
319 };
320
321 struct hclge_pkt_buf_alloc {
322         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
323         struct hclge_shared_buf s_buf;
324 };
325
326 #define HCLGE_RX_COM_WL_EN_B    15
327 struct hclge_rx_com_wl_buf_cmd {
328         __le16 high_wl;
329         __le16 low_wl;
330         u8 rsv[20];
331 };
332
333 #define HCLGE_RX_PKT_EN_B       15
334 struct hclge_rx_pkt_buf_cmd {
335         __le16 high_pkt;
336         __le16 low_pkt;
337         u8 rsv[20];
338 };
339
340 #define HCLGE_PF_STATE_DONE_B   0
341 #define HCLGE_PF_STATE_MAIN_B   1
342 #define HCLGE_PF_STATE_BOND_B   2
343 #define HCLGE_PF_STATE_MAC_N_B  6
344 #define HCLGE_PF_MAC_NUM_MASK   0x3
345 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
346 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
347 struct hclge_func_status_cmd {
348         __le32  vf_rst_state[4];
349         u8 pf_state;
350         u8 mac_id;
351         u8 rsv1;
352         u8 pf_cnt_in_mac;
353         u8 pf_num;
354         u8 vf_num;
355         u8 rsv[2];
356 };
357
358 struct hclge_pf_res_cmd {
359         __le16 tqp_num;
360         __le16 buf_size;
361         __le16 msixcap_localid_ba_nic;
362         __le16 msixcap_localid_ba_rocee;
363 #define HCLGE_MSIX_OFT_ROCEE_S          0
364 #define HCLGE_MSIX_OFT_ROCEE_M          GENMASK(15, 0)
365 #define HCLGE_PF_VEC_NUM_S              0
366 #define HCLGE_PF_VEC_NUM_M              GENMASK(7, 0)
367         __le16 pf_intr_vector_number;
368         __le16 pf_own_fun_number;
369         __le32 rsv[3];
370 };
371
372 #define HCLGE_CFG_OFFSET_S      0
373 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
374 #define HCLGE_CFG_RD_LEN_S      24
375 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
376 #define HCLGE_CFG_RD_LEN_BYTES  16
377 #define HCLGE_CFG_RD_LEN_UNIT   4
378
379 #define HCLGE_CFG_VMDQ_S        0
380 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
381 #define HCLGE_CFG_TC_NUM_S      8
382 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
383 #define HCLGE_CFG_TQP_DESC_N_S  16
384 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
385 #define HCLGE_CFG_PHY_ADDR_S    0
386 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
387 #define HCLGE_CFG_MEDIA_TP_S    8
388 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
389 #define HCLGE_CFG_RX_BUF_LEN_S  16
390 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
391 #define HCLGE_CFG_MAC_ADDR_H_S  0
392 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
393 #define HCLGE_CFG_DEFAULT_SPEED_S       16
394 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
395 #define HCLGE_CFG_RSS_SIZE_S    24
396 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
397 #define HCLGE_CFG_SPEED_ABILITY_S       0
398 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
399 #define HCLGE_CFG_UMV_TBL_SPACE_S       16
400 #define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
401
402 struct hclge_cfg_param_cmd {
403         __le32 offset;
404         __le32 rsv;
405         __le32 param[4];
406 };
407
408 #define HCLGE_MAC_MODE          0x0
409 #define HCLGE_DESC_NUM          0x40
410
411 #define HCLGE_ALLOC_VALID_B     0
412 struct hclge_vf_num_cmd {
413         u8 alloc_valid;
414         u8 rsv[23];
415 };
416
417 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
418 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
419 #define HCLGE_RSS_HASH_KEY_NUM          16
420 struct hclge_rss_config_cmd {
421         u8 hash_config;
422         u8 rsv[7];
423         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
424 };
425
426 struct hclge_rss_input_tuple_cmd {
427         u8 ipv4_tcp_en;
428         u8 ipv4_udp_en;
429         u8 ipv4_sctp_en;
430         u8 ipv4_fragment_en;
431         u8 ipv6_tcp_en;
432         u8 ipv6_udp_en;
433         u8 ipv6_sctp_en;
434         u8 ipv6_fragment_en;
435         u8 rsv[16];
436 };
437
438 #define HCLGE_RSS_CFG_TBL_SIZE  16
439
440 struct hclge_rss_indirection_table_cmd {
441         __le16 start_table_index;
442         __le16 rss_set_bitmap;
443         u8 rsv[4];
444         u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
445 };
446
447 #define HCLGE_RSS_TC_OFFSET_S           0
448 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(9, 0)
449 #define HCLGE_RSS_TC_SIZE_S             12
450 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
451 #define HCLGE_RSS_TC_VALID_B            15
452 struct hclge_rss_tc_mode_cmd {
453         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
454         u8 rsv[8];
455 };
456
457 #define HCLGE_LINK_STATUS_UP_B  0
458 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
459 struct hclge_link_status_cmd {
460         u8 status;
461         u8 rsv[23];
462 };
463
464 struct hclge_promisc_param {
465         u8 vf_id;
466         u8 enable;
467 };
468
469 #define HCLGE_PROMISC_TX_EN_B   BIT(4)
470 #define HCLGE_PROMISC_RX_EN_B   BIT(5)
471 #define HCLGE_PROMISC_EN_B      1
472 #define HCLGE_PROMISC_EN_ALL    0x7
473 #define HCLGE_PROMISC_EN_UC     0x1
474 #define HCLGE_PROMISC_EN_MC     0x2
475 #define HCLGE_PROMISC_EN_BC     0x4
476 struct hclge_promisc_cfg_cmd {
477         u8 flag;
478         u8 vf_id;
479         __le16 rsv0;
480         u8 rsv1[20];
481 };
482
483 enum hclge_promisc_type {
484         HCLGE_UNICAST   = 1,
485         HCLGE_MULTICAST = 2,
486         HCLGE_BROADCAST = 3,
487 };
488
489 #define HCLGE_MAC_TX_EN_B       6
490 #define HCLGE_MAC_RX_EN_B       7
491 #define HCLGE_MAC_PAD_TX_B      11
492 #define HCLGE_MAC_PAD_RX_B      12
493 #define HCLGE_MAC_1588_TX_B     13
494 #define HCLGE_MAC_1588_RX_B     14
495 #define HCLGE_MAC_APP_LP_B      15
496 #define HCLGE_MAC_LINE_LP_B     16
497 #define HCLGE_MAC_FCS_TX_B      17
498 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
499 #define HCLGE_MAC_RX_FCS_STRIP_B        19
500 #define HCLGE_MAC_RX_FCS_B      20
501 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
502 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
503
504 struct hclge_config_mac_mode_cmd {
505         __le32 txrx_pad_fcs_loop_en;
506         u8 rsv[20];
507 };
508
509 #define HCLGE_CFG_SPEED_S               0
510 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
511
512 #define HCLGE_CFG_DUPLEX_B              7
513 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
514
515 struct hclge_config_mac_speed_dup_cmd {
516         u8 speed_dup;
517
518 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
519         u8 mac_change_fec_en;
520         u8 rsv[22];
521 };
522
523 #define HCLGE_QUERY_SPEED_S             3
524 #define HCLGE_QUERY_AN_B                0
525 #define HCLGE_QUERY_DUPLEX_B            2
526
527 #define HCLGE_QUERY_SPEED_M             GENMASK(4, 0)
528 #define HCLGE_QUERY_AN_M                BIT(HCLGE_QUERY_AN_B)
529 #define HCLGE_QUERY_DUPLEX_M            BIT(HCLGE_QUERY_DUPLEX_B)
530
531 struct hclge_query_an_speed_dup_cmd {
532         u8 an_syn_dup_speed;
533         u8 pause;
534         u8 rsv[23];
535 };
536
537 #define HCLGE_RING_ID_MASK              GENMASK(9, 0)
538 #define HCLGE_TQP_ENABLE_B              0
539
540 #define HCLGE_MAC_CFG_AN_EN_B           0
541 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
542 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
543 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
544 #define HCLGE_MAC_CFG_AN_RST_B          4
545
546 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
547
548 struct hclge_config_auto_neg_cmd {
549         __le32  cfg_an_cmd_flag;
550         u8      rsv[20];
551 };
552
553 #define HCLGE_MAC_UPLINK_PORT           0x100
554
555 struct hclge_config_max_frm_size_cmd {
556         __le16  max_frm_size;
557         u8      min_frm_size;
558         u8      rsv[21];
559 };
560
561 enum hclge_mac_vlan_tbl_opcode {
562         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
563         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
564         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
565         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
566 };
567
568 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
569 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
570 #define HCLGE_MAC_EPORT_SW_EN_B         12
571 #define HCLGE_MAC_EPORT_TYPE_B          11
572 #define HCLGE_MAC_EPORT_VFID_S          3
573 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
574 #define HCLGE_MAC_EPORT_PFID_S          0
575 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
576 struct hclge_mac_vlan_tbl_entry_cmd {
577         u8      flags;
578         u8      resp_code;
579         __le16  vlan_tag;
580         __le32  mac_addr_hi32;
581         __le16  mac_addr_lo16;
582         __le16  rsv1;
583         u8      entry_type;
584         u8      mc_mac_en;
585         __le16  egress_port;
586         __le16  egress_queue;
587         u8      rsv2[6];
588 };
589
590 #define HCLGE_UMV_SPC_ALC_B     0
591 struct hclge_umv_spc_alc_cmd {
592         u8 allocate;
593         u8 rsv1[3];
594         __le32 space_size;
595         u8 rsv2[16];
596 };
597
598 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
599 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
600 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
601 #define HCLGE_MAC_ETHERTYPE_LLDP                0x88cc
602
603 struct hclge_mac_mgr_tbl_entry_cmd {
604         u8      flags;
605         u8      resp_code;
606         __le16  vlan_tag;
607         __le32  mac_addr_hi32;
608         __le16  mac_addr_lo16;
609         __le16  rsv1;
610         __le16  ethter_type;
611         __le16  egress_port;
612         __le16  egress_queue;
613         u8      sw_port_id_aware;
614         u8      rsv2;
615         u8      i_port_bitmap;
616         u8      i_port_direction;
617         u8      rsv3[2];
618 };
619
620 struct hclge_mac_vlan_add_cmd {
621         __le16  flags;
622         __le16  mac_addr_hi16;
623         __le32  mac_addr_lo32;
624         __le32  mac_addr_msk_hi32;
625         __le16  mac_addr_msk_lo16;
626         __le16  vlan_tag;
627         __le16  ingress_port;
628         __le16  egress_port;
629         u8      rsv[4];
630 };
631
632 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
633 struct hclge_mac_vlan_remove_cmd {
634         __le16  flags;
635         __le16  mac_addr_hi16;
636         __le32  mac_addr_lo32;
637         __le32  mac_addr_msk_hi32;
638         __le16  mac_addr_msk_lo16;
639         __le16  vlan_tag;
640         __le16  ingress_port;
641         __le16  egress_port;
642         u8      rsv[4];
643 };
644
645 struct hclge_vlan_filter_ctrl_cmd {
646         u8 vlan_type;
647         u8 vlan_fe;
648         u8 rsv[22];
649 };
650
651 struct hclge_vlan_filter_pf_cfg_cmd {
652         u8 vlan_offset;
653         u8 vlan_cfg;
654         u8 rsv[2];
655         u8 vlan_offset_bitmap[20];
656 };
657
658 struct hclge_vlan_filter_vf_cfg_cmd {
659         __le16 vlan_id;
660         u8  resp_code;
661         u8  rsv;
662         u8  vlan_cfg;
663         u8  rsv1[3];
664         u8  vf_bitmap[16];
665 };
666
667 #define HCLGE_ACCEPT_TAG1_B             0
668 #define HCLGE_ACCEPT_UNTAG1_B           1
669 #define HCLGE_PORT_INS_TAG1_EN_B        2
670 #define HCLGE_PORT_INS_TAG2_EN_B        3
671 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
672 #define HCLGE_ACCEPT_TAG2_B             5
673 #define HCLGE_ACCEPT_UNTAG2_B           6
674
675 struct hclge_vport_vtag_tx_cfg_cmd {
676         u8 vport_vlan_cfg;
677         u8 vf_offset;
678         u8 rsv1[2];
679         __le16 def_vlan_tag1;
680         __le16 def_vlan_tag2;
681         u8 vf_bitmap[8];
682         u8 rsv2[8];
683 };
684
685 #define HCLGE_REM_TAG1_EN_B             0
686 #define HCLGE_REM_TAG2_EN_B             1
687 #define HCLGE_SHOW_TAG1_EN_B            2
688 #define HCLGE_SHOW_TAG2_EN_B            3
689 struct hclge_vport_vtag_rx_cfg_cmd {
690         u8 vport_vlan_cfg;
691         u8 vf_offset;
692         u8 rsv1[6];
693         u8 vf_bitmap[8];
694         u8 rsv2[8];
695 };
696
697 struct hclge_tx_vlan_type_cfg_cmd {
698         __le16 ot_vlan_type;
699         __le16 in_vlan_type;
700         u8 rsv[20];
701 };
702
703 struct hclge_rx_vlan_type_cfg_cmd {
704         __le16 ot_fst_vlan_type;
705         __le16 ot_sec_vlan_type;
706         __le16 in_fst_vlan_type;
707         __le16 in_sec_vlan_type;
708         u8 rsv[16];
709 };
710
711 struct hclge_cfg_com_tqp_queue_cmd {
712         __le16 tqp_id;
713         __le16 stream_id;
714         u8 enable;
715         u8 rsv[19];
716 };
717
718 struct hclge_cfg_tx_queue_pointer_cmd {
719         __le16 tqp_id;
720         __le16 tx_tail;
721         __le16 tx_head;
722         __le16 fbd_num;
723         __le16 ring_offset;
724         u8 rsv[14];
725 };
726
727 #define HCLGE_TSO_MSS_MIN_S     0
728 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
729
730 #define HCLGE_TSO_MSS_MAX_S     16
731 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
732
733 struct hclge_cfg_tso_status_cmd {
734         __le16 tso_mss_min;
735         __le16 tso_mss_max;
736         u8 rsv[20];
737 };
738
739 #define HCLGE_TSO_MSS_MIN       256
740 #define HCLGE_TSO_MSS_MAX       9668
741
742 #define HCLGE_TQP_RESET_B       0
743 struct hclge_reset_tqp_queue_cmd {
744         __le16 tqp_id;
745         u8 reset_req;
746         u8 ready_to_reset;
747         u8 rsv[20];
748 };
749
750 #define HCLGE_CFG_RESET_MAC_B           3
751 #define HCLGE_CFG_RESET_FUNC_B          7
752 struct hclge_reset_cmd {
753         u8 mac_func_reset;
754         u8 fun_reset_vfid;
755         u8 rsv[22];
756 };
757
758 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
759 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
760 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
761 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
762 struct hclge_serdes_lb_cmd {
763         u8 mask;
764         u8 enable;
765         u8 result;
766         u8 rsv[21];
767 };
768
769 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
770 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
771 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
772 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
773
774 #define HCLGE_TYPE_CRQ                  0
775 #define HCLGE_TYPE_CSQ                  1
776 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
777 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
778 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
779 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
780 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
781 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
782 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
783 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
784 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
785 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
786 #define HCLGE_NIC_CMQ_EN_B              16
787 #define HCLGE_NIC_CMQ_ENABLE            BIT(HCLGE_NIC_CMQ_EN_B)
788 #define HCLGE_NIC_CMQ_DESC_NUM          1024
789 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
790
791 #define HCLGE_LED_LOCATE_STATE_S        0
792 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
793
794 struct hclge_set_led_state_cmd {
795         u8 rsv1[3];
796         u8 locate_led_config;
797         u8 rsv2[20];
798 };
799
800 struct hclge_get_fd_mode_cmd {
801         u8 mode;
802         u8 enable;
803         u8 rsv[22];
804 };
805
806 struct hclge_get_fd_allocation_cmd {
807         __le32 stage1_entry_num;
808         __le32 stage2_entry_num;
809         __le16 stage1_counter_num;
810         __le16 stage2_counter_num;
811         u8 rsv[12];
812 };
813
814 struct hclge_set_fd_key_config_cmd {
815         u8 stage;
816         u8 key_select;
817         u8 inner_sipv6_word_en;
818         u8 inner_dipv6_word_en;
819         u8 outer_sipv6_word_en;
820         u8 outer_dipv6_word_en;
821         u8 rsv1[2];
822         __le32 tuple_mask;
823         __le32 meta_data_mask;
824         u8 rsv2[8];
825 };
826
827 #define HCLGE_FD_EPORT_SW_EN_B          0
828 struct hclge_fd_tcam_config_1_cmd {
829         u8 stage;
830         u8 xy_sel;
831         u8 port_info;
832         u8 rsv1[1];
833         __le32 index;
834         u8 entry_vld;
835         u8 rsv2[7];
836         u8 tcam_data[8];
837 };
838
839 struct hclge_fd_tcam_config_2_cmd {
840         u8 tcam_data[24];
841 };
842
843 struct hclge_fd_tcam_config_3_cmd {
844         u8 tcam_data[20];
845         u8 rsv[4];
846 };
847
848 #define HCLGE_FD_AD_DROP_B              0
849 #define HCLGE_FD_AD_DIRECT_QID_B        1
850 #define HCLGE_FD_AD_QID_S               2
851 #define HCLGE_FD_AD_QID_M               GENMASK(12, 2)
852 #define HCLGE_FD_AD_USE_COUNTER_B       12
853 #define HCLGE_FD_AD_COUNTER_NUM_S       13
854 #define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
855 #define HCLGE_FD_AD_NXT_STEP_B          20
856 #define HCLGE_FD_AD_NXT_KEY_S           21
857 #define HCLGE_FD_AD_NXT_KEY_M           GENMASK(26, 21)
858 #define HCLGE_FD_AD_WR_RULE_ID_B        0
859 #define HCLGE_FD_AD_RULE_ID_S           1
860 #define HCLGE_FD_AD_RULE_ID_M           GENMASK(13, 1)
861
862 struct hclge_fd_ad_config_cmd {
863         u8 stage;
864         u8 rsv1[3];
865         __le32 index;
866         __le64 ad_data;
867         u8 rsv2[8];
868 };
869
870 int hclge_cmd_init(struct hclge_dev *hdev);
871 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
872 {
873         writel(value, base + reg);
874 }
875
876 #define hclge_write_dev(a, reg, value) \
877         hclge_write_reg((a)->io_base, (reg), (value))
878 #define hclge_read_dev(a, reg) \
879         hclge_read_reg((a)->io_base, (reg))
880
881 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
882 {
883         u8 __iomem *reg_addr = READ_ONCE(base);
884
885         return readl(reg_addr + reg);
886 }
887
888 #define HCLGE_SEND_SYNC(flag) \
889         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
890
891 struct hclge_hw;
892 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
893 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
894                                 enum hclge_opcode_type opcode, bool is_read);
895 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
896
897 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
898                                struct hclge_promisc_param *param);
899
900 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
901                                            struct hclge_desc *desc);
902 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
903                                           struct hclge_desc *desc);
904
905 void hclge_destroy_cmd_queue(struct hclge_hw *hw);
906 int hclge_cmd_queue_init(struct hclge_dev *hdev);
907 #endif