8525f18f3f5a34b2f90aa5a38fd049c82d69708f
[muen/linux.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_cmd.h
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_CMD_H
5 #define __HCLGE_CMD_H
6 #include <linux/types.h>
7 #include <linux/io.h>
8
9 #define HCLGE_CMDQ_TX_TIMEOUT           30000
10
11 struct hclge_dev;
12 struct hclge_desc {
13         __le16 opcode;
14
15 #define HCLGE_CMDQ_RX_INVLD_B           0
16 #define HCLGE_CMDQ_RX_OUTVLD_B          1
17
18         __le16 flag;
19         __le16 retval;
20         __le16 rsv;
21         __le32 data[6];
22 };
23
24 struct hclge_cmq_ring {
25         dma_addr_t desc_dma_addr;
26         struct hclge_desc *desc;
27         struct hclge_dev *dev;
28         u32 head;
29         u32 tail;
30
31         u16 buf_size;
32         u16 desc_num;
33         int next_to_use;
34         int next_to_clean;
35         u8 ring_type; /* cmq ring type */
36         spinlock_t lock; /* Command queue lock */
37 };
38
39 enum hclge_cmd_return_status {
40         HCLGE_CMD_EXEC_SUCCESS  = 0,
41         HCLGE_CMD_NO_AUTH       = 1,
42         HCLGE_CMD_NOT_EXEC      = 2,
43         HCLGE_CMD_QUEUE_FULL    = 3,
44 };
45
46 enum hclge_cmd_status {
47         HCLGE_STATUS_SUCCESS    = 0,
48         HCLGE_ERR_CSQ_FULL      = -1,
49         HCLGE_ERR_CSQ_TIMEOUT   = -2,
50         HCLGE_ERR_CSQ_ERROR     = -3,
51 };
52
53 struct hclge_misc_vector {
54         u8 __iomem *addr;
55         int vector_irq;
56 };
57
58 struct hclge_cmq {
59         struct hclge_cmq_ring csq;
60         struct hclge_cmq_ring crq;
61         u16 tx_timeout;
62         enum hclge_cmd_status last_status;
63 };
64
65 #define HCLGE_CMD_FLAG_IN       BIT(0)
66 #define HCLGE_CMD_FLAG_OUT      BIT(1)
67 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
68 #define HCLGE_CMD_FLAG_WR       BIT(3)
69 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
71
72 enum hclge_opcode_type {
73         /* Generic commands */
74         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
75         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
76         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
77         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
78         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
79         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
80         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
81
82         HCLGE_OPC_STATS_64_BIT          = 0x0030,
83         HCLGE_OPC_STATS_32_BIT          = 0x0031,
84         HCLGE_OPC_STATS_MAC             = 0x0032,
85
86         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
87         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
88         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
89
90         /* MAC command */
91         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
92         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
93         HCLGE_OPC_QUERY_AN_RESULT       = 0x0306,
94         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
95         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
96         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
97         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
98
99         /* PFC/Pause commands */
100         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
101         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
102         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
103         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
104         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
105         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
106         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
107         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
108         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
109         HCLGE_OPC_QOS_MAP               = 0x070A,
110
111         /* ETS/scheduler commands */
112         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
113         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
114         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
115         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
116         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
117         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
118         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
119         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
120         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
121         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
122         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
123         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
124         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
125         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
126         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
127         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
128         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
129
130         /* Packet buffer allocate commands */
131         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
132         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
133         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
134         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
135         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
136         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
137
138         /* TQP management command */
139         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
140
141         /* TQP commands */
142         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
143         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
144         HCLGE_OPC_QUERY_TX_STATUS       = 0x0B03,
145         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
146         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
147         HCLGE_OPC_QUERY_RX_STATUS       = 0x0B13,
148         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
149         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
150         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
151         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
152
153         /* TSO command */
154         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
155
156         /* RSS commands */
157         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
158         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
159         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
160         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
161
162         /* Promisuous mode command */
163         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
164
165         /* Vlan offload commands */
166         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
167         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
168
169         /* Interrupts commands */
170         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
171         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
172
173         /* MAC commands */
174         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
175         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
176         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
177         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
178         HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
179         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
180         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
181
182         /* VLAN commands */
183         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
184         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
185         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
186
187         /* Flow Director commands */
188         HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
189         HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
190         HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
191         HCLGE_OPC_FD_TCAM_OP            = 0x1203,
192         HCLGE_OPC_FD_AD_OP              = 0x1204,
193
194         /* MDIO command */
195         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
196
197         /* QCN commands */
198         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
199         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
200         HCLGE_OPC_QCN_SHAPPING_IR_CFG   = 0x1A03,
201         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
202         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
203         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
204         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
205         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
206
207         /* Mailbox command */
208         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
209
210         /* Led command */
211         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
212
213         /* Error INT commands */
214         HCLGE_COMMON_ECC_INT_CFG        = 0x1505,
215 };
216
217 #define HCLGE_TQP_REG_OFFSET            0x80000
218 #define HCLGE_TQP_REG_SIZE              0x200
219
220 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
221 #define HCLGE_RCB_INIT_FLAG_EN_B        0
222 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
223 struct hclge_config_rcb_init_cmd {
224         __le16 rcb_init_flag;
225         u8 rsv[22];
226 };
227
228 struct hclge_tqp_map_cmd {
229         __le16 tqp_id;  /* Absolute tqp id for in this pf */
230         u8 tqp_vf;      /* VF id */
231 #define HCLGE_TQP_MAP_TYPE_PF           0
232 #define HCLGE_TQP_MAP_TYPE_VF           1
233 #define HCLGE_TQP_MAP_TYPE_B            0
234 #define HCLGE_TQP_MAP_EN_B              1
235         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
236         __le16 tqp_vid; /* Virtual id in this pf/vf */
237         u8 rsv[18];
238 };
239
240 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
241
242 enum hclge_int_type {
243         HCLGE_INT_TX,
244         HCLGE_INT_RX,
245         HCLGE_INT_EVENT,
246 };
247
248 struct hclge_ctrl_vector_chain_cmd {
249         u8 int_vector_id;
250         u8 int_cause_num;
251 #define HCLGE_INT_TYPE_S        0
252 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
253 #define HCLGE_TQP_ID_S          2
254 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
255 #define HCLGE_INT_GL_IDX_S      13
256 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
257         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
258         u8 vfid;
259         u8 rsv;
260 };
261
262 #define HCLGE_TC_NUM            8
263 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
264 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
265 struct hclge_tx_buff_alloc_cmd {
266         __le16 tx_pkt_buff[HCLGE_TC_NUM];
267         u8 tx_buff_rsv[8];
268 };
269
270 struct hclge_rx_priv_buff_cmd {
271         __le16 buf_num[HCLGE_TC_NUM];
272         __le16 shared_buf;
273         u8 rsv[6];
274 };
275
276 struct hclge_query_version_cmd {
277         __le32 firmware;
278         __le32 firmware_rsv[5];
279 };
280
281 #define HCLGE_RX_PRIV_EN_B      15
282 #define HCLGE_TC_NUM_ONE_DESC   4
283 struct hclge_priv_wl {
284         __le16 high;
285         __le16 low;
286 };
287
288 struct hclge_rx_priv_wl_buf {
289         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
290 };
291
292 struct hclge_rx_com_thrd {
293         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
294 };
295
296 struct hclge_rx_com_wl {
297         struct hclge_priv_wl com_wl;
298 };
299
300 struct hclge_waterline {
301         u32 low;
302         u32 high;
303 };
304
305 struct hclge_tc_thrd {
306         u32 low;
307         u32 high;
308 };
309
310 struct hclge_priv_buf {
311         struct hclge_waterline wl;      /* Waterline for low and high*/
312         u32 buf_size;   /* TC private buffer size */
313         u32 tx_buf_size;
314         u32 enable;     /* Enable TC private buffer or not */
315 };
316
317 #define HCLGE_MAX_TC_NUM        8
318 struct hclge_shared_buf {
319         struct hclge_waterline self;
320         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
321         u32 buf_size;
322 };
323
324 struct hclge_pkt_buf_alloc {
325         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
326         struct hclge_shared_buf s_buf;
327 };
328
329 #define HCLGE_RX_COM_WL_EN_B    15
330 struct hclge_rx_com_wl_buf_cmd {
331         __le16 high_wl;
332         __le16 low_wl;
333         u8 rsv[20];
334 };
335
336 #define HCLGE_RX_PKT_EN_B       15
337 struct hclge_rx_pkt_buf_cmd {
338         __le16 high_pkt;
339         __le16 low_pkt;
340         u8 rsv[20];
341 };
342
343 #define HCLGE_PF_STATE_DONE_B   0
344 #define HCLGE_PF_STATE_MAIN_B   1
345 #define HCLGE_PF_STATE_BOND_B   2
346 #define HCLGE_PF_STATE_MAC_N_B  6
347 #define HCLGE_PF_MAC_NUM_MASK   0x3
348 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
349 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
350 struct hclge_func_status_cmd {
351         __le32  vf_rst_state[4];
352         u8 pf_state;
353         u8 mac_id;
354         u8 rsv1;
355         u8 pf_cnt_in_mac;
356         u8 pf_num;
357         u8 vf_num;
358         u8 rsv[2];
359 };
360
361 struct hclge_pf_res_cmd {
362         __le16 tqp_num;
363         __le16 buf_size;
364         __le16 msixcap_localid_ba_nic;
365         __le16 msixcap_localid_ba_rocee;
366 #define HCLGE_MSIX_OFT_ROCEE_S          0
367 #define HCLGE_MSIX_OFT_ROCEE_M          GENMASK(15, 0)
368 #define HCLGE_PF_VEC_NUM_S              0
369 #define HCLGE_PF_VEC_NUM_M              GENMASK(7, 0)
370         __le16 pf_intr_vector_number;
371         __le16 pf_own_fun_number;
372         __le32 rsv[3];
373 };
374
375 #define HCLGE_CFG_OFFSET_S      0
376 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
377 #define HCLGE_CFG_RD_LEN_S      24
378 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
379 #define HCLGE_CFG_RD_LEN_BYTES  16
380 #define HCLGE_CFG_RD_LEN_UNIT   4
381
382 #define HCLGE_CFG_VMDQ_S        0
383 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
384 #define HCLGE_CFG_TC_NUM_S      8
385 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
386 #define HCLGE_CFG_TQP_DESC_N_S  16
387 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
388 #define HCLGE_CFG_PHY_ADDR_S    0
389 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
390 #define HCLGE_CFG_MEDIA_TP_S    8
391 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
392 #define HCLGE_CFG_RX_BUF_LEN_S  16
393 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
394 #define HCLGE_CFG_MAC_ADDR_H_S  0
395 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
396 #define HCLGE_CFG_DEFAULT_SPEED_S       16
397 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
398 #define HCLGE_CFG_RSS_SIZE_S    24
399 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
400 #define HCLGE_CFG_SPEED_ABILITY_S       0
401 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
402 #define HCLGE_CFG_UMV_TBL_SPACE_S       16
403 #define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
404
405 struct hclge_cfg_param_cmd {
406         __le32 offset;
407         __le32 rsv;
408         __le32 param[4];
409 };
410
411 #define HCLGE_MAC_MODE          0x0
412 #define HCLGE_DESC_NUM          0x40
413
414 #define HCLGE_ALLOC_VALID_B     0
415 struct hclge_vf_num_cmd {
416         u8 alloc_valid;
417         u8 rsv[23];
418 };
419
420 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
421 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
422 #define HCLGE_RSS_HASH_KEY_NUM          16
423 struct hclge_rss_config_cmd {
424         u8 hash_config;
425         u8 rsv[7];
426         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
427 };
428
429 struct hclge_rss_input_tuple_cmd {
430         u8 ipv4_tcp_en;
431         u8 ipv4_udp_en;
432         u8 ipv4_sctp_en;
433         u8 ipv4_fragment_en;
434         u8 ipv6_tcp_en;
435         u8 ipv6_udp_en;
436         u8 ipv6_sctp_en;
437         u8 ipv6_fragment_en;
438         u8 rsv[16];
439 };
440
441 #define HCLGE_RSS_CFG_TBL_SIZE  16
442
443 struct hclge_rss_indirection_table_cmd {
444         __le16 start_table_index;
445         __le16 rss_set_bitmap;
446         u8 rsv[4];
447         u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
448 };
449
450 #define HCLGE_RSS_TC_OFFSET_S           0
451 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(9, 0)
452 #define HCLGE_RSS_TC_SIZE_S             12
453 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
454 #define HCLGE_RSS_TC_VALID_B            15
455 struct hclge_rss_tc_mode_cmd {
456         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
457         u8 rsv[8];
458 };
459
460 #define HCLGE_LINK_STATUS_UP_B  0
461 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
462 struct hclge_link_status_cmd {
463         u8 status;
464         u8 rsv[23];
465 };
466
467 struct hclge_promisc_param {
468         u8 vf_id;
469         u8 enable;
470 };
471
472 #define HCLGE_PROMISC_TX_EN_B   BIT(4)
473 #define HCLGE_PROMISC_RX_EN_B   BIT(5)
474 #define HCLGE_PROMISC_EN_B      1
475 #define HCLGE_PROMISC_EN_ALL    0x7
476 #define HCLGE_PROMISC_EN_UC     0x1
477 #define HCLGE_PROMISC_EN_MC     0x2
478 #define HCLGE_PROMISC_EN_BC     0x4
479 struct hclge_promisc_cfg_cmd {
480         u8 flag;
481         u8 vf_id;
482         __le16 rsv0;
483         u8 rsv1[20];
484 };
485
486 enum hclge_promisc_type {
487         HCLGE_UNICAST   = 1,
488         HCLGE_MULTICAST = 2,
489         HCLGE_BROADCAST = 3,
490 };
491
492 #define HCLGE_MAC_TX_EN_B       6
493 #define HCLGE_MAC_RX_EN_B       7
494 #define HCLGE_MAC_PAD_TX_B      11
495 #define HCLGE_MAC_PAD_RX_B      12
496 #define HCLGE_MAC_1588_TX_B     13
497 #define HCLGE_MAC_1588_RX_B     14
498 #define HCLGE_MAC_APP_LP_B      15
499 #define HCLGE_MAC_LINE_LP_B     16
500 #define HCLGE_MAC_FCS_TX_B      17
501 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
502 #define HCLGE_MAC_RX_FCS_STRIP_B        19
503 #define HCLGE_MAC_RX_FCS_B      20
504 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
505 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
506
507 struct hclge_config_mac_mode_cmd {
508         __le32 txrx_pad_fcs_loop_en;
509         u8 rsv[20];
510 };
511
512 #define HCLGE_CFG_SPEED_S               0
513 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
514
515 #define HCLGE_CFG_DUPLEX_B              7
516 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
517
518 struct hclge_config_mac_speed_dup_cmd {
519         u8 speed_dup;
520
521 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
522         u8 mac_change_fec_en;
523         u8 rsv[22];
524 };
525
526 #define HCLGE_QUERY_SPEED_S             3
527 #define HCLGE_QUERY_AN_B                0
528 #define HCLGE_QUERY_DUPLEX_B            2
529
530 #define HCLGE_QUERY_SPEED_M             GENMASK(4, 0)
531 #define HCLGE_QUERY_AN_M                BIT(HCLGE_QUERY_AN_B)
532 #define HCLGE_QUERY_DUPLEX_M            BIT(HCLGE_QUERY_DUPLEX_B)
533
534 struct hclge_query_an_speed_dup_cmd {
535         u8 an_syn_dup_speed;
536         u8 pause;
537         u8 rsv[23];
538 };
539
540 #define HCLGE_RING_ID_MASK              GENMASK(9, 0)
541 #define HCLGE_TQP_ENABLE_B              0
542
543 #define HCLGE_MAC_CFG_AN_EN_B           0
544 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
545 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
546 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
547 #define HCLGE_MAC_CFG_AN_RST_B          4
548
549 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
550
551 struct hclge_config_auto_neg_cmd {
552         __le32  cfg_an_cmd_flag;
553         u8      rsv[20];
554 };
555
556 #define HCLGE_MAC_UPLINK_PORT           0x100
557
558 struct hclge_config_max_frm_size_cmd {
559         __le16  max_frm_size;
560         u8      min_frm_size;
561         u8      rsv[21];
562 };
563
564 enum hclge_mac_vlan_tbl_opcode {
565         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
566         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
567         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
568         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
569 };
570
571 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
572 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
573 #define HCLGE_MAC_EPORT_SW_EN_B         12
574 #define HCLGE_MAC_EPORT_TYPE_B          11
575 #define HCLGE_MAC_EPORT_VFID_S          3
576 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
577 #define HCLGE_MAC_EPORT_PFID_S          0
578 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
579 struct hclge_mac_vlan_tbl_entry_cmd {
580         u8      flags;
581         u8      resp_code;
582         __le16  vlan_tag;
583         __le32  mac_addr_hi32;
584         __le16  mac_addr_lo16;
585         __le16  rsv1;
586         u8      entry_type;
587         u8      mc_mac_en;
588         __le16  egress_port;
589         __le16  egress_queue;
590         u8      rsv2[6];
591 };
592
593 #define HCLGE_UMV_SPC_ALC_B     0
594 struct hclge_umv_spc_alc_cmd {
595         u8 allocate;
596         u8 rsv1[3];
597         __le32 space_size;
598         u8 rsv2[16];
599 };
600
601 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
602 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
603 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
604 #define HCLGE_MAC_ETHERTYPE_LLDP                0x88cc
605
606 struct hclge_mac_mgr_tbl_entry_cmd {
607         u8      flags;
608         u8      resp_code;
609         __le16  vlan_tag;
610         __le32  mac_addr_hi32;
611         __le16  mac_addr_lo16;
612         __le16  rsv1;
613         __le16  ethter_type;
614         __le16  egress_port;
615         __le16  egress_queue;
616         u8      sw_port_id_aware;
617         u8      rsv2;
618         u8      i_port_bitmap;
619         u8      i_port_direction;
620         u8      rsv3[2];
621 };
622
623 struct hclge_mac_vlan_add_cmd {
624         __le16  flags;
625         __le16  mac_addr_hi16;
626         __le32  mac_addr_lo32;
627         __le32  mac_addr_msk_hi32;
628         __le16  mac_addr_msk_lo16;
629         __le16  vlan_tag;
630         __le16  ingress_port;
631         __le16  egress_port;
632         u8      rsv[4];
633 };
634
635 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
636 struct hclge_mac_vlan_remove_cmd {
637         __le16  flags;
638         __le16  mac_addr_hi16;
639         __le32  mac_addr_lo32;
640         __le32  mac_addr_msk_hi32;
641         __le16  mac_addr_msk_lo16;
642         __le16  vlan_tag;
643         __le16  ingress_port;
644         __le16  egress_port;
645         u8      rsv[4];
646 };
647
648 struct hclge_vlan_filter_ctrl_cmd {
649         u8 vlan_type;
650         u8 vlan_fe;
651         u8 rsv[22];
652 };
653
654 struct hclge_vlan_filter_pf_cfg_cmd {
655         u8 vlan_offset;
656         u8 vlan_cfg;
657         u8 rsv[2];
658         u8 vlan_offset_bitmap[20];
659 };
660
661 struct hclge_vlan_filter_vf_cfg_cmd {
662         __le16 vlan_id;
663         u8  resp_code;
664         u8  rsv;
665         u8  vlan_cfg;
666         u8  rsv1[3];
667         u8  vf_bitmap[16];
668 };
669
670 #define HCLGE_ACCEPT_TAG1_B             0
671 #define HCLGE_ACCEPT_UNTAG1_B           1
672 #define HCLGE_PORT_INS_TAG1_EN_B        2
673 #define HCLGE_PORT_INS_TAG2_EN_B        3
674 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
675 #define HCLGE_ACCEPT_TAG2_B             5
676 #define HCLGE_ACCEPT_UNTAG2_B           6
677
678 struct hclge_vport_vtag_tx_cfg_cmd {
679         u8 vport_vlan_cfg;
680         u8 vf_offset;
681         u8 rsv1[2];
682         __le16 def_vlan_tag1;
683         __le16 def_vlan_tag2;
684         u8 vf_bitmap[8];
685         u8 rsv2[8];
686 };
687
688 #define HCLGE_REM_TAG1_EN_B             0
689 #define HCLGE_REM_TAG2_EN_B             1
690 #define HCLGE_SHOW_TAG1_EN_B            2
691 #define HCLGE_SHOW_TAG2_EN_B            3
692 struct hclge_vport_vtag_rx_cfg_cmd {
693         u8 vport_vlan_cfg;
694         u8 vf_offset;
695         u8 rsv1[6];
696         u8 vf_bitmap[8];
697         u8 rsv2[8];
698 };
699
700 struct hclge_tx_vlan_type_cfg_cmd {
701         __le16 ot_vlan_type;
702         __le16 in_vlan_type;
703         u8 rsv[20];
704 };
705
706 struct hclge_rx_vlan_type_cfg_cmd {
707         __le16 ot_fst_vlan_type;
708         __le16 ot_sec_vlan_type;
709         __le16 in_fst_vlan_type;
710         __le16 in_sec_vlan_type;
711         u8 rsv[16];
712 };
713
714 struct hclge_cfg_com_tqp_queue_cmd {
715         __le16 tqp_id;
716         __le16 stream_id;
717         u8 enable;
718         u8 rsv[19];
719 };
720
721 struct hclge_cfg_tx_queue_pointer_cmd {
722         __le16 tqp_id;
723         __le16 tx_tail;
724         __le16 tx_head;
725         __le16 fbd_num;
726         __le16 ring_offset;
727         u8 rsv[14];
728 };
729
730 #define HCLGE_TSO_MSS_MIN_S     0
731 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
732
733 #define HCLGE_TSO_MSS_MAX_S     16
734 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
735
736 struct hclge_cfg_tso_status_cmd {
737         __le16 tso_mss_min;
738         __le16 tso_mss_max;
739         u8 rsv[20];
740 };
741
742 #define HCLGE_TSO_MSS_MIN       256
743 #define HCLGE_TSO_MSS_MAX       9668
744
745 #define HCLGE_TQP_RESET_B       0
746 struct hclge_reset_tqp_queue_cmd {
747         __le16 tqp_id;
748         u8 reset_req;
749         u8 ready_to_reset;
750         u8 rsv[20];
751 };
752
753 #define HCLGE_CFG_RESET_MAC_B           3
754 #define HCLGE_CFG_RESET_FUNC_B          7
755 struct hclge_reset_cmd {
756         u8 mac_func_reset;
757         u8 fun_reset_vfid;
758         u8 rsv[22];
759 };
760
761 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
762 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
763 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
764 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
765 struct hclge_serdes_lb_cmd {
766         u8 mask;
767         u8 enable;
768         u8 result;
769         u8 rsv[21];
770 };
771
772 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
773 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
774 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
775 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
776
777 #define HCLGE_TYPE_CRQ                  0
778 #define HCLGE_TYPE_CSQ                  1
779 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
780 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
781 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
782 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
783 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
784 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
785 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
786 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
787 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
788 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
789 #define HCLGE_NIC_CMQ_EN_B              16
790 #define HCLGE_NIC_CMQ_ENABLE            BIT(HCLGE_NIC_CMQ_EN_B)
791 #define HCLGE_NIC_CMQ_DESC_NUM          1024
792 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
793
794 #define HCLGE_LED_LOCATE_STATE_S        0
795 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
796
797 struct hclge_set_led_state_cmd {
798         u8 rsv1[3];
799         u8 locate_led_config;
800         u8 rsv2[20];
801 };
802
803 struct hclge_get_fd_mode_cmd {
804         u8 mode;
805         u8 enable;
806         u8 rsv[22];
807 };
808
809 struct hclge_get_fd_allocation_cmd {
810         __le32 stage1_entry_num;
811         __le32 stage2_entry_num;
812         __le16 stage1_counter_num;
813         __le16 stage2_counter_num;
814         u8 rsv[12];
815 };
816
817 struct hclge_set_fd_key_config_cmd {
818         u8 stage;
819         u8 key_select;
820         u8 inner_sipv6_word_en;
821         u8 inner_dipv6_word_en;
822         u8 outer_sipv6_word_en;
823         u8 outer_dipv6_word_en;
824         u8 rsv1[2];
825         __le32 tuple_mask;
826         __le32 meta_data_mask;
827         u8 rsv2[8];
828 };
829
830 #define HCLGE_FD_EPORT_SW_EN_B          0
831 struct hclge_fd_tcam_config_1_cmd {
832         u8 stage;
833         u8 xy_sel;
834         u8 port_info;
835         u8 rsv1[1];
836         __le32 index;
837         u8 entry_vld;
838         u8 rsv2[7];
839         u8 tcam_data[8];
840 };
841
842 struct hclge_fd_tcam_config_2_cmd {
843         u8 tcam_data[24];
844 };
845
846 struct hclge_fd_tcam_config_3_cmd {
847         u8 tcam_data[20];
848         u8 rsv[4];
849 };
850
851 #define HCLGE_FD_AD_DROP_B              0
852 #define HCLGE_FD_AD_DIRECT_QID_B        1
853 #define HCLGE_FD_AD_QID_S               2
854 #define HCLGE_FD_AD_QID_M               GENMASK(12, 2)
855 #define HCLGE_FD_AD_USE_COUNTER_B       12
856 #define HCLGE_FD_AD_COUNTER_NUM_S       13
857 #define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
858 #define HCLGE_FD_AD_NXT_STEP_B          20
859 #define HCLGE_FD_AD_NXT_KEY_S           21
860 #define HCLGE_FD_AD_NXT_KEY_M           GENMASK(26, 21)
861 #define HCLGE_FD_AD_WR_RULE_ID_B        0
862 #define HCLGE_FD_AD_RULE_ID_S           1
863 #define HCLGE_FD_AD_RULE_ID_M           GENMASK(13, 1)
864
865 struct hclge_fd_ad_config_cmd {
866         u8 stage;
867         u8 rsv1[3];
868         __le32 index;
869         __le64 ad_data;
870         u8 rsv2[8];
871 };
872
873 int hclge_cmd_init(struct hclge_dev *hdev);
874 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
875 {
876         writel(value, base + reg);
877 }
878
879 #define hclge_write_dev(a, reg, value) \
880         hclge_write_reg((a)->io_base, (reg), (value))
881 #define hclge_read_dev(a, reg) \
882         hclge_read_reg((a)->io_base, (reg))
883
884 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
885 {
886         u8 __iomem *reg_addr = READ_ONCE(base);
887
888         return readl(reg_addr + reg);
889 }
890
891 #define HCLGE_SEND_SYNC(flag) \
892         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
893
894 struct hclge_hw;
895 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
896 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
897                                 enum hclge_opcode_type opcode, bool is_read);
898 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
899
900 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
901                                struct hclge_promisc_param *param);
902
903 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
904                                            struct hclge_desc *desc);
905 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
906                                           struct hclge_desc *desc);
907
908 void hclge_destroy_cmd_queue(struct hclge_hw *hw);
909 int hclge_cmd_queue_init(struct hclge_dev *hdev);
910 #endif