d2640d14522224842d0ce5e3ce3477a09b3db3f8
[muen/linux.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_err.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3
4 #include "hclge_err.h"
5
6 static const struct hclge_hw_blk hw_blk[] = {
7         { /* sentinel */ }
8 };
9
10 int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state)
11 {
12         struct device *dev = &hdev->pdev->dev;
13         int ret = 0;
14         int i = 0;
15
16         while (hw_blk[i].name) {
17                 if (!hw_blk[i].enable_error) {
18                         i++;
19                         continue;
20                 }
21                 ret = hw_blk[i].enable_error(hdev, state);
22                 if (ret) {
23                         dev_err(dev, "fail(%d) to en/disable err int\n", ret);
24                         return ret;
25                 }
26                 i++;
27         }
28
29         return ret;
30 }
31
32 pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev)
33 {
34         struct hclge_dev *hdev = ae_dev->priv;
35         struct device *dev = &hdev->pdev->dev;
36         u32 sts, val;
37         int i = 0;
38
39         sts = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
40
41         /* Processing Non-fatal errors */
42         if (sts & HCLGE_RAS_REG_NFE_MASK) {
43                 val = (sts >> HCLGE_RAS_REG_NFE_SHIFT) & 0xFF;
44                 i = 0;
45                 while (hw_blk[i].name) {
46                         if (!(hw_blk[i].msk & val)) {
47                                 i++;
48                                 continue;
49                         }
50                         dev_warn(dev, "%s ras non-fatal error identified\n",
51                                  hw_blk[i].name);
52                         if (hw_blk[i].process_error)
53                                 hw_blk[i].process_error(hdev,
54                                                          HCLGE_ERR_INT_RAS_NFE);
55                         i++;
56                 }
57         }
58
59         return PCI_ERS_RESULT_NEED_RESET;
60 }