drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <net/rtnetlink.h>
  16 #include "hclge_cmd.h"
  17 #include "hclge_dcb.h"
  18 #include "hclge_main.h"
  19 #include "hclge_mbx.h"
  20 #include "hclge_mdio.h"
  21 #include "hclge_tm.h"
  22 #include "hclge_err.h"
  23 #include "hnae3.h"
  24
  25 #define HCLGE_NAME                      "hclge"
  26 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  27 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
  28
  29 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
  30 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  31 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  32 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
  33                                u16 *allocated_size, bool is_alloc);
  34
  35 static struct hnae3_ae_algo ae_algo;
  36
  37 static const struct pci_device_id ae_algo_pci_tbl[] = {
  38         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  39         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  40         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  41         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  42         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  43         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  44         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  45         /* required last entry */
  46         {0, }
  47 };
  48
  49 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  50
  51 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
  52         "App    Loopback test",
  53         "Serdes serial Loopback test",
  54         "Serdes parallel Loopback test",
  55         "Phy    Loopback test"
  56 };
  57
  58 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
  59         {"mac_tx_mac_pause_num",
  60                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
  61         {"mac_rx_mac_pause_num",
  62                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
  63         {"mac_tx_pfc_pri0_pkt_num",
  64                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
  65         {"mac_tx_pfc_pri1_pkt_num",
  66                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
  67         {"mac_tx_pfc_pri2_pkt_num",
  68                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
  69         {"mac_tx_pfc_pri3_pkt_num",
  70                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
  71         {"mac_tx_pfc_pri4_pkt_num",
  72                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
  73         {"mac_tx_pfc_pri5_pkt_num",
  74                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
  75         {"mac_tx_pfc_pri6_pkt_num",
  76                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
  77         {"mac_tx_pfc_pri7_pkt_num",
  78                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
  79         {"mac_rx_pfc_pri0_pkt_num",
  80                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
  81         {"mac_rx_pfc_pri1_pkt_num",
  82                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
  83         {"mac_rx_pfc_pri2_pkt_num",
  84                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
  85         {"mac_rx_pfc_pri3_pkt_num",
  86                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
  87         {"mac_rx_pfc_pri4_pkt_num",
  88                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
  89         {"mac_rx_pfc_pri5_pkt_num",
  90                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
  91         {"mac_rx_pfc_pri6_pkt_num",
  92                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
  93         {"mac_rx_pfc_pri7_pkt_num",
  94                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
  95         {"mac_tx_total_pkt_num",
  96                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
  97         {"mac_tx_total_oct_num",
  98                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
  99         {"mac_tx_good_pkt_num",
 100                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 101         {"mac_tx_bad_pkt_num",
 102                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 103         {"mac_tx_good_oct_num",
 104                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 105         {"mac_tx_bad_oct_num",
 106                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 107         {"mac_tx_uni_pkt_num",
 108                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 109         {"mac_tx_multi_pkt_num",
 110                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 111         {"mac_tx_broad_pkt_num",
 112                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 113         {"mac_tx_undersize_pkt_num",
 114                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 115         {"mac_tx_oversize_pkt_num",
 116                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 117         {"mac_tx_64_oct_pkt_num",
 118                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 119         {"mac_tx_65_127_oct_pkt_num",
 120                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 121         {"mac_tx_128_255_oct_pkt_num",
 122                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 123         {"mac_tx_256_511_oct_pkt_num",
 124                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 125         {"mac_tx_512_1023_oct_pkt_num",
 126                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 127         {"mac_tx_1024_1518_oct_pkt_num",
 128                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 129         {"mac_tx_1519_2047_oct_pkt_num",
 130                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 131         {"mac_tx_2048_4095_oct_pkt_num",
 132                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 133         {"mac_tx_4096_8191_oct_pkt_num",
 134                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 135         {"mac_tx_8192_9216_oct_pkt_num",
 136                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 137         {"mac_tx_9217_12287_oct_pkt_num",
 138                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 139         {"mac_tx_12288_16383_oct_pkt_num",
 140                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 141         {"mac_tx_1519_max_good_pkt_num",
 142                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 143         {"mac_tx_1519_max_bad_pkt_num",
 144                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 145         {"mac_rx_total_pkt_num",
 146                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 147         {"mac_rx_total_oct_num",
 148                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 149         {"mac_rx_good_pkt_num",
 150                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 151         {"mac_rx_bad_pkt_num",
 152                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 153         {"mac_rx_good_oct_num",
 154                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 155         {"mac_rx_bad_oct_num",
 156                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 157         {"mac_rx_uni_pkt_num",
 158                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 159         {"mac_rx_multi_pkt_num",
 160                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 161         {"mac_rx_broad_pkt_num",
 162                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 163         {"mac_rx_undersize_pkt_num",
 164                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 165         {"mac_rx_oversize_pkt_num",
 166                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 167         {"mac_rx_64_oct_pkt_num",
 168                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 169         {"mac_rx_65_127_oct_pkt_num",
 170                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 171         {"mac_rx_128_255_oct_pkt_num",
 172                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 173         {"mac_rx_256_511_oct_pkt_num",
 174                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 175         {"mac_rx_512_1023_oct_pkt_num",
 176                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 177         {"mac_rx_1024_1518_oct_pkt_num",
 178                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 179         {"mac_rx_1519_2047_oct_pkt_num",
 180                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 181         {"mac_rx_2048_4095_oct_pkt_num",
 182                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 183         {"mac_rx_4096_8191_oct_pkt_num",
 184                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 185         {"mac_rx_8192_9216_oct_pkt_num",
 186                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 187         {"mac_rx_9217_12287_oct_pkt_num",
 188                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 189         {"mac_rx_12288_16383_oct_pkt_num",
 190                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 191         {"mac_rx_1519_max_good_pkt_num",
 192                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 193         {"mac_rx_1519_max_bad_pkt_num",
 194                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 195
 196         {"mac_tx_fragment_pkt_num",
 197                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 198         {"mac_tx_undermin_pkt_num",
 199                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 200         {"mac_tx_jabber_pkt_num",
 201                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 202         {"mac_tx_err_all_pkt_num",
 203                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 204         {"mac_tx_from_app_good_pkt_num",
 205                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 206         {"mac_tx_from_app_bad_pkt_num",
 207                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 208         {"mac_rx_fragment_pkt_num",
 209                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 210         {"mac_rx_undermin_pkt_num",
 211                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 212         {"mac_rx_jabber_pkt_num",
 213                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 214         {"mac_rx_fcs_err_pkt_num",
 215                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 216         {"mac_rx_send_app_good_pkt_num",
 217                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 218         {"mac_rx_send_app_bad_pkt_num",
 219                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 220 };
 221
 222 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 223         {
 224                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 225                 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
 226                 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
 227                 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
 228                 .i_port_bitmap = 0x1,
 229         },
 230 };
 231
 232 static int hclge_mac_update_stats(struct hclge_dev *hdev)
 233 {
 234 #define HCLGE_MAC_CMD_NUM 21
 235 #define HCLGE_RTN_DATA_NUM 4
 236
 237         u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
 238         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 239         __le64 *desc_data;
 240         int i, k, n;
 241         int ret;
 242
 243         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 244         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 245         if (ret) {
 246                 dev_err(&hdev->pdev->dev,
 247                         "Get MAC pkt stats fail, status = %d.\n", ret);
 248
 249                 return ret;
 250         }
 251
 252         for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
 253                 if (unlikely(i == 0)) {
 254                         desc_data = (__le64 *)(&desc[i].data[0]);
 255                         n = HCLGE_RTN_DATA_NUM - 2;
 256                 } else {
 257                         desc_data = (__le64 *)(&desc[i]);
 258                         n = HCLGE_RTN_DATA_NUM;
 259                 }
 260                 for (k = 0; k < n; k++) {
 261                         *data++ += le64_to_cpu(*desc_data);
 262                         desc_data++;
 263                 }
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
 270 {
 271         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 272         struct hclge_vport *vport = hclge_get_vport(handle);
 273         struct hclge_dev *hdev = vport->back;
 274         struct hnae3_queue *queue;
 275         struct hclge_desc desc[1];
 276         struct hclge_tqp *tqp;
 277         int ret, i;
 278
 279         for (i = 0; i < kinfo->num_tqps; i++) {
 280                 queue = handle->kinfo.tqp[i];
 281                 tqp = container_of(queue, struct hclge_tqp, q);
 282                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 283                 hclge_cmd_setup_basic_desc(&desc[0],
 284                                            HCLGE_OPC_QUERY_RX_STATUS,
 285                                            true);
 286
 287                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 288                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 289                 if (ret) {
 290                         dev_err(&hdev->pdev->dev,
 291                                 "Query tqp stat fail, status = %d,queue = %d\n",
 292                                 ret,    i);
 293                         return ret;
 294                 }
 295                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 296                         le32_to_cpu(desc[0].data[1]);
 297         }
 298
 299         for (i = 0; i < kinfo->num_tqps; i++) {
 300                 queue = handle->kinfo.tqp[i];
 301                 tqp = container_of(queue, struct hclge_tqp, q);
 302                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 303                 hclge_cmd_setup_basic_desc(&desc[0],
 304                                            HCLGE_OPC_QUERY_TX_STATUS,
 305                                            true);
 306
 307                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 308                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 309                 if (ret) {
 310                         dev_err(&hdev->pdev->dev,
 311                                 "Query tqp stat fail, status = %d,queue = %d\n",
 312                                 ret, i);
 313                         return ret;
 314                 }
 315                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 316                         le32_to_cpu(desc[0].data[1]);
 317         }
 318
 319         return 0;
 320 }
 321
 322 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 323 {
 324         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 325         struct hclge_tqp *tqp;
 326         u64 *buff = data;
 327         int i;
 328
 329         for (i = 0; i < kinfo->num_tqps; i++) {
 330                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 331                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 332         }
 333
 334         for (i = 0; i < kinfo->num_tqps; i++) {
 335                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 336                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 337         }
 338
 339         return buff;
 340 }
 341
 342 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
 343 {
 344         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 345
 346         return kinfo->num_tqps * (2);
 347 }
 348
 349 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 350 {
 351         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 352         u8 *buff = data;
 353         int i = 0;
 354
 355         for (i = 0; i < kinfo->num_tqps; i++) {
 356                 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
 357                         struct hclge_tqp, q);
 358                 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
 359                          tqp->index);
 360                 buff = buff + ETH_GSTRING_LEN;
 361         }
 362
 363         for (i = 0; i < kinfo->num_tqps; i++) {
 364                 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
 365                         struct hclge_tqp, q);
 366                 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
 367                          tqp->index);
 368                 buff = buff + ETH_GSTRING_LEN;
 369         }
 370
 371         return buff;
 372 }
 373
 374 static u64 *hclge_comm_get_stats(void *comm_stats,
 375                                  const struct hclge_comm_stats_str strs[],
 376                                  int size, u64 *data)
 377 {
 378         u64 *buf = data;
 379         u32 i;
 380
 381         for (i = 0; i < size; i++)
 382                 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
 383
 384         return buf + size;
 385 }
 386
 387 static u8 *hclge_comm_get_strings(u32 stringset,
 388                                   const struct hclge_comm_stats_str strs[],
 389                                   int size, u8 *data)
 390 {
 391         char *buff = (char *)data;
 392         u32 i;
 393
 394         if (stringset != ETH_SS_STATS)
 395                 return buff;
 396
 397         for (i = 0; i < size; i++) {
 398                 snprintf(buff, ETH_GSTRING_LEN,
 399                          strs[i].desc);
 400                 buff = buff + ETH_GSTRING_LEN;
 401         }
 402
 403         return (u8 *)buff;
 404 }
 405
 406 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
 407                                  struct net_device_stats *net_stats)
 408 {
 409         net_stats->tx_dropped = 0;
 410         net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 411         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 412         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 413
 414         net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
 415         net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
 416
 417         net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 418         net_stats->rx_length_errors =
 419                 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 420         net_stats->rx_length_errors +=
 421                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 422         net_stats->rx_over_errors =
 423                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 424 }
 425
 426 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 427 {
 428         struct hnae3_handle *handle;
 429         int status;
 430
 431         handle = &hdev->vport[0].nic;
 432         if (handle->client) {
 433                 status = hclge_tqps_update_stats(handle);
 434                 if (status) {
 435                         dev_err(&hdev->pdev->dev,
 436                                 "Update TQPS stats fail, status = %d.\n",
 437                                 status);
 438                 }
 439         }
 440
 441         status = hclge_mac_update_stats(hdev);
 442         if (status)
 443                 dev_err(&hdev->pdev->dev,
 444                         "Update MAC stats fail, status = %d.\n", status);
 445
 446         hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
 447 }
 448
 449 static void hclge_update_stats(struct hnae3_handle *handle,
 450                                struct net_device_stats *net_stats)
 451 {
 452         struct hclge_vport *vport = hclge_get_vport(handle);
 453         struct hclge_dev *hdev = vport->back;
 454         struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
 455         int status;
 456
 457         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 458                 return;
 459
 460         status = hclge_mac_update_stats(hdev);
 461         if (status)
 462                 dev_err(&hdev->pdev->dev,
 463                         "Update MAC stats fail, status = %d.\n",
 464                         status);
 465
 466         status = hclge_tqps_update_stats(handle);
 467         if (status)
 468                 dev_err(&hdev->pdev->dev,
 469                         "Update TQPS stats fail, status = %d.\n",
 470                         status);
 471
 472         hclge_update_netstat(hw_stats, net_stats);
 473
 474         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 475 }
 476
 477 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 478 {
 479 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
 480                 HNAE3_SUPPORT_PHY_LOOPBACK |\
 481                 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
 482                 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
 483
 484         struct hclge_vport *vport = hclge_get_vport(handle);
 485         struct hclge_dev *hdev = vport->back;
 486         int count = 0;
 487
 488         /* Loopback test support rules:
 489          * mac: only GE mode support
 490          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 491          * phy: only support when phy device exist on board
 492          */
 493         if (stringset == ETH_SS_TEST) {
 494                 /* clear loopback bit flags at first */
 495                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 496                 if (hdev->pdev->revision >= 0x21 ||
 497                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 498                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 499                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 500                         count += 1;
 501                         handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
 502                 }
 503
 504                 count += 2;
 505                 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 506                 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
 507         } else if (stringset == ETH_SS_STATS) {
 508                 count = ARRAY_SIZE(g_mac_stats_string) +
 509                         hclge_tqps_get_sset_count(handle, stringset);
 510         }
 511
 512         return count;
 513 }
 514
 515 static void hclge_get_strings(struct hnae3_handle *handle,
 516                               u32 stringset,
 517                               u8 *data)
 518 {
 519         u8 *p = (char *)data;
 520         int size;
 521
 522         if (stringset == ETH_SS_STATS) {
 523                 size = ARRAY_SIZE(g_mac_stats_string);
 524                 p = hclge_comm_get_strings(stringset,
 525                                            g_mac_stats_string,
 526                                            size,
 527                                            p);
 528                 p = hclge_tqps_get_strings(handle, p);
 529         } else if (stringset == ETH_SS_TEST) {
 530                 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
 531                         memcpy(p,
 532                                hns3_nic_test_strs[HNAE3_LOOP_APP],
 533                                ETH_GSTRING_LEN);
 534                         p += ETH_GSTRING_LEN;
 535                 }
 536                 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
 537                         memcpy(p,
 538                                hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
 539                                ETH_GSTRING_LEN);
 540                         p += ETH_GSTRING_LEN;
 541                 }
 542                 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
 543                         memcpy(p,
 544                                hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
 545                                ETH_GSTRING_LEN);
 546                         p += ETH_GSTRING_LEN;
 547                 }
 548                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 549                         memcpy(p,
 550                                hns3_nic_test_strs[HNAE3_LOOP_PHY],
 551                                ETH_GSTRING_LEN);
 552                         p += ETH_GSTRING_LEN;
 553                 }
 554         }
 555 }
 556
 557 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 558 {
 559         struct hclge_vport *vport = hclge_get_vport(handle);
 560         struct hclge_dev *hdev = vport->back;
 561         u64 *p;
 562
 563         p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
 564                                  g_mac_stats_string,
 565                                  ARRAY_SIZE(g_mac_stats_string),
 566                                  data);
 567         p = hclge_tqps_get_stats(handle, p);
 568 }
 569
 570 static int hclge_parse_func_status(struct hclge_dev *hdev,
 571                                    struct hclge_func_status_cmd *status)
 572 {
 573         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 574                 return -EINVAL;
 575
 576         /* Set the pf to main pf */
 577         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 578                 hdev->flag |= HCLGE_FLAG_MAIN;
 579         else
 580                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 581
 582         return 0;
 583 }
 584
 585 static int hclge_query_function_status(struct hclge_dev *hdev)
 586 {
 587         struct hclge_func_status_cmd *req;
 588         struct hclge_desc desc;
 589         int timeout = 0;
 590         int ret;
 591
 592         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 593         req = (struct hclge_func_status_cmd *)desc.data;
 594
 595         do {
 596                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 597                 if (ret) {
 598                         dev_err(&hdev->pdev->dev,
 599                                 "query function status failed %d.\n",
 600                                 ret);
 601
 602                         return ret;
 603                 }
 604
 605                 /* Check pf reset is done */
 606                 if (req->pf_state)
 607                         break;
 608                 usleep_range(1000, 2000);
 609         } while (timeout++ < 5);
 610
 611         ret = hclge_parse_func_status(hdev, req);
 612
 613         return ret;
 614 }
 615
 616 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 617 {
 618         struct hclge_pf_res_cmd *req;
 619         struct hclge_desc desc;
 620         int ret;
 621
 622         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 623         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 624         if (ret) {
 625                 dev_err(&hdev->pdev->dev,
 626                         "query pf resource failed %d.\n", ret);
 627                 return ret;
 628         }
 629
 630         req = (struct hclge_pf_res_cmd *)desc.data;
 631         hdev->num_tqps = __le16_to_cpu(req->tqp_num);
 632         hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 633
 634         if (hnae3_dev_roce_supported(hdev)) {
 635                 hdev->roce_base_msix_offset =
 636                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
 637                                 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
 638                 hdev->num_roce_msi =
 639                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 640                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 641
 642                 /* PF should have NIC vectors and Roce vectors,
 643                  * NIC vectors are queued before Roce vectors.
 644                  */
 645                 hdev->num_msi = hdev->num_roce_msi  +
 646                                 hdev->roce_base_msix_offset;
 647         } else {
 648                 hdev->num_msi =
 649                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 650                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 651         }
 652
 653         return 0;
 654 }
 655
 656 static int hclge_parse_speed(int speed_cmd, int *speed)
 657 {
 658         switch (speed_cmd) {
 659         case 6:
 660                 *speed = HCLGE_MAC_SPEED_10M;
 661                 break;
 662         case 7:
 663                 *speed = HCLGE_MAC_SPEED_100M;
 664                 break;
 665         case 0:
 666                 *speed = HCLGE_MAC_SPEED_1G;
 667                 break;
 668         case 1:
 669                 *speed = HCLGE_MAC_SPEED_10G;
 670                 break;
 671         case 2:
 672                 *speed = HCLGE_MAC_SPEED_25G;
 673                 break;
 674         case 3:
 675                 *speed = HCLGE_MAC_SPEED_40G;
 676                 break;
 677         case 4:
 678                 *speed = HCLGE_MAC_SPEED_50G;
 679                 break;
 680         case 5:
 681                 *speed = HCLGE_MAC_SPEED_100G;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686
 687         return 0;
 688 }
 689
 690 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
 691                                         u8 speed_ability)
 692 {
 693         unsigned long *supported = hdev->hw.mac.supported;
 694
 695         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
 696                 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 697                         supported);
 698
 699         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
 700                 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 701                         supported);
 702
 703         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
 704                 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 705                         supported);
 706
 707         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
 708                 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
 709                         supported);
 710
 711         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
 712                 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 713                         supported);
 714
 715         set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 716         set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
 717 }
 718
 719 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
 720 {
 721         u8 media_type = hdev->hw.mac.media_type;
 722
 723         if (media_type != HNAE3_MEDIA_TYPE_FIBER)
 724                 return;
 725
 726         hclge_parse_fiber_link_mode(hdev, speed_ability);
 727 }
 728
 729 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
 730 {
 731         struct hclge_cfg_param_cmd *req;
 732         u64 mac_addr_tmp_high;
 733         u64 mac_addr_tmp;
 734         int i;
 735
 736         req = (struct hclge_cfg_param_cmd *)desc[0].data;
 737
 738         /* get the configuration */
 739         cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 740                                               HCLGE_CFG_VMDQ_M,
 741                                               HCLGE_CFG_VMDQ_S);
 742         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 743                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
 744         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 745                                             HCLGE_CFG_TQP_DESC_N_M,
 746                                             HCLGE_CFG_TQP_DESC_N_S);
 747
 748         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
 749                                         HCLGE_CFG_PHY_ADDR_M,
 750                                         HCLGE_CFG_PHY_ADDR_S);
 751         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
 752                                           HCLGE_CFG_MEDIA_TP_M,
 753                                           HCLGE_CFG_MEDIA_TP_S);
 754         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
 755                                           HCLGE_CFG_RX_BUF_LEN_M,
 756                                           HCLGE_CFG_RX_BUF_LEN_S);
 757         /* get mac_address */
 758         mac_addr_tmp = __le32_to_cpu(req->param[2]);
 759         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
 760                                             HCLGE_CFG_MAC_ADDR_H_M,
 761                                             HCLGE_CFG_MAC_ADDR_H_S);
 762
 763         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
 764
 765         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
 766                                              HCLGE_CFG_DEFAULT_SPEED_M,
 767                                              HCLGE_CFG_DEFAULT_SPEED_S);
 768         cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
 769                                             HCLGE_CFG_RSS_SIZE_M,
 770                                             HCLGE_CFG_RSS_SIZE_S);
 771
 772         for (i = 0; i < ETH_ALEN; i++)
 773                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
 774
 775         req = (struct hclge_cfg_param_cmd *)desc[1].data;
 776         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
 777
 778         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
 779                                              HCLGE_CFG_SPEED_ABILITY_M,
 780                                              HCLGE_CFG_SPEED_ABILITY_S);
 781         cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
 782                                          HCLGE_CFG_UMV_TBL_SPACE_M,
 783                                          HCLGE_CFG_UMV_TBL_SPACE_S);
 784         if (!cfg->umv_space)
 785                 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
 786 }
 787
 788 /* hclge_get_cfg: query the static parameter from flash
 789  * @hdev: pointer to struct hclge_dev
 790  * @hcfg: the config structure to be getted
 791  */
 792 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
 793 {
 794         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
 795         struct hclge_cfg_param_cmd *req;
 796         int i, ret;
 797
 798         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
 799                 u32 offset = 0;
 800
 801                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
 802                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
 803                                            true);
 804                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
 805                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
 806                 /* Len should be united by 4 bytes when send to hardware */
 807                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
 808                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
 809                 req->offset = cpu_to_le32(offset);
 810         }
 811
 812         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
 813         if (ret) {
 814                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
 815                 return ret;
 816         }
 817
 818         hclge_parse_cfg(hcfg, desc);
 819
 820         return 0;
 821 }
 822
 823 static int hclge_get_cap(struct hclge_dev *hdev)
 824 {
 825         int ret;
 826
 827         ret = hclge_query_function_status(hdev);
 828         if (ret) {
 829                 dev_err(&hdev->pdev->dev,
 830                         "query function status error %d.\n", ret);
 831                 return ret;
 832         }
 833
 834         /* get pf resource */
 835         ret = hclge_query_pf_resource(hdev);
 836         if (ret)
 837                 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
 838
 839         return ret;
 840 }
 841
 842 static int hclge_configure(struct hclge_dev *hdev)
 843 {
 844         struct hclge_cfg cfg;
 845         int ret, i;
 846
 847         ret = hclge_get_cfg(hdev, &cfg);
 848         if (ret) {
 849                 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
 850                 return ret;
 851         }
 852
 853         hdev->num_vmdq_vport = cfg.vmdq_vport_num;
 854         hdev->base_tqp_pid = 0;
 855         hdev->rss_size_max = cfg.rss_size_max;
 856         hdev->rx_buf_len = cfg.rx_buf_len;
 857         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
 858         hdev->hw.mac.media_type = cfg.media_type;
 859         hdev->hw.mac.phy_addr = cfg.phy_addr;
 860         hdev->num_desc = cfg.tqp_desc_num;
 861         hdev->tm_info.num_pg = 1;
 862         hdev->tc_max = cfg.tc_num;
 863         hdev->tm_info.hw_pfc_map = 0;
 864         hdev->wanted_umv_size = cfg.umv_space;
 865
 866         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
 867         if (ret) {
 868                 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
 869                 return ret;
 870         }
 871
 872         hclge_parse_link_mode(hdev, cfg.speed_ability);
 873
 874         if ((hdev->tc_max > HNAE3_MAX_TC) ||
 875             (hdev->tc_max < 1)) {
 876                 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
 877                          hdev->tc_max);
 878                 hdev->tc_max = 1;
 879         }
 880
 881         /* Dev does not support DCB */
 882         if (!hnae3_dev_dcb_supported(hdev)) {
 883                 hdev->tc_max = 1;
 884                 hdev->pfc_max = 0;
 885         } else {
 886                 hdev->pfc_max = hdev->tc_max;
 887         }
 888
 889         hdev->tm_info.num_tc = hdev->tc_max;
 890
 891         /* Currently not support uncontiuous tc */
 892         for (i = 0; i < hdev->tm_info.num_tc; i++)
 893                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
 894
 895         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
 896
 897         return ret;
 898 }
 899
 900 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
 901                             int tso_mss_max)
 902 {
 903         struct hclge_cfg_tso_status_cmd *req;
 904         struct hclge_desc desc;
 905         u16 tso_mss;
 906
 907         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
 908
 909         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
 910
 911         tso_mss = 0;
 912         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
 913                         HCLGE_TSO_MSS_MIN_S, tso_mss_min);
 914         req->tso_mss_min = cpu_to_le16(tso_mss);
 915
 916         tso_mss = 0;
 917         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
 918                         HCLGE_TSO_MSS_MIN_S, tso_mss_max);
 919         req->tso_mss_max = cpu_to_le16(tso_mss);
 920
 921         return hclge_cmd_send(&hdev->hw, &desc, 1);
 922 }
 923
 924 static int hclge_alloc_tqps(struct hclge_dev *hdev)
 925 {
 926         struct hclge_tqp *tqp;
 927         int i;
 928
 929         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
 930                                   sizeof(struct hclge_tqp), GFP_KERNEL);
 931         if (!hdev->htqp)
 932                 return -ENOMEM;
 933
 934         tqp = hdev->htqp;
 935
 936         for (i = 0; i < hdev->num_tqps; i++) {
 937                 tqp->dev = &hdev->pdev->dev;
 938                 tqp->index = i;
 939
 940                 tqp->q.ae_algo = &ae_algo;
 941                 tqp->q.buf_size = hdev->rx_buf_len;
 942                 tqp->q.desc_num = hdev->num_desc;
 943                 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
 944                         i * HCLGE_TQP_REG_SIZE;
 945
 946                 tqp++;
 947         }
 948
 949         return 0;
 950 }
 951
 952 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
 953                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
 954 {
 955         struct hclge_tqp_map_cmd *req;
 956         struct hclge_desc desc;
 957         int ret;
 958
 959         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
 960
 961         req = (struct hclge_tqp_map_cmd *)desc.data;
 962         req->tqp_id = cpu_to_le16(tqp_pid);
 963         req->tqp_vf = func_id;
 964         req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
 965                         1 << HCLGE_TQP_MAP_EN_B;
 966         req->tqp_vid = cpu_to_le16(tqp_vid);
 967
 968         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 969         if (ret)
 970                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
 971
 972         return ret;
 973 }
 974
 975 static int  hclge_assign_tqp(struct hclge_vport *vport)
 976 {
 977         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
 978         struct hclge_dev *hdev = vport->back;
 979         int i, alloced;
 980
 981         for (i = 0, alloced = 0; i < hdev->num_tqps &&
 982              alloced < kinfo->num_tqps; i++) {
 983                 if (!hdev->htqp[i].alloced) {
 984                         hdev->htqp[i].q.handle = &vport->nic;
 985                         hdev->htqp[i].q.tqp_index = alloced;
 986                         hdev->htqp[i].q.desc_num = kinfo->num_desc;
 987                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
 988                         hdev->htqp[i].alloced = true;
 989                         alloced++;
 990                 }
 991         }
 992         vport->alloc_tqps = kinfo->num_tqps;
 993
 994         return 0;
 995 }
 996
 997 static int hclge_knic_setup(struct hclge_vport *vport,
 998                             u16 num_tqps, u16 num_desc)
 999 {
1000         struct hnae3_handle *nic = &vport->nic;
1001         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1002         struct hclge_dev *hdev = vport->back;
1003         int i, ret;
1004
1005         kinfo->num_desc = num_desc;
1006         kinfo->rx_buf_len = hdev->rx_buf_len;
1007         kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1008         kinfo->rss_size
1009                 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1010         kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1011
1012         for (i = 0; i < HNAE3_MAX_TC; i++) {
1013                 if (hdev->hw_tc_map & BIT(i)) {
1014                         kinfo->tc_info[i].enable = true;
1015                         kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1016                         kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1017                         kinfo->tc_info[i].tc = i;
1018                 } else {
1019                         /* Set to default queue if TC is disable */
1020                         kinfo->tc_info[i].enable = false;
1021                         kinfo->tc_info[i].tqp_offset = 0;
1022                         kinfo->tc_info[i].tqp_count = 1;
1023                         kinfo->tc_info[i].tc = 0;
1024                 }
1025         }
1026
1027         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1028                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1029         if (!kinfo->tqp)
1030                 return -ENOMEM;
1031
1032         ret = hclge_assign_tqp(vport);
1033         if (ret)
1034                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1035
1036         return ret;
1037 }
1038
1039 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1040                                   struct hclge_vport *vport)
1041 {
1042         struct hnae3_handle *nic = &vport->nic;
1043         struct hnae3_knic_private_info *kinfo;
1044         u16 i;
1045
1046         kinfo = &nic->kinfo;
1047         for (i = 0; i < kinfo->num_tqps; i++) {
1048                 struct hclge_tqp *q =
1049                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
1050                 bool is_pf;
1051                 int ret;
1052
1053                 is_pf = !(vport->vport_id);
1054                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1055                                              i, is_pf);
1056                 if (ret)
1057                         return ret;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int hclge_map_tqp(struct hclge_dev *hdev)
1064 {
1065         struct hclge_vport *vport = hdev->vport;
1066         u16 i, num_vport;
1067
1068         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1069         for (i = 0; i < num_vport; i++) {
1070                 int ret;
1071
1072                 ret = hclge_map_tqp_to_vport(hdev, vport);
1073                 if (ret)
1074                         return ret;
1075
1076                 vport++;
1077         }
1078
1079         return 0;
1080 }
1081
1082 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1083 {
1084         /* this would be initialized later */
1085 }
1086
1087 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1088 {
1089         struct hnae3_handle *nic = &vport->nic;
1090         struct hclge_dev *hdev = vport->back;
1091         int ret;
1092
1093         nic->pdev = hdev->pdev;
1094         nic->ae_algo = &ae_algo;
1095         nic->numa_node_mask = hdev->numa_node_mask;
1096
1097         if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1098                 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
1099                 if (ret) {
1100                         dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1101                                 ret);
1102                         return ret;
1103                 }
1104         } else {
1105                 hclge_unic_setup(vport, num_tqps);
1106         }
1107
1108         return 0;
1109 }
1110
1111 static int hclge_alloc_vport(struct hclge_dev *hdev)
1112 {
1113         struct pci_dev *pdev = hdev->pdev;
1114         struct hclge_vport *vport;
1115         u32 tqp_main_vport;
1116         u32 tqp_per_vport;
1117         int num_vport, i;
1118         int ret;
1119
1120         /* We need to alloc a vport for main NIC of PF */
1121         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1122
1123         if (hdev->num_tqps < num_vport) {
1124                 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1125                         hdev->num_tqps, num_vport);
1126                 return -EINVAL;
1127         }
1128
1129         /* Alloc the same number of TQPs for every vport */
1130         tqp_per_vport = hdev->num_tqps / num_vport;
1131         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1132
1133         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1134                              GFP_KERNEL);
1135         if (!vport)
1136                 return -ENOMEM;
1137
1138         hdev->vport = vport;
1139         hdev->num_alloc_vport = num_vport;
1140
1141         if (IS_ENABLED(CONFIG_PCI_IOV))
1142                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1143
1144         for (i = 0; i < num_vport; i++) {
1145                 vport->back = hdev;
1146                 vport->vport_id = i;
1147
1148                 if (i == 0)
1149                         ret = hclge_vport_setup(vport, tqp_main_vport);
1150                 else
1151                         ret = hclge_vport_setup(vport, tqp_per_vport);
1152                 if (ret) {
1153                         dev_err(&pdev->dev,
1154                                 "vport setup failed for vport %d, %d\n",
1155                                 i, ret);
1156                         return ret;
1157                 }
1158
1159                 vport++;
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1166                                     struct hclge_pkt_buf_alloc *buf_alloc)
1167 {
1168 /* TX buffer size is unit by 128 byte */
1169 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1170 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1171         struct hclge_tx_buff_alloc_cmd *req;
1172         struct hclge_desc desc;
1173         int ret;
1174         u8 i;
1175
1176         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1177
1178         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1179         for (i = 0; i < HCLGE_TC_NUM; i++) {
1180                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1181
1182                 req->tx_pkt_buff[i] =
1183                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1184                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1185         }
1186
1187         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1188         if (ret)
1189                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1190                         ret);
1191
1192         return ret;
1193 }
1194
1195 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1196                                  struct hclge_pkt_buf_alloc *buf_alloc)
1197 {
1198         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1199
1200         if (ret)
1201                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1202
1203         return ret;
1204 }
1205
1206 static int hclge_get_tc_num(struct hclge_dev *hdev)
1207 {
1208         int i, cnt = 0;
1209
1210         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1211                 if (hdev->hw_tc_map & BIT(i))
1212                         cnt++;
1213         return cnt;
1214 }
1215
1216 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1217 {
1218         int i, cnt = 0;
1219
1220         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1221                 if (hdev->hw_tc_map & BIT(i) &&
1222                     hdev->tm_info.hw_pfc_map & BIT(i))
1223                         cnt++;
1224         return cnt;
1225 }
1226
1227 /* Get the number of pfc enabled TCs, which have private buffer */
1228 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1229                                   struct hclge_pkt_buf_alloc *buf_alloc)
1230 {
1231         struct hclge_priv_buf *priv;
1232         int i, cnt = 0;
1233
1234         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1235                 priv = &buf_alloc->priv_buf[i];
1236                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1237                     priv->enable)
1238                         cnt++;
1239         }
1240
1241         return cnt;
1242 }
1243
1244 /* Get the number of pfc disabled TCs, which have private buffer */
1245 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1246                                      struct hclge_pkt_buf_alloc *buf_alloc)
1247 {
1248         struct hclge_priv_buf *priv;
1249         int i, cnt = 0;
1250
1251         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1252                 priv = &buf_alloc->priv_buf[i];
1253                 if (hdev->hw_tc_map & BIT(i) &&
1254                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1255                     priv->enable)
1256                         cnt++;
1257         }
1258
1259         return cnt;
1260 }
1261
1262 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1263 {
1264         struct hclge_priv_buf *priv;
1265         u32 rx_priv = 0;
1266         int i;
1267
1268         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1269                 priv = &buf_alloc->priv_buf[i];
1270                 if (priv->enable)
1271                         rx_priv += priv->buf_size;
1272         }
1273         return rx_priv;
1274 }
1275
1276 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1277 {
1278         u32 i, total_tx_size = 0;
1279
1280         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1281                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1282
1283         return total_tx_size;
1284 }
1285
1286 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1287                                 struct hclge_pkt_buf_alloc *buf_alloc,
1288                                 u32 rx_all)
1289 {
1290         u32 shared_buf_min, shared_buf_tc, shared_std;
1291         int tc_num, pfc_enable_num;
1292         u32 shared_buf;
1293         u32 rx_priv;
1294         int i;
1295
1296         tc_num = hclge_get_tc_num(hdev);
1297         pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1298
1299         if (hnae3_dev_dcb_supported(hdev))
1300                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1301         else
1302                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1303
1304         shared_buf_tc = pfc_enable_num * hdev->mps +
1305                         (tc_num - pfc_enable_num) * hdev->mps / 2 +
1306                         hdev->mps;
1307         shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1308
1309         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1310         if (rx_all <= rx_priv + shared_std)
1311                 return false;
1312
1313         shared_buf = rx_all - rx_priv;
1314         buf_alloc->s_buf.buf_size = shared_buf;
1315         buf_alloc->s_buf.self.high = shared_buf;
1316         buf_alloc->s_buf.self.low =  2 * hdev->mps;
1317
1318         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1319                 if ((hdev->hw_tc_map & BIT(i)) &&
1320                     (hdev->tm_info.hw_pfc_map & BIT(i))) {
1321                         buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1322                         buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1323                 } else {
1324                         buf_alloc->s_buf.tc_thrd[i].low = 0;
1325                         buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1326                 }
1327         }
1328
1329         return true;
1330 }
1331
1332 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1333                                 struct hclge_pkt_buf_alloc *buf_alloc)
1334 {
1335         u32 i, total_size;
1336
1337         total_size = hdev->pkt_buf_size;
1338
1339         /* alloc tx buffer for all enabled tc */
1340         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1341                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1342
1343                 if (total_size < HCLGE_DEFAULT_TX_BUF)
1344                         return -ENOMEM;
1345
1346                 if (hdev->hw_tc_map & BIT(i))
1347                         priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1348                 else
1349                         priv->tx_buf_size = 0;
1350
1351                 total_size -= priv->tx_buf_size;
1352         }
1353
1354         return 0;
1355 }
1356
1357 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1358  * @hdev: pointer to struct hclge_dev
1359  * @buf_alloc: pointer to buffer calculation data
1360  * @return: 0: calculate sucessful, negative: fail
1361  */
1362 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1363                                 struct hclge_pkt_buf_alloc *buf_alloc)
1364 {
1365 #define HCLGE_BUF_SIZE_UNIT     128
1366         u32 rx_all = hdev->pkt_buf_size, aligned_mps;
1367         int no_pfc_priv_num, pfc_priv_num;
1368         struct hclge_priv_buf *priv;
1369         int i;
1370
1371         aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1372         rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1373
1374         /* When DCB is not supported, rx private
1375          * buffer is not allocated.
1376          */
1377         if (!hnae3_dev_dcb_supported(hdev)) {
1378                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1379                         return -ENOMEM;
1380
1381                 return 0;
1382         }
1383
1384         /* step 1, try to alloc private buffer for all enabled tc */
1385         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1386                 priv = &buf_alloc->priv_buf[i];
1387                 if (hdev->hw_tc_map & BIT(i)) {
1388                         priv->enable = 1;
1389                         if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1390                                 priv->wl.low = aligned_mps;
1391                                 priv->wl.high = priv->wl.low + aligned_mps;
1392                                 priv->buf_size = priv->wl.high +
1393                                                 HCLGE_DEFAULT_DV;
1394                         } else {
1395                                 priv->wl.low = 0;
1396                                 priv->wl.high = 2 * aligned_mps;
1397                                 priv->buf_size = priv->wl.high;
1398                         }
1399                 } else {
1400                         priv->enable = 0;
1401                         priv->wl.low = 0;
1402                         priv->wl.high = 0;
1403                         priv->buf_size = 0;
1404                 }
1405         }
1406
1407         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1408                 return 0;
1409
1410         /* step 2, try to decrease the buffer size of
1411          * no pfc TC's private buffer
1412          */
1413         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1414                 priv = &buf_alloc->priv_buf[i];
1415
1416                 priv->enable = 0;
1417                 priv->wl.low = 0;
1418                 priv->wl.high = 0;
1419                 priv->buf_size = 0;
1420
1421                 if (!(hdev->hw_tc_map & BIT(i)))
1422                         continue;
1423
1424                 priv->enable = 1;
1425
1426                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1427                         priv->wl.low = 128;
1428                         priv->wl.high = priv->wl.low + aligned_mps;
1429                         priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1430                 } else {
1431                         priv->wl.low = 0;
1432                         priv->wl.high = aligned_mps;
1433                         priv->buf_size = priv->wl.high;
1434                 }
1435         }
1436
1437         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1438                 return 0;
1439
1440         /* step 3, try to reduce the number of pfc disabled TCs,
1441          * which have private buffer
1442          */
1443         /* get the total no pfc enable TC number, which have private buffer */
1444         no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1445
1446         /* let the last to be cleared first */
1447         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1448                 priv = &buf_alloc->priv_buf[i];
1449
1450                 if (hdev->hw_tc_map & BIT(i) &&
1451                     !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1452                         /* Clear the no pfc TC private buffer */
1453                         priv->wl.low = 0;
1454                         priv->wl.high = 0;
1455                         priv->buf_size = 0;
1456                         priv->enable = 0;
1457                         no_pfc_priv_num--;
1458                 }
1459
1460                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1461                     no_pfc_priv_num == 0)
1462                         break;
1463         }
1464
1465         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1466                 return 0;
1467
1468         /* step 4, try to reduce the number of pfc enabled TCs
1469          * which have private buffer.
1470          */
1471         pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1472
1473         /* let the last to be cleared first */
1474         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1475                 priv = &buf_alloc->priv_buf[i];
1476
1477                 if (hdev->hw_tc_map & BIT(i) &&
1478                     hdev->tm_info.hw_pfc_map & BIT(i)) {
1479                         /* Reduce the number of pfc TC with private buffer */
1480                         priv->wl.low = 0;
1481                         priv->enable = 0;
1482                         priv->wl.high = 0;
1483                         priv->buf_size = 0;
1484                         pfc_priv_num--;
1485                 }
1486
1487                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1488                     pfc_priv_num == 0)
1489                         break;
1490         }
1491         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1492                 return 0;
1493
1494         return -ENOMEM;
1495 }
1496
1497 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1498                                    struct hclge_pkt_buf_alloc *buf_alloc)
1499 {
1500         struct hclge_rx_priv_buff_cmd *req;
1501         struct hclge_desc desc;
1502         int ret;
1503         int i;
1504
1505         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1506         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1507
1508         /* Alloc private buffer TCs */
1509         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1510                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1511
1512                 req->buf_num[i] =
1513                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1514                 req->buf_num[i] |=
1515                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1516         }
1517
1518         req->shared_buf =
1519                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1520                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
1521
1522         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1523         if (ret)
1524                 dev_err(&hdev->pdev->dev,
1525                         "rx private buffer alloc cmd failed %d\n", ret);
1526
1527         return ret;
1528 }
1529
1530 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1531                                    struct hclge_pkt_buf_alloc *buf_alloc)
1532 {
1533         struct hclge_rx_priv_wl_buf *req;
1534         struct hclge_priv_buf *priv;
1535         struct hclge_desc desc[2];
1536         int i, j;
1537         int ret;
1538
1539         for (i = 0; i < 2; i++) {
1540                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1541                                            false);
1542                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1543
1544                 /* The first descriptor set the NEXT bit to 1 */
1545                 if (i == 0)
1546                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1547                 else
1548                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1549
1550                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1551                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1552
1553                         priv = &buf_alloc->priv_buf[idx];
1554                         req->tc_wl[j].high =
1555                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1556                         req->tc_wl[j].high |=
1557                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1558                         req->tc_wl[j].low =
1559                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1560                         req->tc_wl[j].low |=
1561                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1562                 }
1563         }
1564
1565         /* Send 2 descriptor at one time */
1566         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1567         if (ret)
1568                 dev_err(&hdev->pdev->dev,
1569                         "rx private waterline config cmd failed %d\n",
1570                         ret);
1571         return ret;
1572 }
1573
1574 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1575                                     struct hclge_pkt_buf_alloc *buf_alloc)
1576 {
1577         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1578         struct hclge_rx_com_thrd *req;
1579         struct hclge_desc desc[2];
1580         struct hclge_tc_thrd *tc;
1581         int i, j;
1582         int ret;
1583
1584         for (i = 0; i < 2; i++) {
1585                 hclge_cmd_setup_basic_desc(&desc[i],
1586                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1587                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1588
1589                 /* The first descriptor set the NEXT bit to 1 */
1590                 if (i == 0)
1591                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1592                 else
1593                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1594
1595                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1596                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1597
1598                         req->com_thrd[j].high =
1599                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1600                         req->com_thrd[j].high |=
1601                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1602                         req->com_thrd[j].low =
1603                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1604                         req->com_thrd[j].low |=
1605                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1606                 }
1607         }
1608
1609         /* Send 2 descriptors at one time */
1610         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1611         if (ret)
1612                 dev_err(&hdev->pdev->dev,
1613                         "common threshold config cmd failed %d\n", ret);
1614         return ret;
1615 }
1616
1617 static int hclge_common_wl_config(struct hclge_dev *hdev,
1618                                   struct hclge_pkt_buf_alloc *buf_alloc)
1619 {
1620         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1621         struct hclge_rx_com_wl *req;
1622         struct hclge_desc desc;
1623         int ret;
1624
1625         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1626
1627         req = (struct hclge_rx_com_wl *)desc.data;
1628         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1629         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1630
1631         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1632         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1633
1634         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1635         if (ret)
1636                 dev_err(&hdev->pdev->dev,
1637                         "common waterline config cmd failed %d\n", ret);
1638
1639         return ret;
1640 }
1641
1642 int hclge_buffer_alloc(struct hclge_dev *hdev)
1643 {
1644         struct hclge_pkt_buf_alloc *pkt_buf;
1645         int ret;
1646
1647         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1648         if (!pkt_buf)
1649                 return -ENOMEM;
1650
1651         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1652         if (ret) {
1653                 dev_err(&hdev->pdev->dev,
1654                         "could not calc tx buffer size for all TCs %d\n", ret);
1655                 goto out;
1656         }
1657
1658         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1659         if (ret) {
1660                 dev_err(&hdev->pdev->dev,
1661                         "could not alloc tx buffers %d\n", ret);
1662                 goto out;
1663         }
1664
1665         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1666         if (ret) {
1667                 dev_err(&hdev->pdev->dev,
1668                         "could not calc rx priv buffer size for all TCs %d\n",
1669                         ret);
1670                 goto out;
1671         }
1672
1673         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1674         if (ret) {
1675                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1676                         ret);
1677                 goto out;
1678         }
1679
1680         if (hnae3_dev_dcb_supported(hdev)) {
1681                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1682                 if (ret) {
1683                         dev_err(&hdev->pdev->dev,
1684                                 "could not configure rx private waterline %d\n",
1685                                 ret);
1686                         goto out;
1687                 }
1688
1689                 ret = hclge_common_thrd_config(hdev, pkt_buf);
1690                 if (ret) {
1691                         dev_err(&hdev->pdev->dev,
1692                                 "could not configure common threshold %d\n",
1693                                 ret);
1694                         goto out;
1695                 }
1696         }
1697
1698         ret = hclge_common_wl_config(hdev, pkt_buf);
1699         if (ret)
1700                 dev_err(&hdev->pdev->dev,
1701                         "could not configure common waterline %d\n", ret);
1702
1703 out:
1704         kfree(pkt_buf);
1705         return ret;
1706 }
1707
1708 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1709 {
1710         struct hnae3_handle *roce = &vport->roce;
1711         struct hnae3_handle *nic = &vport->nic;
1712
1713         roce->rinfo.num_vectors = vport->back->num_roce_msi;
1714
1715         if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1716             vport->back->num_msi_left == 0)
1717                 return -EINVAL;
1718
1719         roce->rinfo.base_vector = vport->back->roce_base_vector;
1720
1721         roce->rinfo.netdev = nic->kinfo.netdev;
1722         roce->rinfo.roce_io_base = vport->back->hw.io_base;
1723
1724         roce->pdev = nic->pdev;
1725         roce->ae_algo = nic->ae_algo;
1726         roce->numa_node_mask = nic->numa_node_mask;
1727
1728         return 0;
1729 }
1730
1731 static int hclge_init_msi(struct hclge_dev *hdev)
1732 {
1733         struct pci_dev *pdev = hdev->pdev;
1734         int vectors;
1735         int i;
1736
1737         vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1738                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
1739         if (vectors < 0) {
1740                 dev_err(&pdev->dev,
1741                         "failed(%d) to allocate MSI/MSI-X vectors\n",
1742                         vectors);
1743                 return vectors;
1744         }
1745         if (vectors < hdev->num_msi)
1746                 dev_warn(&hdev->pdev->dev,
1747                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1748                          hdev->num_msi, vectors);
1749
1750         hdev->num_msi = vectors;
1751         hdev->num_msi_left = vectors;
1752         hdev->base_msi_vector = pdev->irq;
1753         hdev->roce_base_vector = hdev->base_msi_vector +
1754                                 hdev->roce_base_msix_offset;
1755
1756         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1757                                            sizeof(u16), GFP_KERNEL);
1758         if (!hdev->vector_status) {
1759                 pci_free_irq_vectors(pdev);
1760                 return -ENOMEM;
1761         }
1762
1763         for (i = 0; i < hdev->num_msi; i++)
1764                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1765
1766         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1767                                         sizeof(int), GFP_KERNEL);
1768         if (!hdev->vector_irq) {
1769                 pci_free_irq_vectors(pdev);
1770                 return -ENOMEM;
1771         }
1772
1773         return 0;
1774 }
1775
1776 static u8 hclge_check_speed_dup(u8 duplex, int speed)
1777 {
1778
1779         if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1780                 duplex = HCLGE_MAC_FULL;
1781
1782         return duplex;
1783 }
1784
1785 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1786                                       u8 duplex)
1787 {
1788         struct hclge_config_mac_speed_dup_cmd *req;
1789         struct hclge_desc desc;
1790         int ret;
1791
1792         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
1793
1794         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1795
1796         hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
1797
1798         switch (speed) {
1799         case HCLGE_MAC_SPEED_10M:
1800                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1801                                 HCLGE_CFG_SPEED_S, 6);
1802                 break;
1803         case HCLGE_MAC_SPEED_100M:
1804                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1805                                 HCLGE_CFG_SPEED_S, 7);
1806                 break;
1807         case HCLGE_MAC_SPEED_1G:
1808                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1809                                 HCLGE_CFG_SPEED_S, 0);
1810                 break;
1811         case HCLGE_MAC_SPEED_10G:
1812                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1813                                 HCLGE_CFG_SPEED_S, 1);
1814                 break;
1815         case HCLGE_MAC_SPEED_25G:
1816                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1817                                 HCLGE_CFG_SPEED_S, 2);
1818                 break;
1819         case HCLGE_MAC_SPEED_40G:
1820                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1821                                 HCLGE_CFG_SPEED_S, 3);
1822                 break;
1823         case HCLGE_MAC_SPEED_50G:
1824                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1825                                 HCLGE_CFG_SPEED_S, 4);
1826                 break;
1827         case HCLGE_MAC_SPEED_100G:
1828                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1829                                 HCLGE_CFG_SPEED_S, 5);
1830                 break;
1831         default:
1832                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
1833                 return -EINVAL;
1834         }
1835
1836         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1837                       1);
1838
1839         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1840         if (ret) {
1841                 dev_err(&hdev->pdev->dev,
1842                         "mac speed/duplex config cmd failed %d.\n", ret);
1843                 return ret;
1844         }
1845
1846         return 0;
1847 }
1848
1849 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1850 {
1851         int ret;
1852
1853         duplex = hclge_check_speed_dup(duplex, speed);
1854         if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1855                 return 0;
1856
1857         ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1858         if (ret)
1859                 return ret;
1860
1861         hdev->hw.mac.speed = speed;
1862         hdev->hw.mac.duplex = duplex;
1863
1864         return 0;
1865 }
1866
1867 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1868                                      u8 duplex)
1869 {
1870         struct hclge_vport *vport = hclge_get_vport(handle);
1871         struct hclge_dev *hdev = vport->back;
1872
1873         return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1874 }
1875
1876 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1877                                         u8 *duplex)
1878 {
1879         struct hclge_query_an_speed_dup_cmd *req;
1880         struct hclge_desc desc;
1881         int speed_tmp;
1882         int ret;
1883
1884         req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
1885
1886         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1887         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1888         if (ret) {
1889                 dev_err(&hdev->pdev->dev,
1890                         "mac speed/autoneg/duplex query cmd failed %d\n",
1891                         ret);
1892                 return ret;
1893         }
1894
1895         *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1896         speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1897                                     HCLGE_QUERY_SPEED_S);
1898
1899         ret = hclge_parse_speed(speed_tmp, speed);
1900         if (ret)
1901                 dev_err(&hdev->pdev->dev,
1902                         "could not parse speed(=%d), %d\n", speed_tmp, ret);
1903
1904         return ret;
1905 }
1906
1907 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1908 {
1909         struct hclge_config_auto_neg_cmd *req;
1910         struct hclge_desc desc;
1911         u32 flag = 0;
1912         int ret;
1913
1914         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1915
1916         req = (struct hclge_config_auto_neg_cmd *)desc.data;
1917         hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
1918         req->cfg_an_cmd_flag = cpu_to_le32(flag);
1919
1920         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1921         if (ret)
1922                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1923                         ret);
1924
1925         return ret;
1926 }
1927
1928 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1929 {
1930         struct hclge_vport *vport = hclge_get_vport(handle);
1931         struct hclge_dev *hdev = vport->back;
1932
1933         return hclge_set_autoneg_en(hdev, enable);
1934 }
1935
1936 static int hclge_get_autoneg(struct hnae3_handle *handle)
1937 {
1938         struct hclge_vport *vport = hclge_get_vport(handle);
1939         struct hclge_dev *hdev = vport->back;
1940         struct phy_device *phydev = hdev->hw.mac.phydev;
1941
1942         if (phydev)
1943                 return phydev->autoneg;
1944
1945         return hdev->hw.mac.autoneg;
1946 }
1947
1948 static int hclge_mac_init(struct hclge_dev *hdev)
1949 {
1950         struct hnae3_handle *handle = &hdev->vport[0].nic;
1951         struct net_device *netdev = handle->kinfo.netdev;
1952         struct hclge_mac *mac = &hdev->hw.mac;
1953         int mtu;
1954         int ret;
1955
1956         hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1957         ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1958                                          hdev->hw.mac.duplex);
1959         if (ret) {
1960                 dev_err(&hdev->pdev->dev,
1961                         "Config mac speed dup fail ret=%d\n", ret);
1962                 return ret;
1963         }
1964
1965         mac->link = 0;
1966
1967         if (netdev)
1968                 mtu = netdev->mtu;
1969         else
1970                 mtu = ETH_DATA_LEN;
1971
1972         ret = hclge_set_mtu(handle, mtu);
1973         if (ret)
1974                 dev_err(&hdev->pdev->dev,
1975                         "set mtu failed ret=%d\n", ret);
1976
1977         return ret;
1978 }
1979
1980 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
1981 {
1982         if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
1983                 schedule_work(&hdev->mbx_service_task);
1984 }
1985
1986 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
1987 {
1988         if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
1989                 schedule_work(&hdev->rst_service_task);
1990 }
1991
1992 static void hclge_task_schedule(struct hclge_dev *hdev)
1993 {
1994         if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
1995             !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
1996             !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
1997                 (void)schedule_work(&hdev->service_task);
1998 }
1999
2000 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2001 {
2002         struct hclge_link_status_cmd *req;
2003         struct hclge_desc desc;
2004         int link_status;
2005         int ret;
2006
2007         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2008         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2009         if (ret) {
2010                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2011                         ret);
2012                 return ret;
2013         }
2014
2015         req = (struct hclge_link_status_cmd *)desc.data;
2016         link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2017
2018         return !!link_status;
2019 }
2020
2021 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2022 {
2023         int mac_state;
2024         int link_stat;
2025
2026         if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2027                 return 0;
2028
2029         mac_state = hclge_get_mac_link_status(hdev);
2030
2031         if (hdev->hw.mac.phydev) {
2032                 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
2033                         link_stat = mac_state &
2034                                 hdev->hw.mac.phydev->link;
2035                 else
2036                         link_stat = 0;
2037
2038         } else {
2039                 link_stat = mac_state;
2040         }
2041
2042         return !!link_stat;
2043 }
2044
2045 static void hclge_update_link_status(struct hclge_dev *hdev)
2046 {
2047         struct hnae3_client *client = hdev->nic_client;
2048         struct hnae3_handle *handle;
2049         int state;
2050         int i;
2051
2052         if (!client)
2053                 return;
2054         state = hclge_get_mac_phy_link(hdev);
2055         if (state != hdev->hw.mac.link) {
2056                 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2057                         handle = &hdev->vport[i].nic;
2058                         client->ops->link_status_change(handle, state);
2059                 }
2060                 hdev->hw.mac.link = state;
2061         }
2062 }
2063
2064 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2065 {
2066         struct hclge_mac mac = hdev->hw.mac;
2067         u8 duplex;
2068         int speed;
2069         int ret;
2070
2071         /* get the speed and duplex as autoneg'result from mac cmd when phy
2072          * doesn't exit.
2073          */
2074         if (mac.phydev || !mac.autoneg)
2075                 return 0;
2076
2077         ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2078         if (ret) {
2079                 dev_err(&hdev->pdev->dev,
2080                         "mac autoneg/speed/duplex query failed %d\n", ret);
2081                 return ret;
2082         }
2083
2084         ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2085         if (ret) {
2086                 dev_err(&hdev->pdev->dev,
2087                         "mac speed/duplex config failed %d\n", ret);
2088                 return ret;
2089         }
2090
2091         return 0;
2092 }
2093
2094 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2095 {
2096         struct hclge_vport *vport = hclge_get_vport(handle);
2097         struct hclge_dev *hdev = vport->back;
2098
2099         return hclge_update_speed_duplex(hdev);
2100 }
2101
2102 static int hclge_get_status(struct hnae3_handle *handle)
2103 {
2104         struct hclge_vport *vport = hclge_get_vport(handle);
2105         struct hclge_dev *hdev = vport->back;
2106
2107         hclge_update_link_status(hdev);
2108
2109         return hdev->hw.mac.link;
2110 }
2111
2112 static void hclge_service_timer(struct timer_list *t)
2113 {
2114         struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2115
2116         mod_timer(&hdev->service_timer, jiffies + HZ);
2117         hdev->hw_stats.stats_timer++;
2118         hclge_task_schedule(hdev);
2119 }
2120
2121 static void hclge_service_complete(struct hclge_dev *hdev)
2122 {
2123         WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2124
2125         /* Flush memory before next watchdog */
2126         smp_mb__before_atomic();
2127         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2128 }
2129
2130 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2131 {
2132         u32 rst_src_reg;
2133         u32 cmdq_src_reg;
2134
2135         /* fetch the events from their corresponding regs */
2136         rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
2137         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2138
2139         /* Assumption: If by any chance reset and mailbox events are reported
2140          * together then we will only process reset event in this go and will
2141          * defer the processing of the mailbox events. Since, we would have not
2142          * cleared RX CMDQ event this time we would receive again another
2143          * interrupt from H/W just for the mailbox.
2144          */
2145
2146         /* check for vector0 reset event sources */
2147         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2148                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2149                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2150                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2151                 return HCLGE_VECTOR0_EVENT_RST;
2152         }
2153
2154         if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2155                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2156                 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2157                 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2158                 return HCLGE_VECTOR0_EVENT_RST;
2159         }
2160
2161         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2162                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2163                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2164                 return HCLGE_VECTOR0_EVENT_RST;
2165         }
2166
2167         /* check for vector0 mailbox(=CMDQ RX) event source */
2168         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2169                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2170                 *clearval = cmdq_src_reg;
2171                 return HCLGE_VECTOR0_EVENT_MBX;
2172         }
2173
2174         return HCLGE_VECTOR0_EVENT_OTHER;
2175 }
2176
2177 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2178                                     u32 regclr)
2179 {
2180         switch (event_type) {
2181         case HCLGE_VECTOR0_EVENT_RST:
2182                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2183                 break;
2184         case HCLGE_VECTOR0_EVENT_MBX:
2185                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2186                 break;
2187         default:
2188                 break;
2189         }
2190 }
2191
2192 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2193 {
2194         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2195                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2196                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2197                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2198         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2199 }
2200
2201 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2202 {
2203         writel(enable ? 1 : 0, vector->addr);
2204 }
2205
2206 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2207 {
2208         struct hclge_dev *hdev = data;
2209         u32 event_cause;
2210         u32 clearval;
2211
2212         hclge_enable_vector(&hdev->misc_vector, false);
2213         event_cause = hclge_check_event_cause(hdev, &clearval);
2214
2215         /* vector 0 interrupt is shared with reset and mailbox source events.*/
2216         switch (event_cause) {
2217         case HCLGE_VECTOR0_EVENT_RST:
2218                 hclge_reset_task_schedule(hdev);
2219                 break;
2220         case HCLGE_VECTOR0_EVENT_MBX:
2221                 /* If we are here then,
2222                  * 1. Either we are not handling any mbx task and we are not
2223                  *    scheduled as well
2224                  *                        OR
2225                  * 2. We could be handling a mbx task but nothing more is
2226                  *    scheduled.
2227                  * In both cases, we should schedule mbx task as there are more
2228                  * mbx messages reported by this interrupt.
2229                  */
2230                 hclge_mbx_task_schedule(hdev);
2231                 break;
2232         default:
2233                 dev_warn(&hdev->pdev->dev,
2234                          "received unknown or unhandled event of vector0\n");
2235                 break;
2236         }
2237
2238         /* clear the source of interrupt if it is not cause by reset */
2239         if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2240                 hclge_clear_event_cause(hdev, event_cause, clearval);
2241                 hclge_enable_vector(&hdev->misc_vector, true);
2242         }
2243
2244         return IRQ_HANDLED;
2245 }
2246
2247 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2248 {
2249         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2250                 dev_warn(&hdev->pdev->dev,
2251                          "vector(vector_id %d) has been freed.\n", vector_id);
2252                 return;
2253         }
2254
2255         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2256         hdev->num_msi_left += 1;
2257         hdev->num_msi_used -= 1;
2258 }
2259
2260 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2261 {
2262         struct hclge_misc_vector *vector = &hdev->misc_vector;
2263
2264         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2265
2266         vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2267         hdev->vector_status[0] = 0;
2268
2269         hdev->num_msi_left -= 1;
2270         hdev->num_msi_used += 1;
2271 }
2272
2273 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2274 {
2275         int ret;
2276
2277         hclge_get_misc_vector(hdev);
2278
2279         /* this would be explicitly freed in the end */
2280         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2281                           0, "hclge_misc", hdev);
2282         if (ret) {
2283                 hclge_free_vector(hdev, 0);
2284                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2285                         hdev->misc_vector.vector_irq);
2286         }
2287
2288         return ret;
2289 }
2290
2291 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2292 {
2293         free_irq(hdev->misc_vector.vector_irq, hdev);
2294         hclge_free_vector(hdev, 0);
2295 }
2296
2297 static int hclge_notify_client(struct hclge_dev *hdev,
2298                                enum hnae3_reset_notify_type type)
2299 {
2300         struct hnae3_client *client = hdev->nic_client;
2301         u16 i;
2302
2303         if (!client->ops->reset_notify)
2304                 return -EOPNOTSUPP;
2305
2306         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2307                 struct hnae3_handle *handle = &hdev->vport[i].nic;
2308                 int ret;
2309
2310                 ret = client->ops->reset_notify(handle, type);
2311                 if (ret)
2312                         return ret;
2313         }
2314
2315         return 0;
2316 }
2317
2318 static int hclge_reset_wait(struct hclge_dev *hdev)
2319 {
2320 #define HCLGE_RESET_WATI_MS     100
2321 #define HCLGE_RESET_WAIT_CNT    5
2322         u32 val, reg, reg_bit;
2323         u32 cnt = 0;
2324
2325         switch (hdev->reset_type) {
2326         case HNAE3_GLOBAL_RESET:
2327                 reg = HCLGE_GLOBAL_RESET_REG;
2328                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2329                 break;
2330         case HNAE3_CORE_RESET:
2331                 reg = HCLGE_GLOBAL_RESET_REG;
2332                 reg_bit = HCLGE_CORE_RESET_BIT;
2333                 break;
2334         case HNAE3_FUNC_RESET:
2335                 reg = HCLGE_FUN_RST_ING;
2336                 reg_bit = HCLGE_FUN_RST_ING_B;
2337                 break;
2338         default:
2339                 dev_err(&hdev->pdev->dev,
2340                         "Wait for unsupported reset type: %d\n",
2341                         hdev->reset_type);
2342                 return -EINVAL;
2343         }
2344
2345         val = hclge_read_dev(&hdev->hw, reg);
2346         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2347                 msleep(HCLGE_RESET_WATI_MS);
2348                 val = hclge_read_dev(&hdev->hw, reg);
2349                 cnt++;
2350         }
2351
2352         if (cnt >= HCLGE_RESET_WAIT_CNT) {
2353                 dev_warn(&hdev->pdev->dev,
2354                          "Wait for reset timeout: %d\n", hdev->reset_type);
2355                 return -EBUSY;
2356         }
2357
2358         return 0;
2359 }
2360
2361 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2362 {
2363         struct hclge_desc desc;
2364         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2365         int ret;
2366
2367         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2368         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2369         req->fun_reset_vfid = func_id;
2370
2371         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2372         if (ret)
2373                 dev_err(&hdev->pdev->dev,
2374                         "send function reset cmd fail, status =%d\n", ret);
2375
2376         return ret;
2377 }
2378
2379 static void hclge_do_reset(struct hclge_dev *hdev)
2380 {
2381         struct pci_dev *pdev = hdev->pdev;
2382         u32 val;
2383
2384         switch (hdev->reset_type) {
2385         case HNAE3_GLOBAL_RESET:
2386                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2387                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2388                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2389                 dev_info(&pdev->dev, "Global Reset requested\n");
2390                 break;
2391         case HNAE3_CORE_RESET:
2392                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2393                 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2394                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2395                 dev_info(&pdev->dev, "Core Reset requested\n");
2396                 break;
2397         case HNAE3_FUNC_RESET:
2398                 dev_info(&pdev->dev, "PF Reset requested\n");
2399                 hclge_func_reset_cmd(hdev, 0);
2400                 /* schedule again to check later */
2401                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2402                 hclge_reset_task_schedule(hdev);
2403                 break;
2404         default:
2405                 dev_warn(&pdev->dev,
2406                          "Unsupported reset type: %d\n", hdev->reset_type);
2407                 break;
2408         }
2409 }
2410
2411 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2412                                                    unsigned long *addr)
2413 {
2414         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2415
2416         /* return the highest priority reset level amongst all */
2417         if (test_bit(HNAE3_GLOBAL_RESET, addr))
2418                 rst_level = HNAE3_GLOBAL_RESET;
2419         else if (test_bit(HNAE3_CORE_RESET, addr))
2420                 rst_level = HNAE3_CORE_RESET;
2421         else if (test_bit(HNAE3_IMP_RESET, addr))
2422                 rst_level = HNAE3_IMP_RESET;
2423         else if (test_bit(HNAE3_FUNC_RESET, addr))
2424                 rst_level = HNAE3_FUNC_RESET;
2425
2426         /* now, clear all other resets */
2427         clear_bit(HNAE3_GLOBAL_RESET, addr);
2428         clear_bit(HNAE3_CORE_RESET, addr);
2429         clear_bit(HNAE3_IMP_RESET, addr);
2430         clear_bit(HNAE3_FUNC_RESET, addr);
2431
2432         return rst_level;
2433 }
2434
2435 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2436 {
2437         u32 clearval = 0;
2438
2439         switch (hdev->reset_type) {
2440         case HNAE3_IMP_RESET:
2441                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2442                 break;
2443         case HNAE3_GLOBAL_RESET:
2444                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2445                 break;
2446         case HNAE3_CORE_RESET:
2447                 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2448                 break;
2449         default:
2450                 break;
2451         }
2452
2453         if (!clearval)
2454                 return;
2455
2456         hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2457         hclge_enable_vector(&hdev->misc_vector, true);
2458 }
2459
2460 static void hclge_reset(struct hclge_dev *hdev)
2461 {
2462         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2463         struct hnae3_handle *handle;
2464
2465         /* Initialize ae_dev reset status as well, in case enet layer wants to
2466          * know if device is undergoing reset
2467          */
2468         ae_dev->reset_type = hdev->reset_type;
2469         /* perform reset of the stack & ae device for a client */
2470         handle = &hdev->vport[0].nic;
2471         rtnl_lock();
2472         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2473
2474         if (!hclge_reset_wait(hdev)) {
2475                 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2476                 hclge_reset_ae_dev(hdev->ae_dev);
2477                 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2478
2479                 hclge_clear_reset_cause(hdev);
2480         } else {
2481                 /* schedule again to check pending resets later */
2482                 set_bit(hdev->reset_type, &hdev->reset_pending);
2483                 hclge_reset_task_schedule(hdev);
2484         }
2485
2486         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2487         handle->last_reset_time = jiffies;
2488         rtnl_unlock();
2489         ae_dev->reset_type = HNAE3_NONE_RESET;
2490 }
2491
2492 static void hclge_reset_event(struct hnae3_handle *handle)
2493 {
2494         struct hclge_vport *vport = hclge_get_vport(handle);
2495         struct hclge_dev *hdev = vport->back;
2496
2497         /* check if this is a new reset request and we are not here just because
2498          * last reset attempt did not succeed and watchdog hit us again. We will
2499          * know this if last reset request did not occur very recently (watchdog
2500          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2501          * In case of new request we reset the "reset level" to PF reset.
2502          * And if it is a repeat reset request of the most recent one then we
2503          * want to make sure we throttle the reset request. Therefore, we will
2504          * not allow it again before 3*HZ times.
2505          */
2506         if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2507                 return;
2508         else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2509                 handle->reset_level = HNAE3_FUNC_RESET;
2510
2511         dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2512                  handle->reset_level);
2513
2514         /* request reset & schedule reset task */
2515         set_bit(handle->reset_level, &hdev->reset_request);
2516         hclge_reset_task_schedule(hdev);
2517
2518         if (handle->reset_level < HNAE3_GLOBAL_RESET)
2519                 handle->reset_level++;
2520 }
2521
2522 static void hclge_reset_subtask(struct hclge_dev *hdev)
2523 {
2524         /* check if there is any ongoing reset in the hardware. This status can
2525          * be checked from reset_pending. If there is then, we need to wait for
2526          * hardware to complete reset.
2527          *    a. If we are able to figure out in reasonable time that hardware
2528          *       has fully resetted then, we can proceed with driver, client
2529          *       reset.
2530          *    b. else, we can come back later to check this status so re-sched
2531          *       now.
2532          */
2533         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2534         if (hdev->reset_type != HNAE3_NONE_RESET)
2535                 hclge_reset(hdev);
2536
2537         /* check if we got any *new* reset requests to be honored */
2538         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2539         if (hdev->reset_type != HNAE3_NONE_RESET)
2540                 hclge_do_reset(hdev);
2541
2542         hdev->reset_type = HNAE3_NONE_RESET;
2543 }
2544
2545 static void hclge_reset_service_task(struct work_struct *work)
2546 {
2547         struct hclge_dev *hdev =
2548                 container_of(work, struct hclge_dev, rst_service_task);
2549
2550         if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2551                 return;
2552
2553         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2554
2555         hclge_reset_subtask(hdev);
2556
2557         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2558 }
2559
2560 static void hclge_mailbox_service_task(struct work_struct *work)
2561 {
2562         struct hclge_dev *hdev =
2563                 container_of(work, struct hclge_dev, mbx_service_task);
2564
2565         if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2566                 return;
2567
2568         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2569
2570         hclge_mbx_handler(hdev);
2571
2572         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2573 }
2574
2575 static void hclge_service_task(struct work_struct *work)
2576 {
2577         struct hclge_dev *hdev =
2578                 container_of(work, struct hclge_dev, service_task);
2579
2580         if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2581                 hclge_update_stats_for_all(hdev);
2582                 hdev->hw_stats.stats_timer = 0;
2583         }
2584
2585         hclge_update_speed_duplex(hdev);
2586         hclge_update_link_status(hdev);
2587         hclge_service_complete(hdev);
2588 }
2589
2590 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2591 {
2592         /* VF handle has no client */
2593         if (!handle->client)
2594                 return container_of(handle, struct hclge_vport, nic);
2595         else if (handle->client->type == HNAE3_CLIENT_ROCE)
2596                 return container_of(handle, struct hclge_vport, roce);
2597         else
2598                 return container_of(handle, struct hclge_vport, nic);
2599 }
2600
2601 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2602                             struct hnae3_vector_info *vector_info)
2603 {
2604         struct hclge_vport *vport = hclge_get_vport(handle);
2605         struct hnae3_vector_info *vector = vector_info;
2606         struct hclge_dev *hdev = vport->back;
2607         int alloc = 0;
2608         int i, j;
2609
2610         vector_num = min(hdev->num_msi_left, vector_num);
2611
2612         for (j = 0; j < vector_num; j++) {
2613                 for (i = 1; i < hdev->num_msi; i++) {
2614                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2615                                 vector->vector = pci_irq_vector(hdev->pdev, i);
2616                                 vector->io_addr = hdev->hw.io_base +
2617                                         HCLGE_VECTOR_REG_BASE +
2618                                         (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2619                                         vport->vport_id *
2620                                         HCLGE_VECTOR_VF_OFFSET;
2621                                 hdev->vector_status[i] = vport->vport_id;
2622                                 hdev->vector_irq[i] = vector->vector;
2623
2624                                 vector++;
2625                                 alloc++;
2626
2627                                 break;
2628                         }
2629                 }
2630         }
2631         hdev->num_msi_left -= alloc;
2632         hdev->num_msi_used += alloc;
2633
2634         return alloc;
2635 }
2636
2637 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2638 {
2639         int i;
2640
2641         for (i = 0; i < hdev->num_msi; i++)
2642                 if (vector == hdev->vector_irq[i])
2643                         return i;
2644
2645         return -EINVAL;
2646 }
2647
2648 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2649 {
2650         struct hclge_vport *vport = hclge_get_vport(handle);
2651         struct hclge_dev *hdev = vport->back;
2652         int vector_id;
2653
2654         vector_id = hclge_get_vector_index(hdev, vector);
2655         if (vector_id < 0) {
2656                 dev_err(&hdev->pdev->dev,
2657                         "Get vector index fail. vector_id =%d\n", vector_id);
2658                 return vector_id;
2659         }
2660
2661         hclge_free_vector(hdev, vector_id);
2662
2663         return 0;
2664 }
2665
2666 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2667 {
2668         return HCLGE_RSS_KEY_SIZE;
2669 }
2670
2671 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2672 {
2673         return HCLGE_RSS_IND_TBL_SIZE;
2674 }
2675
2676 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2677                                   const u8 hfunc, const u8 *key)
2678 {
2679         struct hclge_rss_config_cmd *req;
2680         struct hclge_desc desc;
2681         int key_offset;
2682         int key_size;
2683         int ret;
2684
2685         req = (struct hclge_rss_config_cmd *)desc.data;
2686
2687         for (key_offset = 0; key_offset < 3; key_offset++) {
2688                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2689                                            false);
2690
2691                 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2692                 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2693
2694                 if (key_offset == 2)
2695                         key_size =
2696                         HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2697                 else
2698                         key_size = HCLGE_RSS_HASH_KEY_NUM;
2699
2700                 memcpy(req->hash_key,
2701                        key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2702
2703                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2704                 if (ret) {
2705                         dev_err(&hdev->pdev->dev,
2706                                 "Configure RSS config fail, status = %d\n",
2707                                 ret);
2708                         return ret;
2709                 }
2710         }
2711         return 0;
2712 }
2713
2714 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
2715 {
2716         struct hclge_rss_indirection_table_cmd *req;
2717         struct hclge_desc desc;
2718         int i, j;
2719         int ret;
2720
2721         req = (struct hclge_rss_indirection_table_cmd *)desc.data;
2722
2723         for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2724                 hclge_cmd_setup_basic_desc
2725                         (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2726
2727                 req->start_table_index =
2728                         cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2729                 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
2730
2731                 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2732                         req->rss_result[j] =
2733                                 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2734
2735                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2736                 if (ret) {
2737                         dev_err(&hdev->pdev->dev,
2738                                 "Configure rss indir table fail,status = %d\n",
2739                                 ret);
2740                         return ret;
2741                 }
2742         }
2743         return 0;
2744 }
2745
2746 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2747                                  u16 *tc_size, u16 *tc_offset)
2748 {
2749         struct hclge_rss_tc_mode_cmd *req;
2750         struct hclge_desc desc;
2751         int ret;
2752         int i;
2753
2754         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2755         req = (struct hclge_rss_tc_mode_cmd *)desc.data;
2756
2757         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2758                 u16 mode = 0;
2759
2760                 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2761                 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
2762                                 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2763                 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
2764                                 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2765
2766                 req->rss_tc_mode[i] = cpu_to_le16(mode);
2767         }
2768
2769         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2770         if (ret)
2771                 dev_err(&hdev->pdev->dev,
2772                         "Configure rss tc mode fail, status = %d\n", ret);
2773
2774         return ret;
2775 }
2776
2777 static void hclge_get_rss_type(struct hclge_vport *vport)
2778 {
2779         if (vport->rss_tuple_sets.ipv4_tcp_en ||
2780             vport->rss_tuple_sets.ipv4_udp_en ||
2781             vport->rss_tuple_sets.ipv4_sctp_en ||
2782             vport->rss_tuple_sets.ipv6_tcp_en ||
2783             vport->rss_tuple_sets.ipv6_udp_en ||
2784             vport->rss_tuple_sets.ipv6_sctp_en)
2785                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
2786         else if (vport->rss_tuple_sets.ipv4_fragment_en ||
2787                  vport->rss_tuple_sets.ipv6_fragment_en)
2788                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
2789         else
2790                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
2791 }
2792
2793 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2794 {
2795         struct hclge_rss_input_tuple_cmd *req;
2796         struct hclge_desc desc;
2797         int ret;
2798
2799         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2800
2801         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
2802
2803         /* Get the tuple cfg from pf */
2804         req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
2805         req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
2806         req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
2807         req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
2808         req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
2809         req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
2810         req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
2811         req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
2812         hclge_get_rss_type(&hdev->vport[0]);
2813         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2814         if (ret)
2815                 dev_err(&hdev->pdev->dev,
2816                         "Configure rss input fail, status = %d\n", ret);
2817         return ret;
2818 }
2819
2820 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2821                          u8 *key, u8 *hfunc)
2822 {
2823         struct hclge_vport *vport = hclge_get_vport(handle);
2824         int i;
2825
2826         /* Get hash algorithm */
2827         if (hfunc) {
2828                 switch (vport->rss_algo) {
2829                 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
2830                         *hfunc = ETH_RSS_HASH_TOP;
2831                         break;
2832                 case HCLGE_RSS_HASH_ALGO_SIMPLE:
2833                         *hfunc = ETH_RSS_HASH_XOR;
2834                         break;
2835                 default:
2836                         *hfunc = ETH_RSS_HASH_UNKNOWN;
2837                         break;
2838                 }
2839         }
2840
2841         /* Get the RSS Key required by the user */
2842         if (key)
2843                 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2844
2845         /* Get indirect table */
2846         if (indir)
2847                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2848                         indir[i] =  vport->rss_indirection_tbl[i];
2849
2850         return 0;
2851 }
2852
2853 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2854                          const  u8 *key, const  u8 hfunc)
2855 {
2856         struct hclge_vport *vport = hclge_get_vport(handle);
2857         struct hclge_dev *hdev = vport->back;
2858         u8 hash_algo;
2859         int ret, i;
2860
2861         /* Set the RSS Hash Key if specififed by the user */
2862         if (key) {
2863                 switch (hfunc) {
2864                 case ETH_RSS_HASH_TOP:
2865                         hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2866                         break;
2867                 case ETH_RSS_HASH_XOR:
2868                         hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
2869                         break;
2870                 case ETH_RSS_HASH_NO_CHANGE:
2871                         hash_algo = vport->rss_algo;
2872                         break;
2873                 default:
2874                         return -EINVAL;
2875                 }
2876
2877                 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2878                 if (ret)
2879                         return ret;
2880
2881                 /* Update the shadow RSS key with user specified qids */
2882                 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2883                 vport->rss_algo = hash_algo;
2884         }
2885
2886         /* Update the shadow RSS table with user specified qids */
2887         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2888                 vport->rss_indirection_tbl[i] = indir[i];
2889
2890         /* Update the hardware */
2891         return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
2892 }
2893
2894 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2895 {
2896         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2897
2898         if (nfc->data & RXH_L4_B_2_3)
2899                 hash_sets |= HCLGE_D_PORT_BIT;
2900         else
2901                 hash_sets &= ~HCLGE_D_PORT_BIT;
2902
2903         if (nfc->data & RXH_IP_SRC)
2904                 hash_sets |= HCLGE_S_IP_BIT;
2905         else
2906                 hash_sets &= ~HCLGE_S_IP_BIT;
2907
2908         if (nfc->data & RXH_IP_DST)
2909                 hash_sets |= HCLGE_D_IP_BIT;
2910         else
2911                 hash_sets &= ~HCLGE_D_IP_BIT;
2912
2913         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
2914                 hash_sets |= HCLGE_V_TAG_BIT;
2915
2916         return hash_sets;
2917 }
2918
2919 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
2920                                struct ethtool_rxnfc *nfc)
2921 {
2922         struct hclge_vport *vport = hclge_get_vport(handle);
2923         struct hclge_dev *hdev = vport->back;
2924         struct hclge_rss_input_tuple_cmd *req;
2925         struct hclge_desc desc;
2926         u8 tuple_sets;
2927         int ret;
2928
2929         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2930                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
2931                 return -EINVAL;
2932
2933         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
2934         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2935
2936         req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
2937         req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
2938         req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
2939         req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
2940         req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
2941         req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
2942         req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
2943         req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
2944
2945         tuple_sets = hclge_get_rss_hash_bits(nfc);
2946         switch (nfc->flow_type) {
2947         case TCP_V4_FLOW:
2948                 req->ipv4_tcp_en = tuple_sets;
2949                 break;
2950         case TCP_V6_FLOW:
2951                 req->ipv6_tcp_en = tuple_sets;
2952                 break;
2953         case UDP_V4_FLOW:
2954                 req->ipv4_udp_en = tuple_sets;
2955                 break;
2956         case UDP_V6_FLOW:
2957                 req->ipv6_udp_en = tuple_sets;
2958                 break;
2959         case SCTP_V4_FLOW:
2960                 req->ipv4_sctp_en = tuple_sets;
2961                 break;
2962         case SCTP_V6_FLOW:
2963                 if ((nfc->data & RXH_L4_B_0_1) ||
2964                     (nfc->data & RXH_L4_B_2_3))
2965                         return -EINVAL;
2966
2967                 req->ipv6_sctp_en = tuple_sets;
2968                 break;
2969         case IPV4_FLOW:
2970                 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2971                 break;
2972         case IPV6_FLOW:
2973                 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2974                 break;
2975         default:
2976                 return -EINVAL;
2977         }
2978
2979         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2980         if (ret) {
2981                 dev_err(&hdev->pdev->dev,
2982                         "Set rss tuple fail, status = %d\n", ret);
2983                 return ret;
2984         }
2985
2986         vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
2987         vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
2988         vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
2989         vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
2990         vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
2991         vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
2992         vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
2993         vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
2994         hclge_get_rss_type(vport);
2995         return 0;
2996 }
2997
2998 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
2999                                struct ethtool_rxnfc *nfc)
3000 {
3001         struct hclge_vport *vport = hclge_get_vport(handle);
3002         u8 tuple_sets;
3003
3004         nfc->data = 0;
3005
3006         switch (nfc->flow_type) {
3007         case TCP_V4_FLOW:
3008                 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3009                 break;
3010         case UDP_V4_FLOW:
3011                 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3012                 break;
3013         case TCP_V6_FLOW:
3014                 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3015                 break;
3016         case UDP_V6_FLOW:
3017                 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3018                 break;
3019         case SCTP_V4_FLOW:
3020                 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3021                 break;
3022         case SCTP_V6_FLOW:
3023                 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3024                 break;
3025         case IPV4_FLOW:
3026         case IPV6_FLOW:
3027                 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3028                 break;
3029         default:
3030                 return -EINVAL;
3031         }
3032
3033         if (!tuple_sets)
3034                 return 0;
3035
3036         if (tuple_sets & HCLGE_D_PORT_BIT)
3037                 nfc->data |= RXH_L4_B_2_3;
3038         if (tuple_sets & HCLGE_S_PORT_BIT)
3039                 nfc->data |= RXH_L4_B_0_1;
3040         if (tuple_sets & HCLGE_D_IP_BIT)
3041                 nfc->data |= RXH_IP_DST;
3042         if (tuple_sets & HCLGE_S_IP_BIT)
3043                 nfc->data |= RXH_IP_SRC;
3044
3045         return 0;
3046 }
3047
3048 static int hclge_get_tc_size(struct hnae3_handle *handle)
3049 {
3050         struct hclge_vport *vport = hclge_get_vport(handle);
3051         struct hclge_dev *hdev = vport->back;
3052
3053         return hdev->rss_size_max;
3054 }
3055
3056 int hclge_rss_init_hw(struct hclge_dev *hdev)
3057 {
3058         struct hclge_vport *vport = hdev->vport;
3059         u8 *rss_indir = vport[0].rss_indirection_tbl;
3060         u16 rss_size = vport[0].alloc_rss_size;
3061         u8 *key = vport[0].rss_hash_key;
3062         u8 hfunc = vport[0].rss_algo;
3063         u16 tc_offset[HCLGE_MAX_TC_NUM];
3064         u16 tc_valid[HCLGE_MAX_TC_NUM];
3065         u16 tc_size[HCLGE_MAX_TC_NUM];
3066         u16 roundup_size;
3067         int i, ret;
3068
3069         ret = hclge_set_rss_indir_table(hdev, rss_indir);
3070         if (ret)
3071                 return ret;
3072
3073         ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3074         if (ret)
3075                 return ret;
3076
3077         ret = hclge_set_rss_input_tuple(hdev);
3078         if (ret)
3079                 return ret;
3080
3081         /* Each TC have the same queue size, and tc_size set to hardware is
3082          * the log2 of roundup power of two of rss_size, the acutal queue
3083          * size is limited by indirection table.
3084          */
3085         if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3086                 dev_err(&hdev->pdev->dev,
3087                         "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3088                         rss_size);
3089                 return -EINVAL;
3090         }
3091
3092         roundup_size = roundup_pow_of_two(rss_size);
3093         roundup_size = ilog2(roundup_size);
3094
3095         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3096                 tc_valid[i] = 0;
3097
3098                 if (!(hdev->hw_tc_map & BIT(i)))
3099                         continue;
3100
3101                 tc_valid[i] = 1;
3102                 tc_size[i] = roundup_size;
3103                 tc_offset[i] = rss_size * i;
3104         }
3105
3106         return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3107 }
3108
3109 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3110 {
3111         struct hclge_vport *vport = hdev->vport;
3112         int i, j;
3113
3114         for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3115                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3116                         vport[j].rss_indirection_tbl[i] =
3117                                 i % vport[j].alloc_rss_size;
3118         }
3119 }
3120
3121 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3122 {
3123         struct hclge_vport *vport = hdev->vport;
3124         int i;
3125
3126         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3127                 vport[i].rss_tuple_sets.ipv4_tcp_en =
3128                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3129                 vport[i].rss_tuple_sets.ipv4_udp_en =
3130                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3131                 vport[i].rss_tuple_sets.ipv4_sctp_en =
3132                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3133                 vport[i].rss_tuple_sets.ipv4_fragment_en =
3134                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3135                 vport[i].rss_tuple_sets.ipv6_tcp_en =
3136                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3137                 vport[i].rss_tuple_sets.ipv6_udp_en =
3138                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3139                 vport[i].rss_tuple_sets.ipv6_sctp_en =
3140                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3141                 vport[i].rss_tuple_sets.ipv6_fragment_en =
3142                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3143
3144                 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3145
3146                 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3147         }
3148
3149         hclge_rss_indir_init_cfg(hdev);
3150 }
3151
3152 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3153                                 int vector_id, bool en,
3154                                 struct hnae3_ring_chain_node *ring_chain)
3155 {
3156         struct hclge_dev *hdev = vport->back;
3157         struct hnae3_ring_chain_node *node;
3158         struct hclge_desc desc;
3159         struct hclge_ctrl_vector_chain_cmd *req
3160                 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3161         enum hclge_cmd_status status;
3162         enum hclge_opcode_type op;
3163         u16 tqp_type_and_id;
3164         int i;
3165
3166         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3167         hclge_cmd_setup_basic_desc(&desc, op, false);
3168         req->int_vector_id = vector_id;
3169
3170         i = 0;
3171         for (node = ring_chain; node; node = node->next) {
3172                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3173                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
3174                                 HCLGE_INT_TYPE_S,
3175                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3176                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3177                                 HCLGE_TQP_ID_S, node->tqp_index);
3178                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3179                                 HCLGE_INT_GL_IDX_S,
3180                                 hnae3_get_field(node->int_gl_idx,
3181                                                 HNAE3_RING_GL_IDX_M,
3182                                                 HNAE3_RING_GL_IDX_S));
3183                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3184                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3185                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3186                         req->vfid = vport->vport_id;
3187
3188                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
3189                         if (status) {
3190                                 dev_err(&hdev->pdev->dev,
3191                                         "Map TQP fail, status is %d.\n",
3192                                         status);
3193                                 return -EIO;
3194                         }
3195                         i = 0;
3196
3197                         hclge_cmd_setup_basic_desc(&desc,
3198                                                    op,
3199                                                    false);
3200                         req->int_vector_id = vector_id;
3201                 }
3202         }
3203
3204         if (i > 0) {
3205                 req->int_cause_num = i;
3206                 req->vfid = vport->vport_id;
3207                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3208                 if (status) {
3209                         dev_err(&hdev->pdev->dev,
3210                                 "Map TQP fail, status is %d.\n", status);
3211                         return -EIO;
3212                 }
3213         }
3214
3215         return 0;
3216 }
3217
3218 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3219                                     int vector,
3220                                     struct hnae3_ring_chain_node *ring_chain)
3221 {
3222         struct hclge_vport *vport = hclge_get_vport(handle);
3223         struct hclge_dev *hdev = vport->back;
3224         int vector_id;
3225
3226         vector_id = hclge_get_vector_index(hdev, vector);
3227         if (vector_id < 0) {
3228                 dev_err(&hdev->pdev->dev,
3229                         "Get vector index fail. vector_id =%d\n", vector_id);
3230                 return vector_id;
3231         }
3232
3233         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3234 }
3235
3236 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3237                                        int vector,
3238                                        struct hnae3_ring_chain_node *ring_chain)
3239 {
3240         struct hclge_vport *vport = hclge_get_vport(handle);
3241         struct hclge_dev *hdev = vport->back;
3242         int vector_id, ret;
3243
3244         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3245                 return 0;
3246
3247         vector_id = hclge_get_vector_index(hdev, vector);
3248         if (vector_id < 0) {
3249                 dev_err(&handle->pdev->dev,
3250                         "Get vector index fail. ret =%d\n", vector_id);
3251                 return vector_id;
3252         }
3253
3254         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3255         if (ret)
3256                 dev_err(&handle->pdev->dev,
3257                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3258                         vector_id,
3259                         ret);
3260
3261         return ret;
3262 }
3263
3264 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3265                                struct hclge_promisc_param *param)
3266 {
3267         struct hclge_promisc_cfg_cmd *req;
3268         struct hclge_desc desc;
3269         int ret;
3270
3271         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3272
3273         req = (struct hclge_promisc_cfg_cmd *)desc.data;
3274         req->vf_id = param->vf_id;
3275
3276         /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3277          * pdev revision(0x20), new revision support them. The
3278          * value of this two fields will not return error when driver
3279          * send command to fireware in revision(0x20).
3280          */
3281         req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3282                 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3283
3284         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3285         if (ret)
3286                 dev_err(&hdev->pdev->dev,
3287                         "Set promisc mode fail, status is %d.\n", ret);
3288
3289         return ret;
3290 }
3291
3292 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3293                               bool en_mc, bool en_bc, int vport_id)
3294 {
3295         if (!param)
3296                 return;
3297
3298         memset(param, 0, sizeof(struct hclge_promisc_param));
3299         if (en_uc)
3300                 param->enable = HCLGE_PROMISC_EN_UC;
3301         if (en_mc)
3302                 param->enable |= HCLGE_PROMISC_EN_MC;
3303         if (en_bc)
3304                 param->enable |= HCLGE_PROMISC_EN_BC;
3305         param->vf_id = vport_id;
3306 }
3307
3308 static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3309                                    bool en_mc_pmc)
3310 {
3311         struct hclge_vport *vport = hclge_get_vport(handle);
3312         struct hclge_dev *hdev = vport->back;
3313         struct hclge_promisc_param param;
3314
3315         hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3316                                  vport->vport_id);
3317         hclge_cmd_set_promisc_mode(hdev, &param);
3318 }
3319
3320 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3321 {
3322         struct hclge_get_fd_mode_cmd *req;
3323         struct hclge_desc desc;
3324         int ret;
3325
3326         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3327
3328         req = (struct hclge_get_fd_mode_cmd *)desc.data;
3329
3330         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3331         if (ret) {
3332                 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3333                 return ret;
3334         }
3335
3336         *fd_mode = req->mode;
3337
3338         return ret;
3339 }
3340
3341 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3342                                    u32 *stage1_entry_num,
3343                                    u32 *stage2_entry_num,
3344                                    u16 *stage1_counter_num,
3345                                    u16 *stage2_counter_num)
3346 {
3347         struct hclge_get_fd_allocation_cmd *req;
3348         struct hclge_desc desc;
3349         int ret;
3350
3351         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3352
3353         req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3354
3355         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3356         if (ret) {
3357                 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3358                         ret);
3359                 return ret;
3360         }
3361
3362         *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3363         *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3364         *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3365         *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3366
3367         return ret;
3368 }
3369
3370 static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3371 {
3372         struct hclge_set_fd_key_config_cmd *req;
3373         struct hclge_fd_key_cfg *stage;
3374         struct hclge_desc desc;
3375         int ret;
3376
3377         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3378
3379         req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3380         stage = &hdev->fd_cfg.key_cfg[stage_num];
3381         req->stage = stage_num;
3382         req->key_select = stage->key_sel;
3383         req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3384         req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3385         req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3386         req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3387         req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3388         req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3389
3390         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3391         if (ret)
3392                 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3393
3394         return ret;
3395 }
3396
3397 static int hclge_init_fd_config(struct hclge_dev *hdev)
3398 {
3399 #define LOW_2_WORDS             0x03
3400         struct hclge_fd_key_cfg *key_cfg;
3401         int ret;
3402
3403         if (!hnae3_dev_fd_supported(hdev))
3404                 return 0;
3405
3406         ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3407         if (ret)
3408                 return ret;
3409
3410         switch (hdev->fd_cfg.fd_mode) {
3411         case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3412                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3413                 break;
3414         case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3415                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3416                 break;
3417         default:
3418                 dev_err(&hdev->pdev->dev,
3419                         "Unsupported flow director mode %d\n",
3420                         hdev->fd_cfg.fd_mode);
3421                 return -EOPNOTSUPP;
3422         }
3423
3424         hdev->fd_cfg.fd_en = true;
3425         hdev->fd_cfg.proto_support =
3426                 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3427                 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3428         key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3429         key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3430         key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3431         key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3432         key_cfg->outer_sipv6_word_en = 0;
3433         key_cfg->outer_dipv6_word_en = 0;
3434
3435         key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3436                                 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3437                                 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3438                                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3439
3440         /* If use max 400bit key, we can support tuples for ether type */
3441         if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3442                 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3443                 key_cfg->tuple_active |=
3444                                 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3445         }
3446
3447         /* roce_type is used to filter roce frames
3448          * dst_vport is used to specify the rule
3449          */
3450         key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3451
3452         ret = hclge_get_fd_allocation(hdev,
3453                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3454                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3455                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3456                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3457         if (ret)
3458                 return ret;
3459
3460         return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3461 }
3462
3463 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3464                                 int loc, u8 *key, bool is_add)
3465 {
3466         struct hclge_fd_tcam_config_1_cmd *req1;
3467         struct hclge_fd_tcam_config_2_cmd *req2;
3468         struct hclge_fd_tcam_config_3_cmd *req3;
3469         struct hclge_desc desc[3];
3470         int ret;
3471
3472         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3473         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3474         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3475         desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3476         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3477
3478         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3479         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3480         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3481
3482         req1->stage = stage;
3483         req1->xy_sel = sel_x ? 1 : 0;
3484         hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3485         req1->index = cpu_to_le32(loc);
3486         req1->entry_vld = sel_x ? is_add : 0;
3487
3488         if (key) {
3489                 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3490                 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3491                        sizeof(req2->tcam_data));
3492                 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3493                        sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3494         }
3495
3496         ret = hclge_cmd_send(&hdev->hw, desc, 3);
3497         if (ret)
3498                 dev_err(&hdev->pdev->dev,
3499                         "config tcam key fail, ret=%d\n",
3500                         ret);
3501
3502         return ret;
3503 }
3504
3505 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3506                               struct hclge_fd_ad_data *action)
3507 {
3508         struct hclge_fd_ad_config_cmd *req;
3509         struct hclge_desc desc;
3510         u64 ad_data = 0;
3511         int ret;
3512
3513         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3514
3515         req = (struct hclge_fd_ad_config_cmd *)desc.data;
3516         req->index = cpu_to_le32(loc);
3517         req->stage = stage;
3518
3519         hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,