ixgbe: fix MAC anti-spoofing filter after VFLR
[muen/linux.git] / drivers / net / ethernet / hisilicon / hns3 / hns3vf / hclgevf_main.c
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/etherdevice.h>
5 #include <net/rtnetlink.h>
6 #include "hclgevf_cmd.h"
7 #include "hclgevf_main.h"
8 #include "hclge_mbx.h"
9 #include "hnae3.h"
10
11 #define HCLGEVF_NAME    "hclgevf"
12
13 static int hclgevf_init_hdev(struct hclgevf_dev *hdev);
14 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev);
15 static struct hnae3_ae_algo ae_algovf;
16
17 static const struct pci_device_id ae_algovf_pci_tbl[] = {
18         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
19         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
20         /* required last entry */
21         {0, }
22 };
23
24 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
25
26 static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
27         struct hnae3_handle *handle)
28 {
29         return container_of(handle, struct hclgevf_dev, nic);
30 }
31
32 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
33 {
34         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
35         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
36         struct hclgevf_desc desc;
37         struct hclgevf_tqp *tqp;
38         int status;
39         int i;
40
41         for (i = 0; i < kinfo->num_tqps; i++) {
42                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
43                 hclgevf_cmd_setup_basic_desc(&desc,
44                                              HCLGEVF_OPC_QUERY_RX_STATUS,
45                                              true);
46
47                 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
48                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
49                 if (status) {
50                         dev_err(&hdev->pdev->dev,
51                                 "Query tqp stat fail, status = %d,queue = %d\n",
52                                 status, i);
53                         return status;
54                 }
55                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
56                         le32_to_cpu(desc.data[1]);
57
58                 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
59                                              true);
60
61                 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
62                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
63                 if (status) {
64                         dev_err(&hdev->pdev->dev,
65                                 "Query tqp stat fail, status = %d,queue = %d\n",
66                                 status, i);
67                         return status;
68                 }
69                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
70                         le32_to_cpu(desc.data[1]);
71         }
72
73         return 0;
74 }
75
76 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
77 {
78         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
79         struct hclgevf_tqp *tqp;
80         u64 *buff = data;
81         int i;
82
83         for (i = 0; i < kinfo->num_tqps; i++) {
84                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
85                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
86         }
87         for (i = 0; i < kinfo->num_tqps; i++) {
88                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
89                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
90         }
91
92         return buff;
93 }
94
95 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
96 {
97         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
98
99         return kinfo->num_tqps * 2;
100 }
101
102 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
103 {
104         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
105         u8 *buff = data;
106         int i = 0;
107
108         for (i = 0; i < kinfo->num_tqps; i++) {
109                 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
110                                                        struct hclgevf_tqp, q);
111                 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
112                          tqp->index);
113                 buff += ETH_GSTRING_LEN;
114         }
115
116         for (i = 0; i < kinfo->num_tqps; i++) {
117                 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
118                                                        struct hclgevf_tqp, q);
119                 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
120                          tqp->index);
121                 buff += ETH_GSTRING_LEN;
122         }
123
124         return buff;
125 }
126
127 static void hclgevf_update_stats(struct hnae3_handle *handle,
128                                  struct net_device_stats *net_stats)
129 {
130         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
131         int status;
132
133         status = hclgevf_tqps_update_stats(handle);
134         if (status)
135                 dev_err(&hdev->pdev->dev,
136                         "VF update of TQPS stats fail, status = %d.\n",
137                         status);
138 }
139
140 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
141 {
142         if (strset == ETH_SS_TEST)
143                 return -EOPNOTSUPP;
144         else if (strset == ETH_SS_STATS)
145                 return hclgevf_tqps_get_sset_count(handle, strset);
146
147         return 0;
148 }
149
150 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
151                                 u8 *data)
152 {
153         u8 *p = (char *)data;
154
155         if (strset == ETH_SS_STATS)
156                 p = hclgevf_tqps_get_strings(handle, p);
157 }
158
159 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
160 {
161         hclgevf_tqps_get_stats(handle, data);
162 }
163
164 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
165 {
166         u8 resp_msg;
167         int status;
168
169         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0,
170                                       true, &resp_msg, sizeof(u8));
171         if (status) {
172                 dev_err(&hdev->pdev->dev,
173                         "VF request to get TC info from PF failed %d",
174                         status);
175                 return status;
176         }
177
178         hdev->hw_tc_map = resp_msg;
179
180         return 0;
181 }
182
183 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
184 {
185 #define HCLGEVF_TQPS_RSS_INFO_LEN       8
186         u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
187         int status;
188
189         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0,
190                                       true, resp_msg,
191                                       HCLGEVF_TQPS_RSS_INFO_LEN);
192         if (status) {
193                 dev_err(&hdev->pdev->dev,
194                         "VF request to get tqp info from PF failed %d",
195                         status);
196                 return status;
197         }
198
199         memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16));
200         memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16));
201         memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16));
202         memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16));
203
204         return 0;
205 }
206
207 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
208 {
209         struct hclgevf_tqp *tqp;
210         int i;
211
212         /* if this is on going reset then we need to re-allocate the TPQs
213          * since we cannot assume we would get same number of TPQs back from PF
214          */
215         if (hclgevf_dev_ongoing_reset(hdev))
216                 devm_kfree(&hdev->pdev->dev, hdev->htqp);
217
218         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
219                                   sizeof(struct hclgevf_tqp), GFP_KERNEL);
220         if (!hdev->htqp)
221                 return -ENOMEM;
222
223         tqp = hdev->htqp;
224
225         for (i = 0; i < hdev->num_tqps; i++) {
226                 tqp->dev = &hdev->pdev->dev;
227                 tqp->index = i;
228
229                 tqp->q.ae_algo = &ae_algovf;
230                 tqp->q.buf_size = hdev->rx_buf_len;
231                 tqp->q.desc_num = hdev->num_desc;
232                 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
233                         i * HCLGEVF_TQP_REG_SIZE;
234
235                 tqp++;
236         }
237
238         return 0;
239 }
240
241 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
242 {
243         struct hnae3_handle *nic = &hdev->nic;
244         struct hnae3_knic_private_info *kinfo;
245         u16 new_tqps = hdev->num_tqps;
246         int i;
247
248         kinfo = &nic->kinfo;
249         kinfo->num_tc = 0;
250         kinfo->num_desc = hdev->num_desc;
251         kinfo->rx_buf_len = hdev->rx_buf_len;
252         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
253                 if (hdev->hw_tc_map & BIT(i))
254                         kinfo->num_tc++;
255
256         kinfo->rss_size
257                 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
258         new_tqps = kinfo->rss_size * kinfo->num_tc;
259         kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
260
261         /* if this is on going reset then we need to re-allocate the hnae queues
262          * as well since number of TPQs from PF might have changed.
263          */
264         if (hclgevf_dev_ongoing_reset(hdev))
265                 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
266
267         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
268                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
269         if (!kinfo->tqp)
270                 return -ENOMEM;
271
272         for (i = 0; i < kinfo->num_tqps; i++) {
273                 hdev->htqp[i].q.handle = &hdev->nic;
274                 hdev->htqp[i].q.tqp_index = i;
275                 kinfo->tqp[i] = &hdev->htqp[i].q;
276         }
277
278         return 0;
279 }
280
281 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
282 {
283         int status;
284         u8 resp_msg;
285
286         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL,
287                                       0, false, &resp_msg, sizeof(u8));
288         if (status)
289                 dev_err(&hdev->pdev->dev,
290                         "VF failed to fetch link status(%d) from PF", status);
291 }
292
293 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
294 {
295         struct hnae3_handle *handle = &hdev->nic;
296         struct hnae3_client *client;
297
298         client = handle->client;
299
300         link_state =
301                 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
302
303         if (link_state != hdev->hw.mac.link) {
304                 client->ops->link_status_change(handle, !!link_state);
305                 hdev->hw.mac.link = link_state;
306         }
307 }
308
309 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
310 {
311         struct hnae3_handle *nic = &hdev->nic;
312         int ret;
313
314         nic->ae_algo = &ae_algovf;
315         nic->pdev = hdev->pdev;
316         nic->numa_node_mask = hdev->numa_node_mask;
317         nic->flags |= HNAE3_SUPPORT_VF;
318
319         if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) {
320                 dev_err(&hdev->pdev->dev, "unsupported device type %d\n",
321                         hdev->ae_dev->dev_type);
322                 return -EINVAL;
323         }
324
325         ret = hclgevf_knic_setup(hdev);
326         if (ret)
327                 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
328                         ret);
329         return ret;
330 }
331
332 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
333 {
334         if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
335                 dev_warn(&hdev->pdev->dev,
336                          "vector(vector_id %d) has been freed.\n", vector_id);
337                 return;
338         }
339
340         hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
341         hdev->num_msi_left += 1;
342         hdev->num_msi_used -= 1;
343 }
344
345 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
346                               struct hnae3_vector_info *vector_info)
347 {
348         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
349         struct hnae3_vector_info *vector = vector_info;
350         int alloc = 0;
351         int i, j;
352
353         vector_num = min(hdev->num_msi_left, vector_num);
354
355         for (j = 0; j < vector_num; j++) {
356                 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
357                         if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
358                                 vector->vector = pci_irq_vector(hdev->pdev, i);
359                                 vector->io_addr = hdev->hw.io_base +
360                                         HCLGEVF_VECTOR_REG_BASE +
361                                         (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
362                                 hdev->vector_status[i] = 0;
363                                 hdev->vector_irq[i] = vector->vector;
364
365                                 vector++;
366                                 alloc++;
367
368                                 break;
369                         }
370                 }
371         }
372         hdev->num_msi_left -= alloc;
373         hdev->num_msi_used += alloc;
374
375         return alloc;
376 }
377
378 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
379 {
380         int i;
381
382         for (i = 0; i < hdev->num_msi; i++)
383                 if (vector == hdev->vector_irq[i])
384                         return i;
385
386         return -EINVAL;
387 }
388
389 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
390                                     const u8 hfunc, const u8 *key)
391 {
392         struct hclgevf_rss_config_cmd *req;
393         struct hclgevf_desc desc;
394         int key_offset;
395         int key_size;
396         int ret;
397
398         req = (struct hclgevf_rss_config_cmd *)desc.data;
399
400         for (key_offset = 0; key_offset < 3; key_offset++) {
401                 hclgevf_cmd_setup_basic_desc(&desc,
402                                              HCLGEVF_OPC_RSS_GENERIC_CONFIG,
403                                              false);
404
405                 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
406                 req->hash_config |=
407                         (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
408
409                 if (key_offset == 2)
410                         key_size =
411                         HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2;
412                 else
413                         key_size = HCLGEVF_RSS_HASH_KEY_NUM;
414
415                 memcpy(req->hash_key,
416                        key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
417
418                 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
419                 if (ret) {
420                         dev_err(&hdev->pdev->dev,
421                                 "Configure RSS config fail, status = %d\n",
422                                 ret);
423                         return ret;
424                 }
425         }
426
427         return 0;
428 }
429
430 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
431 {
432         return HCLGEVF_RSS_KEY_SIZE;
433 }
434
435 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
436 {
437         return HCLGEVF_RSS_IND_TBL_SIZE;
438 }
439
440 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
441 {
442         const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
443         struct hclgevf_rss_indirection_table_cmd *req;
444         struct hclgevf_desc desc;
445         int status;
446         int i, j;
447
448         req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
449
450         for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
451                 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
452                                              false);
453                 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
454                 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
455                 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
456                         req->rss_result[j] =
457                                 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
458
459                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
460                 if (status) {
461                         dev_err(&hdev->pdev->dev,
462                                 "VF failed(=%d) to set RSS indirection table\n",
463                                 status);
464                         return status;
465                 }
466         }
467
468         return 0;
469 }
470
471 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
472 {
473         struct hclgevf_rss_tc_mode_cmd *req;
474         u16 tc_offset[HCLGEVF_MAX_TC_NUM];
475         u16 tc_valid[HCLGEVF_MAX_TC_NUM];
476         u16 tc_size[HCLGEVF_MAX_TC_NUM];
477         struct hclgevf_desc desc;
478         u16 roundup_size;
479         int status;
480         int i;
481
482         req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
483
484         roundup_size = roundup_pow_of_two(rss_size);
485         roundup_size = ilog2(roundup_size);
486
487         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
488                 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
489                 tc_size[i] = roundup_size;
490                 tc_offset[i] = rss_size * i;
491         }
492
493         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
494         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
495                 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
496                               (tc_valid[i] & 0x1));
497                 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
498                                 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
499                 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
500                                 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
501         }
502         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
503         if (status)
504                 dev_err(&hdev->pdev->dev,
505                         "VF failed(=%d) to set rss tc mode\n", status);
506
507         return status;
508 }
509
510 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
511                            u8 *hfunc)
512 {
513         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
514         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
515         int i;
516
517         if (handle->pdev->revision >= 0x21) {
518                 /* Get hash algorithm */
519                 if (hfunc) {
520                         switch (rss_cfg->hash_algo) {
521                         case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
522                                 *hfunc = ETH_RSS_HASH_TOP;
523                                 break;
524                         case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
525                                 *hfunc = ETH_RSS_HASH_XOR;
526                                 break;
527                         default:
528                                 *hfunc = ETH_RSS_HASH_UNKNOWN;
529                                 break;
530                         }
531                 }
532
533                 /* Get the RSS Key required by the user */
534                 if (key)
535                         memcpy(key, rss_cfg->rss_hash_key,
536                                HCLGEVF_RSS_KEY_SIZE);
537         }
538
539         if (indir)
540                 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
541                         indir[i] = rss_cfg->rss_indirection_tbl[i];
542
543         return 0;
544 }
545
546 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
547                            const  u8 *key, const  u8 hfunc)
548 {
549         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
550         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
551         int ret, i;
552
553         if (handle->pdev->revision >= 0x21) {
554                 /* Set the RSS Hash Key if specififed by the user */
555                 if (key) {
556                         switch (hfunc) {
557                         case ETH_RSS_HASH_TOP:
558                                 rss_cfg->hash_algo =
559                                         HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
560                                 break;
561                         case ETH_RSS_HASH_XOR:
562                                 rss_cfg->hash_algo =
563                                         HCLGEVF_RSS_HASH_ALGO_SIMPLE;
564                                 break;
565                         case ETH_RSS_HASH_NO_CHANGE:
566                                 break;
567                         default:
568                                 return -EINVAL;
569                         }
570
571                         ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
572                                                        key);
573                         if (ret)
574                                 return ret;
575
576                         /* Update the shadow RSS key with user specified qids */
577                         memcpy(rss_cfg->rss_hash_key, key,
578                                HCLGEVF_RSS_KEY_SIZE);
579                 }
580         }
581
582         /* update the shadow RSS table with user specified qids */
583         for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
584                 rss_cfg->rss_indirection_tbl[i] = indir[i];
585
586         /* update the hardware */
587         return hclgevf_set_rss_indir_table(hdev);
588 }
589
590 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
591 {
592         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
593
594         if (nfc->data & RXH_L4_B_2_3)
595                 hash_sets |= HCLGEVF_D_PORT_BIT;
596         else
597                 hash_sets &= ~HCLGEVF_D_PORT_BIT;
598
599         if (nfc->data & RXH_IP_SRC)
600                 hash_sets |= HCLGEVF_S_IP_BIT;
601         else
602                 hash_sets &= ~HCLGEVF_S_IP_BIT;
603
604         if (nfc->data & RXH_IP_DST)
605                 hash_sets |= HCLGEVF_D_IP_BIT;
606         else
607                 hash_sets &= ~HCLGEVF_D_IP_BIT;
608
609         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
610                 hash_sets |= HCLGEVF_V_TAG_BIT;
611
612         return hash_sets;
613 }
614
615 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
616                                  struct ethtool_rxnfc *nfc)
617 {
618         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
619         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
620         struct hclgevf_rss_input_tuple_cmd *req;
621         struct hclgevf_desc desc;
622         u8 tuple_sets;
623         int ret;
624
625         if (handle->pdev->revision == 0x20)
626                 return -EOPNOTSUPP;
627
628         if (nfc->data &
629             ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
630                 return -EINVAL;
631
632         req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
633         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
634
635         req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
636         req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
637         req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
638         req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
639         req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
640         req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
641         req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
642         req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
643
644         tuple_sets = hclgevf_get_rss_hash_bits(nfc);
645         switch (nfc->flow_type) {
646         case TCP_V4_FLOW:
647                 req->ipv4_tcp_en = tuple_sets;
648                 break;
649         case TCP_V6_FLOW:
650                 req->ipv6_tcp_en = tuple_sets;
651                 break;
652         case UDP_V4_FLOW:
653                 req->ipv4_udp_en = tuple_sets;
654                 break;
655         case UDP_V6_FLOW:
656                 req->ipv6_udp_en = tuple_sets;
657                 break;
658         case SCTP_V4_FLOW:
659                 req->ipv4_sctp_en = tuple_sets;
660                 break;
661         case SCTP_V6_FLOW:
662                 if ((nfc->data & RXH_L4_B_0_1) ||
663                     (nfc->data & RXH_L4_B_2_3))
664                         return -EINVAL;
665
666                 req->ipv6_sctp_en = tuple_sets;
667                 break;
668         case IPV4_FLOW:
669                 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
670                 break;
671         case IPV6_FLOW:
672                 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
673                 break;
674         default:
675                 return -EINVAL;
676         }
677
678         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
679         if (ret) {
680                 dev_err(&hdev->pdev->dev,
681                         "Set rss tuple fail, status = %d\n", ret);
682                 return ret;
683         }
684
685         rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
686         rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
687         rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
688         rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
689         rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
690         rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
691         rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
692         rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
693         return 0;
694 }
695
696 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
697                                  struct ethtool_rxnfc *nfc)
698 {
699         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
700         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
701         u8 tuple_sets;
702
703         if (handle->pdev->revision == 0x20)
704                 return -EOPNOTSUPP;
705
706         nfc->data = 0;
707
708         switch (nfc->flow_type) {
709         case TCP_V4_FLOW:
710                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
711                 break;
712         case UDP_V4_FLOW:
713                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en;
714                 break;
715         case TCP_V6_FLOW:
716                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
717                 break;
718         case UDP_V6_FLOW:
719                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en;
720                 break;
721         case SCTP_V4_FLOW:
722                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
723                 break;
724         case SCTP_V6_FLOW:
725                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
726                 break;
727         case IPV4_FLOW:
728         case IPV6_FLOW:
729                 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
730                 break;
731         default:
732                 return -EINVAL;
733         }
734
735         if (!tuple_sets)
736                 return 0;
737
738         if (tuple_sets & HCLGEVF_D_PORT_BIT)
739                 nfc->data |= RXH_L4_B_2_3;
740         if (tuple_sets & HCLGEVF_S_PORT_BIT)
741                 nfc->data |= RXH_L4_B_0_1;
742         if (tuple_sets & HCLGEVF_D_IP_BIT)
743                 nfc->data |= RXH_IP_DST;
744         if (tuple_sets & HCLGEVF_S_IP_BIT)
745                 nfc->data |= RXH_IP_SRC;
746
747         return 0;
748 }
749
750 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
751                                        struct hclgevf_rss_cfg *rss_cfg)
752 {
753         struct hclgevf_rss_input_tuple_cmd *req;
754         struct hclgevf_desc desc;
755         int ret;
756
757         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
758
759         req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
760
761         req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
762         req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
763         req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
764         req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
765         req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
766         req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
767         req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
768         req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
769
770         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
771         if (ret)
772                 dev_err(&hdev->pdev->dev,
773                         "Configure rss input fail, status = %d\n", ret);
774         return ret;
775 }
776
777 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
778 {
779         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
780         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
781
782         return rss_cfg->rss_size;
783 }
784
785 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
786                                        int vector_id,
787                                        struct hnae3_ring_chain_node *ring_chain)
788 {
789         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
790         struct hnae3_ring_chain_node *node;
791         struct hclge_mbx_vf_to_pf_cmd *req;
792         struct hclgevf_desc desc;
793         int i = 0;
794         int status;
795         u8 type;
796
797         req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
798
799         for (node = ring_chain; node; node = node->next) {
800                 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM +
801                                         HCLGE_MBX_RING_NODE_VARIABLE_NUM * i;
802
803                 if (i == 0) {
804                         hclgevf_cmd_setup_basic_desc(&desc,
805                                                      HCLGEVF_OPC_MBX_VF_TO_PF,
806                                                      false);
807                         type = en ?
808                                 HCLGE_MBX_MAP_RING_TO_VECTOR :
809                                 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
810                         req->msg[0] = type;
811                         req->msg[1] = vector_id;
812                 }
813
814                 req->msg[idx_offset] =
815                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
816                 req->msg[idx_offset + 1] = node->tqp_index;
817                 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx,
818                                                            HNAE3_RING_GL_IDX_M,
819                                                            HNAE3_RING_GL_IDX_S);
820
821                 i++;
822                 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM -
823                      HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) /
824                      HCLGE_MBX_RING_NODE_VARIABLE_NUM) ||
825                     !node->next) {
826                         req->msg[2] = i;
827
828                         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
829                         if (status) {
830                                 dev_err(&hdev->pdev->dev,
831                                         "Map TQP fail, status is %d.\n",
832                                         status);
833                                 return status;
834                         }
835                         i = 0;
836                         hclgevf_cmd_setup_basic_desc(&desc,
837                                                      HCLGEVF_OPC_MBX_VF_TO_PF,
838                                                      false);
839                         req->msg[0] = type;
840                         req->msg[1] = vector_id;
841                 }
842         }
843
844         return 0;
845 }
846
847 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
848                                       struct hnae3_ring_chain_node *ring_chain)
849 {
850         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
851         int vector_id;
852
853         vector_id = hclgevf_get_vector_index(hdev, vector);
854         if (vector_id < 0) {
855                 dev_err(&handle->pdev->dev,
856                         "Get vector index fail. ret =%d\n", vector_id);
857                 return vector_id;
858         }
859
860         return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
861 }
862
863 static int hclgevf_unmap_ring_from_vector(
864                                 struct hnae3_handle *handle,
865                                 int vector,
866                                 struct hnae3_ring_chain_node *ring_chain)
867 {
868         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
869         int ret, vector_id;
870
871         vector_id = hclgevf_get_vector_index(hdev, vector);
872         if (vector_id < 0) {
873                 dev_err(&handle->pdev->dev,
874                         "Get vector index fail. ret =%d\n", vector_id);
875                 return vector_id;
876         }
877
878         ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
879         if (ret)
880                 dev_err(&handle->pdev->dev,
881                         "Unmap ring from vector fail. vector=%d, ret =%d\n",
882                         vector_id,
883                         ret);
884
885         return ret;
886 }
887
888 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
889 {
890         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
891         int vector_id;
892
893         vector_id = hclgevf_get_vector_index(hdev, vector);
894         if (vector_id < 0) {
895                 dev_err(&handle->pdev->dev,
896                         "hclgevf_put_vector get vector index fail. ret =%d\n",
897                         vector_id);
898                 return vector_id;
899         }
900
901         hclgevf_free_vector(hdev, vector_id);
902
903         return 0;
904 }
905
906 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
907                                         bool en_uc_pmc, bool en_mc_pmc)
908 {
909         struct hclge_mbx_vf_to_pf_cmd *req;
910         struct hclgevf_desc desc;
911         int status;
912
913         req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
914
915         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false);
916         req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE;
917         req->msg[1] = en_uc_pmc ? 1 : 0;
918         req->msg[2] = en_mc_pmc ? 1 : 0;
919
920         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
921         if (status)
922                 dev_err(&hdev->pdev->dev,
923                         "Set promisc mode fail, status is %d.\n", status);
924
925         return status;
926 }
927
928 static void hclgevf_set_promisc_mode(struct hnae3_handle *handle,
929                                      bool en_uc_pmc, bool en_mc_pmc)
930 {
931         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
932
933         hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc);
934 }
935
936 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id,
937                               int stream_id, bool enable)
938 {
939         struct hclgevf_cfg_com_tqp_queue_cmd *req;
940         struct hclgevf_desc desc;
941         int status;
942
943         req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
944
945         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
946                                      false);
947         req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
948         req->stream_id = cpu_to_le16(stream_id);
949         req->enable |= enable << HCLGEVF_TQP_ENABLE_B;
950
951         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
952         if (status)
953                 dev_err(&hdev->pdev->dev,
954                         "TQP enable fail, status =%d.\n", status);
955
956         return status;
957 }
958
959 static int hclgevf_get_queue_id(struct hnae3_queue *queue)
960 {
961         struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q);
962
963         return tqp->index;
964 }
965
966 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
967 {
968         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
969         struct hclgevf_tqp *tqp;
970         int i;
971
972         for (i = 0; i < kinfo->num_tqps; i++) {
973                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
974                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
975         }
976 }
977
978 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
979 {
980         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
981
982         ether_addr_copy(p, hdev->hw.mac.mac_addr);
983 }
984
985 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
986                                 bool is_first)
987 {
988         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
989         u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
990         u8 *new_mac_addr = (u8 *)p;
991         u8 msg_data[ETH_ALEN * 2];
992         u16 subcode;
993         int status;
994
995         ether_addr_copy(msg_data, new_mac_addr);
996         ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr);
997
998         subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD :
999                         HCLGE_MBX_MAC_VLAN_UC_MODIFY;
1000
1001         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1002                                       subcode, msg_data, ETH_ALEN * 2,
1003                                       true, NULL, 0);
1004         if (!status)
1005                 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
1006
1007         return status;
1008 }
1009
1010 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
1011                                const unsigned char *addr)
1012 {
1013         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1014
1015         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1016                                     HCLGE_MBX_MAC_VLAN_UC_ADD,
1017                                     addr, ETH_ALEN, false, NULL, 0);
1018 }
1019
1020 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1021                               const unsigned char *addr)
1022 {
1023         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1024
1025         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1026                                     HCLGE_MBX_MAC_VLAN_UC_REMOVE,
1027                                     addr, ETH_ALEN, false, NULL, 0);
1028 }
1029
1030 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1031                                const unsigned char *addr)
1032 {
1033         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1034
1035         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
1036                                     HCLGE_MBX_MAC_VLAN_MC_ADD,
1037                                     addr, ETH_ALEN, false, NULL, 0);
1038 }
1039
1040 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1041                               const unsigned char *addr)
1042 {
1043         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1044
1045         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
1046                                     HCLGE_MBX_MAC_VLAN_MC_REMOVE,
1047                                     addr, ETH_ALEN, false, NULL, 0);
1048 }
1049
1050 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1051                                    __be16 proto, u16 vlan_id,
1052                                    bool is_kill)
1053 {
1054 #define HCLGEVF_VLAN_MBX_MSG_LEN 5
1055         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1056         u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN];
1057
1058         if (vlan_id > 4095)
1059                 return -EINVAL;
1060
1061         if (proto != htons(ETH_P_8021Q))
1062                 return -EPROTONOSUPPORT;
1063
1064         msg_data[0] = is_kill;
1065         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1066         memcpy(&msg_data[3], &proto, sizeof(proto));
1067         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
1068                                     HCLGE_MBX_VLAN_FILTER, msg_data,
1069                                     HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0);
1070 }
1071
1072 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1073 {
1074         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1075         u8 msg_data;
1076
1077         msg_data = enable ? 1 : 0;
1078         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
1079                                     HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data,
1080                                     1, false, NULL, 0);
1081 }
1082
1083 static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
1084 {
1085         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1086         u8 msg_data[2];
1087         int ret;
1088
1089         memcpy(&msg_data[0], &queue_id, sizeof(queue_id));
1090
1091         /* disable vf queue before send queue reset msg to PF */
1092         ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
1093         if (ret)
1094                 return;
1095
1096         hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data,
1097                              2, true, NULL, 0);
1098 }
1099
1100 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1101                                  enum hnae3_reset_notify_type type)
1102 {
1103         struct hnae3_client *client = hdev->nic_client;
1104         struct hnae3_handle *handle = &hdev->nic;
1105
1106         if (!client->ops->reset_notify)
1107                 return -EOPNOTSUPP;
1108
1109         return client->ops->reset_notify(handle, type);
1110 }
1111
1112 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1113 {
1114 #define HCLGEVF_RESET_WAIT_MS   500
1115 #define HCLGEVF_RESET_WAIT_CNT  20
1116         u32 val, cnt = 0;
1117
1118         /* wait to check the hardware reset completion status */
1119         val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
1120         while (hnae3_get_bit(val, HCLGEVF_FUN_RST_ING_B) &&
1121                (cnt < HCLGEVF_RESET_WAIT_CNT)) {
1122                 msleep(HCLGEVF_RESET_WAIT_MS);
1123                 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
1124                 cnt++;
1125         }
1126
1127         /* hardware completion status should be available by this time */
1128         if (cnt >= HCLGEVF_RESET_WAIT_CNT) {
1129                 dev_warn(&hdev->pdev->dev,
1130                          "could'nt get reset done status from h/w, timeout!\n");
1131                 return -EBUSY;
1132         }
1133
1134         /* we will wait a bit more to let reset of the stack to complete. This
1135          * might happen in case reset assertion was made by PF. Yes, this also
1136          * means we might end up waiting bit more even for VF reset.
1137          */
1138         msleep(5000);
1139
1140         return 0;
1141 }
1142
1143 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1144 {
1145         int ret;
1146
1147         /* uninitialize the nic client */
1148         hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1149
1150         /* re-initialize the hclge device */
1151         ret = hclgevf_init_hdev(hdev);
1152         if (ret) {
1153                 dev_err(&hdev->pdev->dev,
1154                         "hclge device re-init failed, VF is disabled!\n");
1155                 return ret;
1156         }
1157
1158         /* bring up the nic client again */
1159         hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1160
1161         return 0;
1162 }
1163
1164 static int hclgevf_reset(struct hclgevf_dev *hdev)
1165 {
1166         int ret;
1167
1168         rtnl_lock();
1169
1170         /* bring down the nic to stop any ongoing TX/RX */
1171         hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1172
1173         /* check if VF could successfully fetch the hardware reset completion
1174          * status from the hardware
1175          */
1176         ret = hclgevf_reset_wait(hdev);
1177         if (ret) {
1178                 /* can't do much in this situation, will disable VF */
1179                 dev_err(&hdev->pdev->dev,
1180                         "VF failed(=%d) to fetch H/W reset completion status\n",
1181                         ret);
1182
1183                 dev_warn(&hdev->pdev->dev, "VF reset failed, disabling VF!\n");
1184                 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1185
1186                 rtnl_unlock();
1187                 return ret;
1188         }
1189
1190         /* now, re-initialize the nic client and ae device*/
1191         ret = hclgevf_reset_stack(hdev);
1192         if (ret)
1193                 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1194
1195         /* bring up the nic to enable TX/RX again */
1196         hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1197
1198         rtnl_unlock();
1199
1200         return ret;
1201 }
1202
1203 static int hclgevf_do_reset(struct hclgevf_dev *hdev)
1204 {
1205         int status;
1206         u8 respmsg;
1207
1208         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL,
1209                                       0, false, &respmsg, sizeof(u8));
1210         if (status)
1211                 dev_err(&hdev->pdev->dev,
1212                         "VF reset request to PF failed(=%d)\n", status);
1213
1214         return status;
1215 }
1216
1217 static void hclgevf_reset_event(struct pci_dev *pdev,
1218                                 struct hnae3_handle *handle)
1219 {
1220         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1221
1222         dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1223
1224         handle->reset_level = HNAE3_VF_RESET;
1225
1226         /* reset of this VF requested */
1227         set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1228         hclgevf_reset_task_schedule(hdev);
1229
1230         handle->last_reset_time = jiffies;
1231 }
1232
1233 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1234 {
1235         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1236
1237         return hdev->fw_version;
1238 }
1239
1240 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1241 {
1242         struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1243
1244         vector->vector_irq = pci_irq_vector(hdev->pdev,
1245                                             HCLGEVF_MISC_VECTOR_NUM);
1246         vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1247         /* vector status always valid for Vector 0 */
1248         hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1249         hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1250
1251         hdev->num_msi_left -= 1;
1252         hdev->num_msi_used += 1;
1253 }
1254
1255 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1256 {
1257         if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) &&
1258             !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) {
1259                 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1260                 schedule_work(&hdev->rst_service_task);
1261         }
1262 }
1263
1264 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
1265 {
1266         if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) &&
1267             !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) {
1268                 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1269                 schedule_work(&hdev->mbx_service_task);
1270         }
1271 }
1272
1273 static void hclgevf_task_schedule(struct hclgevf_dev *hdev)
1274 {
1275         if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state)  &&
1276             !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state))
1277                 schedule_work(&hdev->service_task);
1278 }
1279
1280 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev)
1281 {
1282         /* if we have any pending mailbox event then schedule the mbx task */
1283         if (hdev->mbx_event_pending)
1284                 hclgevf_mbx_task_schedule(hdev);
1285
1286         if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state))
1287                 hclgevf_reset_task_schedule(hdev);
1288 }
1289
1290 static void hclgevf_service_timer(struct timer_list *t)
1291 {
1292         struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer);
1293
1294         mod_timer(&hdev->service_timer, jiffies + 5 * HZ);
1295
1296         hclgevf_task_schedule(hdev);
1297 }
1298
1299 static void hclgevf_reset_service_task(struct work_struct *work)
1300 {
1301         struct hclgevf_dev *hdev =
1302                 container_of(work, struct hclgevf_dev, rst_service_task);
1303         int ret;
1304
1305         if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1306                 return;
1307
1308         clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1309
1310         if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1311                                &hdev->reset_state)) {
1312                 /* PF has initmated that it is about to reset the hardware.
1313                  * We now have to poll & check if harware has actually completed
1314                  * the reset sequence. On hardware reset completion, VF needs to
1315                  * reset the client and ae device.
1316                  */
1317                 hdev->reset_attempts = 0;
1318
1319                 ret = hclgevf_reset(hdev);
1320                 if (ret)
1321                         dev_err(&hdev->pdev->dev, "VF stack reset failed.\n");
1322         } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1323                                       &hdev->reset_state)) {
1324                 /* we could be here when either of below happens:
1325                  * 1. reset was initiated due to watchdog timeout due to
1326                  *    a. IMP was earlier reset and our TX got choked down and
1327                  *       which resulted in watchdog reacting and inducing VF
1328                  *       reset. This also means our cmdq would be unreliable.
1329                  *    b. problem in TX due to other lower layer(example link
1330                  *       layer not functioning properly etc.)
1331                  * 2. VF reset might have been initiated due to some config
1332                  *    change.
1333                  *
1334                  * NOTE: Theres no clear way to detect above cases than to react
1335                  * to the response of PF for this reset request. PF will ack the
1336                  * 1b and 2. cases but we will not get any intimation about 1a
1337                  * from PF as cmdq would be in unreliable state i.e. mailbox
1338                  * communication between PF and VF would be broken.
1339                  */
1340
1341                 /* if we are never geting into pending state it means either:
1342                  * 1. PF is not receiving our request which could be due to IMP
1343                  *    reset
1344                  * 2. PF is screwed
1345                  * We cannot do much for 2. but to check first we can try reset
1346                  * our PCIe + stack and see if it alleviates the problem.
1347                  */
1348                 if (hdev->reset_attempts > 3) {
1349                         /* prepare for full reset of stack + pcie interface */
1350                         hdev->nic.reset_level = HNAE3_VF_FULL_RESET;
1351
1352                         /* "defer" schedule the reset task again */
1353                         set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1354                 } else {
1355                         hdev->reset_attempts++;
1356
1357                         /* request PF for resetting this VF via mailbox */
1358                         ret = hclgevf_do_reset(hdev);
1359                         if (ret)
1360                                 dev_warn(&hdev->pdev->dev,
1361                                          "VF rst fail, stack will call\n");
1362                 }
1363         }
1364
1365         clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1366 }
1367
1368 static void hclgevf_mailbox_service_task(struct work_struct *work)
1369 {
1370         struct hclgevf_dev *hdev;
1371
1372         hdev = container_of(work, struct hclgevf_dev, mbx_service_task);
1373
1374         if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1375                 return;
1376
1377         clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1378
1379         hclgevf_mbx_async_handler(hdev);
1380
1381         clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1382 }
1383
1384 static void hclgevf_service_task(struct work_struct *work)
1385 {
1386         struct hclgevf_dev *hdev;
1387
1388         hdev = container_of(work, struct hclgevf_dev, service_task);
1389
1390         /* request the link status from the PF. PF would be able to tell VF
1391          * about such updates in future so we might remove this later
1392          */
1393         hclgevf_request_link_info(hdev);
1394
1395         hclgevf_deferred_task_schedule(hdev);
1396
1397         clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1398 }
1399
1400 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1401 {
1402         hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
1403 }
1404
1405 static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval)
1406 {
1407         u32 cmdq_src_reg;
1408
1409         /* fetch the events from their corresponding regs */
1410         cmdq_src_reg = hclgevf_read_dev(&hdev->hw,
1411                                         HCLGEVF_VECTOR0_CMDQ_SRC_REG);
1412
1413         /* check for vector0 mailbox(=CMDQ RX) event source */
1414         if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
1415                 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1416                 *clearval = cmdq_src_reg;
1417                 return true;
1418         }
1419
1420         dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n");
1421
1422         return false;
1423 }
1424
1425 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1426 {
1427         writel(en ? 1 : 0, vector->addr);
1428 }
1429
1430 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
1431 {
1432         struct hclgevf_dev *hdev = data;
1433         u32 clearval;
1434
1435         hclgevf_enable_vector(&hdev->misc_vector, false);
1436         if (!hclgevf_check_event_cause(hdev, &clearval))
1437                 goto skip_sched;
1438
1439         hclgevf_mbx_handler(hdev);
1440
1441         hclgevf_clear_event_cause(hdev, clearval);
1442
1443 skip_sched:
1444         hclgevf_enable_vector(&hdev->misc_vector, true);
1445
1446         return IRQ_HANDLED;
1447 }
1448
1449 static int hclgevf_configure(struct hclgevf_dev *hdev)
1450 {
1451         int ret;
1452
1453         hdev->hw.mac.media_type = HNAE3_MEDIA_TYPE_NONE;
1454
1455         /* get queue configuration from PF */
1456         ret = hclgevf_get_queue_info(hdev);
1457         if (ret)
1458                 return ret;
1459         /* get tc configuration from PF */
1460         return hclgevf_get_tc_info(hdev);
1461 }
1462
1463 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
1464 {
1465         struct pci_dev *pdev = ae_dev->pdev;
1466         struct hclgevf_dev *hdev = ae_dev->priv;
1467
1468         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
1469         if (!hdev)
1470                 return -ENOMEM;
1471
1472         hdev->pdev = pdev;
1473         hdev->ae_dev = ae_dev;
1474         ae_dev->priv = hdev;
1475
1476         return 0;
1477 }
1478
1479 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
1480 {
1481         struct hnae3_handle *roce = &hdev->roce;
1482         struct hnae3_handle *nic = &hdev->nic;
1483
1484         roce->rinfo.num_vectors = hdev->num_roce_msix;
1485
1486         if (hdev->num_msi_left < roce->rinfo.num_vectors ||
1487             hdev->num_msi_left == 0)
1488                 return -EINVAL;
1489
1490         roce->rinfo.base_vector = hdev->roce_base_vector;
1491
1492         roce->rinfo.netdev = nic->kinfo.netdev;
1493         roce->rinfo.roce_io_base = hdev->hw.io_base;
1494
1495         roce->pdev = nic->pdev;
1496         roce->ae_algo = nic->ae_algo;
1497         roce->numa_node_mask = nic->numa_node_mask;
1498
1499         return 0;
1500 }
1501
1502 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
1503 {
1504         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1505         int i, ret;
1506
1507         rss_cfg->rss_size = hdev->rss_size_max;
1508
1509         if (hdev->pdev->revision >= 0x21) {
1510                 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
1511                 netdev_rss_key_fill(rss_cfg->rss_hash_key,
1512                                     HCLGEVF_RSS_KEY_SIZE);
1513
1514                 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
1515                                                rss_cfg->rss_hash_key);
1516                 if (ret)
1517                         return ret;
1518
1519                 rss_cfg->rss_tuple_sets.ipv4_tcp_en =
1520                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1521                 rss_cfg->rss_tuple_sets.ipv4_udp_en =
1522                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1523                 rss_cfg->rss_tuple_sets.ipv4_sctp_en =
1524                                         HCLGEVF_RSS_INPUT_TUPLE_SCTP;
1525                 rss_cfg->rss_tuple_sets.ipv4_fragment_en =
1526                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1527                 rss_cfg->rss_tuple_sets.ipv6_tcp_en =
1528                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1529                 rss_cfg->rss_tuple_sets.ipv6_udp_en =
1530                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1531                 rss_cfg->rss_tuple_sets.ipv6_sctp_en =
1532                                         HCLGEVF_RSS_INPUT_TUPLE_SCTP;
1533                 rss_cfg->rss_tuple_sets.ipv6_fragment_en =
1534                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1535
1536                 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
1537                 if (ret)
1538                         return ret;
1539
1540         }
1541
1542         /* Initialize RSS indirect table for each vport */
1543         for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
1544                 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max;
1545
1546         ret = hclgevf_set_rss_indir_table(hdev);
1547         if (ret)
1548                 return ret;
1549
1550         return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max);
1551 }
1552
1553 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
1554 {
1555         /* other vlan config(like, VLAN TX/RX offload) would also be added
1556          * here later
1557          */
1558         return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
1559                                        false);
1560 }
1561
1562 static int hclgevf_ae_start(struct hnae3_handle *handle)
1563 {
1564         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1565         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1566         int i, queue_id;
1567
1568         for (i = 0; i < kinfo->num_tqps; i++) {
1569                 /* ring enable */
1570                 queue_id = hclgevf_get_queue_id(kinfo->tqp[i]);
1571                 if (queue_id < 0) {
1572                         dev_warn(&hdev->pdev->dev,
1573                                  "Get invalid queue id, ignore it\n");
1574                         continue;
1575                 }
1576
1577                 hclgevf_tqp_enable(hdev, queue_id, 0, true);
1578         }
1579
1580         /* reset tqp stats */
1581         hclgevf_reset_tqp_stats(handle);
1582
1583         hclgevf_request_link_info(hdev);
1584
1585         clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1586         mod_timer(&hdev->service_timer, jiffies + HZ);
1587
1588         return 0;
1589 }
1590
1591 static void hclgevf_ae_stop(struct hnae3_handle *handle)
1592 {
1593         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1594         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1595         int i, queue_id;
1596
1597         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1598
1599         for (i = 0; i < kinfo->num_tqps; i++) {
1600                 /* Ring disable */
1601                 queue_id = hclgevf_get_queue_id(kinfo->tqp[i]);
1602                 if (queue_id < 0) {
1603                         dev_warn(&hdev->pdev->dev,
1604                                  "Get invalid queue id, ignore it\n");
1605                         continue;
1606                 }
1607
1608                 hclgevf_tqp_enable(hdev, queue_id, 0, false);
1609         }
1610
1611         /* reset tqp stats */
1612         hclgevf_reset_tqp_stats(handle);
1613         del_timer_sync(&hdev->service_timer);
1614         cancel_work_sync(&hdev->service_task);
1615         clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1616         hclgevf_update_link_status(hdev, 0);
1617 }
1618
1619 static void hclgevf_state_init(struct hclgevf_dev *hdev)
1620 {
1621         /* if this is on going reset then skip this initialization */
1622         if (hclgevf_dev_ongoing_reset(hdev))
1623                 return;
1624
1625         /* setup tasks for the MBX */
1626         INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task);
1627         clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1628         clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1629
1630         /* setup tasks for service timer */
1631         timer_setup(&hdev->service_timer, hclgevf_service_timer, 0);
1632
1633         INIT_WORK(&hdev->service_task, hclgevf_service_task);
1634         clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1635
1636         INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task);
1637
1638         mutex_init(&hdev->mbx_resp.mbx_mutex);
1639
1640         /* bring the device down */
1641         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1642 }
1643
1644 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
1645 {
1646         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1647
1648         if (hdev->service_timer.function)
1649                 del_timer_sync(&hdev->service_timer);
1650         if (hdev->service_task.func)
1651                 cancel_work_sync(&hdev->service_task);
1652         if (hdev->mbx_service_task.func)
1653                 cancel_work_sync(&hdev->mbx_service_task);
1654         if (hdev->rst_service_task.func)
1655                 cancel_work_sync(&hdev->rst_service_task);
1656
1657         mutex_destroy(&hdev->mbx_resp.mbx_mutex);
1658 }
1659
1660 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
1661 {
1662         struct pci_dev *pdev = hdev->pdev;
1663         int vectors;
1664         int i;
1665
1666         /* if this is on going reset then skip this initialization */
1667         if (hclgevf_dev_ongoing_reset(hdev))
1668                 return 0;
1669
1670         if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B))
1671                 vectors = pci_alloc_irq_vectors(pdev,
1672                                                 hdev->roce_base_msix_offset + 1,
1673                                                 hdev->num_msi,
1674                                                 PCI_IRQ_MSIX);
1675         else
1676                 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1677                                                 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1678
1679         if (vectors < 0) {
1680                 dev_err(&pdev->dev,
1681                         "failed(%d) to allocate MSI/MSI-X vectors\n",
1682                         vectors);
1683                 return vectors;
1684         }
1685         if (vectors < hdev->num_msi)
1686                 dev_warn(&hdev->pdev->dev,
1687                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1688                          hdev->num_msi, vectors);
1689
1690         hdev->num_msi = vectors;
1691         hdev->num_msi_left = vectors;
1692         hdev->base_msi_vector = pdev->irq;
1693         hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
1694
1695         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1696                                            sizeof(u16), GFP_KERNEL);
1697         if (!hdev->vector_status) {
1698                 pci_free_irq_vectors(pdev);
1699                 return -ENOMEM;
1700         }
1701
1702         for (i = 0; i < hdev->num_msi; i++)
1703                 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
1704
1705         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1706                                         sizeof(int), GFP_KERNEL);
1707         if (!hdev->vector_irq) {
1708                 pci_free_irq_vectors(pdev);
1709                 return -ENOMEM;
1710         }
1711
1712         return 0;
1713 }
1714
1715 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
1716 {
1717         struct pci_dev *pdev = hdev->pdev;
1718
1719         pci_free_irq_vectors(pdev);
1720 }
1721
1722 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
1723 {
1724         int ret = 0;
1725
1726         /* if this is on going reset then skip this initialization */
1727         if (hclgevf_dev_ongoing_reset(hdev))
1728                 return 0;
1729
1730         hclgevf_get_misc_vector(hdev);
1731
1732         ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
1733                           0, "hclgevf_cmd", hdev);
1734         if (ret) {
1735                 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
1736                         hdev->misc_vector.vector_irq);
1737                 return ret;
1738         }
1739
1740         hclgevf_clear_event_cause(hdev, 0);
1741
1742         /* enable misc. vector(vector 0) */
1743         hclgevf_enable_vector(&hdev->misc_vector, true);
1744
1745         return ret;
1746 }
1747
1748 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
1749 {
1750         /* disable misc vector(vector 0) */
1751         hclgevf_enable_vector(&hdev->misc_vector, false);
1752         synchronize_irq(hdev->misc_vector.vector_irq);
1753         free_irq(hdev->misc_vector.vector_irq, hdev);
1754         hclgevf_free_vector(hdev, 0);
1755 }
1756
1757 static int hclgevf_init_client_instance(struct hnae3_client *client,
1758                                         struct hnae3_ae_dev *ae_dev)
1759 {
1760         struct hclgevf_dev *hdev = ae_dev->priv;
1761         int ret;
1762
1763         switch (client->type) {
1764         case HNAE3_CLIENT_KNIC:
1765                 hdev->nic_client = client;
1766                 hdev->nic.client = client;
1767
1768                 ret = client->ops->init_instance(&hdev->nic);
1769                 if (ret)
1770                         goto clear_nic;
1771
1772                 hnae3_set_client_init_flag(client, ae_dev, 1);
1773
1774                 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) {
1775                         struct hnae3_client *rc = hdev->roce_client;
1776
1777                         ret = hclgevf_init_roce_base_info(hdev);
1778                         if (ret)
1779                                 goto clear_roce;
1780                         ret = rc->ops->init_instance(&hdev->roce);
1781                         if (ret)
1782                                 goto clear_roce;
1783
1784                         hnae3_set_client_init_flag(hdev->roce_client, ae_dev,
1785                                                    1);
1786                 }
1787                 break;
1788         case HNAE3_CLIENT_UNIC:
1789                 hdev->nic_client = client;
1790                 hdev->nic.client = client;
1791
1792                 ret = client->ops->init_instance(&hdev->nic);
1793                 if (ret)
1794                         goto clear_nic;
1795
1796                 hnae3_set_client_init_flag(client, ae_dev, 1);
1797                 break;
1798         case HNAE3_CLIENT_ROCE:
1799                 if (hnae3_dev_roce_supported(hdev)) {
1800                         hdev->roce_client = client;
1801                         hdev->roce.client = client;
1802                 }
1803
1804                 if (hdev->roce_client && hdev->nic_client) {
1805                         ret = hclgevf_init_roce_base_info(hdev);
1806                         if (ret)
1807                                 goto clear_roce;
1808
1809                         ret = client->ops->init_instance(&hdev->roce);
1810                         if (ret)
1811                                 goto clear_roce;
1812                 }
1813
1814                 hnae3_set_client_init_flag(client, ae_dev, 1);
1815                 break;
1816         default:
1817                 return -EINVAL;
1818         }
1819
1820         return 0;
1821
1822 clear_nic:
1823         hdev->nic_client = NULL;
1824         hdev->nic.client = NULL;
1825         return ret;
1826 clear_roce:
1827         hdev->roce_client = NULL;
1828         hdev->roce.client = NULL;
1829         return ret;
1830 }
1831
1832 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
1833                                            struct hnae3_ae_dev *ae_dev)
1834 {
1835         struct hclgevf_dev *hdev = ae_dev->priv;
1836
1837         /* un-init roce, if it exists */
1838         if (hdev->roce_client) {
1839                 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
1840                 hdev->roce_client = NULL;
1841                 hdev->roce.client = NULL;
1842         }
1843
1844         /* un-init nic/unic, if this was not called by roce client */
1845         if (client->ops->uninit_instance && hdev->nic_client &&
1846             client->type != HNAE3_CLIENT_ROCE) {
1847                 client->ops->uninit_instance(&hdev->nic, 0);
1848                 hdev->nic_client = NULL;
1849                 hdev->nic.client = NULL;
1850         }
1851 }
1852
1853 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
1854 {
1855         struct pci_dev *pdev = hdev->pdev;
1856         struct hclgevf_hw *hw;
1857         int ret;
1858
1859         /* check if we need to skip initialization of pci. This will happen if
1860          * device is undergoing VF reset. Otherwise, we would need to
1861          * re-initialize pci interface again i.e. when device is not going
1862          * through *any* reset or actually undergoing full reset.
1863          */
1864         if (hclgevf_dev_ongoing_reset(hdev))
1865                 return 0;
1866
1867         ret = pci_enable_device(pdev);
1868         if (ret) {
1869                 dev_err(&pdev->dev, "failed to enable PCI device\n");
1870                 return ret;
1871         }
1872
1873         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1874         if (ret) {
1875                 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
1876                 goto err_disable_device;
1877         }
1878
1879         ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
1880         if (ret) {
1881                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
1882                 goto err_disable_device;
1883         }
1884
1885         pci_set_master(pdev);
1886         hw = &hdev->hw;
1887         hw->hdev = hdev;
1888         hw->io_base = pci_iomap(pdev, 2, 0);
1889         if (!hw->io_base) {
1890                 dev_err(&pdev->dev, "can't map configuration register space\n");
1891                 ret = -ENOMEM;
1892                 goto err_clr_master;
1893         }
1894
1895         return 0;
1896
1897 err_clr_master:
1898         pci_clear_master(pdev);
1899         pci_release_regions(pdev);
1900 err_disable_device:
1901         pci_disable_device(pdev);
1902
1903         return ret;
1904 }
1905
1906 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
1907 {
1908         struct pci_dev *pdev = hdev->pdev;
1909
1910         pci_iounmap(pdev, hdev->hw.io_base);
1911         pci_clear_master(pdev);
1912         pci_release_regions(pdev);
1913         pci_disable_device(pdev);
1914 }
1915
1916 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
1917 {
1918         struct hclgevf_query_res_cmd *req;
1919         struct hclgevf_desc desc;
1920         int ret;
1921
1922         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
1923         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1924         if (ret) {
1925                 dev_err(&hdev->pdev->dev,
1926                         "query vf resource failed, ret = %d.\n", ret);
1927                 return ret;
1928         }
1929
1930         req = (struct hclgevf_query_res_cmd *)desc.data;
1931
1932         if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) {
1933                 hdev->roce_base_msix_offset =
1934                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
1935                                 HCLGEVF_MSIX_OFT_ROCEE_M,
1936                                 HCLGEVF_MSIX_OFT_ROCEE_S);
1937                 hdev->num_roce_msix =
1938                 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
1939                                 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
1940
1941                 /* VF should have NIC vectors and Roce vectors, NIC vectors
1942                  * are queued before Roce vectors. The offset is fixed to 64.
1943                  */
1944                 hdev->num_msi = hdev->num_roce_msix +
1945                                 hdev->roce_base_msix_offset;
1946         } else {
1947                 hdev->num_msi =
1948                 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
1949                                 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
1950         }
1951
1952         return 0;
1953 }
1954
1955 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
1956 {
1957         struct pci_dev *pdev = hdev->pdev;
1958         int ret;
1959
1960         /* check if device is on-going full reset(i.e. pcie as well) */
1961         if (hclgevf_dev_ongoing_full_reset(hdev)) {
1962                 dev_warn(&pdev->dev, "device is going full reset\n");
1963                 hclgevf_uninit_hdev(hdev);
1964         }
1965
1966         ret = hclgevf_pci_init(hdev);
1967         if (ret) {
1968                 dev_err(&pdev->dev, "PCI initialization failed\n");
1969                 return ret;
1970         }
1971
1972         ret = hclgevf_cmd_init(hdev);
1973         if (ret)
1974                 goto err_cmd_init;
1975
1976         /* Get vf resource */
1977         ret = hclgevf_query_vf_resource(hdev);
1978         if (ret) {
1979                 dev_err(&hdev->pdev->dev,
1980                         "Query vf status error, ret = %d.\n", ret);
1981                 goto err_query_vf;
1982         }
1983
1984         ret = hclgevf_init_msi(hdev);
1985         if (ret) {
1986                 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
1987                 goto err_query_vf;
1988         }
1989
1990         hclgevf_state_init(hdev);
1991
1992         ret = hclgevf_misc_irq_init(hdev);
1993         if (ret) {
1994                 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
1995                         ret);
1996                 goto err_misc_irq_init;
1997         }
1998
1999         ret = hclgevf_configure(hdev);
2000         if (ret) {
2001                 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
2002                 goto err_config;
2003         }
2004
2005         ret = hclgevf_alloc_tqps(hdev);
2006         if (ret) {
2007                 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
2008                 goto err_config;
2009         }
2010
2011         ret = hclgevf_set_handle_info(hdev);
2012         if (ret) {
2013                 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret);
2014                 goto err_config;
2015         }
2016
2017         /* Initialize RSS for this VF */
2018         ret = hclgevf_rss_init_hw(hdev);
2019         if (ret) {
2020                 dev_err(&hdev->pdev->dev,
2021                         "failed(%d) to initialize RSS\n", ret);
2022                 goto err_config;
2023         }
2024
2025         ret = hclgevf_init_vlan_config(hdev);
2026         if (ret) {
2027                 dev_err(&hdev->pdev->dev,
2028                         "failed(%d) to initialize VLAN config\n", ret);
2029                 goto err_config;
2030         }
2031
2032         pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME);
2033
2034         return 0;
2035
2036 err_config:
2037         hclgevf_misc_irq_uninit(hdev);
2038 err_misc_irq_init:
2039         hclgevf_state_uninit(hdev);
2040         hclgevf_uninit_msi(hdev);
2041 err_query_vf:
2042         hclgevf_cmd_uninit(hdev);
2043 err_cmd_init:
2044         hclgevf_pci_uninit(hdev);
2045         return ret;
2046 }
2047
2048 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
2049 {
2050         hclgevf_state_uninit(hdev);
2051         hclgevf_misc_irq_uninit(hdev);
2052         hclgevf_cmd_uninit(hdev);
2053         hclgevf_uninit_msi(hdev);
2054         hclgevf_pci_uninit(hdev);
2055 }
2056
2057 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
2058 {
2059         struct pci_dev *pdev = ae_dev->pdev;
2060         int ret;
2061
2062         ret = hclgevf_alloc_hdev(ae_dev);
2063         if (ret) {
2064                 dev_err(&pdev->dev, "hclge device allocation failed\n");
2065                 return ret;
2066         }
2067
2068         ret = hclgevf_init_hdev(ae_dev->priv);
2069         if (ret)
2070                 dev_err(&pdev->dev, "hclge device initialization failed\n");
2071
2072         return ret;
2073 }
2074
2075 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
2076 {
2077         struct hclgevf_dev *hdev = ae_dev->priv;
2078
2079         hclgevf_uninit_hdev(hdev);
2080         ae_dev->priv = NULL;
2081 }
2082
2083 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
2084 {
2085         struct hnae3_handle *nic = &hdev->nic;
2086         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
2087
2088         return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
2089 }
2090
2091 /**
2092  * hclgevf_get_channels - Get the current channels enabled and max supported.
2093  * @handle: hardware information for network interface
2094  * @ch: ethtool channels structure
2095  *
2096  * We don't support separate tx and rx queues as channels. The other count
2097  * represents how many queues are being used for control. max_combined counts
2098  * how many queue pairs we can support. They may not be mapped 1 to 1 with
2099  * q_vectors since we support a lot more queue pairs than q_vectors.
2100  **/
2101 static void hclgevf_get_channels(struct hnae3_handle *handle,
2102                                  struct ethtool_channels *ch)
2103 {
2104         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2105
2106         ch->max_combined = hclgevf_get_max_channels(hdev);
2107         ch->other_count = 0;
2108         ch->max_other = 0;
2109         ch->combined_count = hdev->num_tqps;
2110 }
2111
2112 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
2113                                           u16 *alloc_tqps, u16 *max_rss_size)
2114 {
2115         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2116
2117         *alloc_tqps = hdev->num_tqps;
2118         *max_rss_size = hdev->rss_size_max;
2119 }
2120
2121 static int hclgevf_get_status(struct hnae3_handle *handle)
2122 {
2123         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2124
2125         return hdev->hw.mac.link;
2126 }
2127
2128 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
2129                                             u8 *auto_neg, u32 *speed,
2130                                             u8 *duplex)
2131 {
2132         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2133
2134         if (speed)
2135                 *speed = hdev->hw.mac.speed;
2136         if (duplex)
2137                 *duplex = hdev->hw.mac.duplex;
2138         if (auto_neg)
2139                 *auto_neg = AUTONEG_DISABLE;
2140 }
2141
2142 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
2143                                  u8 duplex)
2144 {
2145         hdev->hw.mac.speed = speed;
2146         hdev->hw.mac.duplex = duplex;
2147 }
2148
2149 static void hclgevf_get_media_type(struct hnae3_handle *handle,
2150                                   u8 *media_type)
2151 {
2152         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2153         if (media_type)
2154                 *media_type = hdev->hw.mac.media_type;
2155 }
2156
2157 static const struct hnae3_ae_ops hclgevf_ops = {
2158         .init_ae_dev = hclgevf_init_ae_dev,
2159         .uninit_ae_dev = hclgevf_uninit_ae_dev,
2160         .init_client_instance = hclgevf_init_client_instance,
2161         .uninit_client_instance = hclgevf_uninit_client_instance,
2162         .start = hclgevf_ae_start,
2163         .stop = hclgevf_ae_stop,
2164         .map_ring_to_vector = hclgevf_map_ring_to_vector,
2165         .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
2166         .get_vector = hclgevf_get_vector,
2167         .put_vector = hclgevf_put_vector,
2168         .reset_queue = hclgevf_reset_tqp,
2169         .set_promisc_mode = hclgevf_set_promisc_mode,
2170         .get_mac_addr = hclgevf_get_mac_addr,
2171         .set_mac_addr = hclgevf_set_mac_addr,
2172         .add_uc_addr = hclgevf_add_uc_addr,
2173         .rm_uc_addr = hclgevf_rm_uc_addr,
2174         .add_mc_addr = hclgevf_add_mc_addr,
2175         .rm_mc_addr = hclgevf_rm_mc_addr,
2176         .get_stats = hclgevf_get_stats,
2177         .update_stats = hclgevf_update_stats,
2178         .get_strings = hclgevf_get_strings,
2179         .get_sset_count = hclgevf_get_sset_count,
2180         .get_rss_key_size = hclgevf_get_rss_key_size,
2181         .get_rss_indir_size = hclgevf_get_rss_indir_size,
2182         .get_rss = hclgevf_get_rss,
2183         .set_rss = hclgevf_set_rss,
2184         .get_rss_tuple = hclgevf_get_rss_tuple,
2185         .set_rss_tuple = hclgevf_set_rss_tuple,
2186         .get_tc_size = hclgevf_get_tc_size,
2187         .get_fw_version = hclgevf_get_fw_version,
2188         .set_vlan_filter = hclgevf_set_vlan_filter,
2189         .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
2190         .reset_event = hclgevf_reset_event,
2191         .get_channels = hclgevf_get_channels,
2192         .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
2193         .get_status = hclgevf_get_status,
2194         .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
2195         .get_media_type = hclgevf_get_media_type,
2196 };
2197
2198 static struct hnae3_ae_algo ae_algovf = {
2199         .ops = &hclgevf_ops,
2200         .pdev_id_table = ae_algovf_pci_tbl,
2201 };
2202
2203 static int hclgevf_init(void)
2204 {
2205         pr_info("%s is initializing\n", HCLGEVF_NAME);
2206
2207         hnae3_register_ae_algo(&ae_algovf);
2208
2209         return 0;
2210 }
2211
2212 static void hclgevf_exit(void)
2213 {
2214         hnae3_unregister_ae_algo(&ae_algovf);
2215 }
2216 module_init(hclgevf_init);
2217 module_exit(hclgevf_exit);
2218
2219 MODULE_LICENSE("GPL");
2220 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2221 MODULE_DESCRIPTION("HCLGEVF Driver");
2222 MODULE_VERSION(HCLGEVF_MOD_VERSION);