Merge branch 'i2c/for-current-fixed' of git://git.kernel.org/pub/scm/linux/kernel...
[muen/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/bitops.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/netdevice.h>
13 #include <linux/ipv6.h>
14 #include <linux/slab.h>
15 #include <net/checksum.h>
16 #include <net/ip6_checksum.h>
17 #include <net/pkt_sched.h>
18 #include <net/pkt_cls.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/mii.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/ip.h>
28 #include <linux/tcp.h>
29 #include <linux/sctp.h>
30 #include <linux/if_ether.h>
31 #include <linux/aer.h>
32 #include <linux/prefetch.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/etherdevice.h>
35 #ifdef CONFIG_IGB_DCA
36 #include <linux/dca.h>
37 #endif
38 #include <linux/i2c.h>
39 #include "igb.h"
40
41 #define MAJ 5
42 #define MIN 6
43 #define BUILD 0
44 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
45 __stringify(BUILD) "-k"
46
47 enum queue_mode {
48         QUEUE_MODE_STRICT_PRIORITY,
49         QUEUE_MODE_STREAM_RESERVATION,
50 };
51
52 enum tx_queue_prio {
53         TX_QUEUE_PRIO_HIGH,
54         TX_QUEUE_PRIO_LOW,
55 };
56
57 char igb_driver_name[] = "igb";
58 char igb_driver_version[] = DRV_VERSION;
59 static const char igb_driver_string[] =
60                                 "Intel(R) Gigabit Ethernet Network Driver";
61 static const char igb_copyright[] =
62                                 "Copyright (c) 2007-2014 Intel Corporation.";
63
64 static const struct e1000_info *igb_info_tbl[] = {
65         [board_82575] = &e1000_82575_info,
66 };
67
68 static const struct pci_device_id igb_pci_tbl[] = {
69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
72         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
73         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
74         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
75         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
76         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
77         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
78         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
79         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
104         /* required last entry */
105         {0, }
106 };
107
108 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
109
110 static int igb_setup_all_tx_resources(struct igb_adapter *);
111 static int igb_setup_all_rx_resources(struct igb_adapter *);
112 static void igb_free_all_tx_resources(struct igb_adapter *);
113 static void igb_free_all_rx_resources(struct igb_adapter *);
114 static void igb_setup_mrqc(struct igb_adapter *);
115 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
116 static void igb_remove(struct pci_dev *pdev);
117 static int igb_sw_init(struct igb_adapter *);
118 int igb_open(struct net_device *);
119 int igb_close(struct net_device *);
120 static void igb_configure(struct igb_adapter *);
121 static void igb_configure_tx(struct igb_adapter *);
122 static void igb_configure_rx(struct igb_adapter *);
123 static void igb_clean_all_tx_rings(struct igb_adapter *);
124 static void igb_clean_all_rx_rings(struct igb_adapter *);
125 static void igb_clean_tx_ring(struct igb_ring *);
126 static void igb_clean_rx_ring(struct igb_ring *);
127 static void igb_set_rx_mode(struct net_device *);
128 static void igb_update_phy_info(struct timer_list *);
129 static void igb_watchdog(struct timer_list *);
130 static void igb_watchdog_task(struct work_struct *);
131 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
132 static void igb_get_stats64(struct net_device *dev,
133                             struct rtnl_link_stats64 *stats);
134 static int igb_change_mtu(struct net_device *, int);
135 static int igb_set_mac(struct net_device *, void *);
136 static void igb_set_uta(struct igb_adapter *adapter, bool set);
137 static irqreturn_t igb_intr(int irq, void *);
138 static irqreturn_t igb_intr_msi(int irq, void *);
139 static irqreturn_t igb_msix_other(int irq, void *);
140 static irqreturn_t igb_msix_ring(int irq, void *);
141 #ifdef CONFIG_IGB_DCA
142 static void igb_update_dca(struct igb_q_vector *);
143 static void igb_setup_dca(struct igb_adapter *);
144 #endif /* CONFIG_IGB_DCA */
145 static int igb_poll(struct napi_struct *, int);
146 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
147 static int igb_clean_rx_irq(struct igb_q_vector *, int);
148 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
149 static void igb_tx_timeout(struct net_device *);
150 static void igb_reset_task(struct work_struct *);
151 static void igb_vlan_mode(struct net_device *netdev,
152                           netdev_features_t features);
153 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
154 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
155 static void igb_restore_vlan(struct igb_adapter *);
156 static void igb_rar_set_index(struct igb_adapter *, u32);
157 static void igb_ping_all_vfs(struct igb_adapter *);
158 static void igb_msg_task(struct igb_adapter *);
159 static void igb_vmm_control(struct igb_adapter *);
160 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
161 static void igb_flush_mac_table(struct igb_adapter *);
162 static int igb_available_rars(struct igb_adapter *, u8);
163 static void igb_set_default_mac_filter(struct igb_adapter *);
164 static int igb_uc_sync(struct net_device *, const unsigned char *);
165 static int igb_uc_unsync(struct net_device *, const unsigned char *);
166 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
167 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
168 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
169                                int vf, u16 vlan, u8 qos, __be16 vlan_proto);
170 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
171 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
172                                    bool setting);
173 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
174                                 bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176                                  struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
179 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
180
181 #ifdef CONFIG_PCI_IOV
182 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
183 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
184 static int igb_disable_sriov(struct pci_dev *dev);
185 static int igb_pci_disable_sriov(struct pci_dev *dev);
186 #endif
187
188 static int igb_suspend(struct device *);
189 static int igb_resume(struct device *);
190 static int igb_runtime_suspend(struct device *dev);
191 static int igb_runtime_resume(struct device *dev);
192 static int igb_runtime_idle(struct device *dev);
193 static const struct dev_pm_ops igb_pm_ops = {
194         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
195         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
196                         igb_runtime_idle)
197 };
198 static void igb_shutdown(struct pci_dev *);
199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
200 #ifdef CONFIG_IGB_DCA
201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202 static struct notifier_block dca_notifier = {
203         .notifier_call  = igb_notify_dca,
204         .next           = NULL,
205         .priority       = 0
206 };
207 #endif
208 #ifdef CONFIG_PCI_IOV
209 static unsigned int max_vfs;
210 module_param(max_vfs, uint, 0);
211 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
212 #endif /* CONFIG_PCI_IOV */
213
214 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
215                      pci_channel_state_t);
216 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
217 static void igb_io_resume(struct pci_dev *);
218
219 static const struct pci_error_handlers igb_err_handler = {
220         .error_detected = igb_io_error_detected,
221         .slot_reset = igb_io_slot_reset,
222         .resume = igb_io_resume,
223 };
224
225 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
226
227 static struct pci_driver igb_driver = {
228         .name     = igb_driver_name,
229         .id_table = igb_pci_tbl,
230         .probe    = igb_probe,
231         .remove   = igb_remove,
232 #ifdef CONFIG_PM
233         .driver.pm = &igb_pm_ops,
234 #endif
235         .shutdown = igb_shutdown,
236         .sriov_configure = igb_pci_sriov_configure,
237         .err_handler = &igb_err_handler
238 };
239
240 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
241 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
242 MODULE_LICENSE("GPL v2");
243 MODULE_VERSION(DRV_VERSION);
244
245 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
246 static int debug = -1;
247 module_param(debug, int, 0);
248 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
249
250 struct igb_reg_info {
251         u32 ofs;
252         char *name;
253 };
254
255 static const struct igb_reg_info igb_reg_info_tbl[] = {
256
257         /* General Registers */
258         {E1000_CTRL, "CTRL"},
259         {E1000_STATUS, "STATUS"},
260         {E1000_CTRL_EXT, "CTRL_EXT"},
261
262         /* Interrupt Registers */
263         {E1000_ICR, "ICR"},
264
265         /* RX Registers */
266         {E1000_RCTL, "RCTL"},
267         {E1000_RDLEN(0), "RDLEN"},
268         {E1000_RDH(0), "RDH"},
269         {E1000_RDT(0), "RDT"},
270         {E1000_RXDCTL(0), "RXDCTL"},
271         {E1000_RDBAL(0), "RDBAL"},
272         {E1000_RDBAH(0), "RDBAH"},
273
274         /* TX Registers */
275         {E1000_TCTL, "TCTL"},
276         {E1000_TDBAL(0), "TDBAL"},
277         {E1000_TDBAH(0), "TDBAH"},
278         {E1000_TDLEN(0), "TDLEN"},
279         {E1000_TDH(0), "TDH"},
280         {E1000_TDT(0), "TDT"},
281         {E1000_TXDCTL(0), "TXDCTL"},
282         {E1000_TDFH, "TDFH"},
283         {E1000_TDFT, "TDFT"},
284         {E1000_TDFHS, "TDFHS"},
285         {E1000_TDFPC, "TDFPC"},
286
287         /* List Terminator */
288         {}
289 };
290
291 /* igb_regdump - register printout routine */
292 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
293 {
294         int n = 0;
295         char rname[16];
296         u32 regs[8];
297
298         switch (reginfo->ofs) {
299         case E1000_RDLEN(0):
300                 for (n = 0; n < 4; n++)
301                         regs[n] = rd32(E1000_RDLEN(n));
302                 break;
303         case E1000_RDH(0):
304                 for (n = 0; n < 4; n++)
305                         regs[n] = rd32(E1000_RDH(n));
306                 break;
307         case E1000_RDT(0):
308                 for (n = 0; n < 4; n++)
309                         regs[n] = rd32(E1000_RDT(n));
310                 break;
311         case E1000_RXDCTL(0):
312                 for (n = 0; n < 4; n++)
313                         regs[n] = rd32(E1000_RXDCTL(n));
314                 break;
315         case E1000_RDBAL(0):
316                 for (n = 0; n < 4; n++)
317                         regs[n] = rd32(E1000_RDBAL(n));
318                 break;
319         case E1000_RDBAH(0):
320                 for (n = 0; n < 4; n++)
321                         regs[n] = rd32(E1000_RDBAH(n));
322                 break;
323         case E1000_TDBAL(0):
324                 for (n = 0; n < 4; n++)
325                         regs[n] = rd32(E1000_RDBAL(n));
326                 break;
327         case E1000_TDBAH(0):
328                 for (n = 0; n < 4; n++)
329                         regs[n] = rd32(E1000_TDBAH(n));
330                 break;
331         case E1000_TDLEN(0):
332                 for (n = 0; n < 4; n++)
333                         regs[n] = rd32(E1000_TDLEN(n));
334                 break;
335         case E1000_TDH(0):
336                 for (n = 0; n < 4; n++)
337                         regs[n] = rd32(E1000_TDH(n));
338                 break;
339         case E1000_TDT(0):
340                 for (n = 0; n < 4; n++)
341                         regs[n] = rd32(E1000_TDT(n));
342                 break;
343         case E1000_TXDCTL(0):
344                 for (n = 0; n < 4; n++)
345                         regs[n] = rd32(E1000_TXDCTL(n));
346                 break;
347         default:
348                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
349                 return;
350         }
351
352         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
353         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
354                 regs[2], regs[3]);
355 }
356
357 /* igb_dump - Print registers, Tx-rings and Rx-rings */
358 static void igb_dump(struct igb_adapter *adapter)
359 {
360         struct net_device *netdev = adapter->netdev;
361         struct e1000_hw *hw = &adapter->hw;
362         struct igb_reg_info *reginfo;
363         struct igb_ring *tx_ring;
364         union e1000_adv_tx_desc *tx_desc;
365         struct my_u0 { u64 a; u64 b; } *u0;
366         struct igb_ring *rx_ring;
367         union e1000_adv_rx_desc *rx_desc;
368         u32 staterr;
369         u16 i, n;
370
371         if (!netif_msg_hw(adapter))
372                 return;
373
374         /* Print netdevice Info */
375         if (netdev) {
376                 dev_info(&adapter->pdev->dev, "Net device Info\n");
377                 pr_info("Device Name     state            trans_start\n");
378                 pr_info("%-15s %016lX %016lX\n", netdev->name,
379                         netdev->state, dev_trans_start(netdev));
380         }
381
382         /* Print Registers */
383         dev_info(&adapter->pdev->dev, "Register Dump\n");
384         pr_info(" Register Name   Value\n");
385         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
386              reginfo->name; reginfo++) {
387                 igb_regdump(hw, reginfo);
388         }
389
390         /* Print TX Ring Summary */
391         if (!netdev || !netif_running(netdev))
392                 goto exit;
393
394         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
395         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
396         for (n = 0; n < adapter->num_tx_queues; n++) {
397                 struct igb_tx_buffer *buffer_info;
398                 tx_ring = adapter->tx_ring[n];
399                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
400                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
401                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
402                         (u64)dma_unmap_addr(buffer_info, dma),
403                         dma_unmap_len(buffer_info, len),
404                         buffer_info->next_to_watch,
405                         (u64)buffer_info->time_stamp);
406         }
407
408         /* Print TX Rings */
409         if (!netif_msg_tx_done(adapter))
410                 goto rx_ring_summary;
411
412         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
413
414         /* Transmit Descriptor Formats
415          *
416          * Advanced Transmit Descriptor
417          *   +--------------------------------------------------------------+
418          * 0 |         Buffer Address [63:0]                                |
419          *   +--------------------------------------------------------------+
420          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
421          *   +--------------------------------------------------------------+
422          *   63      46 45    40 39 38 36 35 32 31   24             15       0
423          */
424
425         for (n = 0; n < adapter->num_tx_queues; n++) {
426                 tx_ring = adapter->tx_ring[n];
427                 pr_info("------------------------------------\n");
428                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
429                 pr_info("------------------------------------\n");
430                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
431
432                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
433                         const char *next_desc;
434                         struct igb_tx_buffer *buffer_info;
435                         tx_desc = IGB_TX_DESC(tx_ring, i);
436                         buffer_info = &tx_ring->tx_buffer_info[i];
437                         u0 = (struct my_u0 *)tx_desc;
438                         if (i == tx_ring->next_to_use &&
439                             i == tx_ring->next_to_clean)
440                                 next_desc = " NTC/U";
441                         else if (i == tx_ring->next_to_use)
442                                 next_desc = " NTU";
443                         else if (i == tx_ring->next_to_clean)
444                                 next_desc = " NTC";
445                         else
446                                 next_desc = "";
447
448                         pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
449                                 i, le64_to_cpu(u0->a),
450                                 le64_to_cpu(u0->b),
451                                 (u64)dma_unmap_addr(buffer_info, dma),
452                                 dma_unmap_len(buffer_info, len),
453                                 buffer_info->next_to_watch,
454                                 (u64)buffer_info->time_stamp,
455                                 buffer_info->skb, next_desc);
456
457                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
458                                 print_hex_dump(KERN_INFO, "",
459                                         DUMP_PREFIX_ADDRESS,
460                                         16, 1, buffer_info->skb->data,
461                                         dma_unmap_len(buffer_info, len),
462                                         true);
463                 }
464         }
465
466         /* Print RX Rings Summary */
467 rx_ring_summary:
468         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
469         pr_info("Queue [NTU] [NTC]\n");
470         for (n = 0; n < adapter->num_rx_queues; n++) {
471                 rx_ring = adapter->rx_ring[n];
472                 pr_info(" %5d %5X %5X\n",
473                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
474         }
475
476         /* Print RX Rings */
477         if (!netif_msg_rx_status(adapter))
478                 goto exit;
479
480         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
481
482         /* Advanced Receive Descriptor (Read) Format
483          *    63                                           1        0
484          *    +-----------------------------------------------------+
485          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
486          *    +----------------------------------------------+------+
487          *  8 |       Header Buffer Address [63:1]           |  DD  |
488          *    +-----------------------------------------------------+
489          *
490          *
491          * Advanced Receive Descriptor (Write-Back) Format
492          *
493          *   63       48 47    32 31  30      21 20 17 16   4 3     0
494          *   +------------------------------------------------------+
495          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
496          *   | Checksum   Ident  |   |           |    | Type | Type |
497          *   +------------------------------------------------------+
498          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
499          *   +------------------------------------------------------+
500          *   63       48 47    32 31            20 19               0
501          */
502
503         for (n = 0; n < adapter->num_rx_queues; n++) {
504                 rx_ring = adapter->rx_ring[n];
505                 pr_info("------------------------------------\n");
506                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
507                 pr_info("------------------------------------\n");
508                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
509                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
510
511                 for (i = 0; i < rx_ring->count; i++) {
512                         const char *next_desc;
513                         struct igb_rx_buffer *buffer_info;
514                         buffer_info = &rx_ring->rx_buffer_info[i];
515                         rx_desc = IGB_RX_DESC(rx_ring, i);
516                         u0 = (struct my_u0 *)rx_desc;
517                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
518
519                         if (i == rx_ring->next_to_use)
520                                 next_desc = " NTU";
521                         else if (i == rx_ring->next_to_clean)
522                                 next_desc = " NTC";
523                         else
524                                 next_desc = "";
525
526                         if (staterr & E1000_RXD_STAT_DD) {
527                                 /* Descriptor Done */
528                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
529                                         "RWB", i,
530                                         le64_to_cpu(u0->a),
531                                         le64_to_cpu(u0->b),
532                                         next_desc);
533                         } else {
534                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
535                                         "R  ", i,
536                                         le64_to_cpu(u0->a),
537                                         le64_to_cpu(u0->b),
538                                         (u64)buffer_info->dma,
539                                         next_desc);
540
541                                 if (netif_msg_pktdata(adapter) &&
542                                     buffer_info->dma && buffer_info->page) {
543                                         print_hex_dump(KERN_INFO, "",
544                                           DUMP_PREFIX_ADDRESS,
545                                           16, 1,
546                                           page_address(buffer_info->page) +
547                                                       buffer_info->page_offset,
548                                           igb_rx_bufsz(rx_ring), true);
549                                 }
550                         }
551                 }
552         }
553
554 exit:
555         return;
556 }
557
558 /**
559  *  igb_get_i2c_data - Reads the I2C SDA data bit
560  *  @hw: pointer to hardware structure
561  *  @i2cctl: Current value of I2CCTL register
562  *
563  *  Returns the I2C data bit value
564  **/
565 static int igb_get_i2c_data(void *data)
566 {
567         struct igb_adapter *adapter = (struct igb_adapter *)data;
568         struct e1000_hw *hw = &adapter->hw;
569         s32 i2cctl = rd32(E1000_I2CPARAMS);
570
571         return !!(i2cctl & E1000_I2C_DATA_IN);
572 }
573
574 /**
575  *  igb_set_i2c_data - Sets the I2C data bit
576  *  @data: pointer to hardware structure
577  *  @state: I2C data value (0 or 1) to set
578  *
579  *  Sets the I2C data bit
580  **/
581 static void igb_set_i2c_data(void *data, int state)
582 {
583         struct igb_adapter *adapter = (struct igb_adapter *)data;
584         struct e1000_hw *hw = &adapter->hw;
585         s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587         if (state)
588                 i2cctl |= E1000_I2C_DATA_OUT;
589         else
590                 i2cctl &= ~E1000_I2C_DATA_OUT;
591
592         i2cctl &= ~E1000_I2C_DATA_OE_N;
593         i2cctl |= E1000_I2C_CLK_OE_N;
594         wr32(E1000_I2CPARAMS, i2cctl);
595         wrfl();
596
597 }
598
599 /**
600  *  igb_set_i2c_clk - Sets the I2C SCL clock
601  *  @data: pointer to hardware structure
602  *  @state: state to set clock
603  *
604  *  Sets the I2C clock line to state
605  **/
606 static void igb_set_i2c_clk(void *data, int state)
607 {
608         struct igb_adapter *adapter = (struct igb_adapter *)data;
609         struct e1000_hw *hw = &adapter->hw;
610         s32 i2cctl = rd32(E1000_I2CPARAMS);
611
612         if (state) {
613                 i2cctl |= E1000_I2C_CLK_OUT;
614                 i2cctl &= ~E1000_I2C_CLK_OE_N;
615         } else {
616                 i2cctl &= ~E1000_I2C_CLK_OUT;
617                 i2cctl &= ~E1000_I2C_CLK_OE_N;
618         }
619         wr32(E1000_I2CPARAMS, i2cctl);
620         wrfl();
621 }
622
623 /**
624  *  igb_get_i2c_clk - Gets the I2C SCL clock state
625  *  @data: pointer to hardware structure
626  *
627  *  Gets the I2C clock state
628  **/
629 static int igb_get_i2c_clk(void *data)
630 {
631         struct igb_adapter *adapter = (struct igb_adapter *)data;
632         struct e1000_hw *hw = &adapter->hw;
633         s32 i2cctl = rd32(E1000_I2CPARAMS);
634
635         return !!(i2cctl & E1000_I2C_CLK_IN);
636 }
637
638 static const struct i2c_algo_bit_data igb_i2c_algo = {
639         .setsda         = igb_set_i2c_data,
640         .setscl         = igb_set_i2c_clk,
641         .getsda         = igb_get_i2c_data,
642         .getscl         = igb_get_i2c_clk,
643         .udelay         = 5,
644         .timeout        = 20,
645 };
646
647 /**
648  *  igb_get_hw_dev - return device
649  *  @hw: pointer to hardware structure
650  *
651  *  used by hardware layer to print debugging information
652  **/
653 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
654 {
655         struct igb_adapter *adapter = hw->back;
656         return adapter->netdev;
657 }
658
659 /**
660  *  igb_init_module - Driver Registration Routine
661  *
662  *  igb_init_module is the first routine called when the driver is
663  *  loaded. All it does is register with the PCI subsystem.
664  **/
665 static int __init igb_init_module(void)
666 {
667         int ret;
668
669         pr_info("%s - version %s\n",
670                igb_driver_string, igb_driver_version);
671         pr_info("%s\n", igb_copyright);
672
673 #ifdef CONFIG_IGB_DCA
674         dca_register_notify(&dca_notifier);
675 #endif
676         ret = pci_register_driver(&igb_driver);
677         return ret;
678 }
679
680 module_init(igb_init_module);
681
682 /**
683  *  igb_exit_module - Driver Exit Cleanup Routine
684  *
685  *  igb_exit_module is called just before the driver is removed
686  *  from memory.
687  **/
688 static void __exit igb_exit_module(void)
689 {
690 #ifdef CONFIG_IGB_DCA
691         dca_unregister_notify(&dca_notifier);
692 #endif
693         pci_unregister_driver(&igb_driver);
694 }
695
696 module_exit(igb_exit_module);
697
698 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
699 /**
700  *  igb_cache_ring_register - Descriptor ring to register mapping
701  *  @adapter: board private structure to initialize
702  *
703  *  Once we know the feature-set enabled for the device, we'll cache
704  *  the register offset the descriptor ring is assigned to.
705  **/
706 static void igb_cache_ring_register(struct igb_adapter *adapter)
707 {
708         int i = 0, j = 0;
709         u32 rbase_offset = adapter->vfs_allocated_count;
710
711         switch (adapter->hw.mac.type) {
712         case e1000_82576:
713                 /* The queues are allocated for virtualization such that VF 0
714                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
715                  * In order to avoid collision we start at the first free queue
716                  * and continue consuming queues in the same sequence
717                  */
718                 if (adapter->vfs_allocated_count) {
719                         for (; i < adapter->rss_queues; i++)
720                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
721                                                                Q_IDX_82576(i);
722                 }
723                 /* Fall through */
724         case e1000_82575:
725         case e1000_82580:
726         case e1000_i350:
727         case e1000_i354:
728         case e1000_i210:
729         case e1000_i211:
730                 /* Fall through */
731         default:
732                 for (; i < adapter->num_rx_queues; i++)
733                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
734                 for (; j < adapter->num_tx_queues; j++)
735                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
736                 break;
737         }
738 }
739
740 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
741 {
742         struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
743         u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
744         u32 value = 0;
745
746         if (E1000_REMOVED(hw_addr))
747                 return ~value;
748
749         value = readl(&hw_addr[reg]);
750
751         /* reads should not return all F's */
752         if (!(~value) && (!reg || !(~readl(hw_addr)))) {
753                 struct net_device *netdev = igb->netdev;
754                 hw->hw_addr = NULL;
755                 netdev_err(netdev, "PCIe link lost\n");
756         }
757
758         return value;
759 }
760
761 /**
762  *  igb_write_ivar - configure ivar for given MSI-X vector
763  *  @hw: pointer to the HW structure
764  *  @msix_vector: vector number we are allocating to a given ring
765  *  @index: row index of IVAR register to write within IVAR table
766  *  @offset: column offset of in IVAR, should be multiple of 8
767  *
768  *  This function is intended to handle the writing of the IVAR register
769  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
770  *  each containing an cause allocation for an Rx and Tx ring, and a
771  *  variable number of rows depending on the number of queues supported.
772  **/
773 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
774                            int index, int offset)
775 {
776         u32 ivar = array_rd32(E1000_IVAR0, index);
777
778         /* clear any bits that are currently set */
779         ivar &= ~((u32)0xFF << offset);
780
781         /* write vector and valid bit */
782         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
783
784         array_wr32(E1000_IVAR0, index, ivar);
785 }
786
787 #define IGB_N0_QUEUE -1
788 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
789 {
790         struct igb_adapter *adapter = q_vector->adapter;
791         struct e1000_hw *hw = &adapter->hw;
792         int rx_queue = IGB_N0_QUEUE;
793         int tx_queue = IGB_N0_QUEUE;
794         u32 msixbm = 0;
795
796         if (q_vector->rx.ring)
797                 rx_queue = q_vector->rx.ring->reg_idx;
798         if (q_vector->tx.ring)
799                 tx_queue = q_vector->tx.ring->reg_idx;
800
801         switch (hw->mac.type) {
802         case e1000_82575:
803                 /* The 82575 assigns vectors using a bitmask, which matches the
804                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
805                  * or more queues to a vector, we write the appropriate bits
806                  * into the MSIXBM register for that vector.
807                  */
808                 if (rx_queue > IGB_N0_QUEUE)
809                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
810                 if (tx_queue > IGB_N0_QUEUE)
811                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
812                 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
813                         msixbm |= E1000_EIMS_OTHER;
814                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
815                 q_vector->eims_value = msixbm;
816                 break;
817         case e1000_82576:
818                 /* 82576 uses a table that essentially consists of 2 columns
819                  * with 8 rows.  The ordering is column-major so we use the
820                  * lower 3 bits as the row index, and the 4th bit as the
821                  * column offset.
822                  */
823                 if (rx_queue > IGB_N0_QUEUE)
824                         igb_write_ivar(hw, msix_vector,
825                                        rx_queue & 0x7,
826                                        (rx_queue & 0x8) << 1);
827                 if (tx_queue > IGB_N0_QUEUE)
828                         igb_write_ivar(hw, msix_vector,
829                                        tx_queue & 0x7,
830                                        ((tx_queue & 0x8) << 1) + 8);
831                 q_vector->eims_value = BIT(msix_vector);
832                 break;
833         case e1000_82580:
834         case e1000_i350:
835         case e1000_i354:
836         case e1000_i210:
837         case e1000_i211:
838                 /* On 82580 and newer adapters the scheme is similar to 82576
839                  * however instead of ordering column-major we have things
840                  * ordered row-major.  So we traverse the table by using
841                  * bit 0 as the column offset, and the remaining bits as the
842                  * row index.
843                  */
844                 if (rx_queue > IGB_N0_QUEUE)
845                         igb_write_ivar(hw, msix_vector,
846                                        rx_queue >> 1,
847                                        (rx_queue & 0x1) << 4);
848                 if (tx_queue > IGB_N0_QUEUE)
849                         igb_write_ivar(hw, msix_vector,
850                                        tx_queue >> 1,
851                                        ((tx_queue & 0x1) << 4) + 8);
852                 q_vector->eims_value = BIT(msix_vector);
853                 break;
854         default:
855                 BUG();
856                 break;
857         }
858
859         /* add q_vector eims value to global eims_enable_mask */
860         adapter->eims_enable_mask |= q_vector->eims_value;
861
862         /* configure q_vector to set itr on first interrupt */
863         q_vector->set_itr = 1;
864 }
865
866 /**
867  *  igb_configure_msix - Configure MSI-X hardware
868  *  @adapter: board private structure to initialize
869  *
870  *  igb_configure_msix sets up the hardware to properly
871  *  generate MSI-X interrupts.
872  **/
873 static void igb_configure_msix(struct igb_adapter *adapter)
874 {
875         u32 tmp;
876         int i, vector = 0;
877         struct e1000_hw *hw = &adapter->hw;
878
879         adapter->eims_enable_mask = 0;
880
881         /* set vector for other causes, i.e. link changes */
882         switch (hw->mac.type) {
883         case e1000_82575:
884                 tmp = rd32(E1000_CTRL_EXT);
885                 /* enable MSI-X PBA support*/
886                 tmp |= E1000_CTRL_EXT_PBA_CLR;
887
888                 /* Auto-Mask interrupts upon ICR read. */
889                 tmp |= E1000_CTRL_EXT_EIAME;
890                 tmp |= E1000_CTRL_EXT_IRCA;
891
892                 wr32(E1000_CTRL_EXT, tmp);
893
894                 /* enable msix_other interrupt */
895                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
896                 adapter->eims_other = E1000_EIMS_OTHER;
897
898                 break;
899
900         case e1000_82576:
901         case e1000_82580:
902         case e1000_i350:
903         case e1000_i354:
904         case e1000_i210:
905         case e1000_i211:
906                 /* Turn on MSI-X capability first, or our settings
907                  * won't stick.  And it will take days to debug.
908                  */
909                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
910                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
911                      E1000_GPIE_NSICR);
912
913                 /* enable msix_other interrupt */
914                 adapter->eims_other = BIT(vector);
915                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
916
917                 wr32(E1000_IVAR_MISC, tmp);
918                 break;
919         default:
920                 /* do nothing, since nothing else supports MSI-X */
921                 break;
922         } /* switch (hw->mac.type) */
923
924         adapter->eims_enable_mask |= adapter->eims_other;
925
926         for (i = 0; i < adapter->num_q_vectors; i++)
927                 igb_assign_vector(adapter->q_vector[i], vector++);
928
929         wrfl();
930 }
931
932 /**
933  *  igb_request_msix - Initialize MSI-X interrupts
934  *  @adapter: board private structure to initialize
935  *
936  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
937  *  kernel.
938  **/
939 static int igb_request_msix(struct igb_adapter *adapter)
940 {
941         struct net_device *netdev = adapter->netdev;
942         int i, err = 0, vector = 0, free_vector = 0;
943
944         err = request_irq(adapter->msix_entries[vector].vector,
945                           igb_msix_other, 0, netdev->name, adapter);
946         if (err)
947                 goto err_out;
948
949         for (i = 0; i < adapter->num_q_vectors; i++) {
950                 struct igb_q_vector *q_vector = adapter->q_vector[i];
951
952                 vector++;
953
954                 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
955
956                 if (q_vector->rx.ring && q_vector->tx.ring)
957                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
958                                 q_vector->rx.ring->queue_index);
959                 else if (q_vector->tx.ring)
960                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
961                                 q_vector->tx.ring->queue_index);
962                 else if (q_vector->rx.ring)
963                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
964                                 q_vector->rx.ring->queue_index);
965                 else
966                         sprintf(q_vector->name, "%s-unused", netdev->name);
967
968                 err = request_irq(adapter->msix_entries[vector].vector,
969                                   igb_msix_ring, 0, q_vector->name,
970                                   q_vector);
971                 if (err)
972                         goto err_free;
973         }
974
975         igb_configure_msix(adapter);
976         return 0;
977
978 err_free:
979         /* free already assigned IRQs */
980         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
981
982         vector--;
983         for (i = 0; i < vector; i++) {
984                 free_irq(adapter->msix_entries[free_vector++].vector,
985                          adapter->q_vector[i]);
986         }
987 err_out:
988         return err;
989 }
990
991 /**
992  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
993  *  @adapter: board private structure to initialize
994  *  @v_idx: Index of vector to be freed
995  *
996  *  This function frees the memory allocated to the q_vector.
997  **/
998 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
999 {
1000         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1001
1002         adapter->q_vector[v_idx] = NULL;
1003
1004         /* igb_get_stats64() might access the rings on this vector,
1005          * we must wait a grace period before freeing it.
1006          */
1007         if (q_vector)
1008                 kfree_rcu(q_vector, rcu);
1009 }
1010
1011 /**
1012  *  igb_reset_q_vector - Reset config for interrupt vector
1013  *  @adapter: board private structure to initialize
1014  *  @v_idx: Index of vector to be reset
1015  *
1016  *  If NAPI is enabled it will delete any references to the
1017  *  NAPI struct. This is preparation for igb_free_q_vector.
1018  **/
1019 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1020 {
1021         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1022
1023         /* Coming from igb_set_interrupt_capability, the vectors are not yet
1024          * allocated. So, q_vector is NULL so we should stop here.
1025          */
1026         if (!q_vector)
1027                 return;
1028
1029         if (q_vector->tx.ring)
1030                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1031
1032         if (q_vector->rx.ring)
1033                 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1034
1035         netif_napi_del(&q_vector->napi);
1036
1037 }
1038
1039 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1040 {
1041         int v_idx = adapter->num_q_vectors;
1042
1043         if (adapter->flags & IGB_FLAG_HAS_MSIX)
1044                 pci_disable_msix(adapter->pdev);
1045         else if (adapter->flags & IGB_FLAG_HAS_MSI)
1046                 pci_disable_msi(adapter->pdev);
1047
1048         while (v_idx--)
1049                 igb_reset_q_vector(adapter, v_idx);
1050 }
1051
1052 /**
1053  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1054  *  @adapter: board private structure to initialize
1055  *
1056  *  This function frees the memory allocated to the q_vectors.  In addition if
1057  *  NAPI is enabled it will delete any references to the NAPI struct prior
1058  *  to freeing the q_vector.
1059  **/
1060 static void igb_free_q_vectors(struct igb_adapter *adapter)
1061 {
1062         int v_idx = adapter->num_q_vectors;
1063
1064         adapter->num_tx_queues = 0;
1065         adapter->num_rx_queues = 0;
1066         adapter->num_q_vectors = 0;
1067
1068         while (v_idx--) {
1069                 igb_reset_q_vector(adapter, v_idx);
1070                 igb_free_q_vector(adapter, v_idx);
1071         }
1072 }
1073
1074 /**
1075  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1076  *  @adapter: board private structure to initialize
1077  *
1078  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1079  *  MSI-X interrupts allocated.
1080  */
1081 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1082 {
1083         igb_free_q_vectors(adapter);
1084         igb_reset_interrupt_capability(adapter);
1085 }
1086
1087 /**
1088  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1089  *  @adapter: board private structure to initialize
1090  *  @msix: boolean value of MSIX capability
1091  *
1092  *  Attempt to configure interrupts using the best available
1093  *  capabilities of the hardware and kernel.
1094  **/
1095 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1096 {
1097         int err;
1098         int numvecs, i;
1099
1100         if (!msix)
1101                 goto msi_only;
1102         adapter->flags |= IGB_FLAG_HAS_MSIX;
1103
1104         /* Number of supported queues. */
1105         adapter->num_rx_queues = adapter->rss_queues;
1106         if (adapter->vfs_allocated_count)
1107                 adapter->num_tx_queues = 1;
1108         else
1109                 adapter->num_tx_queues = adapter->rss_queues;
1110
1111         /* start with one vector for every Rx queue */
1112         numvecs = adapter->num_rx_queues;
1113
1114         /* if Tx handler is separate add 1 for every Tx queue */
1115         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1116                 numvecs += adapter->num_tx_queues;
1117
1118         /* store the number of vectors reserved for queues */
1119         adapter->num_q_vectors = numvecs;
1120
1121         /* add 1 vector for link status interrupts */
1122         numvecs++;
1123         for (i = 0; i < numvecs; i++)
1124                 adapter->msix_entries[i].entry = i;
1125
1126         err = pci_enable_msix_range(adapter->pdev,
1127                                     adapter->msix_entries,
1128                                     numvecs,
1129                                     numvecs);
1130         if (err > 0)
1131                 return;
1132
1133         igb_reset_interrupt_capability(adapter);
1134
1135         /* If we can't do MSI-X, try MSI */
1136 msi_only:
1137         adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1138 #ifdef CONFIG_PCI_IOV
1139         /* disable SR-IOV for non MSI-X configurations */
1140         if (adapter->vf_data) {
1141                 struct e1000_hw *hw = &adapter->hw;
1142                 /* disable iov and allow time for transactions to clear */
1143                 pci_disable_sriov(adapter->pdev);
1144                 msleep(500);
1145
1146                 kfree(adapter->vf_mac_list);
1147                 adapter->vf_mac_list = NULL;
1148                 kfree(adapter->vf_data);
1149                 adapter->vf_data = NULL;
1150                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1151                 wrfl();
1152                 msleep(100);
1153                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1154         }
1155 #endif
1156         adapter->vfs_allocated_count = 0;
1157         adapter->rss_queues = 1;
1158         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1159         adapter->num_rx_queues = 1;
1160         adapter->num_tx_queues = 1;
1161         adapter->num_q_vectors = 1;
1162         if (!pci_enable_msi(adapter->pdev))
1163                 adapter->flags |= IGB_FLAG_HAS_MSI;
1164 }
1165
1166 static void igb_add_ring(struct igb_ring *ring,
1167                          struct igb_ring_container *head)
1168 {
1169         head->ring = ring;
1170         head->count++;
1171 }
1172
1173 /**
1174  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1175  *  @adapter: board private structure to initialize
1176  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1177  *  @v_idx: index of vector in adapter struct
1178  *  @txr_count: total number of Tx rings to allocate
1179  *  @txr_idx: index of first Tx ring to allocate
1180  *  @rxr_count: total number of Rx rings to allocate
1181  *  @rxr_idx: index of first Rx ring to allocate
1182  *
1183  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1184  **/
1185 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1186                               int v_count, int v_idx,
1187                               int txr_count, int txr_idx,
1188                               int rxr_count, int rxr_idx)
1189 {
1190         struct igb_q_vector *q_vector;
1191         struct igb_ring *ring;
1192         int ring_count;
1193         size_t size;
1194
1195         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1196         if (txr_count > 1 || rxr_count > 1)
1197                 return -ENOMEM;
1198
1199         ring_count = txr_count + rxr_count;
1200         size = struct_size(q_vector, ring, ring_count);
1201
1202         /* allocate q_vector and rings */
1203         q_vector = adapter->q_vector[v_idx];
1204         if (!q_vector) {
1205                 q_vector = kzalloc(size, GFP_KERNEL);
1206         } else if (size > ksize(q_vector)) {
1207                 kfree_rcu(q_vector, rcu);
1208                 q_vector = kzalloc(size, GFP_KERNEL);
1209         } else {
1210                 memset(q_vector, 0, size);
1211         }
1212         if (!q_vector)
1213                 return -ENOMEM;
1214
1215         /* initialize NAPI */
1216         netif_napi_add(adapter->netdev, &q_vector->napi,
1217                        igb_poll, 64);
1218
1219         /* tie q_vector and adapter together */
1220         adapter->q_vector[v_idx] = q_vector;
1221         q_vector->adapter = adapter;
1222
1223         /* initialize work limits */
1224         q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226         /* initialize ITR configuration */
1227         q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1228         q_vector->itr_val = IGB_START_ITR;
1229
1230         /* initialize pointer to rings */
1231         ring = q_vector->ring;
1232
1233         /* intialize ITR */
1234         if (rxr_count) {
1235                 /* rx or rx/tx vector */
1236                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237                         q_vector->itr_val = adapter->rx_itr_setting;
1238         } else {
1239                 /* tx only vector */
1240                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241                         q_vector->itr_val = adapter->tx_itr_setting;
1242         }
1243
1244         if (txr_count) {
1245                 /* assign generic ring traits */
1246                 ring->dev = &adapter->pdev->dev;
1247                 ring->netdev = adapter->netdev;
1248
1249                 /* configure backlink on ring */
1250                 ring->q_vector = q_vector;
1251
1252                 /* update q_vector Tx values */
1253                 igb_add_ring(ring, &q_vector->tx);
1254
1255                 /* For 82575, context index must be unique per ring. */
1256                 if (adapter->hw.mac.type == e1000_82575)
1257                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259                 /* apply Tx specific ring traits */
1260                 ring->count = adapter->tx_ring_count;
1261                 ring->queue_index = txr_idx;
1262
1263                 ring->cbs_enable = false;
1264                 ring->idleslope = 0;
1265                 ring->sendslope = 0;
1266                 ring->hicredit = 0;
1267                 ring->locredit = 0;
1268
1269                 u64_stats_init(&ring->tx_syncp);
1270                 u64_stats_init(&ring->tx_syncp2);
1271
1272                 /* assign ring to adapter */
1273                 adapter->tx_ring[txr_idx] = ring;
1274
1275                 /* push pointer to next ring */
1276                 ring++;
1277         }
1278
1279         if (rxr_count) {
1280                 /* assign generic ring traits */
1281                 ring->dev = &adapter->pdev->dev;
1282                 ring->netdev = adapter->netdev;
1283
1284                 /* configure backlink on ring */
1285                 ring->q_vector = q_vector;
1286
1287                 /* update q_vector Rx values */
1288                 igb_add_ring(ring, &q_vector->rx);
1289
1290                 /* set flag indicating ring supports SCTP checksum offload */
1291                 if (adapter->hw.mac.type >= e1000_82576)
1292                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1293
1294                 /* On i350, i354, i210, and i211, loopback VLAN packets
1295                  * have the tag byte-swapped.
1296                  */
1297                 if (adapter->hw.mac.type >= e1000_i350)
1298                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1299
1300                 /* apply Rx specific ring traits */
1301                 ring->count = adapter->rx_ring_count;
1302                 ring->queue_index = rxr_idx;
1303
1304                 u64_stats_init(&ring->rx_syncp);
1305
1306                 /* assign ring to adapter */
1307                 adapter->rx_ring[rxr_idx] = ring;
1308         }
1309
1310         return 0;
1311 }
1312
1313
1314 /**
1315  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316  *  @adapter: board private structure to initialize
1317  *
1318  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1319  *  return -ENOMEM.
1320  **/
1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1322 {
1323         int q_vectors = adapter->num_q_vectors;
1324         int rxr_remaining = adapter->num_rx_queues;
1325         int txr_remaining = adapter->num_tx_queues;
1326         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327         int err;
1328
1329         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330                 for (; rxr_remaining; v_idx++) {
1331                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332                                                  0, 0, 1, rxr_idx);
1333
1334                         if (err)
1335                                 goto err_out;
1336
1337                         /* update counts and index */
1338                         rxr_remaining--;
1339                         rxr_idx++;
1340                 }
1341         }
1342
1343         for (; v_idx < q_vectors; v_idx++) {
1344                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1346
1347                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348                                          tqpv, txr_idx, rqpv, rxr_idx);
1349
1350                 if (err)
1351                         goto err_out;
1352
1353                 /* update counts and index */
1354                 rxr_remaining -= rqpv;
1355                 txr_remaining -= tqpv;
1356                 rxr_idx++;
1357                 txr_idx++;
1358         }
1359
1360         return 0;
1361
1362 err_out:
1363         adapter->num_tx_queues = 0;
1364         adapter->num_rx_queues = 0;
1365         adapter->num_q_vectors = 0;
1366
1367         while (v_idx--)
1368                 igb_free_q_vector(adapter, v_idx);
1369
1370         return -ENOMEM;
1371 }
1372
1373 /**
1374  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375  *  @adapter: board private structure to initialize
1376  *  @msix: boolean value of MSIX capability
1377  *
1378  *  This function initializes the interrupts and allocates all of the queues.
1379  **/
1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1381 {
1382         struct pci_dev *pdev = adapter->pdev;
1383         int err;
1384
1385         igb_set_interrupt_capability(adapter, msix);
1386
1387         err = igb_alloc_q_vectors(adapter);
1388         if (err) {
1389                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390                 goto err_alloc_q_vectors;
1391         }
1392
1393         igb_cache_ring_register(adapter);
1394
1395         return 0;
1396
1397 err_alloc_q_vectors:
1398         igb_reset_interrupt_capability(adapter);
1399         return err;
1400 }
1401
1402 /**
1403  *  igb_request_irq - initialize interrupts
1404  *  @adapter: board private structure to initialize
1405  *
1406  *  Attempts to configure interrupts using the best available
1407  *  capabilities of the hardware and kernel.
1408  **/
1409 static int igb_request_irq(struct igb_adapter *adapter)
1410 {
1411         struct net_device *netdev = adapter->netdev;
1412         struct pci_dev *pdev = adapter->pdev;
1413         int err = 0;
1414
1415         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416                 err = igb_request_msix(adapter);
1417                 if (!err)
1418                         goto request_done;
1419                 /* fall back to MSI */
1420                 igb_free_all_tx_resources(adapter);
1421                 igb_free_all_rx_resources(adapter);
1422
1423                 igb_clear_interrupt_scheme(adapter);
1424                 err = igb_init_interrupt_scheme(adapter, false);
1425                 if (err)
1426                         goto request_done;
1427
1428                 igb_setup_all_tx_resources(adapter);
1429                 igb_setup_all_rx_resources(adapter);
1430                 igb_configure(adapter);
1431         }
1432
1433         igb_assign_vector(adapter->q_vector[0], 0);
1434
1435         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1437                                   netdev->name, adapter);
1438                 if (!err)
1439                         goto request_done;
1440
1441                 /* fall back to legacy interrupts */
1442                 igb_reset_interrupt_capability(adapter);
1443                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1444         }
1445
1446         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447                           netdev->name, adapter);
1448
1449         if (err)
1450                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1451                         err);
1452
1453 request_done:
1454         return err;
1455 }
1456
1457 static void igb_free_irq(struct igb_adapter *adapter)
1458 {
1459         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1460                 int vector = 0, i;
1461
1462                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1463
1464                 for (i = 0; i < adapter->num_q_vectors; i++)
1465                         free_irq(adapter->msix_entries[vector++].vector,
1466                                  adapter->q_vector[i]);
1467         } else {
1468                 free_irq(adapter->pdev->irq, adapter);
1469         }
1470 }
1471
1472 /**
1473  *  igb_irq_disable - Mask off interrupt generation on the NIC
1474  *  @adapter: board private structure
1475  **/
1476 static void igb_irq_disable(struct igb_adapter *adapter)
1477 {
1478         struct e1000_hw *hw = &adapter->hw;
1479
1480         /* we need to be careful when disabling interrupts.  The VFs are also
1481          * mapped into these registers and so clearing the bits can cause
1482          * issues on the VF drivers so we only need to clear what we set
1483          */
1484         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485                 u32 regval = rd32(E1000_EIAM);
1486
1487                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489                 regval = rd32(E1000_EIAC);
1490                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1491         }
1492
1493         wr32(E1000_IAM, 0);
1494         wr32(E1000_IMC, ~0);
1495         wrfl();
1496         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1497                 int i;
1498
1499                 for (i = 0; i < adapter->num_q_vectors; i++)
1500                         synchronize_irq(adapter->msix_entries[i].vector);
1501         } else {
1502                 synchronize_irq(adapter->pdev->irq);
1503         }
1504 }
1505
1506 /**
1507  *  igb_irq_enable - Enable default interrupt generation settings
1508  *  @adapter: board private structure
1509  **/
1510 static void igb_irq_enable(struct igb_adapter *adapter)
1511 {
1512         struct e1000_hw *hw = &adapter->hw;
1513
1514         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516                 u32 regval = rd32(E1000_EIAC);
1517
1518                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519                 regval = rd32(E1000_EIAM);
1520                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1522                 if (adapter->vfs_allocated_count) {
1523                         wr32(E1000_MBVFIMR, 0xFF);
1524                         ims |= E1000_IMS_VMMB;
1525                 }
1526                 wr32(E1000_IMS, ims);
1527         } else {
1528                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529                                 E1000_IMS_DRSTA);
1530                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531                                 E1000_IMS_DRSTA);
1532         }
1533 }
1534
1535 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536 {
1537         struct e1000_hw *hw = &adapter->hw;
1538         u16 pf_id = adapter->vfs_allocated_count;
1539         u16 vid = adapter->hw.mng_cookie.vlan_id;
1540         u16 old_vid = adapter->mng_vlan_id;
1541
1542         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1543                 /* add VID to filter table */
1544                 igb_vfta_set(hw, vid, pf_id, true, true);
1545                 adapter->mng_vlan_id = vid;
1546         } else {
1547                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1548         }
1549
1550         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1551             (vid != old_vid) &&
1552             !test_bit(old_vid, adapter->active_vlans)) {
1553                 /* remove VID from filter table */
1554                 igb_vfta_set(hw, vid, pf_id, false, true);
1555         }
1556 }
1557
1558 /**
1559  *  igb_release_hw_control - release control of the h/w to f/w
1560  *  @adapter: address of board private structure
1561  *
1562  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1563  *  For ASF and Pass Through versions of f/w this means that the
1564  *  driver is no longer loaded.
1565  **/
1566 static void igb_release_hw_control(struct igb_adapter *adapter)
1567 {
1568         struct e1000_hw *hw = &adapter->hw;
1569         u32 ctrl_ext;
1570
1571         /* Let firmware take over control of h/w */
1572         ctrl_ext = rd32(E1000_CTRL_EXT);
1573         wr32(E1000_CTRL_EXT,
1574                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1575 }
1576
1577 /**
1578  *  igb_get_hw_control - get control of the h/w from f/w
1579  *  @adapter: address of board private structure
1580  *
1581  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1582  *  For ASF and Pass Through versions of f/w this means that
1583  *  the driver is loaded.
1584  **/
1585 static void igb_get_hw_control(struct igb_adapter *adapter)
1586 {
1587         struct e1000_hw *hw = &adapter->hw;
1588         u32 ctrl_ext;
1589
1590         /* Let firmware know the driver has taken over */
1591         ctrl_ext = rd32(E1000_CTRL_EXT);
1592         wr32(E1000_CTRL_EXT,
1593                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1594 }
1595
1596 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1597 {
1598         struct net_device *netdev = adapter->netdev;
1599         struct e1000_hw *hw = &adapter->hw;
1600
1601         WARN_ON(hw->mac.type != e1000_i210);
1602
1603         if (enable)
1604                 adapter->flags |= IGB_FLAG_FQTSS;
1605         else
1606                 adapter->flags &= ~IGB_FLAG_FQTSS;
1607
1608         if (netif_running(netdev))
1609                 schedule_work(&adapter->reset_task);
1610 }
1611
1612 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1613 {
1614         return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1615 }
1616
1617 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1618                                    enum tx_queue_prio prio)
1619 {
1620         u32 val;
1621
1622         WARN_ON(hw->mac.type != e1000_i210);
1623         WARN_ON(queue < 0 || queue > 4);
1624
1625         val = rd32(E1000_I210_TXDCTL(queue));
1626
1627         if (prio == TX_QUEUE_PRIO_HIGH)
1628                 val |= E1000_TXDCTL_PRIORITY;
1629         else
1630                 val &= ~E1000_TXDCTL_PRIORITY;
1631
1632         wr32(E1000_I210_TXDCTL(queue), val);
1633 }
1634
1635 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1636 {
1637         u32 val;
1638
1639         WARN_ON(hw->mac.type != e1000_i210);
1640         WARN_ON(queue < 0 || queue > 1);
1641
1642         val = rd32(E1000_I210_TQAVCC(queue));
1643
1644         if (mode == QUEUE_MODE_STREAM_RESERVATION)
1645                 val |= E1000_TQAVCC_QUEUEMODE;
1646         else
1647                 val &= ~E1000_TQAVCC_QUEUEMODE;
1648
1649         wr32(E1000_I210_TQAVCC(queue), val);
1650 }
1651
1652 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1653 {
1654         int i;
1655
1656         for (i = 0; i < adapter->num_tx_queues; i++) {
1657                 if (adapter->tx_ring[i]->cbs_enable)
1658                         return true;
1659         }
1660
1661         return false;
1662 }
1663
1664 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1665 {
1666         int i;
1667
1668         for (i = 0; i < adapter->num_tx_queues; i++) {
1669                 if (adapter->tx_ring[i]->launchtime_enable)
1670                         return true;
1671         }
1672
1673         return false;
1674 }
1675
1676 /**
1677  *  igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1678  *  @adapter: pointer to adapter struct
1679  *  @queue: queue number
1680  *
1681  *  Configure CBS and Launchtime for a given hardware queue.
1682  *  Parameters are retrieved from the correct Tx ring, so
1683  *  igb_save_cbs_params() and igb_save_txtime_params() should be used
1684  *  for setting those correctly prior to this function being called.
1685  **/
1686 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1687 {
1688         struct igb_ring *ring = adapter->tx_ring[queue];
1689         struct net_device *netdev = adapter->netdev;
1690         struct e1000_hw *hw = &adapter->hw;
1691         u32 tqavcc, tqavctrl;
1692         u16 value;
1693
1694         WARN_ON(hw->mac.type != e1000_i210);
1695         WARN_ON(queue < 0 || queue > 1);
1696
1697         /* If any of the Qav features is enabled, configure queues as SR and
1698          * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1699          * as SP.
1700          */
1701         if (ring->cbs_enable || ring->launchtime_enable) {
1702                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1703                 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1704         } else {
1705                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1706                 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1707         }
1708
1709         /* If CBS is enabled, set DataTranARB and config its parameters. */
1710         if (ring->cbs_enable || queue == 0) {
1711                 /* i210 does not allow the queue 0 to be in the Strict
1712                  * Priority mode while the Qav mode is enabled, so,
1713                  * instead of disabling strict priority mode, we give
1714                  * queue 0 the maximum of credits possible.
1715                  *
1716                  * See section 8.12.19 of the i210 datasheet, "Note:
1717                  * Queue0 QueueMode must be set to 1b when
1718                  * TransmitMode is set to Qav."
1719                  */
1720                 if (queue == 0 && !ring->cbs_enable) {
1721                         /* max "linkspeed" idleslope in kbps */
1722                         ring->idleslope = 1000000;
1723                         ring->hicredit = ETH_FRAME_LEN;
1724                 }
1725
1726                 /* Always set data transfer arbitration to credit-based
1727                  * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1728                  * the queues.
1729                  */
1730                 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1731                 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1732                 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1733
1734                 /* According to i210 datasheet section 7.2.7.7, we should set
1735                  * the 'idleSlope' field from TQAVCC register following the
1736                  * equation:
1737                  *
1738                  * For 100 Mbps link speed:
1739                  *
1740                  *     value = BW * 0x7735 * 0.2                          (E1)
1741                  *
1742                  * For 1000Mbps link speed:
1743                  *
1744                  *     value = BW * 0x7735 * 2                            (E2)
1745                  *
1746                  * E1 and E2 can be merged into one equation as shown below.
1747                  * Note that 'link-speed' is in Mbps.
1748                  *
1749                  *     value = BW * 0x7735 * 2 * link-speed
1750                  *                           --------------               (E3)
1751                  *                                1000
1752                  *
1753                  * 'BW' is the percentage bandwidth out of full link speed
1754                  * which can be found with the following equation. Note that
1755                  * idleSlope here is the parameter from this function which
1756                  * is in kbps.
1757                  *
1758                  *     BW =     idleSlope
1759                  *          -----------------                             (E4)
1760                  *          link-speed * 1000
1761                  *
1762                  * That said, we can come up with a generic equation to
1763                  * calculate the value we should set it TQAVCC register by
1764                  * replacing 'BW' in E3 by E4. The resulting equation is:
1765                  *
1766                  * value =     idleSlope     * 0x7735 * 2 * link-speed
1767                  *         -----------------            --------------    (E5)
1768                  *         link-speed * 1000                 1000
1769                  *
1770                  * 'link-speed' is present in both sides of the fraction so
1771                  * it is canceled out. The final equation is the following:
1772                  *
1773                  *     value = idleSlope * 61034
1774                  *             -----------------                          (E6)
1775                  *                  1000000
1776                  *
1777                  * NOTE: For i210, given the above, we can see that idleslope
1778                  *       is represented in 16.38431 kbps units by the value at
1779                  *       the TQAVCC register (1Gbps / 61034), which reduces
1780                  *       the granularity for idleslope increments.
1781                  *       For instance, if you want to configure a 2576kbps
1782                  *       idleslope, the value to be written on the register
1783                  *       would have to be 157.23. If rounded down, you end
1784                  *       up with less bandwidth available than originally
1785                  *       required (~2572 kbps). If rounded up, you end up
1786                  *       with a higher bandwidth (~2589 kbps). Below the
1787                  *       approach we take is to always round up the
1788                  *       calculated value, so the resulting bandwidth might
1789                  *       be slightly higher for some configurations.
1790                  */
1791                 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1792
1793                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1794                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1795                 tqavcc |= value;
1796                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1797
1798                 wr32(E1000_I210_TQAVHC(queue),
1799                      0x80000000 + ring->hicredit * 0x7735);
1800         } else {
1801
1802                 /* Set idleSlope to zero. */
1803                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1804                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1805                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1806
1807                 /* Set hiCredit to zero. */
1808                 wr32(E1000_I210_TQAVHC(queue), 0);
1809
1810                 /* If CBS is not enabled for any queues anymore, then return to
1811                  * the default state of Data Transmission Arbitration on
1812                  * TQAVCTRL.
1813                  */
1814                 if (!is_any_cbs_enabled(adapter)) {
1815                         tqavctrl = rd32(E1000_I210_TQAVCTRL);
1816                         tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1817                         wr32(E1000_I210_TQAVCTRL, tqavctrl);
1818                 }
1819         }
1820
1821         /* If LaunchTime is enabled, set DataTranTIM. */
1822         if (ring->launchtime_enable) {
1823                 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1824                  * for any of the SR queues, and configure fetchtime delta.
1825                  * XXX NOTE:
1826                  *     - LaunchTime will be enabled for all SR queues.
1827                  *     - A fixed offset can be added relative to the launch
1828                  *       time of all packets if configured at reg LAUNCH_OS0.
1829                  *       We are keeping it as 0 for now (default value).
1830                  */
1831                 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1832                 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1833                        E1000_TQAVCTRL_FETCHTIME_DELTA;
1834                 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1835         } else {
1836                 /* If Launchtime is not enabled for any SR queues anymore,
1837                  * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1838                  * effectively disabling Launchtime.
1839                  */
1840                 if (!is_any_txtime_enabled(adapter)) {
1841                         tqavctrl = rd32(E1000_I210_TQAVCTRL);
1842                         tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1843                         tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1844                         wr32(E1000_I210_TQAVCTRL, tqavctrl);
1845                 }
1846         }
1847
1848         /* XXX: In i210 controller the sendSlope and loCredit parameters from
1849          * CBS are not configurable by software so we don't do any 'controller
1850          * configuration' in respect to these parameters.
1851          */
1852
1853         netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1854                    ring->cbs_enable ? "enabled" : "disabled",
1855                    ring->launchtime_enable ? "enabled" : "disabled",
1856                    queue,
1857                    ring->idleslope, ring->sendslope,
1858                    ring->hicredit, ring->locredit);
1859 }
1860
1861 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1862                                   bool enable)
1863 {
1864         struct igb_ring *ring;
1865
1866         if (queue < 0 || queue > adapter->num_tx_queues)
1867                 return -EINVAL;
1868
1869         ring = adapter->tx_ring[queue];
1870         ring->launchtime_enable = enable;
1871
1872         return 0;
1873 }
1874
1875 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1876                                bool enable, int idleslope, int sendslope,
1877                                int hicredit, int locredit)
1878 {
1879         struct igb_ring *ring;
1880
1881         if (queue < 0 || queue > adapter->num_tx_queues)
1882                 return -EINVAL;
1883
1884         ring = adapter->tx_ring[queue];
1885
1886         ring->cbs_enable = enable;
1887         ring->idleslope = idleslope;
1888         ring->sendslope = sendslope;
1889         ring->hicredit = hicredit;
1890         ring->locredit = locredit;
1891
1892         return 0;
1893 }
1894
1895 /**
1896  *  igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1897  *  @adapter: pointer to adapter struct
1898  *
1899  *  Configure TQAVCTRL register switching the controller's Tx mode
1900  *  if FQTSS mode is enabled or disabled. Additionally, will issue
1901  *  a call to igb_config_tx_modes() per queue so any previously saved
1902  *  Tx parameters are applied.
1903  **/
1904 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1905 {
1906         struct net_device *netdev = adapter->netdev;
1907         struct e1000_hw *hw = &adapter->hw;
1908         u32 val;
1909
1910         /* Only i210 controller supports changing the transmission mode. */
1911         if (hw->mac.type != e1000_i210)
1912                 return;
1913
1914         if (is_fqtss_enabled(adapter)) {
1915                 int i, max_queue;
1916
1917                 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1918                  * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1919                  * so SP queues wait for SR ones.
1920                  */
1921                 val = rd32(E1000_I210_TQAVCTRL);
1922                 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1923                 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1924                 wr32(E1000_I210_TQAVCTRL, val);
1925
1926                 /* Configure Tx and Rx packet buffers sizes as described in
1927                  * i210 datasheet section 7.2.7.7.
1928                  */
1929                 val = rd32(E1000_TXPBS);
1930                 val &= ~I210_TXPBSIZE_MASK;
1931                 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB |
1932                         I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB;
1933                 wr32(E1000_TXPBS, val);
1934
1935                 val = rd32(E1000_RXPBS);
1936                 val &= ~I210_RXPBSIZE_MASK;
1937                 val |= I210_RXPBSIZE_PB_30KB;
1938                 wr32(E1000_RXPBS, val);
1939
1940                 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1941                  * register should not exceed the buffer size programmed in
1942                  * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1943                  * so according to the datasheet we should set MAX_TPKT_SIZE to
1944                  * 4kB / 64.
1945                  *
1946                  * However, when we do so, no frame from queue 2 and 3 are
1947                  * transmitted.  It seems the MAX_TPKT_SIZE should not be great
1948                  * or _equal_ to the buffer size programmed in TXPBS. For this
1949                  * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1950                  */
1951                 val = (4096 - 1) / 64;
1952                 wr32(E1000_I210_DTXMXPKTSZ, val);
1953
1954                 /* Since FQTSS mode is enabled, apply any CBS configuration
1955                  * previously set. If no previous CBS configuration has been
1956                  * done, then the initial configuration is applied, which means
1957                  * CBS is disabled.
1958                  */
1959                 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1960                             adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1961
1962                 for (i = 0; i < max_queue; i++) {
1963                         igb_config_tx_modes(adapter, i);
1964                 }
1965         } else {
1966                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1967                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1968                 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1969
1970                 val = rd32(E1000_I210_TQAVCTRL);
1971                 /* According to Section 8.12.21, the other flags we've set when
1972                  * enabling FQTSS are not relevant when disabling FQTSS so we
1973                  * don't set they here.
1974                  */
1975                 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1976                 wr32(E1000_I210_TQAVCTRL, val);
1977         }
1978
1979         netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1980                    "enabled" : "disabled");
1981 }
1982
1983 /**
1984  *  igb_configure - configure the hardware for RX and TX
1985  *  @adapter: private board structure
1986  **/
1987 static void igb_configure(struct igb_adapter *adapter)
1988 {
1989         struct net_device *netdev = adapter->netdev;
1990         int i;
1991
1992         igb_get_hw_control(adapter);
1993         igb_set_rx_mode(netdev);
1994         igb_setup_tx_mode(adapter);
1995
1996         igb_restore_vlan(adapter);
1997
1998         igb_setup_tctl(adapter);
1999         igb_setup_mrqc(adapter);
2000         igb_setup_rctl(adapter);
2001
2002         igb_nfc_filter_restore(adapter);
2003         igb_configure_tx(adapter);
2004         igb_configure_rx(adapter);
2005
2006         igb_rx_fifo_flush_82575(&adapter->hw);
2007
2008         /* call igb_desc_unused which always leaves
2009          * at least 1 descriptor unused to make sure
2010          * next_to_use != next_to_clean
2011          */
2012         for (i = 0; i < adapter->num_rx_queues; i++) {
2013                 struct igb_ring *ring = adapter->rx_ring[i];
2014                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2015         }
2016 }
2017
2018 /**
2019  *  igb_power_up_link - Power up the phy/serdes link
2020  *  @adapter: address of board private structure
2021  **/
2022 void igb_power_up_link(struct igb_adapter *adapter)
2023 {
2024         igb_reset_phy(&adapter->hw);
2025
2026         if (adapter->hw.phy.media_type == e1000_media_type_copper)
2027                 igb_power_up_phy_copper(&adapter->hw);
2028         else
2029                 igb_power_up_serdes_link_82575(&adapter->hw);
2030
2031         igb_setup_link(&adapter->hw);
2032 }
2033
2034 /**
2035  *  igb_power_down_link - Power down the phy/serdes link
2036  *  @adapter: address of board private structure
2037  */
2038 static void igb_power_down_link(struct igb_adapter *adapter)
2039 {
2040         if (adapter->hw.phy.media_type == e1000_media_type_copper)
2041                 igb_power_down_phy_copper_82575(&adapter->hw);
2042         else
2043                 igb_shutdown_serdes_link_82575(&adapter->hw);
2044 }
2045
2046 /**
2047  * Detect and switch function for Media Auto Sense
2048  * @adapter: address of the board private structure
2049  **/
2050 static void igb_check_swap_media(struct igb_adapter *adapter)
2051 {
2052         struct e1000_hw *hw = &adapter->hw;
2053         u32 ctrl_ext, connsw;
2054         bool swap_now = false;
2055
2056         ctrl_ext = rd32(E1000_CTRL_EXT);
2057         connsw = rd32(E1000_CONNSW);
2058
2059         /* need to live swap if current media is copper and we have fiber/serdes
2060          * to go to.
2061          */
2062
2063         if ((hw->phy.media_type == e1000_media_type_copper) &&
2064             (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2065                 swap_now = true;
2066         } else if (!(connsw & E1000_CONNSW_SERDESD)) {
2067                 /* copper signal takes time to appear */
2068                 if (adapter->copper_tries < 4) {
2069                         adapter->copper_tries++;
2070                         connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2071                         wr32(E1000_CONNSW, connsw);
2072                         return;
2073                 } else {
2074                         adapter->copper_tries = 0;
2075                         if ((connsw & E1000_CONNSW_PHYSD) &&
2076                             (!(connsw & E1000_CONNSW_PHY_PDN))) {
2077                                 swap_now = true;
2078                                 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2079                                 wr32(E1000_CONNSW, connsw);
2080                         }
2081                 }
2082         }
2083
2084         if (!swap_now)
2085                 return;
2086
2087         switch (hw->phy.media_type) {
2088         case e1000_media_type_copper:
2089                 netdev_info(adapter->netdev,
2090                         "MAS: changing media to fiber/serdes\n");
2091                 ctrl_ext |=
2092                         E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2093                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2094                 adapter->copper_tries = 0;
2095                 break;
2096         case e1000_media_type_internal_serdes:
2097         case e1000_media_type_fiber:
2098                 netdev_info(adapter->netdev,
2099                         "MAS: changing media to copper\n");
2100                 ctrl_ext &=
2101                         ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2102                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2103                 break;
2104         default:
2105                 /* shouldn't get here during regular operation */
2106                 netdev_err(adapter->netdev,
2107                         "AMS: Invalid media type found, returning\n");
2108                 break;
2109         }
2110         wr32(E1000_CTRL_EXT, ctrl_ext);
2111 }
2112
2113 /**
2114  *  igb_up - Open the interface and prepare it to handle traffic
2115  *  @adapter: board private structure
2116  **/
2117 int igb_up(struct igb_adapter *adapter)
2118 {
2119         struct e1000_hw *hw = &adapter->hw;
2120         int i;
2121
2122         /* hardware has been reset, we need to reload some things */
2123         igb_configure(adapter);
2124
2125         clear_bit(__IGB_DOWN, &adapter->state);
2126
2127         for (i = 0; i < adapter->num_q_vectors; i++)
2128                 napi_enable(&(adapter->q_vector[i]->napi));
2129
2130         if (adapter->flags & IGB_FLAG_HAS_MSIX)
2131                 igb_configure_msix(adapter);
2132         else
2133                 igb_assign_vector(adapter->q_vector[0], 0);
2134
2135         /* Clear any pending interrupts. */
2136         rd32(E1000_TSICR);
2137         rd32(E1000_ICR);
2138         igb_irq_enable(adapter);
2139
2140         /* notify VFs that reset has been completed */
2141         if (adapter->vfs_allocated_count) {
2142                 u32 reg_data = rd32(E1000_CTRL_EXT);
2143
2144                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2145                 wr32(E1000_CTRL_EXT, reg_data);
2146         }
2147
2148         netif_tx_start_all_queues(adapter->netdev);
2149
2150         /* start the watchdog. */
2151         hw->mac.get_link_status = 1;
2152         schedule_work(&adapter->watchdog_task);
2153
2154         if ((adapter->flags & IGB_FLAG_EEE) &&
2155             (!hw->dev_spec._82575.eee_disable))
2156                 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2157
2158         return 0;
2159 }
2160
2161 void igb_down(struct igb_adapter *adapter)
2162 {
2163         struct net_device *netdev = adapter->netdev;
2164         struct e1000_hw *hw = &adapter->hw;
2165         u32 tctl, rctl;
2166         int i;
2167
2168         /* signal that we're down so the interrupt handler does not
2169          * reschedule our watchdog timer
2170          */
2171         set_bit(__IGB_DOWN, &adapter->state);
2172
2173         /* disable receives in the hardware */
2174         rctl = rd32(E1000_RCTL);
2175         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2176         /* flush and sleep below */
2177
2178         igb_nfc_filter_exit(adapter);
2179
2180         netif_carrier_off(netdev);
2181         netif_tx_stop_all_queues(netdev);
2182
2183         /* disable transmits in the hardware */
2184         tctl = rd32(E1000_TCTL);
2185         tctl &= ~E1000_TCTL_EN;
2186         wr32(E1000_TCTL, tctl);
2187         /* flush both disables and wait for them to finish */
2188         wrfl();
2189         usleep_range(10000, 11000);
2190
2191         igb_irq_disable(adapter);
2192
2193         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2194
2195         for (i = 0; i < adapter->num_q_vectors; i++) {
2196                 if (adapter->q_vector[i]) {
2197                         napi_synchronize(&adapter->q_vector[i]->napi);
2198                         napi_disable(&adapter->q_vector[i]->napi);
2199                 }
2200         }
2201
2202         del_timer_sync(&adapter->watchdog_timer);
2203         del_timer_sync(&adapter->phy_info_timer);
2204
2205         /* record the stats before reset*/
2206         spin_lock(&adapter->stats64_lock);
2207         igb_update_stats(adapter);
2208         spin_unlock(&adapter->stats64_lock);
2209
2210         adapter->link_speed = 0;
2211         adapter->link_duplex = 0;
2212
2213         if (!pci_channel_offline(adapter->pdev))
2214                 igb_reset(adapter);
2215
2216         /* clear VLAN promisc flag so VFTA will be updated if necessary */
2217         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2218
2219         igb_clean_all_tx_rings(adapter);
2220         igb_clean_all_rx_rings(adapter);
2221 #ifdef CONFIG_IGB_DCA
2222
2223         /* since we reset the hardware DCA settings were cleared */
2224         igb_setup_dca(adapter);
2225 #endif
2226 }
2227
2228 void igb_reinit_locked(struct igb_adapter *adapter)
2229 {
2230         WARN_ON(in_interrupt());
2231         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2232                 usleep_range(1000, 2000);
2233         igb_down(adapter);
2234         igb_up(adapter);
2235         clear_bit(__IGB_RESETTING, &adapter->state);
2236 }
2237
2238 /** igb_enable_mas - Media Autosense re-enable after swap
2239  *
2240  * @adapter: adapter struct
2241  **/
2242 static void igb_enable_mas(struct igb_adapter *adapter)
2243 {
2244         struct e1000_hw *hw = &adapter->hw;
2245         u32 connsw = rd32(E1000_CONNSW);
2246
2247         /* configure for SerDes media detect */
2248         if ((hw->phy.media_type == e1000_media_type_copper) &&
2249             (!(connsw & E1000_CONNSW_SERDESD))) {
2250                 connsw |= E1000_CONNSW_ENRGSRC;
2251                 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2252                 wr32(E1000_CONNSW, connsw);
2253                 wrfl();
2254         }
2255 }
2256
2257 void igb_reset(struct igb_adapter *adapter)
2258 {
2259         struct pci_dev *pdev = adapter->pdev;
2260         struct e1000_hw *hw = &adapter->hw;
2261         struct e1000_mac_info *mac = &hw->mac;
2262         struct e1000_fc_info *fc = &hw->fc;
2263         u32 pba, hwm;
2264
2265         /* Repartition Pba for greater than 9k mtu
2266          * To take effect CTRL.RST is required.
2267          */
2268         switch (mac->type) {
2269         case e1000_i350:
2270         case e1000_i354:
2271         case e1000_82580:
2272                 pba = rd32(E1000_RXPBS);
2273                 pba = igb_rxpbs_adjust_82580(pba);
2274                 break;
2275         case e1000_82576:
2276                 pba = rd32(E1000_RXPBS);
2277                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2278                 break;
2279         case e1000_82575:
2280         case e1000_i210:
2281         case e1000_i211:
2282         default:
2283                 pba = E1000_PBA_34K;
2284                 break;
2285         }
2286
2287         if (mac->type == e1000_82575) {
2288                 u32 min_rx_space, min_tx_space, needed_tx_space;
2289
2290                 /* write Rx PBA so that hardware can report correct Tx PBA */
2291                 wr32(E1000_PBA, pba);
2292
2293                 /* To maintain wire speed transmits, the Tx FIFO should be
2294                  * large enough to accommodate two full transmit packets,
2295                  * rounded up to the next 1KB and expressed in KB.  Likewise,
2296                  * the Rx FIFO should be large enough to accommodate at least
2297                  * one full receive packet and is similarly rounded up and
2298                  * expressed in KB.
2299                  */
2300                 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2301
2302                 /* The Tx FIFO also stores 16 bytes of information about the Tx
2303                  * but don't include Ethernet FCS because hardware appends it.
2304                  * We only need to round down to the nearest 512 byte block
2305                  * count since the value we care about is 2 frames, not 1.
2306                  */
2307                 min_tx_space = adapter->max_frame_size;
2308                 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2309                 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2310
2311                 /* upper 16 bits has Tx packet buffer allocation size in KB */
2312                 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2313
2314                 /* If current Tx allocation is less than the min Tx FIFO size,
2315                  * and the min Tx FIFO size is less than the current Rx FIFO
2316                  * allocation, take space away from current Rx allocation.
2317                  */
2318                 if (needed_tx_space < pba) {
2319                         pba -= needed_tx_space;
2320
2321                         /* if short on Rx space, Rx wins and must trump Tx
2322                          * adjustment
2323                          */
2324                         if (pba < min_rx_space)
2325                                 pba = min_rx_space;
2326                 }
2327
2328                 /* adjust PBA for jumbo frames */
2329                 wr32(E1000_PBA, pba);
2330         }
2331
2332         /* flow control settings
2333          * The high water mark must be low enough to fit one full frame
2334          * after transmitting the pause frame.  As such we must have enough
2335          * space to allow for us to complete our current transmit and then
2336          * receive the frame that is in progress from the link partner.
2337          * Set it to:
2338          * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2339          */
2340         hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2341
2342         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
2343         fc->low_water = fc->high_water - 16;
2344         fc->pause_time = 0xFFFF;
2345         fc->send_xon = 1;
2346         fc->current_mode = fc->requested_mode;
2347
2348         /* disable receive for all VFs and wait one second */
2349         if (adapter->vfs_allocated_count) {
2350                 int i;
2351
2352                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2353                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2354
2355                 /* ping all the active vfs to let them know we are going down */
2356                 igb_ping_all_vfs(adapter);
2357
2358                 /* disable transmits and receives */
2359                 wr32(E1000_VFRE, 0);
2360                 wr32(E1000_VFTE, 0);
2361         }
2362
2363         /* Allow time for pending master requests to run */
2364         hw->mac.ops.reset_hw(hw);
2365         wr32(E1000_WUC, 0);
2366
2367         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2368                 /* need to resetup here after media swap */
2369                 adapter->ei.get_invariants(hw);
2370                 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2371         }
2372         if ((mac->type == e1000_82575) &&
2373             (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2374                 igb_enable_mas(adapter);
2375         }
2376         if (hw->mac.ops.init_hw(hw))
2377                 dev_err(&pdev->dev, "Hardware Error\n");
2378
2379         /* RAR registers were cleared during init_hw, clear mac table */
2380         igb_flush_mac_table(adapter);
2381         __dev_uc_unsync(adapter->netdev, NULL);
2382
2383         /* Recover default RAR entry */
2384         igb_set_default_mac_filter(adapter);
2385
2386         /* Flow control settings reset on hardware reset, so guarantee flow
2387          * control is off when forcing speed.
2388          */
2389         if (!hw->mac.autoneg)
2390                 igb_force_mac_fc(hw);
2391
2392         igb_init_dmac(adapter, pba);
2393 #ifdef CONFIG_IGB_HWMON
2394         /* Re-initialize the thermal sensor on i350 devices. */
2395         if (!test_bit(__IGB_DOWN, &adapter->state)) {
2396                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2397                         /* If present, re-initialize the external thermal sensor
2398                          * interface.
2399                          */
2400                         if (adapter->ets)
2401                                 mac->ops.init_thermal_sensor_thresh(hw);
2402                 }
2403         }
2404 #endif
2405         /* Re-establish EEE setting */
2406         if (hw->phy.media_type == e1000_media_type_copper) {
2407                 switch (mac->type) {
2408                 case e1000_i350:
2409                 case e1000_i210:
2410                 case e1000_i211:
2411                         igb_set_eee_i350(hw, true, true);
2412                         break;
2413                 case e1000_i354:
2414                         igb_set_eee_i354(hw, true, true);
2415                         break;
2416                 default:
2417                         break;
2418                 }
2419         }
2420         if (!netif_running(adapter->netdev))
2421                 igb_power_down_link(adapter);
2422
2423         igb_update_mng_vlan(adapter);
2424
2425         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2426         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2427
2428         /* Re-enable PTP, where applicable. */
2429         if (adapter->ptp_flags & IGB_PTP_ENABLED)
2430                 igb_ptp_reset(adapter);
2431
2432         igb_get_phy_info(hw);
2433 }
2434
2435 static netdev_features_t igb_fix_features(struct net_device *netdev,
2436         netdev_features_t features)
2437 {
2438         /* Since there is no support for separate Rx/Tx vlan accel
2439          * enable/disable make sure Tx flag is always in same state as Rx.
2440          */
2441         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2442                 features |= NETIF_F_HW_VLAN_CTAG_TX;
2443         else
2444                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2445
2446         return features;
2447 }
2448
2449 static int igb_set_features(struct net_device *netdev,
2450         netdev_features_t features)
2451 {
2452         netdev_features_t changed = netdev->features ^ features;
2453         struct igb_adapter *adapter = netdev_priv(netdev);
2454
2455         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2456                 igb_vlan_mode(netdev, features);
2457
2458         if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2459                 return 0;
2460
2461         if (!(features & NETIF_F_NTUPLE)) {
2462                 struct hlist_node *node2;
2463                 struct igb_nfc_filter *rule;
2464
2465                 spin_lock(&adapter->nfc_lock);
2466                 hlist_for_each_entry_safe(rule, node2,
2467                                           &adapter->nfc_filter_list, nfc_node) {
2468                         igb_erase_filter(adapter, rule);
2469                         hlist_del(&rule->nfc_node);
2470                         kfree(rule);
2471                 }
2472                 spin_unlock(&adapter->nfc_lock);
2473                 adapter->nfc_filter_count = 0;
2474         }
2475
2476         netdev->features = features;
2477
2478         if (netif_running(netdev))
2479                 igb_reinit_locked(adapter);
2480         else
2481                 igb_reset(adapter);
2482
2483         return 0;
2484 }
2485
2486 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2487                            struct net_device *dev,
2488                            const unsigned char *addr, u16 vid,
2489                            u16 flags,
2490                            struct netlink_ext_ack *extack)
2491 {
2492         /* guarantee we can provide a unique filter for the unicast address */
2493         if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2494                 struct igb_adapter *adapter = netdev_priv(dev);
2495                 int vfn = adapter->vfs_allocated_count;
2496
2497                 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2498                         return -ENOMEM;
2499         }
2500
2501         return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2502 }
2503
2504 #define IGB_MAX_MAC_HDR_LEN     127
2505 #define IGB_MAX_NETWORK_HDR_LEN 511
2506
2507 static netdev_features_t
2508 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2509                    netdev_features_t features)
2510 {
2511         unsigned int network_hdr_len, mac_hdr_len;
2512
2513         /* Make certain the headers can be described by a context descriptor */
2514         mac_hdr_len = skb_network_header(skb) - skb->data;
2515         if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2516                 return features & ~(NETIF_F_HW_CSUM |
2517                                     NETIF_F_SCTP_CRC |
2518                                     NETIF_F_HW_VLAN_CTAG_TX |
2519                                     NETIF_F_TSO |
2520                                     NETIF_F_TSO6);
2521
2522         network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2523         if (unlikely(network_hdr_len >  IGB_MAX_NETWORK_HDR_LEN))
2524                 return features & ~(NETIF_F_HW_CSUM |
2525                                     NETIF_F_SCTP_CRC |
2526                                     NETIF_F_TSO |
2527                                     NETIF_F_TSO6);
2528
2529         /* We can only support IPV4 TSO in tunnels if we can mangle the
2530          * inner IP ID field, so strip TSO if MANGLEID is not supported.
2531          */
2532         if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2533                 features &= ~NETIF_F_TSO;
2534
2535         return features;
2536 }
2537
2538 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2539 {
2540         if (!is_fqtss_enabled(adapter)) {
2541                 enable_fqtss(adapter, true);
2542                 return;
2543         }
2544
2545         igb_config_tx_modes(adapter, queue);
2546
2547         if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2548                 enable_fqtss(adapter, false);
2549 }
2550
2551 static int igb_offload_cbs(struct igb_adapter *adapter,
2552                            struct tc_cbs_qopt_offload *qopt)
2553 {
2554         struct e1000_hw *hw = &adapter->hw;
2555         int err;
2556
2557         /* CBS offloading is only supported by i210 controller. */
2558         if (hw->mac.type != e1000_i210)
2559                 return -EOPNOTSUPP;
2560
2561         /* CBS offloading is only supported by queue 0 and queue 1. */
2562         if (qopt->queue < 0 || qopt->queue > 1)
2563                 return -EINVAL;
2564
2565         err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2566                                   qopt->idleslope, qopt->sendslope,
2567                                   qopt->hicredit, qopt->locredit);
2568         if (err)
2569                 return err;
2570
2571         igb_offload_apply(adapter, qopt->queue);
2572
2573         return 0;
2574 }
2575
2576 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2577 #define VLAN_PRIO_FULL_MASK (0x07)
2578
2579 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2580                                 struct tc_cls_flower_offload *f,
2581                                 int traffic_class,
2582                                 struct igb_nfc_filter *input)
2583 {
2584         struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
2585         struct flow_dissector *dissector = rule->match.dissector;
2586         struct netlink_ext_ack *extack = f->common.extack;
2587
2588         if (dissector->used_keys &
2589             ~(BIT(FLOW_DISSECTOR_KEY_BASIC) |
2590               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2591               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2592               BIT(FLOW_DISSECTOR_KEY_VLAN))) {
2593                 NL_SET_ERR_MSG_MOD(extack,
2594                                    "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2595                 return -EOPNOTSUPP;
2596         }
2597
2598         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2599                 struct flow_match_eth_addrs match;
2600
2601                 flow_rule_match_eth_addrs(rule, &match);
2602                 if (!is_zero_ether_addr(match.mask->dst)) {
2603                         if (!is_broadcast_ether_addr(match.mask->dst)) {
2604                                 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2605                                 return -EINVAL;
2606                         }
2607
2608                         input->filter.match_flags |=
2609                                 IGB_FILTER_FLAG_DST_MAC_ADDR;
2610                         ether_addr_copy(input->filter.dst_addr, match.key->dst);
2611                 }
2612
2613                 if (!is_zero_ether_addr(match.mask->src)) {
2614                         if (!is_broadcast_ether_addr(match.mask->src)) {
2615                                 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2616                                 return -EINVAL;
2617                         }
2618
2619                         input->filter.match_flags |=
2620                                 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2621                         ether_addr_copy(input->filter.src_addr, match.key->src);
2622                 }
2623         }
2624
2625         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2626                 struct flow_match_basic match;
2627
2628                 flow_rule_match_basic(rule, &match);
2629                 if (match.mask->n_proto) {
2630                         if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2631                                 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2632                                 return -EINVAL;
2633                         }
2634
2635                         input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2636                         input->filter.etype = match.key->n_proto;
2637                 }
2638         }
2639
2640         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2641                 struct flow_match_vlan match;
2642
2643                 flow_rule_match_vlan(rule, &match);
2644                 if (match.mask->vlan_priority) {
2645                         if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2646                                 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2647                                 return -EINVAL;
2648                         }
2649
2650                         input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2651                         input->filter.vlan_tci = match.key->vlan_priority;
2652                 }
2653         }
2654
2655         input->action = traffic_class;
2656         input->cookie = f->cookie;
2657
2658         return 0;
2659 }
2660
2661 static int igb_configure_clsflower(struct igb_adapter *adapter,
2662                                    struct tc_cls_flower_offload *cls_flower)
2663 {
2664         struct netlink_ext_ack *extack = cls_flower->common.extack;
2665         struct igb_nfc_filter *filter, *f;
2666         int err, tc;
2667
2668         tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2669         if (tc < 0) {
2670                 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2671                 return -EINVAL;
2672         }
2673
2674         filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2675         if (!filter)
2676                 return -ENOMEM;
2677
2678         err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2679         if (err < 0)
2680                 goto err_parse;
2681
2682         spin_lock(&adapter->nfc_lock);
2683
2684         hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2685                 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2686                         err = -EEXIST;
2687                         NL_SET_ERR_MSG_MOD(extack,
2688                                            "This filter is already set in ethtool");
2689                         goto err_locked;
2690                 }
2691         }
2692
2693         hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2694                 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2695                         err = -EEXIST;
2696                         NL_SET_ERR_MSG_MOD(extack,
2697                                            "This filter is already set in cls_flower");
2698                         goto err_locked;
2699                 }
2700         }
2701
2702         err = igb_add_filter(adapter, filter);
2703         if (err < 0) {
2704                 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2705                 goto err_locked;
2706         }
2707
2708         hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2709
2710         spin_unlock(&adapter->nfc_lock);
2711
2712         return 0;
2713
2714 err_locked:
2715         spin_unlock(&adapter->nfc_lock);
2716
2717 err_parse:
2718         kfree(filter);
2719
2720         return err;
2721 }
2722
2723 static int igb_delete_clsflower(struct igb_adapter *adapter,
2724                                 struct tc_cls_flower_offload *cls_flower)
2725 {
2726         struct igb_nfc_filter *filter;
2727         int err;
2728
2729         spin_lock(&adapter->nfc_lock);
2730
2731         hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2732                 if (filter->cookie == cls_flower->cookie)
2733                         break;
2734
2735         if (!filter) {
2736                 err = -ENOENT;
2737                 goto out;
2738         }
2739
2740         err = igb_erase_filter(adapter, filter);
2741         if (err < 0)
2742                 goto out;
2743
2744         hlist_del(&filter->nfc_node);
2745         kfree(filter);
2746
2747 out:
2748         spin_unlock(&adapter->nfc_lock);
2749
2750         return err;
2751 }
2752
2753 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2754                                    struct tc_cls_flower_offload *cls_flower)
2755 {
2756         switch (cls_flower->command) {
2757         case TC_CLSFLOWER_REPLACE:
2758                 return igb_configure_clsflower(adapter, cls_flower);
2759         case TC_CLSFLOWER_DESTROY:
2760                 return igb_delete_clsflower(adapter, cls_flower);
2761         case TC_CLSFLOWER_STATS:
2762                 return -EOPNOTSUPP;
2763         default:
2764                 return -EOPNOTSUPP;
2765         }
2766 }
2767
2768 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2769                                  void *cb_priv)
2770 {
2771         struct igb_adapter *adapter = cb_priv;
2772
2773         if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2774                 return -EOPNOTSUPP;
2775
2776         switch (type) {
2777         case TC_SETUP_CLSFLOWER:
2778                 return igb_setup_tc_cls_flower(adapter, type_data);
2779
2780         default:
2781                 return -EOPNOTSUPP;
2782         }
2783 }
2784
2785 static int igb_setup_tc_block(struct igb_adapter *adapter,
2786                               struct tc_block_offload *f)
2787 {
2788         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2789                 return -EOPNOTSUPP;
2790
2791         switch (f->command) {
2792         case TC_BLOCK_BIND:
2793                 return tcf_block_cb_register(f->block, igb_setup_tc_block_cb,
2794                                              adapter, adapter, f->extack);
2795         case TC_BLOCK_UNBIND:
2796                 tcf_block_cb_unregister(f->block, igb_setup_tc_block_cb,
2797                                         adapter);
2798                 return 0;
2799         default:
2800                 return -EOPNOTSUPP;
2801         }
2802 }
2803
2804 static int igb_offload_txtime(struct igb_adapter *adapter,
2805                               struct tc_etf_qopt_offload *qopt)
2806 {
2807         struct e1000_hw *hw = &adapter->hw;
2808         int err;
2809
2810         /* Launchtime offloading is only supported by i210 controller. */
2811         if (hw->mac.type != e1000_i210)
2812                 return -EOPNOTSUPP;
2813
2814         /* Launchtime offloading is only supported by queues 0 and 1. */
2815         if (qopt->queue < 0 || qopt->queue > 1)
2816                 return -EINVAL;
2817
2818         err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2819         if (err)
2820                 return err;
2821
2822         igb_offload_apply(adapter, qopt->queue);
2823
2824         return 0;
2825 }
2826
2827 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2828                         void *type_data)
2829 {
2830         struct igb_adapter *adapter = netdev_priv(dev);
2831
2832         switch (type) {
2833         case TC_SETUP_QDISC_CBS:
2834                 return igb_offload_cbs(adapter, type_data);
2835         case TC_SETUP_BLOCK:
2836                 return igb_setup_tc_block(adapter, type_data);
2837         case TC_SETUP_QDISC_ETF:
2838                 return igb_offload_txtime(adapter, type_data);
2839
2840         default:
2841                 return -EOPNOTSUPP;
2842         }
2843 }
2844
2845 static const struct net_device_ops igb_netdev_ops = {
2846         .ndo_open               = igb_open,
2847         .ndo_stop               = igb_close,
2848         .ndo_start_xmit         = igb_xmit_frame,
2849         .ndo_get_stats64        = igb_get_stats64,
2850         .ndo_set_rx_mode        = igb_set_rx_mode,
2851         .ndo_set_mac_address    = igb_set_mac,
2852         .ndo_change_mtu         = igb_change_mtu,
2853         .ndo_do_ioctl           = igb_ioctl,
2854         .ndo_tx_timeout         = igb_tx_timeout,
2855         .ndo_validate_addr      = eth_validate_addr,
2856         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
2857         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
2858         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
2859         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
2860         .ndo_set_vf_rate        = igb_ndo_set_vf_bw,
2861         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
2862         .ndo_set_vf_trust       = igb_ndo_set_vf_trust,
2863         .ndo_get_vf_config      = igb_ndo_get_vf_config,
2864         .ndo_fix_features       = igb_fix_features,
2865         .ndo_set_features       = igb_set_features,
2866         .ndo_fdb_add            = igb_ndo_fdb_add,
2867         .ndo_features_check     = igb_features_check,
2868         .ndo_setup_tc           = igb_setup_tc,
2869 };
2870
2871 /**
2872  * igb_set_fw_version - Configure version string for ethtool
2873  * @adapter: adapter struct
2874  **/
2875 void igb_set_fw_version(struct igb_adapter *adapter)
2876 {
2877         struct e1000_hw *hw = &adapter->hw;
2878         struct e1000_fw_version fw;
2879
2880         igb_get_fw_version(hw, &fw);
2881
2882         switch (hw->mac.type) {
2883         case e1000_i210:
2884         case e1000_i211:
2885                 if (!(igb_get_flash_presence_i210(hw))) {
2886                         snprintf(adapter->fw_version,
2887                                  sizeof(adapter->fw_version),
2888                                  "%2d.%2d-%d",
2889                                  fw.invm_major, fw.invm_minor,
2890                                  fw.invm_img_type);
2891                         break;
2892                 }
2893                 /* fall through */
2894         default:
2895                 /* if option is rom valid, display its version too */
2896                 if (fw.or_valid) {
2897                         snprintf(adapter->fw_version,
2898                                  sizeof(adapter->fw_version),
2899                                  "%d.%d, 0x%08x, %d.%d.%d",
2900                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2901                                  fw.or_major, fw.or_build, fw.or_patch);
2902                 /* no option rom */
2903                 } else if (fw.etrack_id != 0X0000) {
2904                         snprintf(adapter->fw_version,
2905                             sizeof(adapter->fw_version),
2906                             "%d.%d, 0x%08x",
2907                             fw.eep_major, fw.eep_minor, fw.etrack_id);
2908                 } else {
2909                 snprintf(adapter->fw_version,
2910                     sizeof(adapter->fw_version),
2911                     "%d.%d.%d",
2912                     fw.eep_major, fw.eep_minor, fw.eep_build);
2913                 }
2914                 break;
2915         }
2916 }
2917
2918 /**
2919  * igb_init_mas - init Media Autosense feature if enabled in the NVM
2920  *
2921  * @adapter: adapter struct
2922  **/
2923 static void igb_init_mas(struct igb_adapter *adapter)
2924 {
2925         struct e1000_hw *hw = &adapter->hw;
2926         u16 eeprom_data;
2927
2928         hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2929         switch (hw->bus.func) {
2930         case E1000_FUNC_0:
2931                 if (eeprom_data & IGB_MAS_ENABLE_0) {
2932                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2933                         netdev_info(adapter->netdev,
2934                                 "MAS: Enabling Media Autosense for port %d\n",
2935                                 hw->bus.func);
2936                 }
2937                 break;
2938         case E1000_FUNC_1:
2939                 if (eeprom_data & IGB_MAS_ENABLE_1) {
2940                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2941                         netdev_info(adapter->netdev,
2942                                 "MAS: Enabling Media Autosense for port %d\n",
2943                                 hw->bus.func);
2944                 }
2945                 break;
2946         case E1000_FUNC_2:
2947                 if (eeprom_data & IGB_MAS_ENABLE_2) {
2948                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2949                         netdev_info(adapter->netdev,
2950                                 "MAS: Enabling Media Autosense for port %d\n",
2951                                 hw->bus.func);
2952                 }
2953                 break;
2954         case E1000_FUNC_3:
2955                 if (eeprom_data & IGB_MAS_ENABLE_3) {
2956                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2957                         netdev_info(adapter->netdev,
2958                                 "MAS: Enabling Media Autosense for port %d\n",
2959                                 hw->bus.func);
2960                 }
2961                 break;
2962         default:
2963                 /* Shouldn't get here */
2964                 netdev_err(adapter->netdev,
2965                         "MAS: Invalid port configuration, returning\n");
2966                 break;
2967         }
2968 }
2969
2970 /**
2971  *  igb_init_i2c - Init I2C interface
2972  *  @adapter: pointer to adapter structure
2973  **/
2974 static s32 igb_init_i2c(struct igb_adapter *adapter)
2975 {
2976         s32 status = 0;
2977
2978         /* I2C interface supported on i350 devices */
2979         if (adapter->hw.mac.type != e1000_i350)
2980                 return 0;
2981
2982         /* Initialize the i2c bus which is controlled by the registers.
2983          * This bus will use the i2c_algo_bit structue that implements
2984          * the protocol through toggling of the 4 bits in the register.
2985          */
2986         adapter->i2c_adap.owner = THIS_MODULE;
2987         adapter->i2c_algo = igb_i2c_algo;
2988         adapter->i2c_algo.data = adapter;
2989         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2990         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2991         strlcpy(adapter->i2c_adap.name, "igb BB",
2992                 sizeof(adapter->i2c_adap.name));
2993         status = i2c_bit_add_bus(&adapter->i2c_adap);
2994         return status;
2995 }
2996
2997 /**
2998  *  igb_probe - Device Initialization Routine
2999  *  @pdev: PCI device information struct
3000  *  @ent: entry in igb_pci_tbl
3001  *
3002  *  Returns 0 on success, negative on failure
3003  *
3004  *  igb_probe initializes an adapter identified by a pci_dev structure.
3005  *  The OS initialization, configuring of the adapter private structure,
3006  *  and a hardware reset occur.
3007  **/
3008 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3009 {
3010         struct net_device *netdev;
3011         struct igb_adapter *adapter;
3012         struct e1000_hw *hw;
3013         u16 eeprom_data = 0;
3014         s32 ret_val;
3015         static int global_quad_port_a; /* global quad port a indication */
3016         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3017         int err, pci_using_dac;
3018         u8 part_str[E1000_PBANUM_LENGTH];
3019
3020         /* Catch broken hardware that put the wrong VF device ID in
3021          * the PCIe SR-IOV capability.
3022          */
3023         if (pdev->is_virtfn) {
3024                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
3025                         pci_name(pdev), pdev->vendor, pdev->device);
3026                 return -EINVAL;
3027         }
3028
3029         err = pci_enable_device_mem(pdev);
3030         if (err)
3031                 return err;
3032
3033         pci_using_dac = 0;
3034         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3035         if (!err) {
3036                 pci_using_dac = 1;
3037         } else {
3038                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3039                 if (err) {
3040                         dev_err(&pdev->dev,
3041                                 "No usable DMA configuration, aborting\n");
3042                         goto err_dma;
3043                 }
3044         }
3045
3046         err = pci_request_mem_regions(pdev, igb_driver_name);
3047         if (err)
3048                 goto err_pci_reg;
3049
3050         pci_enable_pcie_error_reporting(pdev);
3051
3052         pci_set_master(pdev);
3053         pci_save_state(pdev);
3054
3055         err = -ENOMEM;
3056         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3057                                    IGB_MAX_TX_QUEUES);
3058         if (!netdev)
3059                 goto err_alloc_etherdev;
3060
3061         SET_NETDEV_DEV(netdev, &pdev->dev);
3062
3063         pci_set_drvdata(pdev, netdev);
3064         adapter = netdev_priv(netdev);
3065         adapter->netdev = netdev;
3066         adapter->pdev = pdev;
3067         hw = &adapter->hw;
3068         hw->back = adapter;
3069         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3070
3071         err = -EIO;
3072         adapter->io_addr = pci_iomap(pdev, 0, 0);
3073         if (!adapter->io_addr)
3074                 goto err_ioremap;
3075         /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3076         hw->hw_addr = adapter->io_addr;
3077
3078         netdev->netdev_ops = &igb_netdev_ops;
3079         igb_set_ethtool_ops(netdev);
3080         netdev->watchdog_timeo = 5 * HZ;
3081
3082         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3083
3084         netdev->mem_start = pci_resource_start(pdev, 0);
3085         netdev->mem_end = pci_resource_end(pdev, 0);
3086
3087         /* PCI config space info */
3088         hw->vendor_id = pdev->vendor;
3089         hw->device_id = pdev->device;
3090         hw->revision_id = pdev->revision;
3091         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3092         hw->subsystem_device_id = pdev->subsystem_device;
3093
3094         /* Copy the default MAC, PHY and NVM function pointers */
3095         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3096         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3097         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3098         /* Initialize skew-specific constants */
3099         err = ei->get_invariants(hw);
3100         if (err)
3101                 goto err_sw_init;
3102
3103         /* setup the private structure */
3104         err = igb_sw_init(adapter);
3105         if (err)
3106                 goto err_sw_init;
3107
3108         igb_get_bus_info_pcie(hw);
3109
3110         hw->phy.autoneg_wait_to_complete = false;
3111
3112         /* Copper options */
3113         if (hw->phy.media_type == e1000_media_type_copper) {
3114                 hw->phy.mdix = AUTO_ALL_MODES;
3115                 hw->phy.disable_polarity_correction = false;
3116                 hw->phy.ms_type = e1000_ms_hw_default;
3117         }
3118
3119         if (igb_check_reset_block(hw))
3120                 dev_info(&pdev->dev,
3121                         "PHY reset is blocked due to SOL/IDER session.\n");
3122
3123         /* features is initialized to 0 in allocation, it might have bits
3124          * set by igb_sw_init so we should use an or instead of an
3125          * assignment.
3126          */
3127         netdev->features |= NETIF_F_SG |
3128                             NETIF_F_TSO |
3129                             NETIF_F_TSO6 |
3130                             NETIF_F_RXHASH |
3131                             NETIF_F_RXCSUM |
3132                             NETIF_F_HW_CSUM;
3133
3134         if (hw->mac.type >= e1000_82576)
3135                 netdev->features |= NETIF_F_SCTP_CRC;
3136
3137         if (hw->mac.type >= e1000_i350)
3138                 netdev->features |= NETIF_F_HW_TC;
3139
3140 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3141                                   NETIF_F_GSO_GRE_CSUM | \
3142                                   NETIF_F_GSO_IPXIP4 | \
3143                                   NETIF_F_GSO_IPXIP6 | \
3144                                   NETIF_F_GSO_UDP_TUNNEL | \
3145                                   NETIF_F_GSO_UDP_TUNNEL_CSUM)
3146
3147         netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3148         netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3149
3150         /* copy netdev features into list of user selectable features */
3151         netdev->hw_features |= netdev->features |
3152                                NETIF_F_HW_VLAN_CTAG_RX |
3153                                NETIF_F_HW_VLAN_CTAG_TX |
3154                                NETIF_F_RXALL;
3155
3156         if (hw->mac.type >= e1000_i350)
3157                 netdev->hw_features |= NETIF_F_NTUPLE;
3158
3159         if (pci_using_dac)
3160                 netdev->features |= NETIF_F_HIGHDMA;
3161
3162         netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3163         netdev->mpls_features |= NETIF_F_HW_CSUM;
3164         netdev->hw_enc_features |= netdev->vlan_features;
3165
3166         /* set this bit last since it cannot be part of vlan_features */
3167         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3168                             NETIF_F_HW_VLAN_CTAG_RX |
3169                             NETIF_F_HW_VLAN_CTAG_TX;
3170
3171         netdev->priv_flags |= IFF_SUPP_NOFCS;
3172
3173         netdev->priv_flags |= IFF_UNICAST_FLT;
3174
3175         /* MTU range: 68 - 9216 */
3176         netdev->min_mtu = ETH_MIN_MTU;