5a6d0919533d6e0e619927abd753c5d07ed95dac
[muen/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_rx.c
1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33
34 #include <linux/bpf.h>
35 #include <linux/bpf_trace.h>
36 #include <linux/mlx4/cq.h>
37 #include <linux/slab.h>
38 #include <linux/mlx4/qp.h>
39 #include <linux/skbuff.h>
40 #include <linux/rculist.h>
41 #include <linux/if_ether.h>
42 #include <linux/if_vlan.h>
43 #include <linux/vmalloc.h>
44 #include <linux/irq.h>
45
46 #if IS_ENABLED(CONFIG_IPV6)
47 #include <net/ip6_checksum.h>
48 #endif
49
50 #include "mlx4_en.h"
51
52 static int mlx4_alloc_page(struct mlx4_en_priv *priv,
53                            struct mlx4_en_rx_alloc *frag,
54                            gfp_t gfp)
55 {
56         struct page *page;
57         dma_addr_t dma;
58
59         page = alloc_page(gfp);
60         if (unlikely(!page))
61                 return -ENOMEM;
62         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir);
63         if (unlikely(dma_mapping_error(priv->ddev, dma))) {
64                 __free_page(page);
65                 return -ENOMEM;
66         }
67         frag->page = page;
68         frag->dma = dma;
69         frag->page_offset = priv->rx_headroom;
70         return 0;
71 }
72
73 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
74                                struct mlx4_en_rx_ring *ring,
75                                struct mlx4_en_rx_desc *rx_desc,
76                                struct mlx4_en_rx_alloc *frags,
77                                gfp_t gfp)
78 {
79         int i;
80
81         for (i = 0; i < priv->num_frags; i++, frags++) {
82                 if (!frags->page) {
83                         if (mlx4_alloc_page(priv, frags, gfp))
84                                 return -ENOMEM;
85                         ring->rx_alloc_pages++;
86                 }
87                 rx_desc->data[i].addr = cpu_to_be64(frags->dma +
88                                                     frags->page_offset);
89         }
90         return 0;
91 }
92
93 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv,
94                               struct mlx4_en_rx_alloc *frag)
95 {
96         if (frag->page) {
97                 dma_unmap_page(priv->ddev, frag->dma,
98                                PAGE_SIZE, priv->dma_dir);
99                 __free_page(frag->page);
100         }
101         /* We need to clear all fields, otherwise a change of priv->log_rx_info
102          * could lead to see garbage later in frag->page.
103          */
104         memset(frag, 0, sizeof(*frag));
105 }
106
107 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv,
108                                  struct mlx4_en_rx_ring *ring, int index)
109 {
110         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
111         int possible_frags;
112         int i;
113
114         /* Set size and memtype fields */
115         for (i = 0; i < priv->num_frags; i++) {
116                 rx_desc->data[i].byte_count =
117                         cpu_to_be32(priv->frag_info[i].frag_size);
118                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
119         }
120
121         /* If the number of used fragments does not fill up the ring stride,
122          * remaining (unused) fragments must be padded with null address/size
123          * and a special memory key */
124         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
125         for (i = priv->num_frags; i < possible_frags; i++) {
126                 rx_desc->data[i].byte_count = 0;
127                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
128                 rx_desc->data[i].addr = 0;
129         }
130 }
131
132 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
133                                    struct mlx4_en_rx_ring *ring, int index,
134                                    gfp_t gfp)
135 {
136         struct mlx4_en_rx_desc *rx_desc = ring->buf +
137                 (index << ring->log_stride);
138         struct mlx4_en_rx_alloc *frags = ring->rx_info +
139                                         (index << priv->log_rx_info);
140         if (likely(ring->page_cache.index > 0)) {
141                 /* XDP uses a single page per frame */
142                 if (!frags->page) {
143                         ring->page_cache.index--;
144                         frags->page = ring->page_cache.buf[ring->page_cache.index].page;
145                         frags->dma  = ring->page_cache.buf[ring->page_cache.index].dma;
146                 }
147                 frags->page_offset = XDP_PACKET_HEADROOM;
148                 rx_desc->data[0].addr = cpu_to_be64(frags->dma +
149                                                     XDP_PACKET_HEADROOM);
150                 return 0;
151         }
152
153         return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp);
154 }
155
156 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring)
157 {
158         return ring->prod == ring->cons;
159 }
160
161 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
162 {
163         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
164 }
165
166 /* slow path */
167 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv,
168                                  struct mlx4_en_rx_ring *ring,
169                                  int index)
170 {
171         struct mlx4_en_rx_alloc *frags;
172         int nr;
173
174         frags = ring->rx_info + (index << priv->log_rx_info);
175         for (nr = 0; nr < priv->num_frags; nr++) {
176                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
177                 mlx4_en_free_frag(priv, frags + nr);
178         }
179 }
180
181 /* Function not in fast-path */
182 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
183 {
184         struct mlx4_en_rx_ring *ring;
185         int ring_ind;
186         int buf_ind;
187         int new_size;
188
189         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
190                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
191                         ring = priv->rx_ring[ring_ind];
192
193                         if (mlx4_en_prepare_rx_desc(priv, ring,
194                                                     ring->actual_size,
195                                                     GFP_KERNEL)) {
196                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
197                                         en_err(priv, "Failed to allocate enough rx buffers\n");
198                                         return -ENOMEM;
199                                 } else {
200                                         new_size = rounddown_pow_of_two(ring->actual_size);
201                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
202                                                 ring->actual_size, new_size);
203                                         goto reduce_rings;
204                                 }
205                         }
206                         ring->actual_size++;
207                         ring->prod++;
208                 }
209         }
210         return 0;
211
212 reduce_rings:
213         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
214                 ring = priv->rx_ring[ring_ind];
215                 while (ring->actual_size > new_size) {
216                         ring->actual_size--;
217                         ring->prod--;
218                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
219                 }
220         }
221
222         return 0;
223 }
224
225 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
226                                 struct mlx4_en_rx_ring *ring)
227 {
228         int index;
229
230         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
231                ring->cons, ring->prod);
232
233         /* Unmap and free Rx buffers */
234         for (index = 0; index < ring->size; index++) {
235                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
236                 mlx4_en_free_rx_desc(priv, ring, index);
237         }
238         ring->cons = 0;
239         ring->prod = 0;
240 }
241
242 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
243 {
244         int i;
245         int num_of_eqs;
246         int num_rx_rings;
247         struct mlx4_dev *dev = mdev->dev;
248
249         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
250                 num_of_eqs = max_t(int, MIN_RX_RINGS,
251                                    min_t(int,
252                                          mlx4_get_eqs_per_port(mdev->dev, i),
253                                          DEF_RX_RINGS));
254
255                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
256                         min_t(int, num_of_eqs, num_online_cpus());
257                 mdev->profile.prof[i].rx_ring_num =
258                         rounddown_pow_of_two(num_rx_rings);
259         }
260 }
261
262 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
263                            struct mlx4_en_rx_ring **pring,
264                            u32 size, u16 stride, int node, int queue_index)
265 {
266         struct mlx4_en_dev *mdev = priv->mdev;
267         struct mlx4_en_rx_ring *ring;
268         int err = -ENOMEM;
269         int tmp;
270
271         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
272         if (!ring) {
273                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
274                 if (!ring) {
275                         en_err(priv, "Failed to allocate RX ring structure\n");
276                         return -ENOMEM;
277                 }
278         }
279
280         ring->prod = 0;
281         ring->cons = 0;
282         ring->size = size;
283         ring->size_mask = size - 1;
284         ring->stride = stride;
285         ring->log_stride = ffs(ring->stride) - 1;
286         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
287
288         if (xdp_rxq_info_reg(&ring->xdp_rxq, priv->dev, queue_index) < 0)
289                 goto err_ring;
290
291         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
292                                         sizeof(struct mlx4_en_rx_alloc));
293         ring->rx_info = kvzalloc_node(tmp, GFP_KERNEL, node);
294         if (!ring->rx_info) {
295                 err = -ENOMEM;
296                 goto err_xdp_info;
297         }
298
299         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
300                  ring->rx_info, tmp);
301
302         /* Allocate HW buffers on provided NUMA node */
303         set_dev_node(&mdev->dev->persist->pdev->dev, node);
304         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
305         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
306         if (err)
307                 goto err_info;
308
309         ring->buf = ring->wqres.buf.direct.buf;
310
311         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
312
313         *pring = ring;
314         return 0;
315
316 err_info:
317         kvfree(ring->rx_info);
318         ring->rx_info = NULL;
319 err_xdp_info:
320         xdp_rxq_info_unreg(&ring->xdp_rxq);
321 err_ring:
322         kfree(ring);
323         *pring = NULL;
324
325         return err;
326 }
327
328 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
329 {
330         struct mlx4_en_rx_ring *ring;
331         int i;
332         int ring_ind;
333         int err;
334         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
335                                         DS_SIZE * priv->num_frags);
336
337         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
338                 ring = priv->rx_ring[ring_ind];
339
340                 ring->prod = 0;
341                 ring->cons = 0;
342                 ring->actual_size = 0;
343                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
344
345                 ring->stride = stride;
346                 if (ring->stride <= TXBB_SIZE) {
347                         /* Stamp first unused send wqe */
348                         __be32 *ptr = (__be32 *)ring->buf;
349                         __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
350                         *ptr = stamp;
351                         /* Move pointer to start of rx section */
352                         ring->buf += TXBB_SIZE;
353                 }
354
355                 ring->log_stride = ffs(ring->stride) - 1;
356                 ring->buf_size = ring->size * ring->stride;
357
358                 memset(ring->buf, 0, ring->buf_size);
359                 mlx4_en_update_rx_prod_db(ring);
360
361                 /* Initialize all descriptors */
362                 for (i = 0; i < ring->size; i++)
363                         mlx4_en_init_rx_desc(priv, ring, i);
364         }
365         err = mlx4_en_fill_rx_buffers(priv);
366         if (err)
367                 goto err_buffers;
368
369         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
370                 ring = priv->rx_ring[ring_ind];
371
372                 ring->size_mask = ring->actual_size - 1;
373                 mlx4_en_update_rx_prod_db(ring);
374         }
375
376         return 0;
377
378 err_buffers:
379         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
380                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
381
382         ring_ind = priv->rx_ring_num - 1;
383         while (ring_ind >= 0) {
384                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
385                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
386                 ring_ind--;
387         }
388         return err;
389 }
390
391 /* We recover from out of memory by scheduling our napi poll
392  * function (mlx4_en_process_cq), which tries to allocate
393  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
394  */
395 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
396 {
397         int ring;
398
399         if (!priv->port_up)
400                 return;
401
402         for (ring = 0; ring < priv->rx_ring_num; ring++) {
403                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
404                         local_bh_disable();
405                         napi_reschedule(&priv->rx_cq[ring]->napi);
406                         local_bh_enable();
407                 }
408         }
409 }
410
411 /* When the rx ring is running in page-per-packet mode, a released frame can go
412  * directly into a small cache, to avoid unmapping or touching the page
413  * allocator. In bpf prog performance scenarios, buffers are either forwarded
414  * or dropped, never converted to skbs, so every page can come directly from
415  * this cache when it is sized to be a multiple of the napi budget.
416  */
417 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
418                         struct mlx4_en_rx_alloc *frame)
419 {
420         struct mlx4_en_page_cache *cache = &ring->page_cache;
421
422         if (cache->index >= MLX4_EN_CACHE_SIZE)
423                 return false;
424
425         cache->buf[cache->index].page = frame->page;
426         cache->buf[cache->index].dma = frame->dma;
427         cache->index++;
428         return true;
429 }
430
431 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
432                              struct mlx4_en_rx_ring **pring,
433                              u32 size, u16 stride)
434 {
435         struct mlx4_en_dev *mdev = priv->mdev;
436         struct mlx4_en_rx_ring *ring = *pring;
437         struct bpf_prog *old_prog;
438
439         old_prog = rcu_dereference_protected(
440                                         ring->xdp_prog,
441                                         lockdep_is_held(&mdev->state_lock));
442         if (old_prog)
443                 bpf_prog_put(old_prog);
444         xdp_rxq_info_unreg(&ring->xdp_rxq);
445         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
446         kvfree(ring->rx_info);
447         ring->rx_info = NULL;
448         kfree(ring);
449         *pring = NULL;
450 }
451
452 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
453                                 struct mlx4_en_rx_ring *ring)
454 {
455         int i;
456
457         for (i = 0; i < ring->page_cache.index; i++) {
458                 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma,
459                                PAGE_SIZE, priv->dma_dir);
460                 put_page(ring->page_cache.buf[i].page);
461         }
462         ring->page_cache.index = 0;
463         mlx4_en_free_rx_buf(priv, ring);
464         if (ring->stride <= TXBB_SIZE)
465                 ring->buf -= TXBB_SIZE;
466 }
467
468
469 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
470                                     struct mlx4_en_rx_alloc *frags,
471                                     struct sk_buff *skb,
472                                     int length)
473 {
474         const struct mlx4_en_frag_info *frag_info = priv->frag_info;
475         unsigned int truesize = 0;
476         bool release = true;
477         int nr, frag_size;
478         struct page *page;
479         dma_addr_t dma;
480
481         /* Collect used fragments while replacing them in the HW descriptors */
482         for (nr = 0;; frags++) {
483                 frag_size = min_t(int, length, frag_info->frag_size);
484
485                 page = frags->page;
486                 if (unlikely(!page))
487                         goto fail;
488
489                 dma = frags->dma;
490                 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset,
491                                               frag_size, priv->dma_dir);
492
493                 __skb_fill_page_desc(skb, nr, page, frags->page_offset,
494                                      frag_size);
495
496                 truesize += frag_info->frag_stride;
497                 if (frag_info->frag_stride == PAGE_SIZE / 2) {
498                         frags->page_offset ^= PAGE_SIZE / 2;
499                         release = page_count(page) != 1 ||
500                                   page_is_pfmemalloc(page) ||
501                                   page_to_nid(page) != numa_mem_id();
502                 } else if (!priv->rx_headroom) {
503                         /* rx_headroom for non XDP setup is always 0.
504                          * When XDP is set, the above condition will
505                          * guarantee page is always released.
506                          */
507                         u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES);
508
509                         frags->page_offset += sz_align;
510                         release = frags->page_offset + frag_info->frag_size > PAGE_SIZE;
511                 }
512                 if (release) {
513                         dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir);
514                         frags->page = NULL;
515                 } else {
516                         page_ref_inc(page);
517                 }
518
519                 nr++;
520                 length -= frag_size;
521                 if (!length)
522                         break;
523                 frag_info++;
524         }
525         skb->truesize += truesize;
526         return nr;
527
528 fail:
529         while (nr > 0) {
530                 nr--;
531                 __skb_frag_unref(skb_shinfo(skb)->frags + nr);
532         }
533         return 0;
534 }
535
536 static void validate_loopback(struct mlx4_en_priv *priv, void *va)
537 {
538         const unsigned char *data = va + ETH_HLEN;
539         int i;
540
541         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) {
542                 if (data[i] != (unsigned char)i)
543                         return;
544         }
545         /* Loopback found */
546         priv->loopback_ok = 1;
547 }
548
549 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
550                                       struct mlx4_en_rx_ring *ring)
551 {
552         u32 missing = ring->actual_size - (ring->prod - ring->cons);
553
554         /* Try to batch allocations, but not too much. */
555         if (missing < 8)
556                 return;
557         do {
558                 if (mlx4_en_prepare_rx_desc(priv, ring,
559                                             ring->prod & ring->size_mask,
560                                             GFP_ATOMIC | __GFP_MEMALLOC))
561                         break;
562                 ring->prod++;
563         } while (likely(--missing));
564
565         mlx4_en_update_rx_prod_db(ring);
566 }
567
568 /* When hardware doesn't strip the vlan, we need to calculate the checksum
569  * over it and add it to the hardware's checksum calculation
570  */
571 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
572                                          struct vlan_hdr *vlanh)
573 {
574         return csum_add(hw_checksum, *(__wsum *)vlanh);
575 }
576
577 /* Although the stack expects checksum which doesn't include the pseudo
578  * header, the HW adds it. To address that, we are subtracting the pseudo
579  * header checksum from the checksum value provided by the HW.
580  */
581 static int get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
582                                struct iphdr *iph)
583 {
584         __u16 length_for_csum = 0;
585         __wsum csum_pseudo_header = 0;
586         __u8 ipproto = iph->protocol;
587
588         if (unlikely(ipproto == IPPROTO_SCTP))
589                 return -1;
590
591         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
592         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
593                                                 length_for_csum, ipproto, 0);
594         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
595         return 0;
596 }
597
598 #if IS_ENABLED(CONFIG_IPV6)
599 /* In IPv6 packets, hw_checksum lacks 6 bytes from IPv6 header:
600  * 4 first bytes : priority, version, flow_lbl
601  * and 2 additional bytes : nexthdr, hop_limit.
602  */
603 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
604                                struct ipv6hdr *ipv6h)
605 {
606         __u8 nexthdr = ipv6h->nexthdr;
607         __wsum temp;
608
609         if (unlikely(nexthdr == IPPROTO_FRAGMENT ||
610                      nexthdr == IPPROTO_HOPOPTS ||
611                      nexthdr == IPPROTO_SCTP))
612                 return -1;
613
614         /* priority, version, flow_lbl */
615         temp = csum_add(hw_checksum, *(__wsum *)ipv6h);
616         /* nexthdr and hop_limit */
617         skb->csum = csum_add(temp, (__force __wsum)*(__be16 *)&ipv6h->nexthdr);
618         return 0;
619 }
620 #endif
621
622 /* We reach this function only after checking that any of
623  * the (IPv4 | IPv6) bits are set in cqe->status.
624  */
625 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
626                       netdev_features_t dev_features)
627 {
628         __wsum hw_checksum = 0;
629
630         void *hdr = (u8 *)va + sizeof(struct ethhdr);
631
632         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
633
634         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
635             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
636                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
637                 hdr += sizeof(struct vlan_hdr);
638         }
639
640 #if IS_ENABLED(CONFIG_IPV6)
641         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
642                 return get_fixed_ipv6_csum(hw_checksum, skb, hdr);
643 #endif
644         return get_fixed_ipv4_csum(hw_checksum, skb, hdr);
645 }
646
647 #if IS_ENABLED(CONFIG_IPV6)
648 #define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4 | MLX4_CQE_STATUS_IPV6)
649 #else
650 #define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4)
651 #endif
652
653 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
654 {
655         struct mlx4_en_priv *priv = netdev_priv(dev);
656         int factor = priv->cqe_factor;
657         struct mlx4_en_rx_ring *ring;
658         struct bpf_prog *xdp_prog;
659         int cq_ring = cq->ring;
660         bool doorbell_pending;
661         struct mlx4_cqe *cqe;
662         struct xdp_buff xdp;
663         int polled = 0;
664         int index;
665
666         if (unlikely(!priv->port_up || budget <= 0))
667                 return 0;
668
669         ring = priv->rx_ring[cq_ring];
670
671         /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
672         rcu_read_lock();
673         xdp_prog = rcu_dereference(ring->xdp_prog);
674         xdp.rxq = &ring->xdp_rxq;
675         doorbell_pending = 0;
676
677         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
678          * descriptor offset can be deduced from the CQE index instead of
679          * reading 'cqe->index' */
680         index = cq->mcq.cons_index & ring->size_mask;
681         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
682
683         /* Process all completed CQEs */
684         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
685                     cq->mcq.cons_index & cq->size)) {
686                 struct mlx4_en_rx_alloc *frags;
687                 enum pkt_hash_types hash_type;
688                 struct sk_buff *skb;
689                 unsigned int length;
690                 int ip_summed;
691                 void *va;
692                 int nr;
693
694                 frags = ring->rx_info + (index << priv->log_rx_info);
695                 va = page_address(frags[0].page) + frags[0].page_offset;
696                 prefetchw(va);
697                 /*
698                  * make sure we read the CQE after we read the ownership bit
699                  */
700                 dma_rmb();
701
702                 /* Drop packet on bad receive or bad checksum */
703                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
704                                                 MLX4_CQE_OPCODE_ERROR)) {
705                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
706                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
707                                ((struct mlx4_err_cqe *)cqe)->syndrome);
708                         goto next;
709                 }
710                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
711                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
712                         goto next;
713                 }
714
715                 /* Check if we need to drop the packet if SRIOV is not enabled
716                  * and not performing the selftest or flb disabled
717                  */
718                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
719                         const struct ethhdr *ethh = va;
720                         dma_addr_t dma;
721                         /* Get pointer to first fragment since we haven't
722                          * skb yet and cast it to ethhdr struct
723                          */
724                         dma = frags[0].dma + frags[0].page_offset;
725                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
726                                                 DMA_FROM_DEVICE);
727
728                         if (is_multicast_ether_addr(ethh->h_dest)) {
729                                 struct mlx4_mac_entry *entry;
730                                 struct hlist_head *bucket;
731                                 unsigned int mac_hash;
732
733                                 /* Drop the packet, since HW loopback-ed it */
734                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
735                                 bucket = &priv->mac_hash[mac_hash];
736                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
737                                         if (ether_addr_equal_64bits(entry->mac,
738                                                                     ethh->h_source))
739                                                 goto next;
740                                 }
741                         }
742                 }
743
744                 if (unlikely(priv->validate_loopback)) {
745                         validate_loopback(priv, va);
746                         goto next;
747                 }
748
749                 /*
750                  * Packet is OK - process it.
751                  */
752                 length = be32_to_cpu(cqe->byte_cnt);
753                 length -= ring->fcs_del;
754
755                 /* A bpf program gets first chance to drop the packet. It may
756                  * read bytes but not past the end of the frag.
757                  */
758                 if (xdp_prog) {
759                         dma_addr_t dma;
760                         void *orig_data;
761                         u32 act;
762
763                         dma = frags[0].dma + frags[0].page_offset;
764                         dma_sync_single_for_cpu(priv->ddev, dma,
765                                                 priv->frag_info[0].frag_size,
766                                                 DMA_FROM_DEVICE);
767
768                         xdp.data_hard_start = va - frags[0].page_offset;
769                         xdp.data = va;
770                         xdp_set_data_meta_invalid(&xdp);
771                         xdp.data_end = xdp.data + length;
772                         orig_data = xdp.data;
773
774                         act = bpf_prog_run_xdp(xdp_prog, &xdp);
775
776                         length = xdp.data_end - xdp.data;
777                         if (xdp.data != orig_data) {
778                                 frags[0].page_offset = xdp.data -
779                                         xdp.data_hard_start;
780                                 va = xdp.data;
781                         }
782
783                         switch (act) {
784                         case XDP_PASS:
785                                 break;
786                         case XDP_TX:
787                                 if (likely(!mlx4_en_xmit_frame(ring, frags, priv,
788                                                         length, cq_ring,
789                                                         &doorbell_pending))) {
790                                         frags[0].page = NULL;
791                                         goto next;
792                                 }
793                                 trace_xdp_exception(dev, xdp_prog, act);
794                                 goto xdp_drop_no_cnt; /* Drop on xmit failure */
795                         default:
796                                 bpf_warn_invalid_xdp_action(act);
797                                 /* fall through */
798                         case XDP_ABORTED:
799                                 trace_xdp_exception(dev, xdp_prog, act);
800                                 /* fall through */
801                         case XDP_DROP:
802                                 ring->xdp_drop++;
803 xdp_drop_no_cnt:
804                                 goto next;
805                         }
806                 }
807
808                 ring->bytes += length;
809                 ring->packets++;
810
811                 skb = napi_get_frags(&cq->napi);
812                 if (unlikely(!skb))
813                         goto next;
814
815                 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) {
816                         u64 timestamp = mlx4_en_get_cqe_ts(cqe);
817
818                         mlx4_en_fill_hwtstamps(priv->mdev, skb_hwtstamps(skb),
819                                                timestamp);
820                 }
821                 skb_record_rx_queue(skb, cq_ring);
822
823                 if (likely(dev->features & NETIF_F_RXCSUM)) {
824                         if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
825                                                        MLX4_CQE_STATUS_UDP)) &&
826                             (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
827                             cqe->checksum == cpu_to_be16(0xffff)) {
828                                 bool l2_tunnel;
829
830                                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
831                                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
832                                 ip_summed = CHECKSUM_UNNECESSARY;
833                                 hash_type = PKT_HASH_TYPE_L4;
834                                 if (l2_tunnel)
835                                         skb->csum_level = 1;
836                                 ring->csum_ok++;
837                         } else {
838                                 if (!(priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
839                                       (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IP_ANY))))
840                                         goto csum_none;
841                                 if (check_csum(cqe, skb, va, dev->features))
842                                         goto csum_none;
843                                 ip_summed = CHECKSUM_COMPLETE;
844                                 hash_type = PKT_HASH_TYPE_L3;
845                                 ring->csum_complete++;
846                         }
847                 } else {
848 csum_none:
849                         ip_summed = CHECKSUM_NONE;
850                         hash_type = PKT_HASH_TYPE_L3;
851                         ring->csum_none++;
852                 }
853                 skb->ip_summed = ip_summed;
854                 if (dev->features & NETIF_F_RXHASH)
855                         skb_set_hash(skb,
856                                      be32_to_cpu(cqe->immed_rss_invalid),
857                                      hash_type);
858
859                 if ((cqe->vlan_my_qpn &
860                      cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
861                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
862                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
863                                                be16_to_cpu(cqe->sl_vid));
864                 else if ((cqe->vlan_my_qpn &
865                           cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) &&
866                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
867                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
868                                                be16_to_cpu(cqe->sl_vid));
869
870                 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length);
871                 if (likely(nr)) {
872                         skb_shinfo(skb)->nr_frags = nr;
873                         skb->len = length;
874                         skb->data_len = length;
875                         napi_gro_frags(&cq->napi);
876                 } else {
877                         skb->vlan_tci = 0;
878                         skb_clear_hash(skb);
879                 }
880 next:
881                 ++cq->mcq.cons_index;
882                 index = (cq->mcq.cons_index) & ring->size_mask;
883                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
884                 if (unlikely(++polled == budget))
885                         break;
886         }
887
888         rcu_read_unlock();
889
890         if (likely(polled)) {
891                 if (doorbell_pending) {
892                         priv->tx_cq[TX_XDP][cq_ring]->xdp_busy = true;
893                         mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq_ring]);
894                 }
895
896                 mlx4_cq_set_ci(&cq->mcq);
897                 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
898                 ring->cons = cq->mcq.cons_index;
899         }
900         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
901
902         mlx4_en_refill_rx_buffers(priv, ring);
903
904         return polled;
905 }
906
907
908 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
909 {
910         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
911         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
912
913         if (likely(priv->port_up))
914                 napi_schedule_irqoff(&cq->napi);
915         else
916                 mlx4_en_arm_cq(priv, cq);
917 }
918
919 /* Rx CQ polling - called by NAPI */
920 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
921 {
922         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
923         struct net_device *dev = cq->dev;
924         struct mlx4_en_priv *priv = netdev_priv(dev);
925         struct mlx4_en_cq *xdp_tx_cq = NULL;
926         bool clean_complete = true;
927         int done;
928
929         if (priv->tx_ring_num[TX_XDP]) {
930                 xdp_tx_cq = priv->tx_cq[TX_XDP][cq->ring];
931                 if (xdp_tx_cq->xdp_busy) {
932                         clean_complete = mlx4_en_process_tx_cq(dev, xdp_tx_cq,
933                                                                budget);
934                         xdp_tx_cq->xdp_busy = !clean_complete;
935                 }
936         }
937
938         done = mlx4_en_process_rx_cq(dev, cq, budget);
939
940         /* If we used up all the quota - we're probably not done yet... */
941         if (done == budget || !clean_complete) {
942                 const struct cpumask *aff;
943                 struct irq_data *idata;
944                 int cpu_curr;
945
946                 /* in case we got here because of !clean_complete */
947                 done = budget;
948
949                 INC_PERF_COUNTER(priv->pstats.napi_quota);
950
951                 cpu_curr = smp_processor_id();
952                 idata = irq_desc_get_irq_data(cq->irq_desc);
953                 aff = irq_data_get_affinity_mask(idata);
954
955                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
956                         return budget;
957
958                 /* Current cpu is not according to smp_irq_affinity -
959                  * probably affinity changed. Need to stop this NAPI
960                  * poll, and restart it on the right CPU.
961                  * Try to avoid returning a too small value (like 0),
962                  * to not fool net_rx_action() and its netdev_budget
963                  */
964                 if (done)
965                         done--;
966         }
967         /* Done for now */
968         if (likely(napi_complete_done(napi, done)))
969                 mlx4_en_arm_cq(priv, cq);
970         return done;
971 }
972
973 void mlx4_en_calc_rx_buf(struct net_device *dev)
974 {
975         struct mlx4_en_priv *priv = netdev_priv(dev);
976         int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
977         int i = 0;
978
979         /* bpf requires buffers to be set up as 1 packet per page.
980          * This only works when num_frags == 1.
981          */
982         if (priv->tx_ring_num[TX_XDP]) {
983                 priv->frag_info[0].frag_size = eff_mtu;
984                 /* This will gain efficient xdp frame recycling at the
985                  * expense of more costly truesize accounting
986                  */
987                 priv->frag_info[0].frag_stride = PAGE_SIZE;
988                 priv->dma_dir = PCI_DMA_BIDIRECTIONAL;
989                 priv->rx_headroom = XDP_PACKET_HEADROOM;
990                 i = 1;
991         } else {
992                 int frag_size_max = 2048, buf_size = 0;
993
994                 /* should not happen, right ? */
995                 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048)
996                         frag_size_max = PAGE_SIZE;
997
998                 while (buf_size < eff_mtu) {
999                         int frag_stride, frag_size = eff_mtu - buf_size;
1000                         int pad, nb;
1001
1002                         if (i < MLX4_EN_MAX_RX_FRAGS - 1)
1003                                 frag_size = min(frag_size, frag_size_max);
1004
1005                         priv->frag_info[i].frag_size = frag_size;
1006                         frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES);
1007                         /* We can only pack 2 1536-bytes frames in on 4K page
1008                          * Therefore, each frame would consume more bytes (truesize)
1009                          */
1010                         nb = PAGE_SIZE / frag_stride;
1011                         pad = (PAGE_SIZE - nb * frag_stride) / nb;
1012                         pad &= ~(SMP_CACHE_BYTES - 1);
1013                         priv->frag_info[i].frag_stride = frag_stride + pad;
1014
1015                         buf_size += frag_size;
1016                         i++;
1017                 }
1018                 priv->dma_dir = PCI_DMA_FROMDEVICE;
1019                 priv->rx_headroom = 0;
1020         }
1021
1022         priv->num_frags = i;
1023         priv->rx_skb_size = eff_mtu;
1024         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1025
1026         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1027                eff_mtu, priv->num_frags);
1028         for (i = 0; i < priv->num_frags; i++) {
1029                 en_dbg(DRV,
1030                        priv,
1031                        "  frag:%d - size:%d stride:%d\n",
1032                        i,
1033                        priv->frag_info[i].frag_size,
1034                        priv->frag_info[i].frag_stride);
1035         }
1036 }
1037
1038 /* RSS related functions */
1039
1040 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1041                                  struct mlx4_en_rx_ring *ring,
1042                                  enum mlx4_qp_state *state,
1043                                  struct mlx4_qp *qp)
1044 {
1045         struct mlx4_en_dev *mdev = priv->mdev;
1046         struct mlx4_qp_context *context;
1047         int err = 0;
1048
1049         context = kmalloc(sizeof(*context), GFP_KERNEL);
1050         if (!context)
1051                 return -ENOMEM;
1052
1053         err = mlx4_qp_alloc(mdev->dev, qpn, qp);
1054         if (err) {
1055                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1056                 goto out;
1057         }
1058         qp->event = mlx4_en_sqp_event;
1059
1060         memset(context, 0, sizeof(*context));
1061         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1062                                 qpn, ring->cqn, -1, context);
1063         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1064
1065         /* Cancel FCS removal if FW allows */
1066         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1067                 context->param3 |= cpu_to_be32(1 << 29);
1068                 if (priv->dev->features & NETIF_F_RXFCS)
1069                         ring->fcs_del = 0;
1070                 else
1071                         ring->fcs_del = ETH_FCS_LEN;
1072         } else
1073                 ring->fcs_del = 0;
1074
1075         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1076         if (err) {
1077                 mlx4_qp_remove(mdev->dev, qp);
1078                 mlx4_qp_free(mdev->dev, qp);
1079         }
1080         mlx4_en_update_rx_prod_db(ring);
1081 out:
1082         kfree(context);
1083         return err;
1084 }
1085
1086 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1087 {
1088         int err;
1089         u32 qpn;
1090
1091         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1092                                     MLX4_RESERVE_A0_QP,
1093                                     MLX4_RES_USAGE_DRIVER);
1094         if (err) {
1095                 en_err(priv, "Failed reserving drop qpn\n");
1096                 return err;
1097         }
1098         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
1099         if (err) {
1100                 en_err(priv, "Failed allocating drop qp\n");
1101                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1102                 return err;
1103         }
1104
1105         return 0;
1106 }
1107
1108 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1109 {
1110         u32 qpn;
1111
1112         qpn = priv->drop_qp.qpn;
1113         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1114         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1115         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1116 }
1117
1118 /* Allocate rx qp's and configure them according to rss map */
1119 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1120 {
1121         struct mlx4_en_dev *mdev = priv->mdev;
1122         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1123         struct mlx4_qp_context context;
1124         struct mlx4_rss_context *rss_context;
1125         int rss_rings;
1126         void *ptr;
1127         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1128                         MLX4_RSS_TCP_IPV6);
1129         int i, qpn;
1130         int err = 0;
1131         int good_qps = 0;
1132         u8 flags;
1133
1134         en_dbg(DRV, priv, "Configuring rss steering\n");
1135
1136         flags = priv->rx_ring_num == 1 ? MLX4_RESERVE_A0_QP : 0;
1137         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1138                                     priv->rx_ring_num,
1139                                     &rss_map->base_qpn, flags,
1140                                     MLX4_RES_USAGE_DRIVER);
1141         if (err) {
1142                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1143                 return err;
1144         }
1145
1146         for (i = 0; i < priv->rx_ring_num; i++) {
1147                 qpn = rss_map->base_qpn + i;
1148                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1149                                             &rss_map->state[i],
1150                                             &rss_map->qps[i]);
1151                 if (err)
1152                         goto rss_err;
1153
1154                 ++good_qps;
1155         }
1156
1157         if (priv->rx_ring_num == 1) {
1158                 rss_map->indir_qp = &rss_map->qps[0];
1159                 priv->base_qpn = rss_map->indir_qp->qpn;
1160                 en_info(priv, "Optimized Non-RSS steering\n");
1161                 return 0;
1162         }
1163
1164         rss_map->indir_qp = kzalloc(sizeof(*rss_map->indir_qp), GFP_KERNEL);
1165         if (!rss_map->indir_qp) {
1166                 err = -ENOMEM;
1167                 goto rss_err;
1168         }
1169
1170         /* Configure RSS indirection qp */
1171         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, rss_map->indir_qp);
1172         if (err) {
1173                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1174                 goto rss_err;
1175         }
1176
1177         rss_map->indir_qp->event = mlx4_en_sqp_event;
1178         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1179                                 priv->rx_ring[0]->cqn, -1, &context);
1180
1181         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1182                 rss_rings = priv->rx_ring_num;
1183         else
1184                 rss_rings = priv->prof->rss_rings;
1185
1186         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1187                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1188         rss_context = ptr;
1189         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1190                                             (rss_map->base_qpn));
1191         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1192         if (priv->mdev->profile.udp_rss) {
1193                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1194                 rss_context->base_qpn_udp = rss_context->default_qpn;
1195         }
1196
1197         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1198                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1199                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1200         }
1201
1202         rss_context->flags = rss_mask;
1203         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1204         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1205                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1206         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1207                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1208                 memcpy(rss_context->rss_key, priv->rss_key,
1209                        MLX4_EN_RSS_KEY_SIZE);
1210         } else {
1211                 en_err(priv, "Unknown RSS hash function requested\n");
1212                 err = -EINVAL;
1213                 goto indir_err;
1214         }
1215
1216         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1217                                rss_map->indir_qp, &rss_map->indir_state);
1218         if (err)
1219                 goto indir_err;
1220
1221         return 0;
1222
1223 indir_err:
1224         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1225                        MLX4_QP_STATE_RST, NULL, 0, 0, rss_map->indir_qp);
1226         mlx4_qp_remove(mdev->dev, rss_map->indir_qp);
1227         mlx4_qp_free(mdev->dev, rss_map->indir_qp);
1228         kfree(rss_map->indir_qp);
1229         rss_map->indir_qp = NULL;
1230 rss_err:
1231         for (i = 0; i < good_qps; i++) {
1232                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1233                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1234                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1235                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1236         }
1237         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1238         return err;
1239 }
1240
1241 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1242 {
1243         struct mlx4_en_dev *mdev = priv->mdev;
1244         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1245         int i;
1246
1247         if (priv->rx_ring_num > 1) {
1248                 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1249                                MLX4_QP_STATE_RST, NULL, 0, 0,
1250                                rss_map->indir_qp);
1251                 mlx4_qp_remove(mdev->dev, rss_map->indir_qp);
1252                 mlx4_qp_free(mdev->dev, rss_map->indir_qp);
1253                 kfree(rss_map->indir_qp);
1254                 rss_map->indir_qp = NULL;
1255         }
1256
1257         for (i = 0; i < priv->rx_ring_num; i++) {
1258                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1259                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1260                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1261                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1262         }
1263         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1264 }