Merge tag 'pci-v4.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[muen/linux.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * OpenIB.org BSD license below:
12  *
13  *     Redistribution and use in source and binary forms, with or
14  *     without modification, are permitted provided that the following
15  *     conditions are met:
16  *
17  *      - Redistributions of source code must retain the above
18  *        copyright notice, this list of conditions and the following
19  *        disclaimer.
20  *
21  *      - Redistributions in binary form must reproduce the above
22  *        copyright notice, this list of conditions and the following
23  *        disclaimer in the documentation and/or other materials
24  *        provided with the distribution.
25  *
26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33  * SOFTWARE.
34  */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/errno.h>
40 #include <linux/pci.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/slab.h>
43 #include <linux/io-mapping.h>
44 #include <linux/delay.h>
45 #include <linux/kmod.h>
46 #include <linux/etherdevice.h>
47 #include <net/devlink.h>
48
49 #include <uapi/rdma/mlx4-abi.h>
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/doorbell.h>
52
53 #include "mlx4.h"
54 #include "fw.h"
55 #include "icm.h"
56
57 MODULE_AUTHOR("Roland Dreier");
58 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
59 MODULE_LICENSE("Dual BSD/GPL");
60 MODULE_VERSION(DRV_VERSION);
61
62 struct workqueue_struct *mlx4_wq;
63
64 #ifdef CONFIG_MLX4_DEBUG
65
66 int mlx4_debug_level = 0;
67 module_param_named(debug_level, mlx4_debug_level, int, 0644);
68 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
69
70 #endif /* CONFIG_MLX4_DEBUG */
71
72 #ifdef CONFIG_PCI_MSI
73
74 static int msi_x = 1;
75 module_param(msi_x, int, 0444);
76 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
77
78 #else /* CONFIG_PCI_MSI */
79
80 #define msi_x (0)
81
82 #endif /* CONFIG_PCI_MSI */
83
84 static uint8_t num_vfs[3] = {0, 0, 0};
85 static int num_vfs_argc;
86 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
87 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
88                           "num_vfs=port1,port2,port1+2");
89
90 static uint8_t probe_vf[3] = {0, 0, 0};
91 static int probe_vfs_argc;
92 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
93 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
94                            "probe_vf=port1,port2,port1+2");
95
96 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
97 module_param_named(log_num_mgm_entry_size,
98                         mlx4_log_num_mgm_entry_size, int, 0444);
99 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
100                                          " of qp per mcg, for example:"
101                                          " 10 gives 248.range: 7 <="
102                                          " log_num_mgm_entry_size <= 12."
103                                          " To activate device managed"
104                                          " flow steering when available, set to -1");
105
106 static bool enable_64b_cqe_eqe = true;
107 module_param(enable_64b_cqe_eqe, bool, 0444);
108 MODULE_PARM_DESC(enable_64b_cqe_eqe,
109                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
110
111 static bool enable_4k_uar;
112 module_param(enable_4k_uar, bool, 0444);
113 MODULE_PARM_DESC(enable_4k_uar,
114                  "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
115
116 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
117                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
118                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
119
120 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
121
122 static char mlx4_version[] =
123         DRV_NAME ": Mellanox ConnectX core driver v"
124         DRV_VERSION "\n";
125
126 static const struct mlx4_profile default_profile = {
127         .num_qp         = 1 << 18,
128         .num_srq        = 1 << 16,
129         .rdmarc_per_qp  = 1 << 4,
130         .num_cq         = 1 << 16,
131         .num_mcg        = 1 << 13,
132         .num_mpt        = 1 << 19,
133         .num_mtt        = 1 << 20, /* It is really num mtt segements */
134 };
135
136 static const struct mlx4_profile low_mem_profile = {
137         .num_qp         = 1 << 17,
138         .num_srq        = 1 << 6,
139         .rdmarc_per_qp  = 1 << 4,
140         .num_cq         = 1 << 8,
141         .num_mcg        = 1 << 8,
142         .num_mpt        = 1 << 9,
143         .num_mtt        = 1 << 7,
144 };
145
146 static int log_num_mac = 7;
147 module_param_named(log_num_mac, log_num_mac, int, 0444);
148 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
149
150 static int log_num_vlan;
151 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
152 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
153 /* Log2 max number of VLANs per ETH port (0-7) */
154 #define MLX4_LOG_NUM_VLANS 7
155 #define MLX4_MIN_LOG_NUM_VLANS 0
156 #define MLX4_MIN_LOG_NUM_MAC 1
157
158 static bool use_prio;
159 module_param_named(use_prio, use_prio, bool, 0444);
160 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
161
162 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
163 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
164 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
165
166 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
167 static int arr_argc = 2;
168 module_param_array(port_type_array, int, &arr_argc, 0444);
169 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
170                                 "1 for IB, 2 for Ethernet");
171
172 struct mlx4_port_config {
173         struct list_head list;
174         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
175         struct pci_dev *pdev;
176 };
177
178 static atomic_t pf_loading = ATOMIC_INIT(0);
179
180 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
181                                               struct mlx4_dev_cap *dev_cap)
182 {
183         /* The reserved_uars is calculated by system page size unit.
184          * Therefore, adjustment is added when the uar page size is less
185          * than the system page size
186          */
187         dev->caps.reserved_uars =
188                 max_t(int,
189                       mlx4_get_num_reserved_uar(dev),
190                       dev_cap->reserved_uars /
191                         (1 << (PAGE_SHIFT - dev->uar_page_shift)));
192 }
193
194 int mlx4_check_port_params(struct mlx4_dev *dev,
195                            enum mlx4_port_type *port_type)
196 {
197         int i;
198
199         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
200                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
201                         if (port_type[i] != port_type[i + 1]) {
202                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
203                                 return -EINVAL;
204                         }
205                 }
206         }
207
208         for (i = 0; i < dev->caps.num_ports; i++) {
209                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
210                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
211                                  i + 1);
212                         return -EINVAL;
213                 }
214         }
215         return 0;
216 }
217
218 static void mlx4_set_port_mask(struct mlx4_dev *dev)
219 {
220         int i;
221
222         for (i = 1; i <= dev->caps.num_ports; ++i)
223                 dev->caps.port_mask[i] = dev->caps.port_type[i];
224 }
225
226 enum {
227         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
228 };
229
230 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
231 {
232         int err = 0;
233         struct mlx4_func func;
234
235         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
236                 err = mlx4_QUERY_FUNC(dev, &func, 0);
237                 if (err) {
238                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
239                         return err;
240                 }
241                 dev_cap->max_eqs = func.max_eq;
242                 dev_cap->reserved_eqs = func.rsvd_eqs;
243                 dev_cap->reserved_uars = func.rsvd_uars;
244                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
245         }
246         return err;
247 }
248
249 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
250 {
251         struct mlx4_caps *dev_cap = &dev->caps;
252
253         /* FW not supporting or cancelled by user */
254         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
255             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
256                 return;
257
258         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
259          * When FW has NCSI it may decide not to report 64B CQE/EQEs
260          */
261         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
262             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
263                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
264                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
265                 return;
266         }
267
268         if (cache_line_size() == 128 || cache_line_size() == 256) {
269                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
270                 /* Changing the real data inside CQE size to 32B */
271                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
272                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
273
274                 if (mlx4_is_master(dev))
275                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
276         } else {
277                 if (cache_line_size() != 32  && cache_line_size() != 64)
278                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
279                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
280                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
281         }
282 }
283
284 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
285                           struct mlx4_port_cap *port_cap)
286 {
287         dev->caps.vl_cap[port]      = port_cap->max_vl;
288         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
289         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
290         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
291         /* set gid and pkey table operating lengths by default
292          * to non-sriov values
293          */
294         dev->caps.gid_table_len[port]  = port_cap->max_gids;
295         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
296         dev->caps.port_width_cap[port] = port_cap->max_port_width;
297         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
298         dev->caps.max_tc_eth           = port_cap->max_tc_eth;
299         dev->caps.def_mac[port]        = port_cap->def_mac;
300         dev->caps.supported_type[port] = port_cap->supported_port_types;
301         dev->caps.suggested_type[port] = port_cap->suggested_type;
302         dev->caps.default_sense[port] = port_cap->default_sense;
303         dev->caps.trans_type[port]          = port_cap->trans_type;
304         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
305         dev->caps.wavelength[port]     = port_cap->wavelength;
306         dev->caps.trans_code[port]     = port_cap->trans_code;
307
308         return 0;
309 }
310
311 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
312                          struct mlx4_port_cap *port_cap)
313 {
314         int err = 0;
315
316         err = mlx4_QUERY_PORT(dev, port, port_cap);
317
318         if (err)
319                 mlx4_err(dev, "QUERY_PORT command failed.\n");
320
321         return err;
322 }
323
324 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
325 {
326         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
327                 return;
328
329         if (mlx4_is_mfunc(dev)) {
330                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
331                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
332                 return;
333         }
334
335         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
336                 mlx4_dbg(dev,
337                          "Keep FCS is not supported - Disabling Ignore FCS");
338                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
339                 return;
340         }
341 }
342
343 #define MLX4_A0_STEERING_TABLE_SIZE     256
344 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
345 {
346         int err;
347         int i;
348
349         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
350         if (err) {
351                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
352                 return err;
353         }
354         mlx4_dev_cap_dump(dev, dev_cap);
355
356         if (dev_cap->min_page_sz > PAGE_SIZE) {
357                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
358                          dev_cap->min_page_sz, PAGE_SIZE);
359                 return -ENODEV;
360         }
361         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
362                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
363                          dev_cap->num_ports, MLX4_MAX_PORTS);
364                 return -ENODEV;
365         }
366
367         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
368                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
369                          dev_cap->uar_size,
370                          (unsigned long long)
371                          pci_resource_len(dev->persist->pdev, 2));
372                 return -ENODEV;
373         }
374
375         dev->caps.num_ports          = dev_cap->num_ports;
376         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
377         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
378                                       dev->caps.num_sys_eqs :
379                                       MLX4_MAX_EQ_NUM;
380         for (i = 1; i <= dev->caps.num_ports; ++i) {
381                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
382                 if (err) {
383                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
384                         return err;
385                 }
386         }
387
388         dev->caps.uar_page_size      = PAGE_SIZE;
389         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
390         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
391         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
392         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
393         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
394         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
395         dev->caps.max_wqes           = dev_cap->max_qp_sz;
396         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
397         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
398         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
399         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
400         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
401         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
402         /*
403          * Subtract 1 from the limit because we need to allocate a
404          * spare CQE so the HCA HW can tell the difference between an
405          * empty CQ and a full CQ.
406          */
407         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
408         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
409         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
410         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
411         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
412
413         dev->caps.reserved_pds       = dev_cap->reserved_pds;
414         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
415                                         dev_cap->reserved_xrcds : 0;
416         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
417                                         dev_cap->max_xrcds : 0;
418         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
419
420         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
421         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
422         dev->caps.flags              = dev_cap->flags;
423         dev->caps.flags2             = dev_cap->flags2;
424         dev->caps.bmme_flags         = dev_cap->bmme_flags;
425         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
426         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
427         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
428         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
429         dev->caps.wol_port[1]          = dev_cap->wol_port[1];
430         dev->caps.wol_port[2]          = dev_cap->wol_port[2];
431
432         /* Save uar page shift */
433         if (!mlx4_is_slave(dev)) {
434                 /* Virtual PCI function needs to determine UAR page size from
435                  * firmware. Only master PCI function can set the uar page size
436                  */
437                 if (enable_4k_uar || !dev->persist->num_vfs)
438                         dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
439                 else
440                         dev->uar_page_shift = PAGE_SHIFT;
441
442                 mlx4_set_num_reserved_uars(dev, dev_cap);
443         }
444
445         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
446                 struct mlx4_init_hca_param hca_param;
447
448                 memset(&hca_param, 0, sizeof(hca_param));
449                 err = mlx4_QUERY_HCA(dev, &hca_param);
450                 /* Turn off PHV_EN flag in case phv_check_en is set.
451                  * phv_check_en is a HW check that parse the packet and verify
452                  * phv bit was reported correctly in the wqe. To allow QinQ
453                  * PHV_EN flag should be set and phv_check_en must be cleared
454                  * otherwise QinQ packets will be drop by the HW.
455                  */
456                 if (err || hca_param.phv_check_en)
457                         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
458         }
459
460         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
461         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
462                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
463         /* Don't do sense port on multifunction devices (for now at least) */
464         if (mlx4_is_mfunc(dev))
465                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
466
467         if (mlx4_low_memory_profile()) {
468                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
469                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
470         } else {
471                 dev->caps.log_num_macs  = log_num_mac;
472                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
473         }
474
475         for (i = 1; i <= dev->caps.num_ports; ++i) {
476                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
477                 if (dev->caps.supported_type[i]) {
478                         /* if only ETH is supported - assign ETH */
479                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
480                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
481                         /* if only IB is supported, assign IB */
482                         else if (dev->caps.supported_type[i] ==
483                                  MLX4_PORT_TYPE_IB)
484                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
485                         else {
486                                 /* if IB and ETH are supported, we set the port
487                                  * type according to user selection of port type;
488                                  * if user selected none, take the FW hint */
489                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
490                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
491                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
492                                 else
493                                         dev->caps.port_type[i] = port_type_array[i - 1];
494                         }
495                 }
496                 /*
497                  * Link sensing is allowed on the port if 3 conditions are true:
498                  * 1. Both protocols are supported on the port.
499                  * 2. Different types are supported on the port
500                  * 3. FW declared that it supports link sensing
501                  */
502                 mlx4_priv(dev)->sense.sense_allowed[i] =
503                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
504                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
505                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
506
507                 /*
508                  * If "default_sense" bit is set, we move the port to "AUTO" mode
509                  * and perform sense_port FW command to try and set the correct
510                  * port type from beginning
511                  */
512                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
513                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
514                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
515                         mlx4_SENSE_PORT(dev, i, &sensed_port);
516                         if (sensed_port != MLX4_PORT_TYPE_NONE)
517                                 dev->caps.port_type[i] = sensed_port;
518                 } else {
519                         dev->caps.possible_type[i] = dev->caps.port_type[i];
520                 }
521
522                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
523                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
524                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
525                                   i, 1 << dev->caps.log_num_macs);
526                 }
527                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
528                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
529                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
530                                   i, 1 << dev->caps.log_num_vlans);
531                 }
532         }
533
534         if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
535             (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
536             (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
537                 mlx4_warn(dev,
538                           "Granular QoS per VF not supported with IB/Eth configuration\n");
539                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
540         }
541
542         dev->caps.max_counters = dev_cap->max_counters;
543
544         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
545         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
546                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
547                 (1 << dev->caps.log_num_macs) *
548                 (1 << dev->caps.log_num_vlans) *
549                 dev->caps.num_ports;
550         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
551
552         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
553             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
554                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
555         else
556                 dev->caps.dmfs_high_rate_qpn_base =
557                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
558
559         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
560             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
561                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
562                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
563                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
564         } else {
565                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
566                 dev->caps.dmfs_high_rate_qpn_base =
567                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
568                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
569         }
570
571         dev->caps.rl_caps = dev_cap->rl_caps;
572
573         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
574                 dev->caps.dmfs_high_rate_qpn_range;
575
576         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
577                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
578                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
579                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
580
581         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
582
583         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
584                 if (dev_cap->flags &
585                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
586                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
587                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
588                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
589                 }
590
591                 if (dev_cap->flags2 &
592                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
593                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
594                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
595                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
596                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
597                 }
598         }
599
600         if ((dev->caps.flags &
601             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
602             mlx4_is_master(dev))
603                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
604
605         if (!mlx4_is_slave(dev)) {
606                 mlx4_enable_cqe_eqe_stride(dev);
607                 dev->caps.alloc_res_qp_mask =
608                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
609                         MLX4_RESERVE_A0_QP;
610
611                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
612                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
613                         mlx4_warn(dev, "Old device ETS support detected\n");
614                         mlx4_warn(dev, "Consider upgrading device FW.\n");
615                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
616                 }
617
618         } else {
619                 dev->caps.alloc_res_qp_mask = 0;
620         }
621
622         mlx4_enable_ignore_fcs(dev);
623
624         return 0;
625 }
626
627 /*The function checks if there are live vf, return the num of them*/
628 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
629 {
630         struct mlx4_priv *priv = mlx4_priv(dev);
631         struct mlx4_slave_state *s_state;
632         int i;
633         int ret = 0;
634
635         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
636                 s_state = &priv->mfunc.master.slave_state[i];
637                 if (s_state->active && s_state->last_cmd !=
638                     MLX4_COMM_CMD_RESET) {
639                         mlx4_warn(dev, "%s: slave: %d is still active\n",
640                                   __func__, i);
641                         ret++;
642                 }
643         }
644         return ret;
645 }
646
647 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
648 {
649         u32 qk = MLX4_RESERVED_QKEY_BASE;
650
651         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
652             qpn < dev->phys_caps.base_proxy_sqpn)
653                 return -EINVAL;
654
655         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
656                 /* tunnel qp */
657                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
658         else
659                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
660         *qkey = qk;
661         return 0;
662 }
663 EXPORT_SYMBOL(mlx4_get_parav_qkey);
664
665 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
666 {
667         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
668
669         if (!mlx4_is_master(dev))
670                 return;
671
672         priv->virt2phys_pkey[slave][port - 1][i] = val;
673 }
674 EXPORT_SYMBOL(mlx4_sync_pkey_table);
675
676 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
677 {
678         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
679
680         if (!mlx4_is_master(dev))
681                 return;
682
683         priv->slave_node_guids[slave] = guid;
684 }
685 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
686
687 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
688 {
689         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
690
691         if (!mlx4_is_master(dev))
692                 return 0;
693
694         return priv->slave_node_guids[slave];
695 }
696 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
697
698 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
699 {
700         struct mlx4_priv *priv = mlx4_priv(dev);
701         struct mlx4_slave_state *s_slave;
702
703         if (!mlx4_is_master(dev))
704                 return 0;
705
706         s_slave = &priv->mfunc.master.slave_state[slave];
707         return !!s_slave->active;
708 }
709 EXPORT_SYMBOL(mlx4_is_slave_active);
710
711 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
712                                        struct _rule_hw *eth_header)
713 {
714         if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
715             is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
716                 struct mlx4_net_trans_rule_hw_eth *eth =
717                         (struct mlx4_net_trans_rule_hw_eth *)eth_header;
718                 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
719                 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
720                         next_rule->rsvd == 0;
721
722                 if (last_rule)
723                         ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
724         }
725 }
726 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
727
728 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
729                                        struct mlx4_dev_cap *dev_cap,
730                                        struct mlx4_init_hca_param *hca_param)
731 {
732         dev->caps.steering_mode = hca_param->steering_mode;
733         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
734                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
735                 dev->caps.fs_log_max_ucast_qp_range_size =
736                         dev_cap->fs_log_max_ucast_qp_range_size;
737         } else
738                 dev->caps.num_qp_per_mgm =
739                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
740
741         mlx4_dbg(dev, "Steering mode is: %s\n",
742                  mlx4_steering_mode_str(dev->caps.steering_mode));
743 }
744
745 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev)
746 {
747         kfree(dev->caps.spec_qps);
748         dev->caps.spec_qps = NULL;
749 }
750
751 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev)
752 {
753         struct mlx4_func_cap *func_cap = NULL;
754         struct mlx4_caps *caps = &dev->caps;
755         int i, err = 0;
756
757         func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
758         caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
759
760         if (!func_cap || !caps->spec_qps) {
761                 mlx4_err(dev, "Failed to allocate memory for special qps cap\n");
762                 err = -ENOMEM;
763                 goto err_mem;
764         }
765
766         for (i = 1; i <= caps->num_ports; ++i) {
767                 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap);
768                 if (err) {
769                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
770                                  i, err);
771                         goto err_mem;
772                 }
773                 caps->spec_qps[i - 1] = func_cap->spec_qps;
774                 caps->port_mask[i] = caps->port_type[i];
775                 caps->phys_port_id[i] = func_cap->phys_port_id;
776                 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
777                                                       &caps->gid_table_len[i],
778                                                       &caps->pkey_table_len[i]);
779                 if (err) {
780                         mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n",
781                                  i, err);
782                         goto err_mem;
783                 }
784         }
785
786 err_mem:
787         if (err)
788                 mlx4_slave_destroy_special_qp_cap(dev);
789         kfree(func_cap);
790         return err;
791 }
792
793 static int mlx4_slave_cap(struct mlx4_dev *dev)
794 {
795         int                        err;
796         u32                        page_size;
797         struct mlx4_dev_cap        *dev_cap = NULL;
798         struct mlx4_func_cap       *func_cap = NULL;
799         struct mlx4_init_hca_param *hca_param = NULL;
800
801         hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL);
802         func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
803         dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
804         if (!hca_param || !func_cap || !dev_cap) {
805                 mlx4_err(dev, "Failed to allocate memory for slave_cap\n");
806                 err = -ENOMEM;
807                 goto free_mem;
808         }
809
810         err = mlx4_QUERY_HCA(dev, hca_param);
811         if (err) {
812                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
813                 goto free_mem;
814         }
815
816         /* fail if the hca has an unknown global capability
817          * at this time global_caps should be always zeroed
818          */
819         if (hca_param->global_caps) {
820                 mlx4_err(dev, "Unknown hca global capabilities\n");
821                 err = -EINVAL;
822                 goto free_mem;
823         }
824
825         dev->caps.hca_core_clock = hca_param->hca_core_clock;
826
827         dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
828         err = mlx4_dev_cap(dev, dev_cap);
829         if (err) {
830                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
831                 goto free_mem;
832         }
833
834         err = mlx4_QUERY_FW(dev);
835         if (err)
836                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
837
838         page_size = ~dev->caps.page_size_cap + 1;
839         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
840         if (page_size > PAGE_SIZE) {
841                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
842                          page_size, PAGE_SIZE);
843                 err = -ENODEV;
844                 goto free_mem;
845         }
846
847         /* Set uar_page_shift for VF */
848         dev->uar_page_shift = hca_param->uar_page_sz + 12;
849
850         /* Make sure the master uar page size is valid */
851         if (dev->uar_page_shift > PAGE_SHIFT) {
852                 mlx4_err(dev,
853                          "Invalid configuration: uar page size is larger than system page size\n");
854                 err = -ENODEV;
855                 goto free_mem;
856         }
857
858         /* Set reserved_uars based on the uar_page_shift */
859         mlx4_set_num_reserved_uars(dev, dev_cap);
860
861         /* Although uar page size in FW differs from system page size,
862          * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
863          * still works with assumption that uar page size == system page size
864          */
865         dev->caps.uar_page_size = PAGE_SIZE;
866
867         err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap);
868         if (err) {
869                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
870                          err);
871                 goto free_mem;
872         }
873
874         if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
875             PF_CONTEXT_BEHAVIOUR_MASK) {
876                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
877                          func_cap->pf_context_behaviour,
878                          PF_CONTEXT_BEHAVIOUR_MASK);
879                 err = -EINVAL;
880                 goto free_mem;
881         }
882
883         dev->caps.num_ports             = func_cap->num_ports;
884         dev->quotas.qp                  = func_cap->qp_quota;
885         dev->quotas.srq                 = func_cap->srq_quota;
886         dev->quotas.cq                  = func_cap->cq_quota;
887         dev->quotas.mpt                 = func_cap->mpt_quota;
888         dev->quotas.mtt                 = func_cap->mtt_quota;
889         dev->caps.num_qps               = 1 << hca_param->log_num_qps;
890         dev->caps.num_srqs              = 1 << hca_param->log_num_srqs;
891         dev->caps.num_cqs               = 1 << hca_param->log_num_cqs;
892         dev->caps.num_mpts              = 1 << hca_param->log_mpt_sz;
893         dev->caps.num_eqs               = func_cap->max_eq;
894         dev->caps.reserved_eqs          = func_cap->reserved_eq;
895         dev->caps.reserved_lkey         = func_cap->reserved_lkey;
896         dev->caps.num_pds               = MLX4_NUM_PDS;
897         dev->caps.num_mgms              = 0;
898         dev->caps.num_amgms             = 0;
899
900         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
901                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
902                          dev->caps.num_ports, MLX4_MAX_PORTS);
903                 err = -ENODEV;
904                 goto free_mem;
905         }
906
907         mlx4_replace_zero_macs(dev);
908
909         err = mlx4_slave_special_qp_cap(dev);
910         if (err) {
911                 mlx4_err(dev, "Set special QP caps failed. aborting\n");
912                 goto free_mem;
913         }
914
915         if (dev->caps.uar_page_size * (dev->caps.num_uars -
916                                        dev->caps.reserved_uars) >
917                                        pci_resource_len(dev->persist->pdev,
918                                                         2)) {
919                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
920                          dev->caps.uar_page_size * dev->caps.num_uars,
921                          (unsigned long long)
922                          pci_resource_len(dev->persist->pdev, 2));
923                 err = -ENOMEM;
924                 goto err_mem;
925         }
926
927         if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
928                 dev->caps.eqe_size   = 64;
929                 dev->caps.eqe_factor = 1;
930         } else {
931                 dev->caps.eqe_size   = 32;
932                 dev->caps.eqe_factor = 0;
933         }
934
935         if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
936                 dev->caps.cqe_size   = 64;
937                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
938         } else {
939                 dev->caps.cqe_size   = 32;
940         }
941
942         if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
943                 dev->caps.eqe_size = hca_param->eqe_size;
944                 dev->caps.eqe_factor = 0;
945         }
946
947         if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
948                 dev->caps.cqe_size = hca_param->cqe_size;
949                 /* User still need to know when CQE > 32B */
950                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
951         }
952
953         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
954         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
955
956         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
957         mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n");
958
959         slave_adjust_steering_mode(dev, dev_cap, hca_param);
960         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
961                  hca_param->rss_ip_frags ? "on" : "off");
962
963         if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
964             dev->caps.bf_reg_size)
965                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
966
967         if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
968                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
969
970 err_mem:
971         if (err)
972                 mlx4_slave_destroy_special_qp_cap(dev);
973 free_mem:
974         kfree(hca_param);
975         kfree(func_cap);
976         kfree(dev_cap);
977         return err;
978 }
979
980 static void mlx4_request_modules(struct mlx4_dev *dev)
981 {
982         int port;
983         int has_ib_port = false;
984         int has_eth_port = false;
985 #define EN_DRV_NAME     "mlx4_en"
986 #define IB_DRV_NAME     "mlx4_ib"
987
988         for (port = 1; port <= dev->caps.num_ports; port++) {
989                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
990                         has_ib_port = true;
991                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
992                         has_eth_port = true;
993         }
994
995         if (has_eth_port)
996                 request_module_nowait(EN_DRV_NAME);
997         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
998                 request_module_nowait(IB_DRV_NAME);
999 }
1000
1001 /*
1002  * Change the port configuration of the device.
1003  * Every user of this function must hold the port mutex.
1004  */
1005 int mlx4_change_port_types(struct mlx4_dev *dev,
1006                            enum mlx4_port_type *port_types)
1007 {
1008         int err = 0;
1009         int change = 0;
1010         int port;
1011
1012         for (port = 0; port <  dev->caps.num_ports; port++) {
1013                 /* Change the port type only if the new type is different
1014                  * from the current, and not set to Auto */
1015                 if (port_types[port] != dev->caps.port_type[port + 1])
1016                         change = 1;
1017         }
1018         if (change) {
1019                 mlx4_unregister_device(dev);
1020                 for (port = 1; port <= dev->caps.num_ports; port++) {
1021                         mlx4_CLOSE_PORT(dev, port);
1022                         dev->caps.port_type[port] = port_types[port - 1];
1023                         err = mlx4_SET_PORT(dev, port, -1);
1024                         if (err) {
1025                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1026                                          port);
1027                                 goto out;
1028                         }
1029                 }
1030                 mlx4_set_port_mask(dev);
1031                 err = mlx4_register_device(dev);
1032                 if (err) {
1033                         mlx4_err(dev, "Failed to register device\n");
1034                         goto out;
1035                 }
1036                 mlx4_request_modules(dev);
1037         }
1038
1039 out:
1040         return err;
1041 }
1042
1043 static ssize_t show_port_type(struct device *dev,
1044                               struct device_attribute *attr,
1045                               char *buf)
1046 {
1047         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1048                                                    port_attr);
1049         struct mlx4_dev *mdev = info->dev;
1050         char type[8];
1051
1052         sprintf(type, "%s",
1053                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1054                 "ib" : "eth");
1055         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1056                 sprintf(buf, "auto (%s)\n", type);
1057         else
1058                 sprintf(buf, "%s\n", type);
1059
1060         return strlen(buf);
1061 }
1062
1063 static int __set_port_type(struct mlx4_port_info *info,
1064                            enum mlx4_port_type port_type)
1065 {
1066         struct mlx4_dev *mdev = info->dev;
1067         struct mlx4_priv *priv = mlx4_priv(mdev);
1068         enum mlx4_port_type types[MLX4_MAX_PORTS];
1069         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1070         int i;
1071         int err = 0;
1072
1073         if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1074                 mlx4_err(mdev,
1075                          "Requested port type for port %d is not supported on this HCA\n",
1076                          info->port);
1077                 err = -EINVAL;
1078                 goto err_sup;
1079         }
1080
1081         mlx4_stop_sense(mdev);
1082         mutex_lock(&priv->port_mutex);
1083         info->tmp_type = port_type;
1084
1085         /* Possible type is always the one that was delivered */
1086         mdev->caps.possible_type[info->port] = info->tmp_type;
1087
1088         for (i = 0; i < mdev->caps.num_ports; i++) {
1089                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1090                                         mdev->caps.possible_type[i+1];
1091                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1092                         types[i] = mdev->caps.port_type[i+1];
1093         }
1094
1095         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1096             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1097                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1098                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1099                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1100                                 err = -EINVAL;
1101                         }
1102                 }
1103         }
1104         if (err) {
1105                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1106                 goto out;
1107         }
1108
1109         mlx4_do_sense_ports(mdev, new_types, types);
1110
1111         err = mlx4_check_port_params(mdev, new_types);
1112         if (err)
1113                 goto out;
1114
1115         /* We are about to apply the changes after the configuration
1116          * was verified, no need to remember the temporary types
1117          * any more */
1118         for (i = 0; i < mdev->caps.num_ports; i++)
1119                 priv->port[i + 1].tmp_type = 0;
1120
1121         err = mlx4_change_port_types(mdev, new_types);
1122
1123 out:
1124         mlx4_start_sense(mdev);
1125         mutex_unlock(&priv->port_mutex);
1126 err_sup:
1127         return err;
1128 }
1129
1130 static ssize_t set_port_type(struct device *dev,
1131                              struct device_attribute *attr,
1132                              const char *buf, size_t count)
1133 {
1134         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1135                                                    port_attr);
1136         struct mlx4_dev *mdev = info->dev;
1137         enum mlx4_port_type port_type;
1138         static DEFINE_MUTEX(set_port_type_mutex);
1139         int err;
1140
1141         mutex_lock(&set_port_type_mutex);
1142
1143         if (!strcmp(buf, "ib\n")) {
1144                 port_type = MLX4_PORT_TYPE_IB;
1145         } else if (!strcmp(buf, "eth\n")) {
1146                 port_type = MLX4_PORT_TYPE_ETH;
1147         } else if (!strcmp(buf, "auto\n")) {
1148                 port_type = MLX4_PORT_TYPE_AUTO;
1149         } else {
1150                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1151                 err = -EINVAL;
1152                 goto err_out;
1153         }
1154
1155         err = __set_port_type(info, port_type);
1156
1157 err_out:
1158         mutex_unlock(&set_port_type_mutex);
1159
1160         return err ? err : count;
1161 }
1162
1163 enum ibta_mtu {
1164         IB_MTU_256  = 1,
1165         IB_MTU_512  = 2,
1166         IB_MTU_1024 = 3,
1167         IB_MTU_2048 = 4,
1168         IB_MTU_4096 = 5
1169 };
1170
1171 static inline int int_to_ibta_mtu(int mtu)
1172 {
1173         switch (mtu) {
1174         case 256:  return IB_MTU_256;
1175         case 512:  return IB_MTU_512;
1176         case 1024: return IB_MTU_1024;
1177         case 2048: return IB_MTU_2048;
1178         case 4096: return IB_MTU_4096;
1179         default: return -1;
1180         }
1181 }
1182
1183 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1184 {
1185         switch (mtu) {
1186         case IB_MTU_256:  return  256;
1187         case IB_MTU_512:  return  512;
1188         case IB_MTU_1024: return 1024;
1189         case IB_MTU_2048: return 2048;
1190         case IB_MTU_4096: return 4096;
1191         default: return -1;
1192         }
1193 }
1194
1195 static ssize_t show_port_ib_mtu(struct device *dev,
1196                              struct device_attribute *attr,
1197                              char *buf)
1198 {
1199         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1200                                                    port_mtu_attr);
1201         struct mlx4_dev *mdev = info->dev;
1202
1203         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1204                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1205
1206         sprintf(buf, "%d\n",
1207                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1208         return strlen(buf);
1209 }
1210
1211 static ssize_t set_port_ib_mtu(struct device *dev,
1212                              struct device_attribute *attr,
1213                              const char *buf, size_t count)
1214 {
1215         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1216                                                    port_mtu_attr);
1217         struct mlx4_dev *mdev = info->dev;
1218         struct mlx4_priv *priv = mlx4_priv(mdev);
1219         int err, port, mtu, ibta_mtu = -1;
1220
1221         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1222                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1223                 return -EINVAL;
1224         }
1225
1226         err = kstrtoint(buf, 0, &mtu);
1227         if (!err)
1228                 ibta_mtu = int_to_ibta_mtu(mtu);
1229
1230         if (err || ibta_mtu < 0) {
1231                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1232                 return -EINVAL;
1233         }
1234
1235         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1236
1237         mlx4_stop_sense(mdev);
1238         mutex_lock(&priv->port_mutex);
1239         mlx4_unregister_device(mdev);
1240         for (port = 1; port <= mdev->caps.num_ports; port++) {
1241                 mlx4_CLOSE_PORT(mdev, port);
1242                 err = mlx4_SET_PORT(mdev, port, -1);
1243                 if (err) {
1244                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1245                                  port);
1246                         goto err_set_port;
1247                 }
1248         }
1249         err = mlx4_register_device(mdev);
1250 err_set_port:
1251         mutex_unlock(&priv->port_mutex);
1252         mlx4_start_sense(mdev);
1253         return err ? err : count;
1254 }
1255
1256 /* bond for multi-function device */
1257 #define MAX_MF_BOND_ALLOWED_SLAVES 63
1258 static int mlx4_mf_bond(struct mlx4_dev *dev)
1259 {
1260         int err = 0;
1261         int nvfs;
1262         struct mlx4_slaves_pport slaves_port1;
1263         struct mlx4_slaves_pport slaves_port2;
1264         DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1265
1266         slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1267         slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1268         bitmap_and(slaves_port_1_2,
1269                    slaves_port1.slaves, slaves_port2.slaves,
1270                    dev->persist->num_vfs + 1);
1271
1272         /* only single port vfs are allowed */
1273         if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1274                 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1275                 return -EINVAL;
1276         }
1277
1278         /* number of virtual functions is number of total functions minus one
1279          * physical function for each port.
1280          */
1281         nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1282                 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1283
1284         /* limit on maximum allowed VFs */
1285         if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1286                 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1287                           nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
1288                 return -EINVAL;
1289         }
1290
1291         if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1292                 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1293                 return -EINVAL;
1294         }
1295
1296         err = mlx4_bond_mac_table(dev);
1297         if (err)
1298                 return err;
1299         err = mlx4_bond_vlan_table(dev);
1300         if (err)
1301                 goto err1;
1302         err = mlx4_bond_fs_rules(dev);
1303         if (err)
1304                 goto err2;
1305
1306         return 0;
1307 err2:
1308         (void)mlx4_unbond_vlan_table(dev);
1309 err1:
1310         (void)mlx4_unbond_mac_table(dev);
1311         return err;
1312 }
1313
1314 static int mlx4_mf_unbond(struct mlx4_dev *dev)
1315 {
1316         int ret, ret1;
1317
1318         ret = mlx4_unbond_fs_rules(dev);
1319         if (ret)
1320                 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret);
1321         ret1 = mlx4_unbond_mac_table(dev);
1322         if (ret1) {
1323                 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1324                 ret = ret1;
1325         }
1326         ret1 = mlx4_unbond_vlan_table(dev);
1327         if (ret1) {
1328                 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1329                 ret = ret1;
1330         }
1331         return ret;
1332 }
1333
1334 int mlx4_bond(struct mlx4_dev *dev)
1335 {
1336         int ret = 0;
1337         struct mlx4_priv *priv = mlx4_priv(dev);
1338
1339         mutex_lock(&priv->bond_mutex);
1340
1341         if (!mlx4_is_bonded(dev)) {
1342                 ret = mlx4_do_bond(dev, true);
1343                 if (ret)
1344                         mlx4_err(dev, "Failed to bond device: %d\n", ret);
1345                 if (!ret && mlx4_is_master(dev)) {
1346                         ret = mlx4_mf_bond(dev);
1347                         if (ret) {
1348                                 mlx4_err(dev, "bond for multifunction failed\n");
1349                                 mlx4_do_bond(dev, false);
1350                         }
1351                 }
1352         }
1353
1354         mutex_unlock(&priv->bond_mutex);
1355         if (!ret)
1356                 mlx4_dbg(dev, "Device is bonded\n");
1357
1358         return ret;
1359 }
1360 EXPORT_SYMBOL_GPL(mlx4_bond);
1361
1362 int mlx4_unbond(struct mlx4_dev *dev)
1363 {
1364         int ret = 0;
1365         struct mlx4_priv *priv = mlx4_priv(dev);
1366
1367         mutex_lock(&priv->bond_mutex);
1368
1369         if (mlx4_is_bonded(dev)) {
1370                 int ret2 = 0;
1371
1372                 ret = mlx4_do_bond(dev, false);
1373                 if (ret)
1374                         mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1375                 if (mlx4_is_master(dev))
1376                         ret2 = mlx4_mf_unbond(dev);
1377                 if (ret2) {
1378                         mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1379                         ret = ret2;
1380                 }
1381         }
1382
1383         mutex_unlock(&priv->bond_mutex);
1384         if (!ret)
1385                 mlx4_dbg(dev, "Device is unbonded\n");
1386
1387         return ret;
1388 }
1389 EXPORT_SYMBOL_GPL(mlx4_unbond);
1390
1391
1392 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1393 {
1394         u8 port1 = v2p->port1;
1395         u8 port2 = v2p->port2;
1396         struct mlx4_priv *priv = mlx4_priv(dev);
1397         int err;
1398
1399         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1400                 return -EOPNOTSUPP;
1401
1402         mutex_lock(&priv->bond_mutex);
1403
1404         /* zero means keep current mapping for this port */
1405         if (port1 == 0)
1406                 port1 = priv->v2p.port1;
1407         if (port2 == 0)
1408                 port2 = priv->v2p.port2;
1409
1410         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1411             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1412             (port1 == 2 && port2 == 1)) {
1413                 /* besides boundary checks cross mapping makes
1414                  * no sense and therefore not allowed */
1415                 err = -EINVAL;
1416         } else if ((port1 == priv->v2p.port1) &&
1417                  (port2 == priv->v2p.port2)) {
1418                 err = 0;
1419         } else {
1420                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1421                 if (!err) {
1422                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1423                                  port1, port2);
1424                         priv->v2p.port1 = port1;
1425                         priv->v2p.port2 = port2;
1426                 } else {
1427                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1428                 }
1429         }
1430
1431         mutex_unlock(&priv->bond_mutex);
1432         return err;
1433 }
1434 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1435
1436 static int mlx4_load_fw(struct mlx4_dev *dev)
1437 {
1438         struct mlx4_priv *priv = mlx4_priv(dev);
1439         int err;
1440
1441         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1442                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1443         if (!priv->fw.fw_icm) {
1444                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1445                 return -ENOMEM;
1446         }
1447
1448         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1449         if (err) {
1450                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1451                 goto err_free;
1452         }
1453
1454         err = mlx4_RUN_FW(dev);
1455         if (err) {
1456                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1457                 goto err_unmap_fa;
1458         }
1459
1460         return 0;
1461
1462 err_unmap_fa:
1463         mlx4_UNMAP_FA(dev);
1464
1465 err_free:
1466         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1467         return err;
1468 }
1469
1470 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1471                                 int cmpt_entry_sz)
1472 {
1473         struct mlx4_priv *priv = mlx4_priv(dev);
1474         int err;
1475         int num_eqs;
1476
1477         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1478                                   cmpt_base +
1479                                   ((u64) (MLX4_CMPT_TYPE_QP *
1480                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1481                                   cmpt_entry_sz, dev->caps.num_qps,
1482                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1483                                   0, 0);
1484         if (err)
1485                 goto err;
1486
1487         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1488                                   cmpt_base +
1489                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1490                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1491                                   cmpt_entry_sz, dev->caps.num_srqs,
1492                                   dev->caps.reserved_srqs, 0, 0);
1493         if (err)
1494                 goto err_qp;
1495
1496         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1497                                   cmpt_base +
1498                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1499                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1500                                   cmpt_entry_sz, dev->caps.num_cqs,
1501                                   dev->caps.reserved_cqs, 0, 0);
1502         if (err)
1503                 goto err_srq;
1504
1505         num_eqs = dev->phys_caps.num_phys_eqs;
1506         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1507                                   cmpt_base +
1508                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1509                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1510                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1511         if (err)
1512                 goto err_cq;
1513
1514         return 0;
1515
1516 err_cq:
1517         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1518
1519 err_srq:
1520         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1521
1522 err_qp:
1523         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1524
1525 err:
1526         return err;
1527 }
1528
1529 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1530                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1531 {
1532         struct mlx4_priv *priv = mlx4_priv(dev);
1533         u64 aux_pages;
1534         int num_eqs;
1535         int err;
1536
1537         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1538         if (err) {
1539                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1540                 return err;
1541         }
1542
1543         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1544                  (unsigned long long) icm_size >> 10,
1545                  (unsigned long long) aux_pages << 2);
1546
1547         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1548                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1549         if (!priv->fw.aux_icm) {
1550                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1551                 return -ENOMEM;
1552         }
1553
1554         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1555         if (err) {
1556                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1557                 goto err_free_aux;
1558         }
1559
1560         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1561         if (err) {
1562                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1563                 goto err_unmap_aux;
1564         }
1565
1566
1567         num_eqs = dev->phys_caps.num_phys_eqs;
1568         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1569                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1570                                   num_eqs, num_eqs, 0, 0);
1571         if (err) {
1572                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1573                 goto err_unmap_cmpt;
1574         }
1575
1576         /*
1577          * Reserved MTT entries must be aligned up to a cacheline
1578          * boundary, since the FW will write to them, while the driver
1579          * writes to all other MTT entries. (The variable
1580          * dev->caps.mtt_entry_sz below is really the MTT segment
1581          * size, not the raw entry size)
1582          */
1583         dev->caps.reserved_mtts =
1584                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1585                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1586
1587         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1588                                   init_hca->mtt_base,
1589                                   dev->caps.mtt_entry_sz,
1590                                   dev->caps.num_mtts,
1591                                   dev->caps.reserved_mtts, 1, 0);
1592         if (err) {
1593                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1594                 goto err_unmap_eq;
1595         }
1596
1597         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1598                                   init_hca->dmpt_base,
1599                                   dev_cap->dmpt_entry_sz,
1600                                   dev->caps.num_mpts,
1601                                   dev->caps.reserved_mrws, 1, 1);
1602         if (err) {
1603                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1604                 goto err_unmap_mtt;
1605         }
1606
1607         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1608                                   init_hca->qpc_base,
1609                                   dev_cap->qpc_entry_sz,
1610                                   dev->caps.num_qps,
1611                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1612                                   0, 0);
1613         if (err) {
1614                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1615                 goto err_unmap_dmpt;
1616         }
1617
1618         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1619                                   init_hca->auxc_base,
1620                                   dev_cap->aux_entry_sz,
1621                                   dev->caps.num_qps,
1622                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1623                                   0, 0);
1624         if (err) {
1625                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1626                 goto err_unmap_qp;
1627         }
1628
1629         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1630                                   init_hca->altc_base,
1631                                   dev_cap->altc_entry_sz,
1632                                   dev->caps.num_qps,
1633                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1634                                   0, 0);
1635         if (err) {
1636                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1637                 goto err_unmap_auxc;
1638         }
1639
1640         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1641                                   init_hca->rdmarc_base,
1642                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1643                                   dev->caps.num_qps,
1644                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1645                                   0, 0);
1646         if (err) {
1647                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1648                 goto err_unmap_altc;
1649         }
1650
1651         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1652                                   init_hca->cqc_base,
1653                                   dev_cap->cqc_entry_sz,
1654                                   dev->caps.num_cqs,
1655                                   dev->caps.reserved_cqs, 0, 0);
1656         if (err) {
1657                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1658                 goto err_unmap_rdmarc;
1659         }
1660
1661         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1662                                   init_hca->srqc_base,
1663                                   dev_cap->srq_entry_sz,
1664                                   dev->caps.num_srqs,
1665                                   dev->caps.reserved_srqs, 0, 0);
1666         if (err) {
1667                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1668                 goto err_unmap_cq;
1669         }
1670
1671         /*
1672          * For flow steering device managed mode it is required to use
1673          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1674          * required, but for simplicity just map the whole multicast
1675          * group table now.  The table isn't very big and it's a lot
1676          * easier than trying to track ref counts.
1677          */
1678         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1679                                   init_hca->mc_base,
1680                                   mlx4_get_mgm_entry_size(dev),
1681                                   dev->caps.num_mgms + dev->caps.num_amgms,
1682                                   dev->caps.num_mgms + dev->caps.num_amgms,
1683                                   0, 0);
1684         if (err) {
1685                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1686                 goto err_unmap_srq;
1687         }
1688
1689         return 0;
1690
1691 err_unmap_srq:
1692         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1693
1694 err_unmap_cq:
1695         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1696
1697 err_unmap_rdmarc:
1698         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1699
1700 err_unmap_altc:
1701         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1702
1703 err_unmap_auxc:
1704         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1705
1706 err_unmap_qp:
1707         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1708
1709 err_unmap_dmpt:
1710         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1711
1712 err_unmap_mtt:
1713         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1714
1715 err_unmap_eq:
1716         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1717
1718 err_unmap_cmpt:
1719         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1720         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1721         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1722         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1723
1724 err_unmap_aux:
1725         mlx4_UNMAP_ICM_AUX(dev);
1726
1727 err_free_aux:
1728         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1729
1730         return err;
1731 }
1732
1733 static void mlx4_free_icms(struct mlx4_dev *dev)
1734 {
1735         struct mlx4_priv *priv = mlx4_priv(dev);
1736
1737         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1738         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1739         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1740         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1741         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1742         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1743         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1744         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1745         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1746         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1747         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1748         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1749         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1750         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1751
1752         mlx4_UNMAP_ICM_AUX(dev);
1753         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1754 }
1755
1756 static void mlx4_slave_exit(struct mlx4_dev *dev)
1757 {
1758         struct mlx4_priv *priv = mlx4_priv(dev);
1759
1760         mutex_lock(&priv->cmd.slave_cmd_mutex);
1761         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1762                           MLX4_COMM_TIME))
1763                 mlx4_warn(dev, "Failed to close slave function\n");
1764         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1765 }
1766
1767 static int map_bf_area(struct mlx4_dev *dev)
1768 {
1769         struct mlx4_priv *priv = mlx4_priv(dev);
1770         resource_size_t bf_start;
1771         resource_size_t bf_len;
1772         int err = 0;
1773
1774         if (!dev->caps.bf_reg_size)
1775                 return -ENXIO;
1776
1777         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1778                         (dev->caps.num_uars << PAGE_SHIFT);
1779         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1780                         (dev->caps.num_uars << PAGE_SHIFT);
1781         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1782         if (!priv->bf_mapping)
1783                 err = -ENOMEM;
1784
1785         return err;
1786 }
1787
1788 static void unmap_bf_area(struct mlx4_dev *dev)
1789 {
1790         if (mlx4_priv(dev)->bf_mapping)
1791                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1792 }
1793
1794 u64 mlx4_read_clock(struct mlx4_dev *dev)
1795 {
1796         u32 clockhi, clocklo, clockhi1;
1797         u64 cycles;
1798         int i;
1799         struct mlx4_priv *priv = mlx4_priv(dev);
1800
1801         for (i = 0; i < 10; i++) {
1802                 clockhi = swab32(readl(priv->clock_mapping));
1803                 clocklo = swab32(readl(priv->clock_mapping + 4));
1804                 clockhi1 = swab32(readl(priv->clock_mapping));
1805                 if (clockhi == clockhi1)
1806                         break;
1807         }
1808
1809         cycles = (u64) clockhi << 32 | (u64) clocklo;
1810
1811         return cycles;
1812 }
1813 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1814
1815
1816 static int map_internal_clock(struct mlx4_dev *dev)
1817 {
1818         struct mlx4_priv *priv = mlx4_priv(dev);
1819
1820         priv->clock_mapping =
1821                 ioremap(pci_resource_start(dev->persist->pdev,
1822                                            priv->fw.clock_bar) +
1823                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1824
1825         if (!priv->clock_mapping)
1826                 return -ENOMEM;
1827
1828         return 0;
1829 }
1830
1831 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1832                                    struct mlx4_clock_params *params)
1833 {
1834         struct mlx4_priv *priv = mlx4_priv(dev);
1835
1836         if (mlx4_is_slave(dev))
1837                 return -EOPNOTSUPP;
1838
1839         if (!params)
1840                 return -EINVAL;
1841
1842         params->bar = priv->fw.clock_bar;
1843         params->offset = priv->fw.clock_offset;
1844         params->size = MLX4_CLOCK_SIZE;
1845
1846         return 0;
1847 }
1848 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1849
1850 static void unmap_internal_clock(struct mlx4_dev *dev)
1851 {
1852         struct mlx4_priv *priv = mlx4_priv(dev);
1853
1854         if (priv->clock_mapping)
1855                 iounmap(priv->clock_mapping);
1856 }
1857
1858 static void mlx4_close_hca(struct mlx4_dev *dev)
1859 {
1860         unmap_internal_clock(dev);
1861         unmap_bf_area(dev);
1862         if (mlx4_is_slave(dev))
1863                 mlx4_slave_exit(dev);
1864         else {
1865                 mlx4_CLOSE_HCA(dev, 0);
1866                 mlx4_free_icms(dev);
1867         }
1868 }
1869
1870 static void mlx4_close_fw(struct mlx4_dev *dev)
1871 {
1872         if (!mlx4_is_slave(dev)) {
1873                 mlx4_UNMAP_FA(dev);
1874                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1875         }
1876 }
1877
1878 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1879 {
1880 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1881
1882         u32 comm_flags;
1883         u32 offline_bit;
1884         unsigned long end;
1885         struct mlx4_priv *priv = mlx4_priv(dev);
1886
1887         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1888         while (time_before(jiffies, end)) {
1889                 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1890                                           MLX4_COMM_CHAN_FLAGS));
1891                 offline_bit = (comm_flags &
1892                                (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1893                 if (!offline_bit)
1894                         return 0;
1895
1896                 /* If device removal has been requested,
1897                  * do not continue retrying.
1898                  */
1899                 if (dev->persist->interface_state &
1900                     MLX4_INTERFACE_STATE_NOWAIT)
1901                         break;
1902
1903                 /* There are cases as part of AER/Reset flow that PF needs
1904                  * around 100 msec to load. We therefore sleep for 100 msec
1905                  * to allow other tasks to make use of that CPU during this
1906                  * time interval.
1907                  */
1908                 msleep(100);
1909         }
1910         mlx4_err(dev, "Communication channel is offline.\n");
1911         return -EIO;
1912 }
1913
1914 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1915 {
1916 #define COMM_CHAN_RST_OFFSET 0x1e
1917
1918         struct mlx4_priv *priv = mlx4_priv(dev);
1919         u32 comm_rst;
1920         u32 comm_caps;
1921
1922         comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1923                                  MLX4_COMM_CHAN_CAPS));
1924         comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1925
1926         if (comm_rst)
1927                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1928 }
1929
1930 static int mlx4_init_slave(struct mlx4_dev *dev)
1931 {
1932         struct mlx4_priv *priv = mlx4_priv(dev);
1933         u64 dma = (u64) priv->mfunc.vhcr_dma;
1934         int ret_from_reset = 0;
1935         u32 slave_read;
1936         u32 cmd_channel_ver;
1937
1938         if (atomic_read(&pf_loading)) {
1939                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1940                 return -EPROBE_DEFER;
1941         }
1942
1943         mutex_lock(&priv->cmd.slave_cmd_mutex);
1944         priv->cmd.max_cmds = 1;
1945         if (mlx4_comm_check_offline(dev)) {
1946                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1947                 goto err_offline;
1948         }
1949
1950         mlx4_reset_vf_support(dev);
1951         mlx4_warn(dev, "Sending reset\n");
1952         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1953                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1954         /* if we are in the middle of flr the slave will try
1955          * NUM_OF_RESET_RETRIES times before leaving.*/
1956         if (ret_from_reset) {
1957                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1958                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1959                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1960                         return -EPROBE_DEFER;
1961                 } else
1962                         goto err;
1963         }
1964
1965         /* check the driver version - the slave I/F revision
1966          * must match the master's */
1967         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1968         cmd_channel_ver = mlx4_comm_get_version();
1969
1970         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1971                 MLX4_COMM_GET_IF_REV(slave_read)) {
1972                 mlx4_err(dev, "slave driver version is not supported by the master\n");
1973                 goto err;
1974         }
1975
1976         mlx4_warn(dev, "Sending vhcr0\n");
1977         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1978                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1979                 goto err;
1980         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1981                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1982                 goto err;
1983         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1984                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1985                 goto err;
1986         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1987                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1988                 goto err;
1989
1990         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1991         return 0;
1992
1993 err:
1994         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
1995 err_offline:
1996         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1997         return -EIO;
1998 }
1999
2000 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2001 {
2002         int i;
2003
2004         for (i = 1; i <= dev->caps.num_ports; i++) {
2005                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2006                         dev->caps.gid_table_len[i] =
2007                                 mlx4_get_slave_num_gids(dev, 0, i);
2008                 else
2009                         dev->caps.gid_table_len[i] = 1;
2010                 dev->caps.pkey_table_len[i] =
2011                         dev->phys_caps.pkey_phys_table_len[i] - 1;
2012         }
2013 }
2014
2015 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2016 {
2017         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2018
2019         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2020               i++) {
2021                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2022                         break;
2023         }
2024
2025         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2026 }
2027
2028 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2029 {
2030         switch (dmfs_high_steer_mode) {
2031         case MLX4_STEERING_DMFS_A0_DEFAULT:
2032                 return "default performance";
2033
2034         case MLX4_STEERING_DMFS_A0_DYNAMIC:
2035                 return "dynamic hybrid mode";
2036
2037         case MLX4_STEERING_DMFS_A0_STATIC:
2038                 return "performance optimized for limited rule configuration (static)";
2039
2040         case MLX4_STEERING_DMFS_A0_DISABLE:
2041                 return "disabled performance optimized steering";
2042
2043         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2044                 return "performance optimized steering not supported";
2045
2046         default:
2047                 return "Unrecognized mode";
2048         }
2049 }
2050
2051 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
2052
2053 static void choose_steering_mode(struct mlx4_dev *dev,
2054                                  struct mlx4_dev_cap *dev_cap)
2055 {
2056         if (mlx4_log_num_mgm_entry_size <= 0) {
2057                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2058                         if (dev->caps.dmfs_high_steer_mode ==
2059                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2060                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
2061                         else
2062                                 dev->caps.dmfs_high_steer_mode =
2063                                         MLX4_STEERING_DMFS_A0_STATIC;
2064                 }
2065         }
2066
2067         if (mlx4_log_num_mgm_entry_size <= 0 &&
2068             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
2069             (!mlx4_is_mfunc(dev) ||
2070              (dev_cap->fs_max_num_qp_per_entry >=
2071              (dev->persist->num_vfs + 1))) &&
2072             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2073                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2074                 dev->oper_log_mgm_entry_size =
2075                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
2076                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2077                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2078                 dev->caps.fs_log_max_ucast_qp_range_size =
2079                         dev_cap->fs_log_max_ucast_qp_range_size;
2080         } else {
2081                 if (dev->caps.dmfs_high_steer_mode !=
2082                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2083                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2084                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2085                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2086                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2087                 else {
2088                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2089
2090                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2091                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2092                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
2093                 }
2094                 dev->oper_log_mgm_entry_size =
2095                         mlx4_log_num_mgm_entry_size > 0 ?
2096                         mlx4_log_num_mgm_entry_size :
2097                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
2098                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2099         }
2100         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
2101                  mlx4_steering_mode_str(dev->caps.steering_mode),
2102                  dev->oper_log_mgm_entry_size,
2103                  mlx4_log_num_mgm_entry_size);
2104 }
2105
2106 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2107                                        struct mlx4_dev_cap *dev_cap)
2108 {
2109         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2110             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
2111                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2112         else
2113                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2114
2115         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
2116                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2117 }
2118
2119 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2120 {
2121         int i;
2122         struct mlx4_port_cap port_cap;
2123
2124         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2125                 return -EINVAL;
2126
2127         for (i = 1; i <= dev->caps.num_ports; i++) {
2128                 if (mlx4_dev_port(dev, i, &port_cap)) {
2129                         mlx4_err(dev,
2130                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2131                 } else if ((dev->caps.dmfs_high_steer_mode !=
2132                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
2133                            (port_cap.dmfs_optimized_state ==
2134                             !!(dev->caps.dmfs_high_steer_mode ==
2135                             MLX4_STEERING_DMFS_A0_DISABLE))) {
2136                         mlx4_err(dev,
2137                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2138                                  dmfs_high_rate_steering_mode_str(
2139                                         dev->caps.dmfs_high_steer_mode),
2140                                  (port_cap.dmfs_optimized_state ?
2141                                         "enabled" : "disabled"));
2142                 }
2143         }
2144
2145         return 0;
2146 }
2147
2148 static int mlx4_init_fw(struct mlx4_dev *dev)
2149 {
2150         struct mlx4_mod_stat_cfg   mlx4_cfg;
2151         int err = 0;
2152
2153         if (!mlx4_is_slave(dev)) {
2154                 err = mlx4_QUERY_FW(dev);
2155                 if (err) {
2156                         if (err == -EACCES)
2157                                 mlx4_info(dev, "non-primary physical function, skipping\n");
2158                         else
2159                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2160                         return err;
2161                 }
2162
2163                 err = mlx4_load_fw(dev);
2164                 if (err) {
2165                         mlx4_err(dev, "Failed to start FW, aborting\n");
2166                         return err;
2167                 }
2168
2169                 mlx4_cfg.log_pg_sz_m = 1;
2170                 mlx4_cfg.log_pg_sz = 0;
2171                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2172                 if (err)
2173                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2174         }
2175
2176         return err;
2177 }
2178
2179 static int mlx4_init_hca(struct mlx4_dev *dev)
2180 {
2181         struct mlx4_priv          *priv = mlx4_priv(dev);
2182         struct mlx4_adapter        adapter;
2183         struct mlx4_dev_cap        dev_cap;
2184         struct mlx4_profile        profile;
2185         struct mlx4_init_hca_param init_hca;
2186         u64 icm_size;
2187         struct mlx4_config_dev_params params;
2188         int err;
2189
2190         if (!mlx4_is_slave(dev)) {
2191                 err = mlx4_dev_cap(dev, &dev_cap);
2192                 if (err) {
2193                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2194                         return err;
2195                 }
2196
2197                 choose_steering_mode(dev, &dev_cap);
2198                 choose_tunnel_offload_mode(dev, &dev_cap);
2199
2200                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2201                     mlx4_is_master(dev))
2202                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2203
2204                 err = mlx4_get_phys_port_id(dev);
2205                 if (err)
2206                         mlx4_err(dev, "Fail to get physical port id\n");
2207
2208                 if (mlx4_is_master(dev))
2209                         mlx4_parav_master_pf_caps(dev);
2210
2211                 if (mlx4_low_memory_profile()) {
2212                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2213                         profile = low_mem_profile;
2214                 } else {
2215                         profile = default_profile;
2216                 }
2217                 if (dev->caps.steering_mode ==
2218                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2219                         profile.num_mcg = MLX4_FS_NUM_MCG;
2220
2221                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2222                                              &init_hca);
2223                 if ((long long) icm_size < 0) {
2224                         err = icm_size;
2225                         return err;
2226                 }
2227
2228                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2229
2230                 if (enable_4k_uar || !dev->persist->num_vfs) {
2231                         init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2232                                                     PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
2233                         init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2234                 } else {
2235                         init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2236                         init_hca.uar_page_sz = PAGE_SHIFT - 12;
2237                 }
2238
2239                 init_hca.mw_enabled = 0;
2240                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2241                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2242                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2243
2244                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2245                 if (err)
2246                         return err;
2247
2248                 err = mlx4_INIT_HCA(dev, &init_hca);
2249                 if (err) {
2250                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2251                         goto err_free_icm;
2252                 }
2253
2254                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2255                         err = mlx4_query_func(dev, &dev_cap);
2256                         if (err < 0) {
2257                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2258                                 goto err_close;
2259                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2260                                 dev->caps.num_eqs = dev_cap.max_eqs;
2261                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2262                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2263                         }
2264                 }
2265
2266                 /*
2267                  * If TS is supported by FW
2268                  * read HCA frequency by QUERY_HCA command
2269                  */
2270                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2271                         memset(&init_hca, 0, sizeof(init_hca));
2272                         err = mlx4_QUERY_HCA(dev, &init_hca);
2273                         if (err) {
2274                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2275                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2276                         } else {
2277                                 dev->caps.hca_core_clock =
2278                                         init_hca.hca_core_clock;
2279                         }
2280
2281                         /* In case we got HCA frequency 0 - disable timestamping
2282                          * to avoid dividing by zero
2283                          */
2284                         if (!dev->caps.hca_core_clock) {
2285                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2286                                 mlx4_err(dev,
2287                                          "HCA frequency is 0 - timestamping is not supported\n");
2288                         } else if (map_internal_clock(dev)) {
2289                                 /*
2290                                  * Map internal clock,
2291                                  * in case of failure disable timestamping
2292                                  */
2293                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2294                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2295                         }
2296                 }
2297
2298                 if (dev->caps.dmfs_high_steer_mode !=
2299                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2300                         if (mlx4_validate_optimized_steering(dev))
2301                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2302
2303                         if (dev->caps.dmfs_high_steer_mode ==
2304                             MLX4_STEERING_DMFS_A0_DISABLE) {
2305                                 dev->caps.dmfs_high_rate_qpn_base =
2306                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2307                                 dev->caps.dmfs_high_rate_qpn_range =
2308                                         MLX4_A0_STEERING_TABLE_SIZE;
2309                         }
2310
2311                         mlx4_info(dev, "DMFS high rate steer mode is: %s\n",
2312                                   dmfs_high_rate_steering_mode_str(
2313                                         dev->caps.dmfs_high_steer_mode));
2314                 }
2315         } else {
2316                 err = mlx4_init_slave(dev);
2317                 if (err) {
2318                         if (err != -EPROBE_DEFER)
2319                                 mlx4_err(dev, "Failed to initialize slave\n");
2320                         return err;
2321                 }
2322
2323                 err = mlx4_slave_cap(dev);
2324                 if (err) {
2325                         mlx4_err(dev, "Failed to obtain slave caps\n");
2326                         goto err_close;
2327                 }
2328         }
2329
2330         if (map_bf_area(dev))
2331                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2332
2333         /*Only the master set the ports, all the rest got it from it.*/
2334         if (!mlx4_is_slave(dev))
2335                 mlx4_set_port_mask(dev);
2336
2337         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2338         if (err) {
2339                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2340                 goto unmap_bf;
2341         }
2342
2343         /* Query CONFIG_DEV parameters */
2344         err = mlx4_config_dev_retrieval(dev, &params);
2345         if (err && err != -EOPNOTSUPP) {
2346                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2347         } else if (!err) {
2348                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2349                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2350         }
2351         priv->eq_table.inta_pin = adapter.inta_pin;
2352         memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id));
2353
2354         return 0;
2355
2356 unmap_bf:
2357         unmap_internal_clock(dev);
2358         unmap_bf_area(dev);
2359
2360         if (mlx4_is_slave(dev))
2361                 mlx4_slave_destroy_special_qp_cap(dev);
2362
2363 err_close:
2364         if (mlx4_is_slave(dev))
2365                 mlx4_slave_exit(dev);
2366         else
2367                 mlx4_CLOSE_HCA(dev, 0);
2368
2369 err_free_icm:
2370         if (!mlx4_is_slave(dev))
2371                 mlx4_free_icms(dev);
2372
2373         return err;
2374 }
2375
2376 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2377 {
2378         struct mlx4_priv *priv = mlx4_priv(dev);
2379         int nent_pow2;
2380
2381         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2382                 return -ENOENT;
2383
2384         if (!dev->caps.max_counters)
2385                 return -ENOSPC;
2386
2387         nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2388         /* reserve last counter index for sink counter */
2389         return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2390                                 nent_pow2 - 1, 0,
2391                                 nent_pow2 - dev->caps.max_counters + 1);
2392 }
2393
2394 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2395 {
2396         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2397                 return;
2398
2399         if (!dev->caps.max_counters)
2400                 return;
2401
2402         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2403 }
2404
2405 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2406 {
2407         struct mlx4_priv *priv = mlx4_priv(dev);
2408         int port;
2409
2410         for (port = 0; port < dev->caps.num_ports; port++)
2411                 if (priv->def_counter[port] != -1)
2412                         mlx4_counter_free(dev,  priv->def_counter[port]);
2413 }
2414
2415 static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2416 {
2417         struct mlx4_priv *priv = mlx4_priv(dev);
2418         int port, err = 0;
2419         u32 idx;
2420
2421         for (port = 0; port < dev->caps.num_ports; port++)
2422                 priv->def_counter[port] = -1;
2423
2424         for (port = 0; port < dev->caps.num_ports; port++) {
2425                 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER);
2426
2427                 if (!err || err == -ENOSPC) {
2428                         priv->def_counter[port] = idx;
2429                 } else if (err == -ENOENT) {
2430                         err = 0;
2431                         continue;
2432                 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2433                         priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2434                         mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2435                                   MLX4_SINK_COUNTER_INDEX(dev));
2436                         err = 0;
2437                 } else {
2438                         mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2439                                  __func__, port + 1, err);
2440                         mlx4_cleanup_default_counters(dev);
2441                         return err;
2442                 }
2443
2444                 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2445                          __func__, priv->def_counter[port], port + 1);
2446         }
2447
2448         return err;
2449 }
2450
2451 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2452 {
2453         struct mlx4_priv *priv = mlx4_priv(dev);
2454
2455         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2456                 return -ENOENT;
2457
2458         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2459         if (*idx == -1) {
2460                 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2461                 return -ENOSPC;
2462         }
2463
2464         return 0;
2465 }
2466
2467 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage)
2468 {
2469         u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30);
2470         u64 out_param;
2471         int err;
2472
2473         if (mlx4_is_mfunc(dev)) {
2474                 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier,
2475                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2476                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2477                 if (!err)
2478                         *idx = get_param_l(&out_param);
2479
2480                 return err;
2481         }
2482         return __mlx4_counter_alloc(dev, idx);
2483 }
2484 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2485
2486 static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2487                                 u8 counter_index)
2488 {
2489         struct mlx4_cmd_mailbox *if_stat_mailbox;
2490         int err;
2491         u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2492
2493         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2494         if (IS_ERR(if_stat_mailbox))
2495                 return PTR_ERR(if_stat_mailbox);
2496
2497         err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2498                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2499                            MLX4_CMD_NATIVE);
2500
2501         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2502         return err;
2503 }
2504
2505 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2506 {
2507         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2508                 return;
2509
2510         if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2511                 return;
2512
2513         __mlx4_clear_if_stat(dev, idx);
2514
2515         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2516         return;
2517 }
2518
2519 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2520 {
2521         u64 in_param = 0;
2522
2523         if (mlx4_is_mfunc(dev)) {
2524                 set_param_l(&in_param, idx);
2525                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2526                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2527                          MLX4_CMD_WRAPPED);
2528                 return;
2529         }
2530         __mlx4_counter_free(dev, idx);
2531 }
2532 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2533
2534 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2535 {
2536         struct mlx4_priv *priv = mlx4_priv(dev);
2537
2538         return priv->def_counter[port - 1];
2539 }
2540 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2541
2542 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2543 {
2544         struct mlx4_priv *priv = mlx4_priv(dev);
2545
2546         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2547 }
2548 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2549
2550 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2551 {
2552         struct mlx4_priv *priv = mlx4_priv(dev);
2553
2554         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2555 }
2556 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2557
2558 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2559 {
2560         struct mlx4_priv *priv = mlx4_priv(dev);
2561         __be64 guid;
2562
2563         /* hw GUID */
2564         if (entry == 0)
2565                 return;
2566
2567         get_random_bytes((char *)&guid, sizeof(guid));
2568         guid &= ~(cpu_to_be64(1ULL << 56));
2569         guid |= cpu_to_be64(1ULL << 57);
2570         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2571 }
2572
2573 static int mlx4_setup_hca(struct mlx4_dev *dev)
2574 {
2575         struct mlx4_priv *priv = mlx4_priv(dev);
2576         int err;
2577         int port;
2578         __be32 ib_port_default_caps;
2579
2580         err = mlx4_init_uar_table(dev);
2581         if (err) {
2582                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2583                 return err;
2584         }
2585
2586         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2587         if (err) {
2588                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2589                 goto err_uar_table_free;
2590         }
2591
2592         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2593         if (!priv->kar) {
2594                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2595                 err = -ENOMEM;
2596                 goto err_uar_free;
2597         }
2598
2599         err = mlx4_init_pd_table(dev);
2600         if (err) {
2601                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2602                 goto err_kar_unmap;
2603         }
2604
2605         err = mlx4_init_xrcd_table(dev);
2606         if (err) {
2607                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2608                 goto err_pd_table_free;
2609         }
2610
2611         err = mlx4_init_mr_table(dev);
2612         if (err) {
2613                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2614                 goto err_xrcd_table_free;
2615         }
2616
2617         if (!mlx4_is_slave(dev)) {
2618                 err = mlx4_init_mcg_table(dev);
2619                 if (err) {
2620                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2621                         goto err_mr_table_free;
2622                 }
2623                 err = mlx4_config_mad_demux(dev);
2624                 if (err) {
2625                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2626                         goto err_mcg_table_free;
2627                 }
2628         }
2629
2630         err = mlx4_init_eq_table(dev);
2631         if (err) {
2632                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2633                 goto err_mcg_table_free;
2634         }
2635
2636         err = mlx4_cmd_use_events(dev);
2637         if (err) {
2638                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2639                 goto err_eq_table_free;
2640         }
2641
2642         err = mlx4_NOP(dev);
2643         if (err) {
2644                 if (dev->flags & MLX4_FLAG_MSI_X) {
2645                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2646                                   priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2647                         mlx4_warn(dev, "Trying again without MSI-X\n");
2648                 } else {
2649                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2650                                  priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2651                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2652                 }
2653
2654                 goto err_cmd_poll;
2655         }
2656
2657         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2658
2659         err = mlx4_init_cq_table(dev);
2660         if (err) {
2661                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2662                 goto err_cmd_poll;
2663         }
2664
2665         err = mlx4_init_srq_table(dev);
2666         if (err) {
2667                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2668                 goto err_cq_table_free;
2669         }
2670
2671         err = mlx4_init_qp_table(dev);
2672         if (err) {
2673                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2674                 goto err_srq_table_free;
2675         }
2676
2677         if (!mlx4_is_slave(dev)) {
2678                 err = mlx4_init_counters_table(dev);
2679                 if (err && err != -ENOENT) {
2680                         mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2681                         goto err_qp_table_free;
2682                 }
2683         }
2684
2685         err = mlx4_allocate_default_counters(dev);
2686         if (err) {
2687                 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2688                 goto err_counters_table_free;
2689         }
2690
2691         if (!mlx4_is_slave(dev)) {
2692                 for (port = 1; port <= dev->caps.num_ports; port++) {
2693                         ib_port_default_caps = 0;
2694                         err = mlx4_get_port_ib_caps(dev, port,
2695                                                     &ib_port_default_caps);
2696                         if (err)
2697                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2698                                           port, err);
2699                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2700
2701                         /* initialize per-slave default ib port capabilities */
2702                         if (mlx4_is_master(dev)) {
2703                                 int i;
2704                                 for (i = 0; i < dev->num_slaves; i++) {
2705                                         if (i == mlx4_master_func_num(dev))
2706                                                 continue;
2707                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2708                                                 ib_port_default_caps;
2709                                 }
2710                         }
2711
2712                         if (mlx4_is_mfunc(dev))
2713                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2714                         else
2715                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2716
2717                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2718                                             dev->caps.pkey_table_len[port] : -1);
2719                         if (err) {
2720                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2721                                          port);
2722                                 goto err_default_countes_free;
2723                         }
2724                 }
2725         }
2726
2727         return 0;
2728
2729 err_default_countes_free:
2730         mlx4_cleanup_default_counters(dev);
2731
2732 err_counters_table_free:
2733         if (!mlx4_is_slave(dev))
2734                 mlx4_cleanup_counters_table(dev);
2735
2736 err_qp_table_free:
2737         mlx4_cleanup_qp_table(dev);
2738
2739 err_srq_table_free:
2740         mlx4_cleanup_srq_table(dev);
2741
2742 err_cq_table_free:
2743         mlx4_cleanup_cq_table(dev);
2744
2745 err_cmd_poll:
2746         mlx4_cmd_use_polling(dev);
2747
2748 err_eq_table_free:
2749         mlx4_cleanup_eq_table(dev);
2750
2751 err_mcg_table_free:
2752         if (!mlx4_is_slave(dev))
2753                 mlx4_cleanup_mcg_table(dev);
2754
2755 err_mr_table_free:
2756         mlx4_cleanup_mr_table(dev);
2757
2758 err_xrcd_table_free:
2759         mlx4_cleanup_xrcd_table(dev);
2760
2761 err_pd_table_free:
2762         mlx4_cleanup_pd_table(dev);
2763
2764 err_kar_unmap:
2765         iounmap(priv->kar);
2766
2767 err_uar_free:
2768         mlx4_uar_free(dev, &priv->driver_uar);
2769
2770 err_uar_table_free:
2771         mlx4_cleanup_uar_table(dev);
2772         return err;
2773 }
2774
2775 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2776 {
2777         int requested_cpu = 0;
2778         struct mlx4_priv *priv = mlx4_priv(dev);
2779         struct mlx4_eq *eq;
2780         int off = 0;
2781         int i;
2782
2783         if (eqn > dev->caps.num_comp_vectors)
2784                 return -EINVAL;
2785
2786         for (i = 1; i < port; i++)
2787                 off += mlx4_get_eqs_per_port(dev, i);
2788
2789         requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2790
2791         /* Meaning EQs are shared, and this call comes from the second port */
2792         if (requested_cpu < 0)
2793                 return 0;
2794
2795         eq = &priv->eq_table.eq[eqn];
2796
2797         if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2798                 return -ENOMEM;
2799
2800         cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2801
2802         return 0;
2803 }
2804
2805 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2806 {
2807         struct mlx4_priv *priv = mlx4_priv(dev);
2808         struct msix_entry *entries;
2809         int i;
2810         int port = 0;
2811
2812         if (msi_x) {
2813                 int nreq = min3(dev->caps.num_ports *
2814                                 (int)num_online_cpus() + 1,
2815                                 dev->caps.num_eqs - dev->caps.reserved_eqs,
2816                                 MAX_MSIX);
2817
2818                 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
2819                 if (!entries)
2820                         goto no_msi;
2821
2822                 for (i = 0; i < nreq; ++i)
2823                         entries[i].entry = i;
2824
2825                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2826                                              nreq);
2827
2828                 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2829                         kfree(entries);
2830                         goto no_msi;
2831                 }
2832                 /* 1 is reserved for events (asyncrounous EQ) */
2833                 dev->caps.num_comp_vectors = nreq - 1;
2834
2835                 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2836                 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2837                             dev->caps.num_ports);
2838
2839                 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2840                         if (i == MLX4_EQ_ASYNC)
2841                                 continue;
2842
2843                         priv->eq_table.eq[i].irq =
2844                                 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2845
2846                         if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2847                                 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2848                                             dev->caps.num_ports);
2849                                 /* We don't set affinity hint when there
2850                                  * aren't enough EQs
2851                                  */
2852                         } else {
2853                                 set_bit(port,
2854                                         priv->eq_table.eq[i].actv_ports.ports);
2855                                 if (mlx4_init_affinity_hint(dev, port + 1, i))
2856                                         mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2857                                                   i);
2858                         }
2859                         /* We divide the Eqs evenly between the two ports.
2860                          * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2861                          * refers to the number of Eqs per port
2862                          * (i.e eqs_per_port). Theoretically, we would like to
2863                          * write something like (i + 1) % eqs_per_port == 0.
2864                          * However, since there's an asynchronous Eq, we have
2865                          * to skip over it by comparing this condition to
2866                          * !!((i + 1) > MLX4_EQ_ASYNC).
2867                          */
2868                         if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2869                             ((i + 1) %
2870                              (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2871                             !!((i + 1) > MLX4_EQ_ASYNC))
2872                                 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2873                                  * everything is shared anyway.
2874                                  */
2875                                 port++;
2876                 }
2877
2878                 dev->flags |= MLX4_FLAG_MSI_X;
2879
2880                 kfree(entries);
2881                 return;
2882         }
2883
2884 no_msi:
2885         dev->caps.num_comp_vectors = 1;
2886
2887         BUG_ON(MLX4_EQ_ASYNC >= 2);
2888         for (i = 0; i < 2; ++i) {
2889                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2890                 if (i != MLX4_EQ_ASYNC) {
2891                         bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2892                                     dev->caps.num_ports);
2893                 }
2894         }
2895 }
2896
2897 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2898 {
2899         struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2900         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2901         int err;
2902
2903         err = devlink_port_register(devlink, &info->devlink_port, port);
2904         if (err)
2905                 return err;
2906
2907         info->dev = dev;
2908         info->port = port;
2909         if (!mlx4_is_slave(dev)) {
2910                 mlx4_init_mac_table(dev, &info->mac_table);
2911                 mlx4_init_vlan_table(dev, &info->vlan_table);
2912                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2913                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2914         }
2915
2916         sprintf(info->dev_name, "mlx4_port%d", port);
2917         info->port_attr.attr.name = info->dev_name;
2918         if (mlx4_is_mfunc(dev)) {
2919                 info->port_attr.attr.mode = 0444;
2920         } else {
2921                 info->port_attr.attr.mode = 0644;
2922                 info->port_attr.store     = set_port_type;
2923         }
2924         info->port_attr.show      = show_port_type;
2925         sysfs_attr_init(&info->port_attr.attr);
2926
2927         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2928         if (err) {
2929                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2930                 devlink_port_unregister(&info->devlink_port);
2931                 info->port = -1;
2932         }
2933
2934         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2935         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2936         if (mlx4_is_mfunc(dev)) {
2937                 info->port_mtu_attr.attr.mode = 0444;
2938         } else {
2939                 info->port_mtu_attr.attr.mode = 0644;
2940                 info->port_mtu_attr.store     = set_port_ib_mtu;
2941         }
2942         info->port_mtu_attr.show      = show_port_ib_mtu;
2943         sysfs_attr_init(&info->port_mtu_attr.attr);
2944
2945         err = device_create_file(&dev->persist->pdev->dev,
2946                                  &info->port_mtu_attr);
2947         if (err) {
2948                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2949                 device_remove_file(&info->dev->persist->pdev->dev,
2950                                    &info->port_attr);
2951                 devlink_port_unregister(&info->devlink_port);
2952                 info->port = -1;
2953         }
2954
2955         return err;
2956 }
2957
2958 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2959 {
2960         if (info->port < 0)
2961                 return;
2962
2963         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2964         device_remove_file(&info->dev->persist->pdev->dev,
2965                            &info->port_mtu_attr);
2966         devlink_port_unregister(&info->devlink_port);
2967
2968 #ifdef CONFIG_RFS_ACCEL
2969         free_irq_cpu_rmap(info->rmap);
2970         info->rmap = NULL;
2971 #endif
2972 }
2973
2974 static int mlx4_init_steering(struct mlx4_dev *dev)
2975 {
2976         struct mlx4_priv *priv = mlx4_priv(dev);
2977         int num_entries = dev->caps.num_ports;
2978         int i, j;
2979
2980         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2981         if (!priv->steer)
2982                 return -ENOMEM;
2983
2984         for (i = 0; i < num_entries; i++)
2985                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2986                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2987                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2988                 }
2989         return 0;
2990 }
2991
2992 static void mlx4_clear_steering(struct mlx4_dev *dev)
2993 {
2994         struct mlx4_priv *priv = mlx4_priv(dev);
2995         struct mlx4_steer_index *entry, *tmp_entry;
2996         struct mlx4_promisc_qp *pqp, *tmp_pqp;
2997         int num_entries = dev->caps.num_ports;
2998         int i, j;
2999
3000         for (i = 0; i < num_entries; i++) {
3001                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3002                         list_for_each_entry_safe(pqp, tmp_pqp,
3003                                                  &priv->steer[i].promisc_qps[j],
3004                                                  list) {
3005                                 list_del(&pqp->list);
3006                                 kfree(pqp);
3007                         }
3008                         list_for_each_entry_safe(entry, tmp_entry,
3009                                                  &priv->steer[i].steer_entries[j],
3010                                                  list) {
3011                                 list_del(&entry->list);
3012                                 list_for_each_entry_safe(pqp, tmp_pqp,
3013                                                          &entry->duplicates,
3014                                                          list) {
3015                                         list_del(&pqp->list);
3016                                         kfree(pqp);
3017                                 }
3018                                 kfree(entry);
3019                         }
3020                 }
3021         }
3022         kfree(priv->steer);
3023 }
3024
3025 static int extended_func_num(struct pci_dev *pdev)
3026 {
3027         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3028 }
3029
3030 #define MLX4_OWNER_BASE 0x8069c
3031 #define MLX4_OWNER_SIZE 4
3032
3033 static int mlx4_get_ownership(struct mlx4_dev *dev)
3034 {
3035         void __iomem *owner;
3036         u32 ret;
3037
3038         if (pci_channel_offline(dev->persist->pdev))
3039                 return -EIO;
3040
3041         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3042                         MLX4_OWNER_BASE,
3043                         MLX4_OWNER_SIZE);
3044         if (!owner) {
3045                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3046                 return -ENOMEM;
3047         }
3048
3049         ret = readl(owner);
3050         iounmap(owner);
3051         return (int) !!ret;
3052 }
3053
3054 static void mlx4_free_ownership(struct mlx4_dev *dev)
3055 {
3056         void __iomem *owner;
3057
3058         if (pci_channel_offline(dev->persist->pdev))
3059                 return;
3060
3061         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3062                         MLX4_OWNER_BASE,
3063                         MLX4_OWNER_SIZE);
3064         if (!owner) {
3065                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3066                 return;
3067         }
3068         writel(0, owner);
3069         msleep(1000);
3070         iounmap(owner);
3071 }
3072
3073 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3074                                   !!((flags) & MLX4_FLAG_MASTER))
3075
3076 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
3077                              u8 total_vfs, int existing_vfs, int reset_flow)
3078 {
3079         u64 dev_flags = dev->flags;
3080         int err = 0;
3081         int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3082                                         MLX4_MAX_NUM_VF);
3083
3084         if (reset_flow) {
3085                 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3086                                        GFP_KERNEL);
3087                 if (!dev->dev_vfs)
3088                         goto free_mem;
3089                 return dev_flags;
3090         }
3091
3092         atomic_inc(&pf_loading);
3093         if (dev->flags &  MLX4_FLAG_SRIOV) {
3094                 if (existing_vfs != total_vfs) {
3095                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3096                                  existing_vfs, total_vfs);
3097                         total_vfs = existing_vfs;
3098                 }
3099         }
3100
3101         dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
3102         if (NULL == dev->dev_vfs) {
3103                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3104                 goto disable_sriov;
3105         }