Merge remote-tracking branch 'lorenzo/pci/cadence' into next
[muen/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "eswitch.h"
39 #include "en.h"
40 #include "en_tc.h"
41 #include "en_rep.h"
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
45 #include "vxlan.h"
46
47 struct mlx5e_rq_param {
48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
49         struct mlx5_wq_param    wq;
50 };
51
52 struct mlx5e_sq_param {
53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
54         struct mlx5_wq_param       wq;
55 };
56
57 struct mlx5e_cq_param {
58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
59         struct mlx5_wq_param       wq;
60         u16                        eq_ix;
61         u8                         cq_period_mode;
62 };
63
64 struct mlx5e_channel_param {
65         struct mlx5e_rq_param      rq;
66         struct mlx5e_sq_param      sq;
67         struct mlx5e_sq_param      xdp_sq;
68         struct mlx5e_sq_param      icosq;
69         struct mlx5e_cq_param      rx_cq;
70         struct mlx5e_cq_param      tx_cq;
71         struct mlx5e_cq_param      icosq_cq;
72 };
73
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75 {
76         return MLX5_CAP_GEN(mdev, striding_rq) &&
77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
79 }
80
81 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
82                                struct mlx5e_params *params, u8 rq_type)
83 {
84         params->rq_wq_type = rq_type;
85         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86         switch (params->rq_wq_type) {
87         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
88                 params->log_rq_size = is_kdump_kernel() ?
89                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
91                 params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,
92                         MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
93                 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
94                         params->mpwqe_log_stride_sz;
95                 break;
96         default: /* MLX5_WQ_TYPE_LINKED_LIST */
97                 params->log_rq_size = is_kdump_kernel() ?
98                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
99                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
100                 params->rq_headroom = params->xdp_prog ?
101                         XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
102                 params->rq_headroom += NET_IP_ALIGN;
103
104                 /* Extra room needed for build_skb */
105                 params->lro_wqe_sz -= params->rq_headroom +
106                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
107         }
108
109         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
111                        BIT(params->log_rq_size),
112                        BIT(params->mpwqe_log_stride_sz),
113                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
114 }
115
116 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,
117                                 struct mlx5e_params *params)
118 {
119         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
120                     !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
121                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
122                     MLX5_WQ_TYPE_LINKED_LIST;
123         mlx5e_init_rq_type_params(mdev, params, rq_type);
124 }
125
126 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
127 {
128         struct mlx5_core_dev *mdev = priv->mdev;
129         u8 port_state;
130
131         port_state = mlx5_query_vport_state(mdev,
132                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
133                                             0);
134
135         if (port_state == VPORT_STATE_UP) {
136                 netdev_info(priv->netdev, "Link up\n");
137                 netif_carrier_on(priv->netdev);
138         } else {
139                 netdev_info(priv->netdev, "Link down\n");
140                 netif_carrier_off(priv->netdev);
141         }
142 }
143
144 static void mlx5e_update_carrier_work(struct work_struct *work)
145 {
146         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147                                                update_carrier_work);
148
149         mutex_lock(&priv->state_lock);
150         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
151                 if (priv->profile->update_carrier)
152                         priv->profile->update_carrier(priv);
153         mutex_unlock(&priv->state_lock);
154 }
155
156 static void mlx5e_tx_timeout_work(struct work_struct *work)
157 {
158         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
159                                                tx_timeout_work);
160         int err;
161
162         rtnl_lock();
163         mutex_lock(&priv->state_lock);
164         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
165                 goto unlock;
166         mlx5e_close_locked(priv->netdev);
167         err = mlx5e_open_locked(priv->netdev);
168         if (err)
169                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
170                            err);
171 unlock:
172         mutex_unlock(&priv->state_lock);
173         rtnl_unlock();
174 }
175
176 void mlx5e_update_stats(struct mlx5e_priv *priv)
177 {
178         int i;
179
180         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
181                 if (mlx5e_stats_grps[i].update_stats)
182                         mlx5e_stats_grps[i].update_stats(priv);
183 }
184
185 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
186 {
187         int i;
188
189         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
190                 if (mlx5e_stats_grps[i].update_stats_mask &
191                     MLX5E_NDO_UPDATE_STATS)
192                         mlx5e_stats_grps[i].update_stats(priv);
193 }
194
195 void mlx5e_update_stats_work(struct work_struct *work)
196 {
197         struct delayed_work *dwork = to_delayed_work(work);
198         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
199                                                update_stats_work);
200         mutex_lock(&priv->state_lock);
201         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
202                 priv->profile->update_stats(priv);
203                 queue_delayed_work(priv->wq, dwork,
204                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
205         }
206         mutex_unlock(&priv->state_lock);
207 }
208
209 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
210                               enum mlx5_dev_event event, unsigned long param)
211 {
212         struct mlx5e_priv *priv = vpriv;
213
214         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
215                 return;
216
217         switch (event) {
218         case MLX5_DEV_EVENT_PORT_UP:
219         case MLX5_DEV_EVENT_PORT_DOWN:
220                 queue_work(priv->wq, &priv->update_carrier_work);
221                 break;
222         default:
223                 break;
224         }
225 }
226
227 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
228 {
229         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
230 }
231
232 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
233 {
234         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
235         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
236 }
237
238 static inline int mlx5e_get_wqe_mtt_sz(void)
239 {
240         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
241          * To avoid copying garbage after the mtt array, we allocate
242          * a little more.
243          */
244         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
245                      MLX5_UMR_MTT_ALIGNMENT);
246 }
247
248 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
249                                        struct mlx5e_icosq *sq,
250                                        struct mlx5e_umr_wqe *wqe,
251                                        u16 ix)
252 {
253         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
254         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
255         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
256         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
257         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
258         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
259
260         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
261                                       ds_cnt);
262         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
263         cseg->imm       = rq->mkey_be;
264
265         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
266         ucseg->xlt_octowords =
267                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
268         ucseg->bsf_octowords =
269                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
270         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
271
272         dseg->lkey = sq->mkey_be;
273         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
274 }
275
276 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
277                                      struct mlx5e_channel *c)
278 {
279         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
280         int mtt_sz = mlx5e_get_wqe_mtt_sz();
281         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
282         int i;
283
284         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
285                                       GFP_KERNEL, cpu_to_node(c->cpu));
286         if (!rq->mpwqe.info)
287                 goto err_out;
288
289         /* We allocate more than mtt_sz as we will align the pointer */
290         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
291                                         cpu_to_node(c->cpu));
292         if (unlikely(!rq->mpwqe.mtt_no_align))
293                 goto err_free_wqe_info;
294
295         for (i = 0; i < wq_sz; i++) {
296                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
297
298                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
299                                         MLX5_UMR_ALIGN);
300                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
301                                                   PCI_DMA_TODEVICE);
302                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
303                         goto err_unmap_mtts;
304
305                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
306         }
307
308         return 0;
309
310 err_unmap_mtts:
311         while (--i >= 0) {
312                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
313
314                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
315                                  PCI_DMA_TODEVICE);
316         }
317         kfree(rq->mpwqe.mtt_no_align);
318 err_free_wqe_info:
319         kfree(rq->mpwqe.info);
320
321 err_out:
322         return -ENOMEM;
323 }
324
325 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
326 {
327         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
328         int mtt_sz = mlx5e_get_wqe_mtt_sz();
329         int i;
330
331         for (i = 0; i < wq_sz; i++) {
332                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
333
334                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
335                                  PCI_DMA_TODEVICE);
336         }
337         kfree(rq->mpwqe.mtt_no_align);
338         kfree(rq->mpwqe.info);
339 }
340
341 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
342                                  u64 npages, u8 page_shift,
343                                  struct mlx5_core_mkey *umr_mkey)
344 {
345         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
346         void *mkc;
347         u32 *in;
348         int err;
349
350         if (!MLX5E_VALID_NUM_MTTS(npages))
351                 return -EINVAL;
352
353         in = kvzalloc(inlen, GFP_KERNEL);
354         if (!in)
355                 return -ENOMEM;
356
357         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
358
359         MLX5_SET(mkc, mkc, free, 1);
360         MLX5_SET(mkc, mkc, umr_en, 1);
361         MLX5_SET(mkc, mkc, lw, 1);
362         MLX5_SET(mkc, mkc, lr, 1);
363         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
364
365         MLX5_SET(mkc, mkc, qpn, 0xffffff);
366         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
367         MLX5_SET64(mkc, mkc, len, npages << page_shift);
368         MLX5_SET(mkc, mkc, translations_octword_size,
369                  MLX5_MTT_OCTW(npages));
370         MLX5_SET(mkc, mkc, log_page_size, page_shift);
371
372         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
373
374         kvfree(in);
375         return err;
376 }
377
378 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
379 {
380         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
381
382         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
383 }
384
385 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
386                           struct mlx5e_params *params,
387                           struct mlx5e_rq_param *rqp,
388                           struct mlx5e_rq *rq)
389 {
390         struct mlx5_core_dev *mdev = c->mdev;
391         void *rqc = rqp->rqc;
392         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
393         u32 byte_count;
394         int npages;
395         int wq_sz;
396         int err;
397         int i;
398
399         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
400
401         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
402                                 &rq->wq_ctrl);
403         if (err)
404                 return err;
405
406         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
407
408         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
409
410         rq->wq_type = params->rq_wq_type;
411         rq->pdev    = c->pdev;
412         rq->netdev  = c->netdev;
413         rq->tstamp  = c->tstamp;
414         rq->clock   = &mdev->clock;
415         rq->channel = c;
416         rq->ix      = c->ix;
417         rq->mdev    = mdev;
418
419         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
420         if (IS_ERR(rq->xdp_prog)) {
421                 err = PTR_ERR(rq->xdp_prog);
422                 rq->xdp_prog = NULL;
423                 goto err_rq_wq_destroy;
424         }
425
426         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
427         if (err < 0)
428                 goto err_rq_wq_destroy;
429
430         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
431         rq->buff.headroom = params->rq_headroom;
432
433         switch (rq->wq_type) {
434         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
435
436                 rq->post_wqes = mlx5e_post_rx_mpwqes;
437                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
438
439                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
440 #ifdef CONFIG_MLX5_EN_IPSEC
441                 if (MLX5_IPSEC_DEV(mdev)) {
442                         err = -EINVAL;
443                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
444                         goto err_rq_wq_destroy;
445                 }
446 #endif
447                 if (!rq->handle_rx_cqe) {
448                         err = -EINVAL;
449                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
450                         goto err_rq_wq_destroy;
451                 }
452
453                 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
454                 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
455
456                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
457
458                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
459                 if (err)
460                         goto err_rq_wq_destroy;
461                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
462
463                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
464                 if (err)
465                         goto err_destroy_umr_mkey;
466                 break;
467         default: /* MLX5_WQ_TYPE_LINKED_LIST */
468                 rq->wqe.frag_info =
469                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
470                                      GFP_KERNEL, cpu_to_node(c->cpu));
471                 if (!rq->wqe.frag_info) {
472                         err = -ENOMEM;
473                         goto err_rq_wq_destroy;
474                 }
475                 rq->post_wqes = mlx5e_post_rx_wqes;
476                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
477
478 #ifdef CONFIG_MLX5_EN_IPSEC
479                 if (c->priv->ipsec)
480                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
481                 else
482 #endif
483                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
484                 if (!rq->handle_rx_cqe) {
485                         kfree(rq->wqe.frag_info);
486                         err = -EINVAL;
487                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
488                         goto err_rq_wq_destroy;
489                 }
490
491                 byte_count = params->lro_en  ?
492                                 params->lro_wqe_sz :
493                                 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
494 #ifdef CONFIG_MLX5_EN_IPSEC
495                 if (MLX5_IPSEC_DEV(mdev))
496                         byte_count += MLX5E_METADATA_ETHER_LEN;
497 #endif
498                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
499
500                 /* calc the required page order */
501                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
502                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
503                 rq->buff.page_order = order_base_2(npages);
504
505                 byte_count |= MLX5_HW_START_PADDING;
506                 rq->mkey_be = c->mkey_be;
507         }
508
509         for (i = 0; i < wq_sz; i++) {
510                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
511
512                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
513                         u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
514
515                         wqe->data.addr = cpu_to_be64(dma_offset);
516                 }
517
518                 wqe->data.byte_count = cpu_to_be32(byte_count);
519                 wqe->data.lkey = rq->mkey_be;
520         }
521
522         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
523
524         switch (params->rx_cq_moderation.cq_period_mode) {
525         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
526                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
527                 break;
528         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
529         default:
530                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
531         }
532
533         rq->page_cache.head = 0;
534         rq->page_cache.tail = 0;
535
536         return 0;
537
538 err_destroy_umr_mkey:
539         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
540
541 err_rq_wq_destroy:
542         if (rq->xdp_prog)
543                 bpf_prog_put(rq->xdp_prog);
544         xdp_rxq_info_unreg(&rq->xdp_rxq);
545         mlx5_wq_destroy(&rq->wq_ctrl);
546
547         return err;
548 }
549
550 static void mlx5e_free_rq(struct mlx5e_rq *rq)
551 {
552         int i;
553
554         if (rq->xdp_prog)
555                 bpf_prog_put(rq->xdp_prog);
556
557         xdp_rxq_info_unreg(&rq->xdp_rxq);
558
559         switch (rq->wq_type) {
560         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
561                 mlx5e_rq_free_mpwqe_info(rq);
562                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
563                 break;
564         default: /* MLX5_WQ_TYPE_LINKED_LIST */
565                 kfree(rq->wqe.frag_info);
566         }
567
568         for (i = rq->page_cache.head; i != rq->page_cache.tail;
569              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
570                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
571
572                 mlx5e_page_release(rq, dma_info, false);
573         }
574         mlx5_wq_destroy(&rq->wq_ctrl);
575 }
576
577 static int mlx5e_create_rq(struct mlx5e_rq *rq,
578                            struct mlx5e_rq_param *param)
579 {
580         struct mlx5_core_dev *mdev = rq->mdev;
581
582         void *in;
583         void *rqc;
584         void *wq;
585         int inlen;
586         int err;
587
588         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
589                 sizeof(u64) * rq->wq_ctrl.buf.npages;
590         in = kvzalloc(inlen, GFP_KERNEL);
591         if (!in)
592                 return -ENOMEM;
593
594         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
595         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
596
597         memcpy(rqc, param->rqc, sizeof(param->rqc));
598
599         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
600         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
601         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
602                                                 MLX5_ADAPTER_PAGE_SHIFT);
603         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
604
605         mlx5_fill_page_array(&rq->wq_ctrl.buf,
606                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
607
608         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
609
610         kvfree(in);
611
612         return err;
613 }
614
615 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
616                                  int next_state)
617 {
618         struct mlx5e_channel *c = rq->channel;
619         struct mlx5_core_dev *mdev = c->mdev;
620
621         void *in;
622         void *rqc;
623         int inlen;
624         int err;
625
626         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
627         in = kvzalloc(inlen, GFP_KERNEL);
628         if (!in)
629                 return -ENOMEM;
630
631         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
632
633         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
634         MLX5_SET(rqc, rqc, state, next_state);
635
636         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
637
638         kvfree(in);
639
640         return err;
641 }
642
643 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
644 {
645         struct mlx5e_channel *c = rq->channel;
646         struct mlx5e_priv *priv = c->priv;
647         struct mlx5_core_dev *mdev = priv->mdev;
648
649         void *in;
650         void *rqc;
651         int inlen;
652         int err;
653
654         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
655         in = kvzalloc(inlen, GFP_KERNEL);
656         if (!in)
657                 return -ENOMEM;
658
659         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
660
661         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
662         MLX5_SET64(modify_rq_in, in, modify_bitmask,
663                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
664         MLX5_SET(rqc, rqc, scatter_fcs, enable);
665         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
666
667         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
668
669         kvfree(in);
670
671         return err;
672 }
673
674 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
675 {
676         struct mlx5e_channel *c = rq->channel;
677         struct mlx5_core_dev *mdev = c->mdev;
678         void *in;
679         void *rqc;
680         int inlen;
681         int err;
682
683         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
684         in = kvzalloc(inlen, GFP_KERNEL);
685         if (!in)
686                 return -ENOMEM;
687
688         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
689
690         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
691         MLX5_SET64(modify_rq_in, in, modify_bitmask,
692                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
693         MLX5_SET(rqc, rqc, vsd, vsd);
694         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
695
696         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
697
698         kvfree(in);
699
700         return err;
701 }
702
703 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
704 {
705         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
706 }
707
708 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
709 {
710         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
711         struct mlx5e_channel *c = rq->channel;
712
713         struct mlx5_wq_ll *wq = &rq->wq;
714         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
715
716         while (time_before(jiffies, exp_time)) {
717                 if (wq->cur_sz >= min_wqes)
718                         return 0;
719
720                 msleep(20);
721         }
722
723         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
724                     rq->rqn, wq->cur_sz, min_wqes);
725         return -ETIMEDOUT;
726 }
727
728 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
729 {
730         struct mlx5_wq_ll *wq = &rq->wq;
731         struct mlx5e_rx_wqe *wqe;
732         __be16 wqe_ix_be;
733         u16 wqe_ix;
734
735         /* UMR WQE (if in progress) is always at wq->head */
736         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
737             rq->mpwqe.umr_in_progress)
738                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
739
740         while (!mlx5_wq_ll_is_empty(wq)) {
741                 wqe_ix_be = *wq->tail_next;
742                 wqe_ix    = be16_to_cpu(wqe_ix_be);
743                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
744                 rq->dealloc_wqe(rq, wqe_ix);
745                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
746                                &wqe->next.next_wqe_index);
747         }
748
749         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
750                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
751                  * but yet to be re-posted.
752                  */
753                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
754
755                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
756                         rq->dealloc_wqe(rq, wqe_ix);
757         }
758 }
759
760 static int mlx5e_open_rq(struct mlx5e_channel *c,
761                          struct mlx5e_params *params,
762                          struct mlx5e_rq_param *param,
763                          struct mlx5e_rq *rq)
764 {
765         int err;
766
767         err = mlx5e_alloc_rq(c, params, param, rq);
768         if (err)
769                 return err;
770
771         err = mlx5e_create_rq(rq, param);
772         if (err)
773                 goto err_free_rq;
774
775         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
776         if (err)
777                 goto err_destroy_rq;
778
779         if (params->rx_dim_enabled)
780                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
781
782         return 0;
783
784 err_destroy_rq:
785         mlx5e_destroy_rq(rq);
786 err_free_rq:
787         mlx5e_free_rq(rq);
788
789         return err;
790 }
791
792 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
793 {
794         struct mlx5e_icosq *sq = &rq->channel->icosq;
795         u16 pi = sq->pc & sq->wq.sz_m1;
796         struct mlx5e_tx_wqe *nopwqe;
797
798         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
799         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
800         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
801         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
802 }
803
804 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
805 {
806         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
807         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
808 }
809
810 static void mlx5e_close_rq(struct mlx5e_rq *rq)
811 {
812         cancel_work_sync(&rq->dim.work);
813         mlx5e_destroy_rq(rq);
814         mlx5e_free_rx_descs(rq);
815         mlx5e_free_rq(rq);
816 }
817
818 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
819 {
820         kfree(sq->db.di);
821 }
822
823 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
824 {
825         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
826
827         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
828                                      GFP_KERNEL, numa);
829         if (!sq->db.di) {
830                 mlx5e_free_xdpsq_db(sq);
831                 return -ENOMEM;
832         }
833
834         return 0;
835 }
836
837 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
838                              struct mlx5e_params *params,
839                              struct mlx5e_sq_param *param,
840                              struct mlx5e_xdpsq *sq)
841 {
842         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
843         struct mlx5_core_dev *mdev = c->mdev;
844         int err;
845
846         sq->pdev      = c->pdev;
847         sq->mkey_be   = c->mkey_be;
848         sq->channel   = c;
849         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
850         sq->min_inline_mode = params->tx_min_inline_mode;
851
852         param->wq.db_numa_node = cpu_to_node(c->cpu);
853         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
854         if (err)
855                 return err;
856         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
857
858         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
859         if (err)
860                 goto err_sq_wq_destroy;
861
862         return 0;
863
864 err_sq_wq_destroy:
865         mlx5_wq_destroy(&sq->wq_ctrl);
866
867         return err;
868 }
869
870 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
871 {
872         mlx5e_free_xdpsq_db(sq);
873         mlx5_wq_destroy(&sq->wq_ctrl);
874 }
875
876 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
877 {
878         kfree(sq->db.ico_wqe);
879 }
880
881 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
882 {
883         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
884
885         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
886                                       GFP_KERNEL, numa);
887         if (!sq->db.ico_wqe)
888                 return -ENOMEM;
889
890         return 0;
891 }
892
893 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
894                              struct mlx5e_sq_param *param,
895                              struct mlx5e_icosq *sq)
896 {
897         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
898         struct mlx5_core_dev *mdev = c->mdev;
899         int err;
900
901         sq->mkey_be   = c->mkey_be;
902         sq->channel   = c;
903         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
904
905         param->wq.db_numa_node = cpu_to_node(c->cpu);
906         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
907         if (err)
908                 return err;
909         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
910
911         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
912         if (err)
913                 goto err_sq_wq_destroy;
914
915         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
916
917         return 0;
918
919 err_sq_wq_destroy:
920         mlx5_wq_destroy(&sq->wq_ctrl);
921
922         return err;
923 }
924
925 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
926 {
927         mlx5e_free_icosq_db(sq);
928         mlx5_wq_destroy(&sq->wq_ctrl);
929 }
930
931 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
932 {
933         kfree(sq->db.wqe_info);
934         kfree(sq->db.dma_fifo);
935 }
936
937 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
938 {
939         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
940         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
941
942         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
943                                            GFP_KERNEL, numa);
944         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
945                                            GFP_KERNEL, numa);
946         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
947                 mlx5e_free_txqsq_db(sq);
948                 return -ENOMEM;
949         }
950
951         sq->dma_fifo_mask = df_sz - 1;
952
953         return 0;
954 }
955
956 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
957                              int txq_ix,
958                              struct mlx5e_params *params,
959                              struct mlx5e_sq_param *param,
960                              struct mlx5e_txqsq *sq)
961 {
962         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
963         struct mlx5_core_dev *mdev = c->mdev;
964         int err;
965
966         sq->pdev      = c->pdev;
967         sq->tstamp    = c->tstamp;
968         sq->clock     = &mdev->clock;
969         sq->mkey_be   = c->mkey_be;
970         sq->channel   = c;
971         sq->txq_ix    = txq_ix;
972         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
973         sq->max_inline      = params->tx_max_inline;
974         sq->min_inline_mode = params->tx_min_inline_mode;
975         if (MLX5_IPSEC_DEV(c->priv->mdev))
976                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
977
978         param->wq.db_numa_node = cpu_to_node(c->cpu);
979         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
980         if (err)
981                 return err;
982         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
983
984         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
985         if (err)
986                 goto err_sq_wq_destroy;
987
988         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
989
990         return 0;
991
992 err_sq_wq_destroy:
993         mlx5_wq_destroy(&sq->wq_ctrl);
994
995         return err;
996 }
997
998 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
999 {
1000         mlx5e_free_txqsq_db(sq);
1001         mlx5_wq_destroy(&sq->wq_ctrl);
1002 }
1003
1004 struct mlx5e_create_sq_param {
1005         struct mlx5_wq_ctrl        *wq_ctrl;
1006         u32                         cqn;
1007         u32                         tisn;
1008         u8                          tis_lst_sz;
1009         u8                          min_inline_mode;
1010 };
1011
1012 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1013                            struct mlx5e_sq_param *param,
1014                            struct mlx5e_create_sq_param *csp,
1015                            u32 *sqn)
1016 {
1017         void *in;
1018         void *sqc;
1019         void *wq;
1020         int inlen;
1021         int err;
1022
1023         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1024                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1025         in = kvzalloc(inlen, GFP_KERNEL);
1026         if (!in)
1027                 return -ENOMEM;
1028
1029         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1030         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1031
1032         memcpy(sqc, param->sqc, sizeof(param->sqc));
1033         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1034         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1035         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1036
1037         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1038                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1039
1040         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1041
1042         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1043         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1044         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1045                                           MLX5_ADAPTER_PAGE_SHIFT);
1046         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1047
1048         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1049
1050         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1051
1052         kvfree(in);
1053
1054         return err;
1055 }
1056
1057 struct mlx5e_modify_sq_param {
1058         int curr_state;
1059         int next_state;
1060         bool rl_update;
1061         int rl_index;
1062 };
1063
1064 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1065                            struct mlx5e_modify_sq_param *p)
1066 {
1067         void *in;
1068         void *sqc;
1069         int inlen;
1070         int err;
1071
1072         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1073         in = kvzalloc(inlen, GFP_KERNEL);
1074         if (!in)
1075                 return -ENOMEM;
1076
1077         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1078
1079         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1080         MLX5_SET(sqc, sqc, state, p->next_state);
1081         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1082                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1083                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1084         }
1085
1086         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1087
1088         kvfree(in);
1089
1090         return err;
1091 }
1092
1093 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1094 {
1095         mlx5_core_destroy_sq(mdev, sqn);
1096 }
1097
1098 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1099                                struct mlx5e_sq_param *param,
1100                                struct mlx5e_create_sq_param *csp,
1101                                u32 *sqn)
1102 {
1103         struct mlx5e_modify_sq_param msp = {0};
1104         int err;
1105
1106         err = mlx5e_create_sq(mdev, param, csp, sqn);
1107         if (err)
1108                 return err;
1109
1110         msp.curr_state = MLX5_SQC_STATE_RST;
1111         msp.next_state = MLX5_SQC_STATE_RDY;
1112         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1113         if (err)
1114                 mlx5e_destroy_sq(mdev, *sqn);
1115
1116         return err;
1117 }
1118
1119 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1120                                 struct mlx5e_txqsq *sq, u32 rate);
1121
1122 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1123                             u32 tisn,
1124                             int txq_ix,
1125                             struct mlx5e_params *params,
1126                             struct mlx5e_sq_param *param,
1127                             struct mlx5e_txqsq *sq)
1128 {
1129         struct mlx5e_create_sq_param csp = {};
1130         u32 tx_rate;
1131         int err;
1132
1133         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1134         if (err)
1135                 return err;
1136
1137         csp.tisn            = tisn;
1138         csp.tis_lst_sz      = 1;
1139         csp.cqn             = sq->cq.mcq.cqn;
1140         csp.wq_ctrl         = &sq->wq_ctrl;
1141         csp.min_inline_mode = sq->min_inline_mode;
1142         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1143         if (err)
1144                 goto err_free_txqsq;
1145
1146         tx_rate = c->priv->tx_rates[sq->txq_ix];
1147         if (tx_rate)
1148                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1149
1150         return 0;
1151
1152 err_free_txqsq:
1153         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1154         mlx5e_free_txqsq(sq);
1155
1156         return err;
1157 }
1158
1159 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1160 {
1161         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1162         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1163         netdev_tx_reset_queue(sq->txq);
1164         netif_tx_start_queue(sq->txq);
1165 }
1166
1167 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1168 {
1169         __netif_tx_lock_bh(txq);
1170         netif_tx_stop_queue(txq);
1171         __netif_tx_unlock_bh(txq);
1172 }
1173
1174 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1175 {
1176         struct mlx5e_channel *c = sq->channel;
1177
1178         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1179         /* prevent netif_tx_wake_queue */
1180         napi_synchronize(&c->napi);
1181
1182         netif_tx_disable_queue(sq->txq);
1183
1184         /* last doorbell out, godspeed .. */
1185         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1186                 struct mlx5e_tx_wqe *nop;
1187
1188                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1189                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1190                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1191         }
1192 }
1193
1194 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1195 {
1196         struct mlx5e_channel *c = sq->channel;
1197         struct mlx5_core_dev *mdev = c->mdev;
1198
1199         mlx5e_destroy_sq(mdev, sq->sqn);
1200         if (sq->rate_limit)
1201                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1202         mlx5e_free_txqsq_descs(sq);
1203         mlx5e_free_txqsq(sq);
1204 }
1205
1206 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1207                             struct mlx5e_params *params,
1208                             struct mlx5e_sq_param *param,
1209                             struct mlx5e_icosq *sq)
1210 {
1211         struct mlx5e_create_sq_param csp = {};
1212         int err;
1213
1214         err = mlx5e_alloc_icosq(c, param, sq);
1215         if (err)
1216                 return err;
1217
1218         csp.cqn             = sq->cq.mcq.cqn;
1219         csp.wq_ctrl         = &sq->wq_ctrl;
1220         csp.min_inline_mode = params->tx_min_inline_mode;
1221         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1222         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1223         if (err)
1224                 goto err_free_icosq;
1225
1226         return 0;
1227
1228 err_free_icosq:
1229         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1230         mlx5e_free_icosq(sq);
1231
1232         return err;
1233 }
1234
1235 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1236 {
1237         struct mlx5e_channel *c = sq->channel;
1238
1239         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1240         napi_synchronize(&c->napi);
1241
1242         mlx5e_destroy_sq(c->mdev, sq->sqn);
1243         mlx5e_free_icosq(sq);
1244 }
1245
1246 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1247                             struct mlx5e_params *params,
1248                             struct mlx5e_sq_param *param,
1249                             struct mlx5e_xdpsq *sq)
1250 {
1251         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1252         struct mlx5e_create_sq_param csp = {};
1253         unsigned int inline_hdr_sz = 0;
1254         int err;
1255         int i;
1256
1257         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1258         if (err)
1259                 return err;
1260
1261         csp.tis_lst_sz      = 1;
1262         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1263         csp.cqn             = sq->cq.mcq.cqn;
1264         csp.wq_ctrl         = &sq->wq_ctrl;
1265         csp.min_inline_mode = sq->min_inline_mode;
1266         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1267         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1268         if (err)
1269                 goto err_free_xdpsq;
1270
1271         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1272                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1273                 ds_cnt++;
1274         }
1275
1276         /* Pre initialize fixed WQE fields */
1277         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1278                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1279                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1280                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1281                 struct mlx5_wqe_data_seg *dseg;
1282
1283                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1284                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1285
1286                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1287                 dseg->lkey = sq->mkey_be;
1288         }
1289
1290         return 0;
1291
1292 err_free_xdpsq:
1293         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1294         mlx5e_free_xdpsq(sq);
1295
1296         return err;
1297 }
1298
1299 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1300 {
1301         struct mlx5e_channel *c = sq->channel;
1302
1303         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1304         napi_synchronize(&c->napi);
1305
1306         mlx5e_destroy_sq(c->mdev, sq->sqn);
1307         mlx5e_free_xdpsq_descs(sq);
1308         mlx5e_free_xdpsq(sq);
1309 }
1310
1311 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1312                                  struct mlx5e_cq_param *param,
1313                                  struct mlx5e_cq *cq)
1314 {
1315         struct mlx5_core_cq *mcq = &cq->mcq;
1316         int eqn_not_used;
1317         unsigned int irqn;
1318         int err;
1319         u32 i;
1320
1321         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1322                                &cq->wq_ctrl);
1323         if (err)
1324                 return err;
1325
1326         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1327
1328         mcq->cqe_sz     = 64;
1329         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1330         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1331         *mcq->set_ci_db = 0;
1332         *mcq->arm_db    = 0;
1333         mcq->vector     = param->eq_ix;
1334         mcq->comp       = mlx5e_completion_event;
1335         mcq->event      = mlx5e_cq_error_event;
1336         mcq->irqn       = irqn;
1337
1338         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1339                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1340
1341                 cqe->op_own = 0xf1;
1342         }
1343
1344         cq->mdev = mdev;
1345
1346         return 0;
1347 }
1348
1349 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1350                           struct mlx5e_cq_param *param,
1351                           struct mlx5e_cq *cq)
1352 {
1353         struct mlx5_core_dev *mdev = c->priv->mdev;
1354         int err;
1355
1356         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1357         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1358         param->eq_ix   = c->ix;
1359
1360         err = mlx5e_alloc_cq_common(mdev, param, cq);
1361
1362         cq->napi    = &c->napi;
1363         cq->channel = c;
1364
1365         return err;
1366 }
1367
1368 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1369 {
1370         mlx5_cqwq_destroy(&cq->wq_ctrl);
1371 }
1372
1373 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1374 {
1375         struct mlx5_core_dev *mdev = cq->mdev;
1376         struct mlx5_core_cq *mcq = &cq->mcq;
1377
1378         void *in;
1379         void *cqc;
1380         int inlen;
1381         unsigned int irqn_not_used;
1382         int eqn;
1383         int err;
1384
1385         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1386                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1387         in = kvzalloc(inlen, GFP_KERNEL);
1388         if (!in)
1389                 return -ENOMEM;
1390
1391         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1392
1393         memcpy(cqc, param->cqc, sizeof(param->cqc));
1394
1395         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1396                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1397
1398         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1399
1400         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1401         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1402         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1403         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1404                                             MLX5_ADAPTER_PAGE_SHIFT);
1405         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1406
1407         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1408
1409         kvfree(in);
1410
1411         if (err)
1412                 return err;
1413
1414         mlx5e_cq_arm(cq);
1415
1416         return 0;
1417 }
1418
1419 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1420 {
1421         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1422 }
1423
1424 static int mlx5e_open_cq(struct mlx5e_channel *c,
1425                          struct net_dim_cq_moder moder,
1426                          struct mlx5e_cq_param *param,
1427                          struct mlx5e_cq *cq)
1428 {
1429         struct mlx5_core_dev *mdev = c->mdev;
1430         int err;
1431
1432         err = mlx5e_alloc_cq(c, param, cq);
1433         if (err)
1434                 return err;
1435
1436         err = mlx5e_create_cq(cq, param);
1437         if (err)
1438                 goto err_free_cq;
1439
1440         if (MLX5_CAP_GEN(mdev, cq_moderation))
1441                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1442         return 0;
1443
1444 err_free_cq:
1445         mlx5e_free_cq(cq);
1446
1447         return err;
1448 }
1449
1450 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1451 {
1452         mlx5e_destroy_cq(cq);
1453         mlx5e_free_cq(cq);
1454 }
1455
1456 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1457 {
1458         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1459 }
1460
1461 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1462                              struct mlx5e_params *params,
1463                              struct mlx5e_channel_param *cparam)
1464 {
1465         int err;
1466         int tc;
1467
1468         for (tc = 0; tc < c->num_tc; tc++) {
1469                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1470                                     &cparam->tx_cq, &c->sq[tc].cq);
1471                 if (err)
1472                         goto err_close_tx_cqs;
1473         }
1474
1475         return 0;
1476
1477 err_close_tx_cqs:
1478         for (tc--; tc >= 0; tc--)
1479                 mlx5e_close_cq(&c->sq[tc].cq);
1480
1481         return err;
1482 }
1483
1484 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1485 {
1486         int tc;
1487
1488         for (tc = 0; tc < c->num_tc; tc++)
1489                 mlx5e_close_cq(&c->sq[tc].cq);
1490 }
1491
1492 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1493                           struct mlx5e_params *params,
1494                           struct mlx5e_channel_param *cparam)
1495 {
1496         int err;
1497         int tc;
1498
1499         for (tc = 0; tc < params->num_tc; tc++) {
1500                 int txq_ix = c->ix + tc * params->num_channels;
1501
1502                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1503                                        params, &cparam->sq, &c->sq[tc]);
1504                 if (err)
1505                         goto err_close_sqs;
1506         }
1507
1508         return 0;
1509
1510 err_close_sqs:
1511         for (tc--; tc >= 0; tc--)
1512                 mlx5e_close_txqsq(&c->sq[tc]);
1513
1514         return err;
1515 }
1516
1517 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1518 {
1519         int tc;
1520
1521         for (tc = 0; tc < c->num_tc; tc++)
1522                 mlx5e_close_txqsq(&c->sq[tc]);
1523 }
1524
1525 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1526                                 struct mlx5e_txqsq *sq, u32 rate)
1527 {
1528         struct mlx5e_priv *priv = netdev_priv(dev);
1529         struct mlx5_core_dev *mdev = priv->mdev;
1530         struct mlx5e_modify_sq_param msp = {0};
1531         u16 rl_index = 0;
1532         int err;
1533
1534         if (rate == sq->rate_limit)
1535                 /* nothing to do */
1536                 return 0;
1537
1538         if (sq->rate_limit)
1539                 /* remove current rl index to free space to next ones */
1540                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1541
1542         sq->rate_limit = 0;
1543
1544         if (rate) {
1545                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1546                 if (err) {
1547                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1548                                    rate, err);
1549                         return err;
1550                 }
1551         }
1552
1553         msp.curr_state = MLX5_SQC_STATE_RDY;
1554         msp.next_state = MLX5_SQC_STATE_RDY;
1555         msp.rl_index   = rl_index;
1556         msp.rl_update  = true;
1557         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1558         if (err) {
1559                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1560                            rate, err);
1561                 /* remove the rate from the table */
1562                 if (rate)
1563                         mlx5_rl_remove_rate(mdev, rate);
1564                 return err;
1565         }
1566
1567         sq->rate_limit = rate;
1568         return 0;
1569 }
1570
1571 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1572 {
1573         struct mlx5e_priv *priv = netdev_priv(dev);
1574         struct mlx5_core_dev *mdev = priv->mdev;
1575         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1576         int err = 0;
1577
1578         if (!mlx5_rl_is_supported(mdev)) {
1579                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1580                 return -EINVAL;
1581         }
1582
1583         /* rate is given in Mb/sec, HW config is in Kb/sec */
1584         rate = rate << 10;
1585
1586         /* Check whether rate in valid range, 0 is always valid */
1587         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1588                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1589                 return -ERANGE;
1590         }
1591
1592         mutex_lock(&priv->state_lock);
1593         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1594                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1595         if (!err)
1596                 priv->tx_rates[index] = rate;
1597         mutex_unlock(&priv->state_lock);
1598
1599         return err;
1600 }
1601
1602 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1603                               struct mlx5e_params *params,
1604                               struct mlx5e_channel_param *cparam,
1605                               struct mlx5e_channel **cp)
1606 {
1607         struct net_dim_cq_moder icocq_moder = {0, 0};
1608         struct net_device *netdev = priv->netdev;
1609         int cpu = mlx5e_get_cpu(priv, ix);
1610         struct mlx5e_channel *c;
1611         unsigned int irq;
1612         int err;
1613         int eqn;
1614
1615         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1616         if (!c)
1617                 return -ENOMEM;
1618
1619         c->priv     = priv;
1620         c->mdev     = priv->mdev;
1621         c->tstamp   = &priv->tstamp;
1622         c->ix       = ix;
1623         c->cpu      = cpu;
1624         c->pdev     = &priv->mdev->pdev->dev;
1625         c->netdev   = priv->netdev;
1626         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1627         c->num_tc   = params->num_tc;
1628         c->xdp      = !!params->xdp_prog;
1629
1630         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1631         c->irq_desc = irq_to_desc(irq);
1632
1633         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1634
1635         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1636         if (err)
1637                 goto err_napi_del;
1638
1639         err = mlx5e_open_tx_cqs(c, params, cparam);
1640         if (err)
1641                 goto err_close_icosq_cq;
1642
1643         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1644         if (err)
1645                 goto err_close_tx_cqs;
1646
1647         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1648         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1649                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1650         if (err)
1651                 goto err_close_rx_cq;
1652
1653         napi_enable(&c->napi);
1654
1655         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1656         if (err)
1657                 goto err_disable_napi;
1658
1659         err = mlx5e_open_sqs(c, params, cparam);
1660         if (err)
1661                 goto err_close_icosq;
1662
1663         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1664         if (err)
1665                 goto err_close_sqs;
1666
1667         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1668         if (err)
1669                 goto err_close_xdp_sq;
1670
1671         *cp = c;
1672
1673         return 0;
1674 err_close_xdp_sq:
1675         if (c->xdp)
1676                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1677
1678 err_close_sqs:
1679         mlx5e_close_sqs(c);
1680
1681 err_close_icosq:
1682         mlx5e_close_icosq(&c->icosq);
1683
1684 err_disable_napi:
1685         napi_disable(&c->napi);
1686         if (c->xdp)
1687                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1688
1689 err_close_rx_cq:
1690         mlx5e_close_cq(&c->rq.cq);
1691
1692 err_close_tx_cqs:
1693         mlx5e_close_tx_cqs(c);
1694
1695 err_close_icosq_cq:
1696         mlx5e_close_cq(&c->icosq.cq);
1697
1698 err_napi_del:
1699         netif_napi_del(&c->napi);
1700         kfree(c);
1701
1702         return err;
1703 }
1704
1705 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1706 {
1707         int tc;
1708
1709         for (tc = 0; tc < c->num_tc; tc++)
1710                 mlx5e_activate_txqsq(&c->sq[tc]);
1711         mlx5e_activate_rq(&c->rq);
1712         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1713 }
1714
1715 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1716 {
1717         int tc;
1718
1719         mlx5e_deactivate_rq(&c->rq);
1720         for (tc = 0; tc < c->num_tc; tc++)
1721                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1722 }
1723
1724 static void mlx5e_close_channel(struct mlx5e_channel *c)
1725 {
1726         mlx5e_close_rq(&c->rq);
1727         if (c->xdp)
1728                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1729         mlx5e_close_sqs(c);
1730         mlx5e_close_icosq(&c->icosq);
1731         napi_disable(&c->napi);
1732         if (c->xdp)
1733                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1734         mlx5e_close_cq(&c->rq.cq);
1735         mlx5e_close_tx_cqs(c);
1736         mlx5e_close_cq(&c->icosq.cq);
1737         netif_napi_del(&c->napi);
1738
1739         kfree(c);
1740 }
1741
1742 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1743                                  struct mlx5e_params *params,
1744                                  struct mlx5e_rq_param *param)
1745 {
1746         void *rqc = param->rqc;
1747         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1748
1749         switch (params->rq_wq_type) {
1750         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1751                 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1752                 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1753                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1754                 break;
1755         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1756                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1757         }
1758
1759         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1760         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1761         MLX5_SET(wq, wq, log_wq_sz,        params->log_rq_size);
1762         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1763         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1764         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1765         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1766
1767         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1768         param->wq.linear = 1;
1769 }
1770
1771 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1772 {
1773         void *rqc = param->rqc;
1774         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1775
1776         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1777         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1778 }
1779
1780 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1781                                         struct mlx5e_sq_param *param)
1782 {
1783         void *sqc = param->sqc;
1784         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1785
1786         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1787         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1788
1789         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1790 }
1791
1792 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1793                                  struct mlx5e_params *params,
1794                                  struct mlx5e_sq_param *param)
1795 {
1796         void *sqc = param->sqc;
1797         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1798
1799         mlx5e_build_sq_param_common(priv, param);
1800         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1801         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1802 }
1803
1804 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1805                                         struct mlx5e_cq_param *param)
1806 {
1807         void *cqc = param->cqc;
1808
1809         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1810 }
1811
1812 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1813                                     struct mlx5e_params *params,
1814                                     struct mlx5e_cq_param *param)
1815 {
1816         void *cqc = param->cqc;
1817         u8 log_cq_size;
1818
1819         switch (params->rq_wq_type) {
1820         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1821                 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1822                 break;
1823         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1824                 log_cq_size = params->log_rq_size;
1825         }
1826
1827         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1828         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1829                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1830                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1831         }
1832
1833         mlx5e_build_common_cq_param(priv, param);
1834         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1835 }
1836
1837 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1838                                     struct mlx5e_params *params,
1839                                     struct mlx5e_cq_param *param)
1840 {
1841         void *cqc = param->cqc;
1842
1843         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1844
1845         mlx5e_build_common_cq_param(priv, param);
1846         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
1847 }
1848
1849 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1850                                      u8 log_wq_size,
1851                                      struct mlx5e_cq_param *param)
1852 {
1853         void *cqc = param->cqc;
1854
1855         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1856
1857         mlx5e_build_common_cq_param(priv, param);
1858
1859         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1860 }
1861
1862 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1863                                     u8 log_wq_size,
1864                                     struct mlx5e_sq_param *param)
1865 {
1866         void *sqc = param->sqc;
1867         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1868
1869         mlx5e_build_sq_param_common(priv, param);
1870
1871         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1872         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1873 }
1874
1875 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1876                                     struct mlx5e_params *params,
1877                                     struct mlx5e_sq_param *param)
1878 {
1879         void *sqc = param->sqc;
1880         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1881
1882         mlx5e_build_sq_param_common(priv, param);
1883         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1884 }
1885
1886 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1887                                       struct mlx5e_params *params,
1888                                       struct mlx5e_channel_param *cparam)
1889 {
1890         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1891
1892         mlx5e_build_rq_param(priv, params, &cparam->rq);
1893         mlx5e_build_sq_param(priv, params, &cparam->sq);
1894         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
1895         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
1896         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
1897         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
1898         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
1899 }
1900
1901 int mlx5e_open_channels(struct mlx5e_priv *priv,
1902                         struct mlx5e_channels *chs)
1903 {
1904         struct mlx5e_channel_param *cparam;
1905         int err = -ENOMEM;
1906         int i;
1907
1908         chs->num = chs->params.num_channels;
1909
1910         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
1911         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1912         if (!chs->c || !cparam)
1913                 goto err_free;
1914
1915         mlx5e_build_channel_param(priv, &chs->params, cparam);
1916         for (i = 0; i < chs->num; i++) {
1917                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
1918                 if (err)
1919                         goto err_close_channels;
1920         }
1921
1922         kfree(cparam);
1923         return 0;
1924
1925 err_close_channels:
1926         for (i--; i >= 0; i--)
1927                 mlx5e_close_channel(chs->c[i]);
1928
1929 err_free:
1930         kfree(chs->c);
1931         kfree(cparam);
1932         chs->num = 0;
1933         return err;
1934 }
1935
1936 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
1937 {
1938         int i;
1939
1940         for (i = 0; i < chs->num; i++)
1941                 mlx5e_activate_channel(chs->c[i]);
1942 }
1943
1944 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
1945 {
1946         int err = 0;
1947         int i;
1948
1949         for (i = 0; i < chs->num; i++) {
1950                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
1951                 if (err)
1952                         break;
1953         }
1954
1955         return err;
1956 }
1957
1958 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
1959 {
1960         int i;
1961
1962         for (i = 0; i < chs->num; i++)
1963                 mlx5e_deactivate_channel(chs->c[i]);
1964 }
1965
1966 void mlx5e_close_channels(struct mlx5e_channels *chs)
1967 {
1968         int i;
1969
1970         for (i = 0; i < chs->num; i++)
1971                 mlx5e_close_channel(chs->c[i]);
1972
1973         kfree(chs->c);
1974         chs->num = 0;
1975 }
1976
1977 static int
1978 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
1979 {
1980         struct mlx5_core_dev *mdev = priv->mdev;
1981         void *rqtc;
1982         int inlen;
1983         int err;
1984         u32 *in;
1985         int i;
1986
1987         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1988         in = kvzalloc(inlen, GFP_KERNEL);
1989         if (!in)
1990                 return -ENOMEM;
1991
1992         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1993
1994         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1995         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1996
1997         for (i = 0; i < sz; i++)
1998                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
1999
2000         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2001         if (!err)
2002                 rqt->enabled = true;
2003
2004         kvfree(in);
2005         return err;
2006 }
2007
2008 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2009 {
2010         rqt->enabled = false;
2011         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2012 }
2013
2014 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2015 {
2016         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2017         int err;
2018
2019         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2020         if (err)
2021                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2022         return err;
2023 }
2024
2025 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2026 {
2027         struct mlx5e_rqt *rqt;
2028         int err;
2029         int ix;
2030
2031         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2032                 rqt = &priv->direct_tir[ix].rqt;
2033                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2034                 if (err)
2035                         goto err_destroy_rqts;
2036         }
2037
2038         return 0;
2039
2040 err_destroy_rqts:
2041         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2042         for (ix--; ix >= 0; ix--)
2043                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2044
2045         return err;
2046 }
2047
2048 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2049 {
2050         int i;
2051
2052         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2053                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2054 }
2055
2056 static int mlx5e_rx_hash_fn(int hfunc)
2057 {
2058         return (hfunc == ETH_RSS_HASH_TOP) ?
2059                MLX5_RX_HASH_FN_TOEPLITZ :
2060                MLX5_RX_HASH_FN_INVERTED_XOR8;
2061 }
2062
2063 int mlx5e_bits_invert(unsigned long a, int size)
2064 {
2065         int inv = 0;
2066         int i;
2067
2068         for (i = 0; i < size; i++)
2069                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2070
2071         return inv;
2072 }
2073
2074 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2075                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2076 {
2077         int i;
2078
2079         for (i = 0; i < sz; i++) {
2080                 u32 rqn;
2081
2082                 if (rrp.is_rss) {
2083                         int ix = i;
2084
2085                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2086                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2087
2088                         ix = priv->channels.params.indirection_rqt[ix];
2089                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2090                 } else {
2091                         rqn = rrp.rqn;
2092                 }
2093                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2094         }
2095 }
2096
2097 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2098                        struct mlx5e_redirect_rqt_param rrp)
2099 {
2100         struct mlx5_core_dev *mdev = priv->mdev;
2101         void *rqtc;
2102         int inlen;
2103         u32 *in;
2104         int err;
2105
2106         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2107         in = kvzalloc(inlen, GFP_KERNEL);
2108         if (!in)
2109                 return -ENOMEM;
2110
2111         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2112
2113         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2114         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2115         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2116         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2117
2118         kvfree(in);
2119         return err;
2120 }
2121
2122 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2123                                 struct mlx5e_redirect_rqt_param rrp)
2124 {
2125         if (!rrp.is_rss)
2126                 return rrp.rqn;
2127
2128         if (ix >= rrp.rss.channels->num)
2129                 return priv->drop_rq.rqn;
2130
2131         return rrp.rss.channels->c[ix]->rq.rqn;
2132 }
2133
2134 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2135                                 struct mlx5e_redirect_rqt_param rrp)
2136 {
2137         u32 rqtn;
2138         int ix;
2139
2140         if (priv->indir_rqt.enabled) {
2141                 /* RSS RQ table */
2142                 rqtn = priv->indir_rqt.rqtn;
2143                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2144         }
2145
2146         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2147                 struct mlx5e_redirect_rqt_param direct_rrp = {
2148                         .is_rss = false,
2149                         {
2150                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2151                         },
2152                 };
2153
2154                 /* Direct RQ Tables */
2155                 if (!priv->direct_tir[ix].rqt.enabled)
2156                         continue;
2157
2158                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2159                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2160         }
2161 }
2162
2163 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2164                                             struct mlx5e_channels *chs)
2165 {
2166         struct mlx5e_redirect_rqt_param rrp = {
2167                 .is_rss        = true,
2168                 {
2169                         .rss = {
2170                                 .channels  = chs,
2171                                 .hfunc     = chs->params.rss_hfunc,
2172                         }
2173                 },
2174         };
2175
2176         mlx5e_redirect_rqts(priv, rrp);
2177 }
2178
2179 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2180 {
2181         struct mlx5e_redirect_rqt_param drop_rrp = {
2182                 .is_rss = false,
2183                 {
2184                         .rqn = priv->drop_rq.rqn,
2185                 },
2186         };
2187
2188         mlx5e_redirect_rqts(priv, drop_rrp);
2189 }
2190
2191 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2192 {
2193         if (!params->lro_en)
2194                 return;
2195
2196 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2197
2198         MLX5_SET(tirc, tirc, lro_enable_mask,
2199                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2200                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2201         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2202                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2203         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2204 }
2205
2206 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2207                                     enum mlx5e_traffic_types tt,
2208                                     void *tirc, bool inner)
2209 {
2210         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2211                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2212
2213 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2214                                  MLX5_HASH_FIELD_SEL_DST_IP)
2215
2216 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2217                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2218                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2219                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2220
2221 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2222                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2223                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2224
2225         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2226         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2227                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2228                                              rx_hash_toeplitz_key);
2229                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2230                                                rx_hash_toeplitz_key);
2231
2232                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2233                 memcpy(rss_key, params->toeplitz_hash_key, len);
2234         }
2235
2236         switch (tt) {
2237         case MLX5E_TT_IPV4_TCP:
2238                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2239                          MLX5_L3_PROT_TYPE_IPV4);
2240                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2241                          MLX5_L4_PROT_TYPE_TCP);
2242                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2243                          MLX5_HASH_IP_L4PORTS);
2244                 break;
2245
2246         case MLX5E_TT_IPV6_TCP:
2247                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2248                          MLX5_L3_PROT_TYPE_IPV6);
2249                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2250                          MLX5_L4_PROT_TYPE_TCP);
2251                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2252                          MLX5_HASH_IP_L4PORTS);
2253                 break;
2254
2255         case MLX5E_TT_IPV4_UDP:
2256                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2257                          MLX5_L3_PROT_TYPE_IPV4);
2258                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2259                          MLX5_L4_PROT_TYPE_UDP);
2260                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2261                          MLX5_HASH_IP_L4PORTS);
2262                 break;
2263
2264         case MLX5E_TT_IPV6_UDP:
2265                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2266                          MLX5_L3_PROT_TYPE_IPV6);
2267                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2268                          MLX5_L4_PROT_TYPE_UDP);
2269                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2270                          MLX5_HASH_IP_L4PORTS);
2271                 break;
2272
2273         case MLX5E_TT_IPV4_IPSEC_AH:
2274                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2275                          MLX5_L3_PROT_TYPE_IPV4);
2276                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2277                          MLX5_HASH_IP_IPSEC_SPI);
2278                 break;
2279
2280         case MLX5E_TT_IPV6_IPSEC_AH:
2281                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2282                          MLX5_L3_PROT_TYPE_IPV6);
2283                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2284                          MLX5_HASH_IP_IPSEC_SPI);
2285                 break;
2286
2287         case MLX5E_TT_IPV4_IPSEC_ESP:
2288                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2289                          MLX5_L3_PROT_TYPE_IPV4);
2290                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2291                          MLX5_HASH_IP_IPSEC_SPI);
2292                 break;
2293
2294         case MLX5E_TT_IPV6_IPSEC_ESP:
2295                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2296                          MLX5_L3_PROT_TYPE_IPV6);
2297                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2298                          MLX5_HASH_IP_IPSEC_SPI);
2299                 break;
2300
2301         case MLX5E_TT_IPV4:
2302                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2303                          MLX5_L3_PROT_TYPE_IPV4);
2304                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2305                          MLX5_HASH_IP);
2306                 break;
2307
2308         case MLX5E_TT_IPV6:
2309                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2310                          MLX5_L3_PROT_TYPE_IPV6);
2311                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2312                          MLX5_HASH_IP);
2313                 break;
2314         default:
2315                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2316         }
2317 }
2318
2319 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2320 {
2321         struct mlx5_core_dev *mdev = priv->mdev;
2322
2323         void *in;
2324         void *tirc;
2325         int inlen;
2326         int err;
2327         int tt;
2328         int ix;
2329
2330         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2331         in = kvzalloc(inlen, GFP_KERNEL);
2332         if (!in)
2333                 return -ENOMEM;
2334
2335         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2336         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2337
2338         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2339
2340         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2341                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2342                                            inlen);
2343                 if (err)
2344                         goto free_in;
2345         }
2346
2347         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2348                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2349                                            in, inlen);
2350                 if (err)
2351                         goto free_in;
2352         }
2353
2354 free_in:
2355         kvfree(in);
2356
2357         return err;
2358 }
2359
2360 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2361                                             enum mlx5e_traffic_types tt,
2362                                             u32 *tirc)
2363 {
2364         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2365
2366         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2367
2368         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2369         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2370         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2371
2372         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2373 }
2374
2375 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2376 {
2377         struct mlx5_core_dev *mdev = priv->mdev;
2378         u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2379         int err;
2380
2381         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2382         if (err)
2383                 return err;
2384
2385         /* Update vport context MTU */
2386         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2387         return 0;
2388 }
2389
2390 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2391 {
2392         struct mlx5_core_dev *mdev = priv->mdev;
2393         u16 hw_mtu = 0;
2394         int err;
2395
2396         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2397         if (err || !hw_mtu) /* fallback to port oper mtu */
2398                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2399
2400         *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2401 }
2402
2403 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2404 {
2405         struct net_device *netdev = priv->netdev;
2406         u16 mtu;
2407         int err;
2408
2409         err = mlx5e_set_mtu(priv, netdev->mtu);
2410         if (err)
2411                 return err;
2412
2413         mlx5e_query_mtu(priv, &mtu);
2414         if (mtu != netdev->mtu)
2415                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2416                             __func__, mtu, netdev->mtu);
2417
2418         netdev->mtu = mtu;
2419         return 0;
2420 }
2421
2422 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2423 {
2424         struct mlx5e_priv *priv = netdev_priv(netdev);
2425         int nch = priv->channels.params.num_channels;
2426         int ntc = priv->channels.params.num_tc;
2427         int tc;
2428
2429         netdev_reset_tc(netdev);
2430
2431         if (ntc == 1)
2432                 return;
2433
2434         netdev_set_num_tc(netdev, ntc);
2435
2436         /* Map netdev TCs to offset 0
2437          * We have our own UP to TXQ mapping for QoS
2438          */
2439         for (tc = 0; tc < ntc; tc++)
2440                 netdev_set_tc_queue(netdev, tc, nch, 0);
2441 }
2442
2443 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2444 {
2445         struct mlx5e_channel *c;
2446         struct mlx5e_txqsq *sq;
2447         int i, tc;
2448
2449         for (i = 0; i < priv->channels.num; i++)
2450                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2451                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2452
2453         for (i = 0; i < priv->channels.num; i++) {
2454                 c = priv->channels.c[i];
2455                 for (tc = 0; tc < c->num_tc; tc++) {
2456                         sq = &c->sq[tc];
2457                         priv->txq2sq[sq->txq_ix] = sq;
2458                 }
2459         }
2460 }
2461
2462 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2463 {
2464         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2465         struct net_device *netdev = priv->netdev;
2466
2467         mlx5e_netdev_set_tcs(netdev);
2468         netif_set_real_num_tx_queues(netdev, num_txqs);
2469         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2470
2471         mlx5e_build_channels_tx_maps(priv);
2472         mlx5e_activate_channels(&priv->channels);
2473         netif_tx_start_all_queues(priv->netdev);
2474
2475         if (MLX5_VPORT_MANAGER(priv->mdev))
2476                 mlx5e_add_sqs_fwd_rules(priv);
2477
2478         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2479         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2480 }
2481
2482 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2483 {
2484         mlx5e_redirect_rqts_to_drop(priv);
2485
2486         if (MLX5_VPORT_MANAGER(priv->mdev))
2487                 mlx5e_remove_sqs_fwd_rules(priv);
2488
2489         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2490          * polling for inactive tx queues.
2491          */
2492         netif_tx_stop_all_queues(priv->netdev);
2493         netif_tx_disable(priv->netdev);
2494         mlx5e_deactivate_channels(&priv->channels);
2495 }
2496
2497 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2498                                 struct mlx5e_channels *new_chs,
2499                                 mlx5e_fp_hw_modify hw_modify)
2500 {
2501         struct net_device *netdev = priv->netdev;
2502         int new_num_txqs;
2503         int carrier_ok;
2504         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2505
2506         carrier_ok = netif_carrier_ok(netdev);
2507         netif_carrier_off(netdev);
2508
2509         if (new_num_txqs < netdev->real_num_tx_queues)
2510                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2511
2512         mlx5e_deactivate_priv_channels(priv);
2513         mlx5e_close_channels(&priv->channels);
2514
2515         priv->channels = *new_chs;
2516
2517         /* New channels are ready to roll, modify HW settings if needed */
2518         if (hw_modify)
2519                 hw_modify(priv);
2520
2521         mlx5e_refresh_tirs(priv, false);
2522         mlx5e_activate_priv_channels(priv);
2523
2524         /* return carrier back if needed */
2525         if (carrier_ok)
2526                 netif_carrier_on(netdev);
2527 }
2528
2529 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2530 {
2531         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2532         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2533 }
2534
2535 int mlx5e_open_locked(struct net_device *netdev)
2536 {
2537         struct mlx5e_priv *priv = netdev_priv(netdev);
2538         int err;
2539
2540         set_bit(MLX5E_STATE_OPENED, &priv->state);
2541
2542         err = mlx5e_open_channels(priv, &priv->channels);
2543         if (err)
2544                 goto err_clear_state_opened_flag;
2545
2546         mlx5e_refresh_tirs(priv, false);
2547         mlx5e_activate_priv_channels(priv);
2548         if (priv->profile->update_carrier)
2549                 priv->profile->update_carrier(priv);
2550
2551         if (priv->profile->update_stats)
2552                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2553
2554         return 0;
2555
2556 err_clear_state_opened_flag:
2557         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2558         return err;
2559 }
2560
2561 int mlx5e_open(struct net_device *netdev)
2562 {
2563         struct mlx5e_priv *priv = netdev_priv(netdev);
2564         int err;
2565
2566         mutex_lock(&priv->state_lock);
2567         err = mlx5e_open_locked(netdev);
2568         if (!err)
2569                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2570         mutex_unlock(&priv->state_lock);
2571
2572         return err;
2573 }
2574
2575 int mlx5e_close_locked(struct net_device *netdev)
2576 {
2577         struct mlx5e_priv *priv = netdev_priv(netdev);
2578
2579         /* May already be CLOSED in case a previous configuration operation
2580          * (e.g RX/TX queue size change) that involves close&open failed.
2581          */
2582         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2583                 return 0;
2584
2585         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2586
2587         netif_carrier_off(priv->netdev);
2588         mlx5e_deactivate_priv_channels(priv);
2589         mlx5e_close_channels(&priv->channels);
2590
2591         return 0;
2592 }
2593
2594 int mlx5e_close(struct net_device *netdev)
2595 {
2596         struct mlx5e_priv *priv = netdev_priv(netdev);
2597         int err;
2598
2599         if (!netif_device_present(netdev))
2600                 return -ENODEV;
2601
2602         mutex_lock(&priv->state_lock);
2603         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2604         err = mlx5e_close_locked(netdev);
2605         mutex_unlock(&priv->state_lock);
2606
2607         return err;
2608 }
2609
2610 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2611                                struct mlx5e_rq *rq,
2612                                struct mlx5e_rq_param *param)
2613 {
2614         void *rqc = param->rqc;
2615         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2616         int err;
2617
2618         param->wq.db_numa_node = param->wq.buf_numa_node;
2619
2620         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2621                                 &rq->wq_ctrl);
2622         if (err)
2623                 return err;
2624
2625         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2626         xdp_rxq_info_unused(&rq->xdp_rxq);
2627
2628         rq->mdev = mdev;
2629
2630         return 0;
2631 }
2632
2633 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2634                                struct mlx5e_cq *cq,
2635                                struct mlx5e_cq_param *param)
2636 {
2637         return mlx5e_alloc_cq_common(mdev, param, cq);
2638 }
2639
2640 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2641                               struct mlx5e_rq *drop_rq)
2642 {
2643         struct mlx5e_cq_param cq_param = {};
2644         struct mlx5e_rq_param rq_param = {};
2645         struct mlx5e_cq *cq = &drop_rq->cq;
2646         int err;
2647
2648         mlx5e_build_drop_rq_param(&rq_param);
2649
2650         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2651         if (err)
2652                 return err;
2653
2654         err = mlx5e_create_cq(cq, &cq_param);
2655         if (err)
2656                 goto err_free_cq;
2657
2658         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2659         if (err)
2660                 goto err_destroy_cq;
2661
2662         err = mlx5e_create_rq(drop_rq, &rq_param);
2663         if (err)
2664                 goto err_free_rq;
2665
2666         return 0;
2667
2668 err_free_rq:
2669         mlx5e_free_rq(drop_rq);
2670
2671 err_destroy_cq:
2672         mlx5e_destroy_cq(cq);
2673
2674 err_free_cq:
2675         mlx5e_free_cq(cq);
2676
2677         return err;
2678 }
2679
2680 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2681 {
2682         mlx5e_destroy_rq(drop_rq);
2683         mlx5e_free_rq(drop_rq);
2684         mlx5e_destroy_cq(&drop_rq->cq);
2685         mlx5e_free_cq(&drop_rq->cq);
2686 }
2687
2688 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2689                      u32 underlay_qpn, u32 *tisn)
2690 {
2691         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2692         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2693
2694         MLX5_SET(tisc, tisc, prio, tc << 1);
2695         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2696         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2697
2698         if (mlx5_lag_is_lacp_owner(mdev))
2699                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2700
2701         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2702 }
2703
2704 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2705 {
2706         mlx5_core_destroy_tis(mdev, tisn);
2707 }
2708
2709 int mlx5e_create_tises(struct mlx5e_priv *priv)
2710 {
2711         int err;
2712         int tc;
2713
2714         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2715                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2716                 if (err)
2717                         goto err_close_tises;
2718         }
2719
2720         return 0;
2721
2722 err_close_tises:
2723         for (tc--; tc >= 0; tc--)
2724                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2725
2726         return err;
2727 }
2728
2729 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2730 {
2731         int tc;
2732
2733         for (tc = 0; tc < priv->profile->max_tc; tc++)
2734                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2735 }
2736
2737 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2738                                       enum mlx5e_traffic_types tt,
2739                                       u32 *tirc)
2740 {
2741         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2742
2743         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2744
2745         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2746         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2747         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2748 }
2749
2750 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2751 {
2752         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2753
2754         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2755
2756         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2757         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2758         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2759 }
2760
2761 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2762 {
2763         struct mlx5e_tir *tir;
2764         void *tirc;
2765         int inlen;
2766         int i = 0;
2767         int err;
2768         u32 *in;
2769         int tt;
2770
2771         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2772         in = kvzalloc(inlen, GFP_KERNEL);
2773         if (!in)
2774                 return -ENOMEM;
2775
2776         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2777                 memset(in, 0, inlen);
2778                 tir = &priv->indir_tir[tt];
2779                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2780                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2781                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2782                 if (err) {
2783                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2784                         goto err_destroy_inner_tirs;
2785                 }
2786         }
2787
2788         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2789                 goto out;
2790
2791         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2792                 memset(in, 0, inlen);
2793                 tir = &priv->inner_indir_tir[i];
2794                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2795                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2796                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2797                 if (err) {
2798                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2799                         goto err_destroy_inner_tirs;
2800                 }
2801         }
2802
2803 out:
2804         kvfree(in);
2805
2806         return 0;
2807
2808 err_destroy_inner_tirs:
2809         for (i--; i >= 0; i--)
2810                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2811
2812         for (tt--; tt >= 0; tt--)
2813                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2814
2815         kvfree(in);
2816
2817         return err;
2818 }
2819
2820 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2821 {
2822         int nch = priv->profile->max_nch(priv->mdev);
2823         struct mlx5e_tir *tir;
2824         void *tirc;
2825         int inlen;
2826         int err;
2827         u32 *in;
2828         int ix;
2829
2830         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2831         in = kvzalloc(inlen, GFP_KERNEL);
2832         if (!in)
2833                 return -ENOMEM;
2834
2835         for (ix = 0; ix < nch; ix++) {
2836                 memset(in, 0, inlen);
2837                 tir = &priv->direct_tir[ix];
2838                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2839                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2840                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2841                 if (err)
2842                         goto err_destroy_ch_tirs;
2843         }
2844
2845         kvfree(in);
2846
2847         return 0;
2848
2849 err_destroy_ch_tirs:
2850         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2851         for (ix--; ix >= 0; ix--)
2852                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2853
2854         kvfree(in);
2855
2856         return err;
2857 }
2858
2859 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2860 {
2861         int i;
2862
2863         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2864                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2865
2866         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2867                 return;
2868
2869         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2870                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2871 }
2872
2873 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2874 {
2875         int nch = priv->profile->max_nch(priv->mdev);
2876         int i;
2877
2878         for (i = 0; i < nch; i++)
2879                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2880 }
2881
2882 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2883 {
2884         int err = 0;
2885         int i;
2886
2887         for (i = 0; i < chs->num; i++) {
2888                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2889                 if (err)
2890                         return err;
2891         }
2892
2893         return 0;
2894 }
2895
2896 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2897 {
2898         int err = 0;
2899         int i;
2900
2901         for (i = 0; i < chs->num; i++) {
2902                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2903                 if (err)
2904                         return err;
2905         }
2906
2907         return 0;
2908 }
2909
2910 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
2911                                  struct tc_mqprio_qopt *mqprio)
2912 {
2913         struct mlx5e_priv *priv = netdev_priv(netdev);
2914         struct mlx5e_channels new_channels = {};
2915         u8 tc = mqprio->num_tc;
2916         int err = 0;
2917
2918         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2919
2920         if (tc && tc != MLX5E_MAX_NUM_TC)
2921                 return -EINVAL;
2922
2923         mutex_lock(&priv->state_lock);
2924
2925         new_channels.params = priv->channels.params;
2926         new_channels.params.num_tc = tc ? tc : 1;
2927
2928         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
2929                 priv->channels.params = new_channels.params;
2930                 goto out;
2931         }
2932
2933         err = mlx5e_open_channels(priv, &new_channels);
2934         if (err)
2935                 goto out;
2936
2937         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
2938 out:
2939         mutex_unlock(&priv->state_lock);
2940         return err;
2941 }
2942
2943 #ifdef CONFIG_MLX5_ESWITCH
2944 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
2945                                      struct tc_cls_flower_offload *cls_flower)
2946 {
2947         switch (cls_flower->command) {
2948         case TC_CLSFLOWER_REPLACE:
2949                 return mlx5e_configure_flower(priv, cls_flower);
2950         case TC_CLSFLOWER_DESTROY:
2951                 return mlx5e_delete_flower(priv, cls_flower);
2952         case TC_CLSFLOWER_STATS:
2953                 return mlx5e_stats_flower(priv, cls_flower);
2954         default:
2955                 return -EOPNOTSUPP;
2956         }
2957 }
2958
2959 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2960                             void *cb_priv)
2961 {
2962         struct mlx5e_priv *priv = cb_priv;
2963
2964         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2965                 return -EOPNOTSUPP;
2966
2967         switch (type) {
2968         case TC_SETUP_CLSFLOWER:
2969                 return mlx5e_setup_tc_cls_flower(priv, type_data);
2970         default:
2971                 return -EOPNOTSUPP;
2972         }
2973 }
2974
2975 static int mlx5e_setup_tc_block(struct net_device *dev,
2976                                 struct tc_block_offload *f)
2977 {
2978         struct mlx5e_priv *priv = netdev_priv(dev);
2979
2980         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2981                 return -EOPNOTSUPP;
2982
2983         switch (f->command) {
2984         case TC_BLOCK_BIND:
2985                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
2986                                              priv, priv);
2987         case TC_BLOCK_UNBIND:
2988                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
2989                                         priv);
2990                 return 0;
2991         default:
2992                 return -EOPNOTSUPP;
2993         }
2994 }
2995 #endif
2996
2997 int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
2998                    void *type_data)
2999 {
3000         switch (type) {
3001 #ifdef CONFIG_MLX5_ESWITCH
3002         case TC_SETUP_BLOCK:
3003                 return mlx5e_setup_tc_block(dev, type_data);
3004 #endif
3005         case TC_SETUP_QDISC_MQPRIO:
3006                 return mlx5e_setup_tc_mqprio(dev, type_data);
3007         default:
3008                 return -EOPNOTSUPP;
3009         }
3010 }
3011
3012 static void
3013 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3014 {
3015         struct mlx5e_priv *priv = netdev_priv(dev);
3016         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3017         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3018         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3019
3020         if (mlx5e_is_uplink_rep(priv)) {
3021                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3022                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3023                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3024                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3025         } else {
3026                 stats->rx_packets = sstats->rx_packets;
3027                 stats->rx_bytes   = sstats->rx_bytes;
3028                 stats->tx_packets = sstats->tx_packets;
3029                 stats->tx_bytes   = sstats->tx_bytes;
3030                 stats->tx_dropped = sstats->tx_queue_dropped;
3031         }
3032
3033         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3034
3035         stats->rx_length_errors =
3036                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3037                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3038                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3039         stats->rx_crc_errors =
3040                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3041         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3042         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3043         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3044                            stats->rx_frame_errors;
3045         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3046
3047         /* vport multicast also counts packets that are dropped due to steering
3048          * or rx out of buffer
3049          */
3050         stats->multicast =
3051                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3052 }
3053
3054 static void mlx5e_set_rx_mode(struct net_device *dev)
3055 {
3056         struct mlx5e_priv *priv = netdev_priv(dev);
3057
3058         queue_work(priv->wq, &priv->set_rx_mode_work);
3059 }
3060
3061 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3062 {
3063         struct mlx5e_priv *priv = netdev_priv(netdev);
3064         struct sockaddr *saddr = addr;
3065
3066         if (!is_valid_ether_addr(saddr->sa_data))
3067                 return -EADDRNOTAVAIL;
3068
3069         netif_addr_lock_bh(netdev);
3070         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3071         netif_addr_unlock_bh(netdev);
3072
3073         queue_work(priv->wq, &priv->set_rx_mode_work);
3074
3075         return 0;
3076 }
3077
3078 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3079         do {                                            \
3080                 if (enable)                             \
3081                         *features |= feature;           \
3082                 else                                    \
3083                         *features &= ~feature;          \
3084         } while (0)
3085
3086 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3087
3088 static int set_feature_lro(struct net_device *netdev, bool enable)
3089 {
3090         struct mlx5e_priv *priv = netdev_priv(netdev);
3091         struct mlx5e_channels new_channels = {};
3092         int err = 0;
3093         bool reset;
3094
3095         mutex_lock(&priv->state_lock);
3096
3097         reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3098         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3099
3100         new_channels.params = priv->channels.params;
3101         new_channels.params.lro_en = enable;
3102
3103         if (!reset) {
3104                 priv->channels.params = new_channels.params;
3105                 err = mlx5e_modify_tirs_lro(priv);
3106                 goto out;
3107         }
3108
3109         err = mlx5e_open_channels(priv, &new_channels);
3110         if (err)
3111                 goto out;
3112
3113         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3114 out:
3115         mutex_unlock(&priv->state_lock);
3116         return err;
3117 }
3118
3119 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3120 {
3121         struct mlx5e_priv *priv = netdev_priv(netdev);
3122
3123         if (enable)
3124                 mlx5e_enable_cvlan_filter(priv);
3125         else
3126                 mlx5e_disable_cvlan_filter(priv);
3127
3128         return 0;
3129 }
3130
3131 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3132 {
3133         struct mlx5e_priv *priv = netdev_priv(netdev);
3134
3135         if (!enable && mlx5e_tc_num_filters(priv)) {
3136                 netdev_err(netdev,
3137                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3138                 return -EINVAL;
3139         }
3140
3141         return 0;
3142 }
3143
3144 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3145 {
3146         struct mlx5e_priv *priv = netdev_priv(netdev);
3147         struct mlx5_core_dev *mdev = priv->mdev;
3148
3149         return mlx5_set_port_fcs(mdev, !enable);
3150 }
3151
3152 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3153 {
3154         struct mlx5e_priv *priv = netdev_priv(netdev);
3155         int err;
3156
3157         mutex_lock(&priv->state_lock);
3158
3159         priv->channels.params.scatter_fcs_en = enable;
3160         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3161         if (err)
3162                 priv->channels.params.scatter_fcs_en = !enable;
3163
3164         mutex_unlock(&priv->state_lock);
3165
3166         return err;
3167 }
3168
3169 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3170 {
3171         struct mlx5e_priv *priv = netdev_priv(netdev);
3172         int err = 0;
3173
3174         mutex_lock(&priv->state_lock);
3175
3176         priv->channels.params.vlan_strip_disable = !enable;
3177         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3178                 goto unlock;
3179
3180         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3181         if (err)
3182                 priv->channels.params.vlan_strip_disable = enable;
3183
3184 unlock:
3185         mutex_unlock(&priv->state_lock);
3186
3187         return err;
3188 }
3189
3190 #ifdef CONFIG_RFS_ACCEL
3191 static int set_feature_arfs(struct net_device *netdev, bool enable)
3192 {
3193         struct mlx5e_priv *priv = netdev_priv(netdev);
3194         int err;
3195
3196         if (enable)
3197                 err = mlx5e_arfs_enable(priv);
3198         else
3199                 err = mlx5e_arfs_disable(priv);
3200
3201         return err;
3202 }
3203 #endif
3204
3205 static int mlx5e_handle_feature(struct net_device *netdev,
3206                                 netdev_features_t *features,
3207                                 netdev_features_t wanted_features,
3208                                 netdev_features_t feature,
3209                                 mlx5e_feature_handler feature_handler)
3210 {
3211         netdev_features_t changes = wanted_features ^ netdev->features;
3212         bool enable = !!(wanted_features & feature);
3213         int err;
3214
3215         if (!(changes & feature))
3216                 return 0;
3217
3218         err = feature_handler(netdev, enable);
3219         if (err) {
3220                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3221                            enable ? "Enable" : "Disable", &feature, err);
3222                 return err;
3223         }
3224
3225         MLX5E_SET_FEATURE(features, feature, enable);
3226         return 0;
3227 }
3228
3229 static int mlx5e_set_features(struct net_device *netdev,
3230                               netdev_features_t features)
3231 {
3232         netdev_features_t oper_features = netdev->features;
3233         int err;
3234
3235         err  = mlx5e_handle_feature(netdev, &oper_features, features,
3236                                     NETIF_F_LRO, set_feature_lro);
3237         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3238                                     NETIF_F_HW_VLAN_CTAG_FILTER,
3239                                     set_feature_cvlan_filter);
3240         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3241                                     NETIF_F_HW_TC, set_feature_tc_num_filters);
3242         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3243                                     NETIF_F_RXALL, set_feature_rx_all);
3244         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3245                                     NETIF_F_RXFCS, set_feature_rx_fcs);
3246         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3247                                     NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3248 #ifdef CONFIG_RFS_ACCEL
3249         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3250                                     NETIF_F_NTUPLE, set_feature_arfs);
3251 #endif
3252
3253         if (err) {
3254                 netdev->features = oper_features;
3255                 return -EINVAL;
3256         }
3257
3258         return 0;