2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/phy.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
33 #define MODULENAME "r8169"
35 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
36 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
37 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
38 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
39 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
40 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
41 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
42 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
43 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
44 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
46 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
47 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
48 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
49 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
50 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
51 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
52 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
53 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
55 #define R8169_MSG_DEFAULT \
56 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
58 #define TX_SLOTS_AVAIL(tp) \
59 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
61 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
62 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
63 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
67 static const int multicast_filter_limit = 32;
69 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
70 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72 #define R8169_REGS_SIZE 256
73 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
74 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
75 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
76 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
77 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79 #define RTL8169_TX_TIMEOUT (6*HZ)
81 /* write/read MMIO register */
82 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
83 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
84 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
85 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
86 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
87 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
90 RTL_GIGA_MAC_VER_01 = 0,
141 RTL_GIGA_MAC_NONE = 0xff,
144 #define JUMBO_1K ETH_DATA_LEN
145 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
146 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
147 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
148 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150 static const struct {
153 } rtl_chip_infos[] = {
155 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
156 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
157 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
158 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
159 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
160 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
162 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
163 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
164 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
165 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
166 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
167 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
169 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
170 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
172 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
173 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
174 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
179 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
181 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
182 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
185 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
187 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
188 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
189 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
190 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
191 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
192 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
193 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
194 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
195 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
196 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
197 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
198 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
199 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
200 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
201 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
202 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
203 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
204 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
215 static const struct pci_device_id rtl8169_pci_tbl[] = {
216 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
217 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
218 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
219 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
221 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
222 { PCI_VENDOR_ID_DLINK, 0x4300,
223 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
224 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
225 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
226 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
227 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
228 { PCI_VENDOR_ID_LINKSYS, 0x1032,
229 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
231 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
237 static int use_dac = -1;
243 MAC0 = 0, /* Ethernet hardware address. */
245 MAR0 = 8, /* Multicast filter. */
246 CounterAddrLow = 0x10,
247 CounterAddrHigh = 0x14,
248 TxDescStartAddrLow = 0x20,
249 TxDescStartAddrHigh = 0x24,
250 TxHDescStartAddrLow = 0x28,
251 TxHDescStartAddrHigh = 0x2c,
260 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
261 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
264 #define RX128_INT_EN (1 << 15) /* 8111c and later */
265 #define RX_MULTI_EN (1 << 14) /* 8111c only */
266 #define RXCFG_FIFO_SHIFT 13
267 /* No threshold before first PCI xfer */
268 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
269 #define RX_EARLY_OFF (1 << 11)
270 #define RXCFG_DMA_SHIFT 8
271 /* Unlimited maximum PCI burst. */
272 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
279 #define PME_SIGNAL (1 << 5) /* 8168c and later */
291 #define RTL_COALESCE_MASK 0x0f
292 #define RTL_COALESCE_SHIFT 4
293 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
294 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
296 RxDescAddrLow = 0xe4,
297 RxDescAddrHigh = 0xe8,
298 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
300 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
302 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
304 #define TxPacketMax (8064 >> 7)
305 #define EarlySize 0x27
308 FuncEventMask = 0xf4,
309 FuncPresetState = 0xf8,
314 FuncForceEvent = 0xfc,
317 enum rtl8168_8101_registers {
320 #define CSIAR_FLAG 0x80000000
321 #define CSIAR_WRITE_CMD 0x80000000
322 #define CSIAR_BYTE_ENABLE 0x0000f000
323 #define CSIAR_ADDR_MASK 0x00000fff
326 #define EPHYAR_FLAG 0x80000000
327 #define EPHYAR_WRITE_CMD 0x80000000
328 #define EPHYAR_REG_MASK 0x1f
329 #define EPHYAR_REG_SHIFT 16
330 #define EPHYAR_DATA_MASK 0xffff
332 #define PFM_EN (1 << 6)
333 #define TX_10M_PS_EN (1 << 7)
335 #define FIX_NAK_1 (1 << 4)
336 #define FIX_NAK_2 (1 << 3)
339 #define NOW_IS_OOB (1 << 7)
340 #define TX_EMPTY (1 << 5)
341 #define RX_EMPTY (1 << 4)
342 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
343 #define EN_NDP (1 << 3)
344 #define EN_OOB_RESET (1 << 2)
345 #define LINK_LIST_RDY (1 << 1)
347 #define EFUSEAR_FLAG 0x80000000
348 #define EFUSEAR_WRITE_CMD 0x80000000
349 #define EFUSEAR_READ_CMD 0x00000000
350 #define EFUSEAR_REG_MASK 0x03ff
351 #define EFUSEAR_REG_SHIFT 8
352 #define EFUSEAR_DATA_MASK 0xff
354 #define PFM_D3COLD_EN (1 << 6)
357 enum rtl8168_registers {
362 #define ERIAR_FLAG 0x80000000
363 #define ERIAR_WRITE_CMD 0x80000000
364 #define ERIAR_READ_CMD 0x00000000
365 #define ERIAR_ADDR_BYTE_ALIGN 4
366 #define ERIAR_TYPE_SHIFT 16
367 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
368 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
369 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
370 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
371 #define ERIAR_MASK_SHIFT 12
372 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
373 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
374 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
375 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
377 EPHY_RXER_NUM = 0x7c,
378 OCPDR = 0xb0, /* OCP GPHY access */
379 #define OCPDR_WRITE_CMD 0x80000000
380 #define OCPDR_READ_CMD 0x00000000
381 #define OCPDR_REG_MASK 0x7f
382 #define OCPDR_GPHY_REG_SHIFT 16
383 #define OCPDR_DATA_MASK 0xffff
385 #define OCPAR_FLAG 0x80000000
386 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
387 #define OCPAR_GPHY_READ_CMD 0x0000f060
389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
391 #define TXPLA_RST (1 << 29)
392 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
393 #define PWM_EN (1 << 22)
394 #define RXDV_GATED_EN (1 << 19)
395 #define EARLY_TALLY_EN (1 << 16)
398 enum rtl_register_content {
399 /* InterruptStatusBits */
403 TxDescUnavail = 0x0080,
427 /* TXPoll register p.5 */
428 HPQ = 0x80, /* Poll cmd on the high prio queue */
429 NPQ = 0x40, /* Poll cmd on the low prio queue */
430 FSWInt = 0x01, /* Forced software interrupt */
434 Cfg9346_Unlock = 0xc0,
439 AcceptBroadcast = 0x08,
440 AcceptMulticast = 0x04,
442 AcceptAllPhys = 0x01,
443 #define RX_CONFIG_ACCEPT_MASK 0x3f
446 TxInterFrameGapShift = 24,
447 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
449 /* Config1 register p.24 */
452 Speed_down = (1 << 4),
456 PMEnable = (1 << 0), /* Power Management Enable */
458 /* Config2 register p. 25 */
459 ClkReqEn = (1 << 7), /* Clock Request Enable */
460 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
461 PCI_Clock_66MHz = 0x01,
462 PCI_Clock_33MHz = 0x00,
464 /* Config3 register p.25 */
465 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
466 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
467 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
468 Rdy_to_L23 = (1 << 1), /* L23 Enable */
469 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
471 /* Config4 register */
472 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
474 /* Config5 register p.27 */
475 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
476 MWF = (1 << 5), /* Accept Multicast wakeup frame */
477 UWF = (1 << 4), /* Accept Unicast wakeup frame */
479 LanWake = (1 << 1), /* LanWake enable/disable */
480 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
481 ASPM_en = (1 << 0), /* ASPM enable */
484 EnableBist = (1 << 15), // 8168 8101
485 Mac_dbgo_oe = (1 << 14), // 8168 8101
486 Normal_mode = (1 << 13), // unused
487 Force_half_dup = (1 << 12), // 8168 8101
488 Force_rxflow_en = (1 << 11), // 8168 8101
489 Force_txflow_en = (1 << 10), // 8168 8101
490 Cxpl_dbg_sel = (1 << 9), // 8168 8101
491 ASF = (1 << 8), // 8168 8101
492 PktCntrDisable = (1 << 7), // 8168 8101
493 Mac_dbgo_sel = 0x001c, // 8168
498 #define INTT_MASK GENMASK(1, 0)
499 INTT_0 = 0x0000, // 8168
500 INTT_1 = 0x0001, // 8168
501 INTT_2 = 0x0002, // 8168
502 INTT_3 = 0x0003, // 8168
504 /* rtl8169_PHYstatus */
515 TBILinkOK = 0x02000000,
517 /* ResetCounterCommand */
520 /* DumpCounterCommand */
523 /* magic enable v2 */
524 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
528 /* First doubleword. */
529 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
530 RingEnd = (1 << 30), /* End of descriptor ring */
531 FirstFrag = (1 << 29), /* First segment of a packet */
532 LastFrag = (1 << 28), /* Final segment of a packet */
536 enum rtl_tx_desc_bit {
537 /* First doubleword. */
538 TD_LSO = (1 << 27), /* Large Send Offload */
539 #define TD_MSS_MAX 0x07ffu /* MSS value */
541 /* Second doubleword. */
542 TxVlanTag = (1 << 17), /* Add VLAN tag */
545 /* 8169, 8168b and 810x except 8102e. */
546 enum rtl_tx_desc_bit_0 {
547 /* First doubleword. */
548 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
549 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
550 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
551 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
554 /* 8102e, 8168c and beyond. */
555 enum rtl_tx_desc_bit_1 {
556 /* First doubleword. */
557 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
558 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
559 #define GTTCPHO_SHIFT 18
560 #define GTTCPHO_MAX 0x7fU
562 /* Second doubleword. */
563 #define TCPHO_SHIFT 18
564 #define TCPHO_MAX 0x3ffU
565 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
566 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
567 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
568 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
569 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
572 enum rtl_rx_desc_bit {
574 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
575 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
577 #define RxProtoUDP (PID1)
578 #define RxProtoTCP (PID0)
579 #define RxProtoIP (PID1 | PID0)
580 #define RxProtoMask RxProtoIP
582 IPFail = (1 << 16), /* IP checksum failed */
583 UDPFail = (1 << 15), /* UDP/IP checksum failed */
584 TCPFail = (1 << 14), /* TCP/IP checksum failed */
585 RxVlanTag = (1 << 16), /* VLAN tag available */
588 #define RsvdMask 0x3fffc000
589 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
606 u8 __pad[sizeof(void *) - sizeof(u32)];
609 struct rtl8169_counters {
616 __le32 tx_one_collision;
617 __le32 tx_multi_collision;
625 struct rtl8169_tc_offsets {
628 __le32 tx_multi_collision;
633 RTL_FLAG_TASK_ENABLED,
634 RTL_FLAG_TASK_SLOW_PENDING,
635 RTL_FLAG_TASK_RESET_PENDING,
639 struct rtl8169_stats {
642 struct u64_stats_sync syncp;
645 struct rtl8169_private {
646 void __iomem *mmio_addr; /* memory map physical address */
647 struct pci_dev *pci_dev;
648 struct net_device *dev;
649 struct napi_struct napi;
652 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
653 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
655 struct rtl8169_stats rx_stats;
656 struct rtl8169_stats tx_stats;
657 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
658 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
659 dma_addr_t TxPhyAddr;
660 dma_addr_t RxPhyAddr;
661 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
662 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
666 const struct rtl_coalesce_info *coalesce_info;
669 void (*write)(struct rtl8169_private *, int, int);
670 int (*read)(struct rtl8169_private *, int);
674 void (*enable)(struct rtl8169_private *);
675 void (*disable)(struct rtl8169_private *);
678 void (*hw_start)(struct rtl8169_private *tp);
679 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
682 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
684 struct work_struct work;
687 unsigned supports_gmii:1;
688 struct mii_bus *mii_bus;
689 dma_addr_t counters_phys_addr;
690 struct rtl8169_counters *counters;
691 struct rtl8169_tc_offsets tc_offset;
695 const struct firmware *fw;
697 #define RTL_VER_SIZE 32
699 char version[RTL_VER_SIZE];
701 struct rtl_fw_phy_action {
706 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
711 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
712 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
713 module_param(use_dac, int, 0);
714 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
715 module_param_named(debug, debug.msg_enable, int, 0);
716 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
717 MODULE_LICENSE("GPL");
718 MODULE_FIRMWARE(FIRMWARE_8168D_1);
719 MODULE_FIRMWARE(FIRMWARE_8168D_2);
720 MODULE_FIRMWARE(FIRMWARE_8168E_1);
721 MODULE_FIRMWARE(FIRMWARE_8168E_2);
722 MODULE_FIRMWARE(FIRMWARE_8168E_3);
723 MODULE_FIRMWARE(FIRMWARE_8105E_1);
724 MODULE_FIRMWARE(FIRMWARE_8168F_1);
725 MODULE_FIRMWARE(FIRMWARE_8168F_2);
726 MODULE_FIRMWARE(FIRMWARE_8402_1);
727 MODULE_FIRMWARE(FIRMWARE_8411_1);
728 MODULE_FIRMWARE(FIRMWARE_8411_2);
729 MODULE_FIRMWARE(FIRMWARE_8106E_1);
730 MODULE_FIRMWARE(FIRMWARE_8106E_2);
731 MODULE_FIRMWARE(FIRMWARE_8168G_2);
732 MODULE_FIRMWARE(FIRMWARE_8168G_3);
733 MODULE_FIRMWARE(FIRMWARE_8168H_1);
734 MODULE_FIRMWARE(FIRMWARE_8168H_2);
735 MODULE_FIRMWARE(FIRMWARE_8107E_1);
736 MODULE_FIRMWARE(FIRMWARE_8107E_2);
738 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
740 return &tp->pci_dev->dev;
743 static void rtl_lock_work(struct rtl8169_private *tp)
745 mutex_lock(&tp->wk.mutex);
748 static void rtl_unlock_work(struct rtl8169_private *tp)
750 mutex_unlock(&tp->wk.mutex);
753 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
755 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
756 PCI_EXP_DEVCTL_READRQ, force);
760 bool (*check)(struct rtl8169_private *);
764 static void rtl_udelay(unsigned int d)
769 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
770 void (*delay)(unsigned int), unsigned int d, int n,
775 for (i = 0; i < n; i++) {
777 if (c->check(tp) == high)
780 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
781 c->msg, !high, n, d);
785 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
786 const struct rtl_cond *c,
787 unsigned int d, int n)
789 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
792 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
793 const struct rtl_cond *c,
794 unsigned int d, int n)
796 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
799 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
800 const struct rtl_cond *c,
801 unsigned int d, int n)
803 return rtl_loop_wait(tp, c, msleep, d, n, true);
806 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
807 const struct rtl_cond *c,
808 unsigned int d, int n)
810 return rtl_loop_wait(tp, c, msleep, d, n, false);
813 #define DECLARE_RTL_COND(name) \
814 static bool name ## _check(struct rtl8169_private *); \
816 static const struct rtl_cond name = { \
817 .check = name ## _check, \
821 static bool name ## _check(struct rtl8169_private *tp)
823 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
825 if (reg & 0xffff0001) {
826 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
832 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
834 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
837 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
839 if (rtl_ocp_reg_failure(tp, reg))
842 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
844 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
847 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
849 if (rtl_ocp_reg_failure(tp, reg))
852 RTL_W32(tp, GPHY_OCP, reg << 15);
854 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
855 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
858 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
860 if (rtl_ocp_reg_failure(tp, reg))
863 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
866 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
868 if (rtl_ocp_reg_failure(tp, reg))
871 RTL_W32(tp, OCPDR, reg << 15);
873 return RTL_R32(tp, OCPDR);
876 #define OCP_STD_PHY_BASE 0xa400
878 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
881 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
885 if (tp->ocp_base != OCP_STD_PHY_BASE)
888 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
891 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
893 if (tp->ocp_base != OCP_STD_PHY_BASE)
896 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
899 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
902 tp->ocp_base = value << 4;
906 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
909 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
911 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
914 DECLARE_RTL_COND(rtl_phyar_cond)
916 return RTL_R32(tp, PHYAR) & 0x80000000;
919 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
921 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
923 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
925 * According to hardware specs a 20us delay is required after write
926 * complete indication, but before sending next command.
931 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
935 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
937 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
938 RTL_R32(tp, PHYAR) & 0xffff : ~0;
941 * According to hardware specs a 20us delay is required after read
942 * complete indication, but before sending next command.
949 DECLARE_RTL_COND(rtl_ocpar_cond)
951 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
954 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
956 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
957 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
958 RTL_W32(tp, EPHY_RXER_NUM, 0);
960 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
963 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
965 r8168dp_1_mdio_access(tp, reg,
966 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
969 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
971 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
974 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
975 RTL_W32(tp, EPHY_RXER_NUM, 0);
977 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
978 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
981 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
983 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
985 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
988 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
990 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
993 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
995 r8168dp_2_mdio_start(tp);
997 r8169_mdio_write(tp, reg, value);
999 r8168dp_2_mdio_stop(tp);
1002 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1006 r8168dp_2_mdio_start(tp);
1008 value = r8169_mdio_read(tp, reg);
1010 r8168dp_2_mdio_stop(tp);
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1017 tp->mdio_ops.write(tp, location, val);
1020 static int rtl_readphy(struct rtl8169_private *tp, int location)
1022 return tp->mdio_ops.read(tp, location);
1025 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1027 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1030 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034 val = rtl_readphy(tp, reg_addr);
1035 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1038 DECLARE_RTL_COND(rtl_ephyar_cond)
1040 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1043 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1045 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1046 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1048 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1053 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1055 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1057 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1058 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1061 DECLARE_RTL_COND(rtl_eriar_cond)
1063 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1066 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1069 BUG_ON((addr & 3) || (mask == 0));
1070 RTL_W32(tp, ERIDR, val);
1071 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1073 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1076 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1078 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1080 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1081 RTL_R32(tp, ERIDR) : ~0;
1084 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1089 val = rtl_eri_read(tp, addr, type);
1090 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1093 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1095 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1096 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1097 RTL_R32(tp, OCPDR) : ~0;
1100 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1102 return rtl_eri_read(tp, reg, ERIAR_OOB);
1105 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1107 switch (tp->mac_version) {
1108 case RTL_GIGA_MAC_VER_27:
1109 case RTL_GIGA_MAC_VER_28:
1110 case RTL_GIGA_MAC_VER_31:
1111 return r8168dp_ocp_read(tp, mask, reg);
1112 case RTL_GIGA_MAC_VER_49:
1113 case RTL_GIGA_MAC_VER_50:
1114 case RTL_GIGA_MAC_VER_51:
1115 return r8168ep_ocp_read(tp, mask, reg);
1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1125 RTL_W32(tp, OCPDR, data);
1126 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1127 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1133 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1139 switch (tp->mac_version) {
1140 case RTL_GIGA_MAC_VER_27:
1141 case RTL_GIGA_MAC_VER_28:
1142 case RTL_GIGA_MAC_VER_31:
1143 r8168dp_ocp_write(tp, mask, reg, data);
1145 case RTL_GIGA_MAC_VER_49:
1146 case RTL_GIGA_MAC_VER_50:
1147 case RTL_GIGA_MAC_VER_51:
1148 r8168ep_ocp_write(tp, mask, reg, data);
1156 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1158 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1160 ocp_write(tp, 0x1, 0x30, 0x00000001);
1163 #define OOB_CMD_RESET 0x00
1164 #define OOB_CMD_DRIVER_START 0x05
1165 #define OOB_CMD_DRIVER_STOP 0x06
1167 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1169 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1172 DECLARE_RTL_COND(rtl_ocp_read_cond)
1176 reg = rtl8168_get_ocp_reg(tp);
1178 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1181 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1183 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1186 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1188 return RTL_R8(tp, IBISR0) & 0x20;
1191 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1193 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1194 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1195 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1196 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1199 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1201 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1202 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1205 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1207 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1208 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1209 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1212 static void rtl8168_driver_start(struct rtl8169_private *tp)
1214 switch (tp->mac_version) {
1215 case RTL_GIGA_MAC_VER_27:
1216 case RTL_GIGA_MAC_VER_28:
1217 case RTL_GIGA_MAC_VER_31:
1218 rtl8168dp_driver_start(tp);
1220 case RTL_GIGA_MAC_VER_49:
1221 case RTL_GIGA_MAC_VER_50:
1222 case RTL_GIGA_MAC_VER_51:
1223 rtl8168ep_driver_start(tp);
1231 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1233 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1234 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1237 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1239 rtl8168ep_stop_cmac(tp);
1240 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1241 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1242 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1245 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1247 switch (tp->mac_version) {
1248 case RTL_GIGA_MAC_VER_27:
1249 case RTL_GIGA_MAC_VER_28:
1250 case RTL_GIGA_MAC_VER_31:
1251 rtl8168dp_driver_stop(tp);
1253 case RTL_GIGA_MAC_VER_49:
1254 case RTL_GIGA_MAC_VER_50:
1255 case RTL_GIGA_MAC_VER_51:
1256 rtl8168ep_driver_stop(tp);
1264 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1266 u16 reg = rtl8168_get_ocp_reg(tp);
1268 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1271 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1273 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1276 static bool r8168_check_dash(struct rtl8169_private *tp)
1278 switch (tp->mac_version) {
1279 case RTL_GIGA_MAC_VER_27:
1280 case RTL_GIGA_MAC_VER_28:
1281 case RTL_GIGA_MAC_VER_31:
1282 return r8168dp_check_dash(tp);
1283 case RTL_GIGA_MAC_VER_49:
1284 case RTL_GIGA_MAC_VER_50:
1285 case RTL_GIGA_MAC_VER_51:
1286 return r8168ep_check_dash(tp);
1298 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1299 const struct exgmac_reg *r, int len)
1302 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1307 DECLARE_RTL_COND(rtl_efusear_cond)
1309 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1312 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1314 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1316 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1317 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1320 static u16 rtl_get_events(struct rtl8169_private *tp)
1322 return RTL_R16(tp, IntrStatus);
1325 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1327 RTL_W16(tp, IntrStatus, bits);
1331 static void rtl_irq_disable(struct rtl8169_private *tp)
1333 RTL_W16(tp, IntrMask, 0);
1337 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1339 RTL_W16(tp, IntrMask, bits);
1342 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1343 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1344 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1346 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1348 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1351 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1353 rtl_irq_disable(tp);
1354 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1355 RTL_R8(tp, ChipCmd);
1358 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1360 struct net_device *dev = tp->dev;
1361 struct phy_device *phydev = dev->phydev;
1363 if (!netif_running(dev))
1366 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1367 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1368 if (phydev->speed == SPEED_1000) {
1369 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1371 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1373 } else if (phydev->speed == SPEED_100) {
1374 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1376 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1379 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1381 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1384 /* Reset packet filter */
1385 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1387 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1389 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1390 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1391 if (phydev->speed == SPEED_1000) {
1392 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1394 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1397 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1399 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1402 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1403 if (phydev->speed == SPEED_10) {
1404 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1406 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1409 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1415 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1417 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1422 options = RTL_R8(tp, Config1);
1423 if (!(options & PMEnable))
1426 options = RTL_R8(tp, Config3);
1427 if (options & LinkUp)
1428 wolopts |= WAKE_PHY;
1429 switch (tp->mac_version) {
1430 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1431 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1432 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1433 wolopts |= WAKE_MAGIC;
1436 if (options & MagicPacket)
1437 wolopts |= WAKE_MAGIC;
1441 options = RTL_R8(tp, Config5);
1443 wolopts |= WAKE_UCAST;
1445 wolopts |= WAKE_BCAST;
1447 wolopts |= WAKE_MCAST;
1452 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1454 struct rtl8169_private *tp = netdev_priv(dev);
1457 wol->supported = WAKE_ANY;
1458 wol->wolopts = tp->saved_wolopts;
1459 rtl_unlock_work(tp);
1462 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1464 unsigned int i, tmp;
1465 static const struct {
1470 { WAKE_PHY, Config3, LinkUp },
1471 { WAKE_UCAST, Config5, UWF },
1472 { WAKE_BCAST, Config5, BWF },
1473 { WAKE_MCAST, Config5, MWF },
1474 { WAKE_ANY, Config5, LanWake },
1475 { WAKE_MAGIC, Config3, MagicPacket }
1479 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1483 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1484 tmp = ARRAY_SIZE(cfg) - 1;
1485 if (wolopts & WAKE_MAGIC)
1501 tmp = ARRAY_SIZE(cfg);
1505 for (i = 0; i < tmp; i++) {
1506 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1507 if (wolopts & cfg[i].opt)
1508 options |= cfg[i].mask;
1509 RTL_W8(tp, cfg[i].reg, options);
1512 switch (tp->mac_version) {
1513 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1514 options = RTL_R8(tp, Config1) & ~PMEnable;
1516 options |= PMEnable;
1517 RTL_W8(tp, Config1, options);
1520 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1522 options |= PME_SIGNAL;
1523 RTL_W8(tp, Config2, options);
1527 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1530 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1532 struct rtl8169_private *tp = netdev_priv(dev);
1533 struct device *d = tp_to_dev(tp);
1535 if (wol->wolopts & ~WAKE_ANY)
1538 pm_runtime_get_noresume(d);
1542 tp->saved_wolopts = wol->wolopts;
1544 if (pm_runtime_active(d))
1545 __rtl8169_set_wol(tp, tp->saved_wolopts);
1547 rtl_unlock_work(tp);
1549 device_set_wakeup_enable(d, tp->saved_wolopts);
1551 pm_runtime_put_noidle(d);
1556 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1558 return rtl_chip_infos[tp->mac_version].fw_name;
1561 static void rtl8169_get_drvinfo(struct net_device *dev,
1562 struct ethtool_drvinfo *info)
1564 struct rtl8169_private *tp = netdev_priv(dev);
1565 struct rtl_fw *rtl_fw = tp->rtl_fw;
1567 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1568 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1569 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1570 if (!IS_ERR_OR_NULL(rtl_fw))
1571 strlcpy(info->fw_version, rtl_fw->version,
1572 sizeof(info->fw_version));
1575 static int rtl8169_get_regs_len(struct net_device *dev)
1577 return R8169_REGS_SIZE;
1580 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1581 netdev_features_t features)
1583 struct rtl8169_private *tp = netdev_priv(dev);
1585 if (dev->mtu > TD_MSS_MAX)
1586 features &= ~NETIF_F_ALL_TSO;
1588 if (dev->mtu > JUMBO_1K &&
1589 tp->mac_version > RTL_GIGA_MAC_VER_06)
1590 features &= ~NETIF_F_IP_CSUM;
1595 static int rtl8169_set_features(struct net_device *dev,
1596 netdev_features_t features)
1598 struct rtl8169_private *tp = netdev_priv(dev);
1603 rx_config = RTL_R32(tp, RxConfig);
1604 if (features & NETIF_F_RXALL)
1605 rx_config |= (AcceptErr | AcceptRunt);
1607 rx_config &= ~(AcceptErr | AcceptRunt);
1609 RTL_W32(tp, RxConfig, rx_config);
1611 if (features & NETIF_F_RXCSUM)
1612 tp->cp_cmd |= RxChkSum;
1614 tp->cp_cmd &= ~RxChkSum;
1616 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1617 tp->cp_cmd |= RxVlan;
1619 tp->cp_cmd &= ~RxVlan;
1621 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1622 RTL_R16(tp, CPlusCmd);
1624 rtl_unlock_work(tp);
1629 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1631 return (skb_vlan_tag_present(skb)) ?
1632 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1635 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1637 u32 opts2 = le32_to_cpu(desc->opts2);
1639 if (opts2 & RxVlanTag)
1640 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1643 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1646 struct rtl8169_private *tp = netdev_priv(dev);
1647 u32 __iomem *data = tp->mmio_addr;
1652 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1653 memcpy_fromio(dw++, data++, 4);
1654 rtl_unlock_work(tp);
1657 static u32 rtl8169_get_msglevel(struct net_device *dev)
1659 struct rtl8169_private *tp = netdev_priv(dev);
1661 return tp->msg_enable;
1664 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1666 struct rtl8169_private *tp = netdev_priv(dev);
1668 tp->msg_enable = value;
1671 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1678 "tx_single_collisions",
1679 "tx_multi_collisions",
1687 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1691 return ARRAY_SIZE(rtl8169_gstrings);
1697 DECLARE_RTL_COND(rtl_counters_cond)
1699 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1702 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1704 dma_addr_t paddr = tp->counters_phys_addr;
1707 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1708 RTL_R32(tp, CounterAddrHigh);
1709 cmd = (u64)paddr & DMA_BIT_MASK(32);
1710 RTL_W32(tp, CounterAddrLow, cmd);
1711 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1713 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1716 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1719 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1722 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1725 return rtl8169_do_counters(tp, CounterReset);
1728 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1731 * Some chips are unable to dump tally counters when the receiver
1734 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1737 return rtl8169_do_counters(tp, CounterDump);
1740 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1742 struct rtl8169_counters *counters = tp->counters;
1746 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1747 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1748 * reset by a power cycle, while the counter values collected by the
1749 * driver are reset at every driver unload/load cycle.
1751 * To make sure the HW values returned by @get_stats64 match the SW
1752 * values, we collect the initial values at first open(*) and use them
1753 * as offsets to normalize the values returned by @get_stats64.
1755 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1756 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1757 * set at open time by rtl_hw_start.
1760 if (tp->tc_offset.inited)
1763 /* If both, reset and update fail, propagate to caller. */
1764 if (rtl8169_reset_counters(tp))
1767 if (rtl8169_update_counters(tp))
1770 tp->tc_offset.tx_errors = counters->tx_errors;
1771 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1772 tp->tc_offset.tx_aborted = counters->tx_aborted;
1773 tp->tc_offset.inited = true;
1778 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1779 struct ethtool_stats *stats, u64 *data)
1781 struct rtl8169_private *tp = netdev_priv(dev);
1782 struct device *d = tp_to_dev(tp);
1783 struct rtl8169_counters *counters = tp->counters;
1787 pm_runtime_get_noresume(d);
1789 if (pm_runtime_active(d))
1790 rtl8169_update_counters(tp);
1792 pm_runtime_put_noidle(d);
1794 data[0] = le64_to_cpu(counters->tx_packets);
1795 data[1] = le64_to_cpu(counters->rx_packets);
1796 data[2] = le64_to_cpu(counters->tx_errors);
1797 data[3] = le32_to_cpu(counters->rx_errors);
1798 data[4] = le16_to_cpu(counters->rx_missed);
1799 data[5] = le16_to_cpu(counters->align_errors);
1800 data[6] = le32_to_cpu(counters->tx_one_collision);
1801 data[7] = le32_to_cpu(counters->tx_multi_collision);
1802 data[8] = le64_to_cpu(counters->rx_unicast);
1803 data[9] = le64_to_cpu(counters->rx_broadcast);
1804 data[10] = le32_to_cpu(counters->rx_multicast);
1805 data[11] = le16_to_cpu(counters->tx_aborted);
1806 data[12] = le16_to_cpu(counters->tx_underun);
1809 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1813 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1819 * Interrupt coalescing
1821 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1822 * > 8169, 8168 and 810x line of chipsets
1824 * 8169, 8168, and 8136(810x) serial chipsets support it.
1826 * > 2 - the Tx timer unit at gigabit speed
1828 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1829 * (0xe0) bit 1 and bit 0.
1832 * bit[1:0] \ speed 1000M 100M 10M
1833 * 0 0 320ns 2.56us 40.96us
1834 * 0 1 2.56us 20.48us 327.7us
1835 * 1 0 5.12us 40.96us 655.4us
1836 * 1 1 10.24us 81.92us 1.31ms
1839 * bit[1:0] \ speed 1000M 100M 10M
1840 * 0 0 5us 2.56us 40.96us
1841 * 0 1 40us 20.48us 327.7us
1842 * 1 0 80us 40.96us 655.4us
1843 * 1 1 160us 81.92us 1.31ms
1846 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1847 struct rtl_coalesce_scale {
1852 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1853 struct rtl_coalesce_info {
1855 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1858 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1859 #define rxtx_x1822(r, t) { \
1862 {{(r)*8*2, (t)*8*2}}, \
1863 {{(r)*8*2*2, (t)*8*2*2}}, \
1865 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1866 /* speed delays: rx00 tx00 */
1867 { SPEED_10, rxtx_x1822(40960, 40960) },
1868 { SPEED_100, rxtx_x1822( 2560, 2560) },
1869 { SPEED_1000, rxtx_x1822( 320, 320) },
1873 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1874 /* speed delays: rx00 tx00 */
1875 { SPEED_10, rxtx_x1822(40960, 40960) },
1876 { SPEED_100, rxtx_x1822( 2560, 2560) },
1877 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1882 /* get rx/tx scale vector corresponding to current speed */
1883 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1885 struct rtl8169_private *tp = netdev_priv(dev);
1886 struct ethtool_link_ksettings ecmd;
1887 const struct rtl_coalesce_info *ci;
1890 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1894 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1895 if (ecmd.base.speed == ci->speed) {
1900 return ERR_PTR(-ELNRNG);
1903 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1905 struct rtl8169_private *tp = netdev_priv(dev);
1906 const struct rtl_coalesce_info *ci;
1907 const struct rtl_coalesce_scale *scale;
1911 } coal_settings [] = {
1912 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1913 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1914 }, *p = coal_settings;
1918 memset(ec, 0, sizeof(*ec));
1920 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1921 ci = rtl_coalesce_info(dev);
1925 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1927 /* read IntrMitigate and adjust according to scale */
1928 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1929 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1930 w >>= RTL_COALESCE_SHIFT;
1931 *p->usecs = w & RTL_COALESCE_MASK;
1934 for (i = 0; i < 2; i++) {
1935 p = coal_settings + i;
1936 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1939 * ethtool_coalesce says it is illegal to set both usecs and
1942 if (!*p->usecs && !*p->max_frames)
1949 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1950 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1951 struct net_device *dev, u32 nsec, u16 *cp01)
1953 const struct rtl_coalesce_info *ci;
1956 ci = rtl_coalesce_info(dev);
1958 return ERR_CAST(ci);
1960 for (i = 0; i < 4; i++) {
1961 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1962 ci->scalev[i].nsecs[1]);
1963 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1965 return &ci->scalev[i];
1969 return ERR_PTR(-EINVAL);
1972 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1974 struct rtl8169_private *tp = netdev_priv(dev);
1975 const struct rtl_coalesce_scale *scale;
1979 } coal_settings [] = {
1980 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1981 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1982 }, *p = coal_settings;
1986 scale = rtl_coalesce_choose_scale(dev,
1987 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1989 return PTR_ERR(scale);
1991 for (i = 0; i < 2; i++, p++) {
1995 * accept max_frames=1 we returned in rtl_get_coalesce.
1996 * accept it not only when usecs=0 because of e.g. the following scenario:
1998 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1999 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2000 * - then user does `ethtool -C eth0 rx-usecs 100`
2002 * since ethtool sends to kernel whole ethtool_coalesce
2003 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2004 * we'll reject it below in `frames % 4 != 0`.
2006 if (p->frames == 1) {
2010 units = p->usecs * 1000 / scale->nsecs[i];
2011 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2014 w <<= RTL_COALESCE_SHIFT;
2016 w <<= RTL_COALESCE_SHIFT;
2017 w |= p->frames >> 2;
2022 RTL_W16(tp, IntrMitigate, swab16(w));
2024 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2025 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2026 RTL_R16(tp, CPlusCmd);
2028 rtl_unlock_work(tp);
2033 static const struct ethtool_ops rtl8169_ethtool_ops = {
2034 .get_drvinfo = rtl8169_get_drvinfo,
2035 .get_regs_len = rtl8169_get_regs_len,
2036 .get_link = ethtool_op_get_link,
2037 .get_coalesce = rtl_get_coalesce,
2038 .set_coalesce = rtl_set_coalesce,
2039 .get_msglevel = rtl8169_get_msglevel,
2040 .set_msglevel = rtl8169_set_msglevel,
2041 .get_regs = rtl8169_get_regs,
2042 .get_wol = rtl8169_get_wol,
2043 .set_wol = rtl8169_set_wol,
2044 .get_strings = rtl8169_get_strings,
2045 .get_sset_count = rtl8169_get_sset_count,
2046 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2047 .get_ts_info = ethtool_op_get_ts_info,
2048 .nway_reset = phy_ethtool_nway_reset,
2049 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2050 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2053 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2057 * The driver currently handles the 8168Bf and the 8168Be identically
2058 * but they can be identified more specifically through the test below
2061 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2063 * Same thing for the 8101Eb and the 8101Ec:
2065 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2067 static const struct rtl_mac_info {
2072 /* 8168EP family. */
2073 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2074 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2075 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2078 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2079 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2082 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2083 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2084 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2085 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2088 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2089 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2090 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2093 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2094 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2095 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2098 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2099 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2101 /* 8168DP family. */
2102 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2103 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2104 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2107 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2108 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2109 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2110 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2111 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2112 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2113 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2116 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2117 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2118 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2121 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2122 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2123 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2124 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2125 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2126 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2127 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2128 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2129 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2130 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2131 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2132 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2133 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2134 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2135 /* FIXME: where did these entries come from ? -- FR */
2136 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2137 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2140 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2141 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2142 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2143 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2144 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2145 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2148 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2150 const struct rtl_mac_info *p = mac_info;
2153 reg = RTL_R32(tp, TxConfig);
2154 while ((reg & p->mask) != p->val)
2156 tp->mac_version = p->mac_version;
2158 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2159 dev_notice(tp_to_dev(tp),
2160 "unknown MAC, using family default\n");
2161 tp->mac_version = default_version;
2162 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2163 tp->mac_version = tp->supports_gmii ?
2164 RTL_GIGA_MAC_VER_42 :
2165 RTL_GIGA_MAC_VER_43;
2166 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2167 tp->mac_version = tp->supports_gmii ?
2168 RTL_GIGA_MAC_VER_45 :
2169 RTL_GIGA_MAC_VER_47;
2170 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2171 tp->mac_version = tp->supports_gmii ?
2172 RTL_GIGA_MAC_VER_46 :
2173 RTL_GIGA_MAC_VER_48;
2177 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2179 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2187 static void rtl_writephy_batch(struct rtl8169_private *tp,
2188 const struct phy_reg *regs, int len)
2191 rtl_writephy(tp, regs->reg, regs->val);
2196 #define PHY_READ 0x00000000
2197 #define PHY_DATA_OR 0x10000000
2198 #define PHY_DATA_AND 0x20000000
2199 #define PHY_BJMPN 0x30000000
2200 #define PHY_MDIO_CHG 0x40000000
2201 #define PHY_CLEAR_READCOUNT 0x70000000
2202 #define PHY_WRITE 0x80000000
2203 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2204 #define PHY_COMP_EQ_SKIPN 0xa0000000
2205 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2206 #define PHY_WRITE_PREVIOUS 0xc0000000
2207 #define PHY_SKIPN 0xd0000000
2208 #define PHY_DELAY_MS 0xe0000000
2212 char version[RTL_VER_SIZE];
2218 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2220 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2222 const struct firmware *fw = rtl_fw->fw;
2223 struct fw_info *fw_info = (struct fw_info *)fw->data;
2224 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2225 char *version = rtl_fw->version;
2228 if (fw->size < FW_OPCODE_SIZE)
2231 if (!fw_info->magic) {
2232 size_t i, size, start;
2235 if (fw->size < sizeof(*fw_info))
2238 for (i = 0; i < fw->size; i++)
2239 checksum += fw->data[i];
2243 start = le32_to_cpu(fw_info->fw_start);
2244 if (start > fw->size)
2247 size = le32_to_cpu(fw_info->fw_len);
2248 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2251 memcpy(version, fw_info->version, RTL_VER_SIZE);
2253 pa->code = (__le32 *)(fw->data + start);
2256 if (fw->size % FW_OPCODE_SIZE)
2259 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2261 pa->code = (__le32 *)fw->data;
2262 pa->size = fw->size / FW_OPCODE_SIZE;
2264 version[RTL_VER_SIZE - 1] = 0;
2271 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2272 struct rtl_fw_phy_action *pa)
2277 for (index = 0; index < pa->size; index++) {
2278 u32 action = le32_to_cpu(pa->code[index]);
2279 u32 regno = (action & 0x0fff0000) >> 16;
2281 switch(action & 0xf0000000) {
2286 case PHY_CLEAR_READCOUNT:
2288 case PHY_WRITE_PREVIOUS:
2293 if (regno > index) {
2294 netif_err(tp, ifup, tp->dev,
2295 "Out of range of firmware\n");
2299 case PHY_READCOUNT_EQ_SKIP:
2300 if (index + 2 >= pa->size) {
2301 netif_err(tp, ifup, tp->dev,
2302 "Out of range of firmware\n");
2306 case PHY_COMP_EQ_SKIPN:
2307 case PHY_COMP_NEQ_SKIPN:
2309 if (index + 1 + regno >= pa->size) {
2310 netif_err(tp, ifup, tp->dev,
2311 "Out of range of firmware\n");
2317 netif_err(tp, ifup, tp->dev,
2318 "Invalid action 0x%08x\n", action);
2327 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2329 struct net_device *dev = tp->dev;
2332 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2333 netif_err(tp, ifup, dev, "invalid firmware\n");
2337 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2343 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2345 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2346 struct mdio_ops org, *ops = &tp->mdio_ops;
2350 predata = count = 0;
2351 org.write = ops->write;
2352 org.read = ops->read;
2354 for (index = 0; index < pa->size; ) {
2355 u32 action = le32_to_cpu(pa->code[index]);
2356 u32 data = action & 0x0000ffff;
2357 u32 regno = (action & 0x0fff0000) >> 16;
2362 switch(action & 0xf0000000) {
2364 predata = rtl_readphy(tp, regno);
2381 ops->write = org.write;
2382 ops->read = org.read;
2383 } else if (data == 1) {
2384 ops->write = mac_mcu_write;
2385 ops->read = mac_mcu_read;
2390 case PHY_CLEAR_READCOUNT:
2395 rtl_writephy(tp, regno, data);
2398 case PHY_READCOUNT_EQ_SKIP:
2399 index += (count == data) ? 2 : 1;
2401 case PHY_COMP_EQ_SKIPN:
2402 if (predata == data)
2406 case PHY_COMP_NEQ_SKIPN:
2407 if (predata != data)
2411 case PHY_WRITE_PREVIOUS:
2412 rtl_writephy(tp, regno, predata);
2428 ops->write = org.write;
2429 ops->read = org.read;
2432 static void rtl_release_firmware(struct rtl8169_private *tp)
2434 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2435 release_firmware(tp->rtl_fw->fw);
2438 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2441 static void rtl_apply_firmware(struct rtl8169_private *tp)
2443 struct rtl_fw *rtl_fw = tp->rtl_fw;
2445 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2446 if (!IS_ERR_OR_NULL(rtl_fw))
2447 rtl_phy_write_fw(tp, rtl_fw);
2450 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2452 if (rtl_readphy(tp, reg) != val)
2453 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2455 rtl_apply_firmware(tp);
2458 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2460 static const struct phy_reg phy_reg_init[] = {
2522 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2525 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2527 static const struct phy_reg phy_reg_init[] = {
2533 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2536 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2538 struct pci_dev *pdev = tp->pci_dev;
2540 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2541 (pdev->subsystem_device != 0xe000))
2544 rtl_writephy(tp, 0x1f, 0x0001);
2545 rtl_writephy(tp, 0x10, 0xf01b);
2546 rtl_writephy(tp, 0x1f, 0x0000);
2549 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2551 static const struct phy_reg phy_reg_init[] = {
2591 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593 rtl8169scd_hw_phy_config_quirk(tp);
2596 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2598 static const struct phy_reg phy_reg_init[] = {
2646 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2649 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2651 static const struct phy_reg phy_reg_init[] = {
2656 rtl_writephy(tp, 0x1f, 0x0001);
2657 rtl_patchphy(tp, 0x16, 1 << 0);
2659 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2662 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2664 static const struct phy_reg phy_reg_init[] = {
2670 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2673 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2675 static const struct phy_reg phy_reg_init[] = {
2683 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2686 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2688 static const struct phy_reg phy_reg_init[] = {
2694 rtl_writephy(tp, 0x1f, 0x0000);
2695 rtl_patchphy(tp, 0x14, 1 << 5);
2696 rtl_patchphy(tp, 0x0d, 1 << 5);
2698 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2701 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2703 static const struct phy_reg phy_reg_init[] = {
2723 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2725 rtl_patchphy(tp, 0x14, 1 << 5);
2726 rtl_patchphy(tp, 0x0d, 1 << 5);
2727 rtl_writephy(tp, 0x1f, 0x0000);
2730 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2732 static const struct phy_reg phy_reg_init[] = {
2750 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2752 rtl_patchphy(tp, 0x16, 1 << 0);
2753 rtl_patchphy(tp, 0x14, 1 << 5);
2754 rtl_patchphy(tp, 0x0d, 1 << 5);
2755 rtl_writephy(tp, 0x1f, 0x0000);
2758 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2760 static const struct phy_reg phy_reg_init[] = {
2772 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2774 rtl_patchphy(tp, 0x16, 1 << 0);
2775 rtl_patchphy(tp, 0x14, 1 << 5);
2776 rtl_patchphy(tp, 0x0d, 1 << 5);
2777 rtl_writephy(tp, 0x1f, 0x0000);
2780 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2782 rtl8168c_3_hw_phy_config(tp);
2785 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2787 static const struct phy_reg phy_reg_init_0[] = {
2788 /* Channel Estimation */
2809 * Enhance line driver power
2818 * Can not link to 1Gbps with bad cable
2819 * Decrease SNR threshold form 21.07dB to 19.04dB
2828 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2832 * Fine Tune Switching regulator parameter
2834 rtl_writephy(tp, 0x1f, 0x0002);
2835 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2836 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2838 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2839 static const struct phy_reg phy_reg_init[] = {
2849 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851 val = rtl_readphy(tp, 0x0d);
2853 if ((val & 0x00ff) != 0x006c) {
2854 static const u32 set[] = {
2855 0x0065, 0x0066, 0x0067, 0x0068,
2856 0x0069, 0x006a, 0x006b, 0x006c
2860 rtl_writephy(tp, 0x1f, 0x0002);
2863 for (i = 0; i < ARRAY_SIZE(set); i++)
2864 rtl_writephy(tp, 0x0d, val | set[i]);
2867 static const struct phy_reg phy_reg_init[] = {
2875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2878 /* RSET couple improve */
2879 rtl_writephy(tp, 0x1f, 0x0002);
2880 rtl_patchphy(tp, 0x0d, 0x0300);
2881 rtl_patchphy(tp, 0x0f, 0x0010);
2883 /* Fine tune PLL performance */
2884 rtl_writephy(tp, 0x1f, 0x0002);
2885 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2886 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2888 rtl_writephy(tp, 0x1f, 0x0005);
2889 rtl_writephy(tp, 0x05, 0x001b);
2891 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2893 rtl_writephy(tp, 0x1f, 0x0000);
2896 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2898 static const struct phy_reg phy_reg_init_0[] = {
2899 /* Channel Estimation */
2920 * Enhance line driver power
2929 * Can not link to 1Gbps with bad cable
2930 * Decrease SNR threshold form 21.07dB to 19.04dB
2939 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2941 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2942 static const struct phy_reg phy_reg_init[] = {
2953 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2955 val = rtl_readphy(tp, 0x0d);
2956 if ((val & 0x00ff) != 0x006c) {
2957 static const u32 set[] = {
2958 0x0065, 0x0066, 0x0067, 0x0068,
2959 0x0069, 0x006a, 0x006b, 0x006c
2963 rtl_writephy(tp, 0x1f, 0x0002);
2966 for (i = 0; i < ARRAY_SIZE(set); i++)
2967 rtl_writephy(tp, 0x0d, val | set[i]);
2970 static const struct phy_reg phy_reg_init[] = {
2978 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2981 /* Fine tune PLL performance */
2982 rtl_writephy(tp, 0x1f, 0x0002);
2983 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2984 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2986 /* Switching regulator Slew rate */
2987 rtl_writephy(tp, 0x1f, 0x0002);
2988 rtl_patchphy(tp, 0x0f, 0x0017);
2990 rtl_writephy(tp, 0x1f, 0x0005);
2991 rtl_writephy(tp, 0x05, 0x001b);
2993 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2995 rtl_writephy(tp, 0x1f, 0x0000);
2998 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3000 static const struct phy_reg phy_reg_init[] = {
3056 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3059 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3061 static const struct phy_reg phy_reg_init[] = {
3071 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3072 rtl_patchphy(tp, 0x0d, 1 << 5);
3075 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3077 static const struct phy_reg phy_reg_init[] = {
3078 /* Enable Delay cap */
3084 /* Channel estimation fine tune */
3093 /* Update PFM & 10M TX idle timer */
3105 rtl_apply_firmware(tp);
3107 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109 /* DCO enable for 10M IDLE Power */
3110 rtl_writephy(tp, 0x1f, 0x0007);
3111 rtl_writephy(tp, 0x1e, 0x0023);
3112 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3113 rtl_writephy(tp, 0x1f, 0x0000);
3115 /* For impedance matching */
3116 rtl_writephy(tp, 0x1f, 0x0002);
3117 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3118 rtl_writephy(tp, 0x1f, 0x0000);
3120 /* PHY auto speed down */
3121 rtl_writephy(tp, 0x1f, 0x0007);
3122 rtl_writephy(tp, 0x1e, 0x002d);
3123 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3124 rtl_writephy(tp, 0x1f, 0x0000);
3125 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3127 rtl_writephy(tp, 0x1f, 0x0005);
3128 rtl_writephy(tp, 0x05, 0x8b86);
3129 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3130 rtl_writephy(tp, 0x1f, 0x0000);
3132 rtl_writephy(tp, 0x1f, 0x0005);
3133 rtl_writephy(tp, 0x05, 0x8b85);
3134 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3135 rtl_writephy(tp, 0x1f, 0x0007);
3136 rtl_writephy(tp, 0x1e, 0x0020);
3137 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3138 rtl_writephy(tp, 0x1f, 0x0006);
3139 rtl_writephy(tp, 0x00, 0x5a00);
3140 rtl_writephy(tp, 0x1f, 0x0000);
3141 rtl_writephy(tp, 0x0d, 0x0007);
3142 rtl_writephy(tp, 0x0e, 0x003c);
3143 rtl_writephy(tp, 0x0d, 0x4007);
3144 rtl_writephy(tp, 0x0e, 0x0000);
3145 rtl_writephy(tp, 0x0d, 0x0000);
3148 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3151 addr[0] | (addr[1] << 8),
3152 addr[2] | (addr[3] << 8),
3153 addr[4] | (addr[5] << 8)
3155 const struct exgmac_reg e[] = {
3156 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3157 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3158 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3159 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3162 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3165 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3167 static const struct phy_reg phy_reg_init[] = {
3168 /* Enable Delay cap */
3177 /* Channel estimation fine tune */
3194 rtl_apply_firmware(tp);
3196 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3198 /* For 4-corner performance improve */
3199 rtl_writephy(tp, 0x1f, 0x0005);
3200 rtl_writephy(tp, 0x05, 0x8b80);
3201 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3202 rtl_writephy(tp, 0x1f, 0x0000);
3204 /* PHY auto speed down */
3205 rtl_writephy(tp, 0x1f, 0x0004);
3206 rtl_writephy(tp, 0x1f, 0x0007);
3207 rtl_writephy(tp, 0x1e, 0x002d);
3208 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3209 rtl_writephy(tp, 0x1f, 0x0002);
3210 rtl_writephy(tp, 0x1f, 0x0000);
3211 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3213 /* improve 10M EEE waveform */
3214 rtl_writephy(tp, 0x1f, 0x0005);
3215 rtl_writephy(tp, 0x05, 0x8b86);
3216 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3217 rtl_writephy(tp, 0x1f, 0x0000);
3219 /* Improve 2-pair detection performance */
3220 rtl_writephy(tp, 0x1f, 0x0005);
3221 rtl_writephy(tp, 0x05, 0x8b85);
3222 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3223 rtl_writephy(tp, 0x1f, 0x0000);
3226 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3227 rtl_writephy(tp, 0x1f, 0x0005);
3228 rtl_writephy(tp, 0x05, 0x8b85);
3229 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3230 rtl_writephy(tp, 0x1f, 0x0004);
3231 rtl_writephy(tp, 0x1f, 0x0007);
3232 rtl_writephy(tp, 0x1e, 0x0020);
3233 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3234 rtl_writephy(tp, 0x1f, 0x0002);
3235 rtl_writephy(tp, 0x1f, 0x0000);
3236 rtl_writephy(tp, 0x0d, 0x0007);
3237 rtl_writephy(tp, 0x0e, 0x003c);
3238 rtl_writephy(tp, 0x0d, 0x4007);
3239 rtl_writephy(tp, 0x0e, 0x0006);
3240 rtl_writephy(tp, 0x0d, 0x0000);
3243 rtl_writephy(tp, 0x1f, 0x0003);
3244 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3245 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3246 rtl_writephy(tp, 0x1f, 0x0000);
3247 rtl_writephy(tp, 0x1f, 0x0005);
3248 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3249 rtl_writephy(tp, 0x1f, 0x0000);