r8169: fix broken Wake-on-LAN from S5 (poweroff)
[muen/linux.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/crc32.h>
22 #include <linux/in.h>
23 #include <linux/io.h>
24 #include <linux/ip.h>
25 #include <linux/tcp.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
33
34 #define MODULENAME "r8169"
35
36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
55
56 #define R8169_MSG_DEFAULT \
57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
58
59 #define TX_SLOTS_AVAIL(tp) \
60         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
61
62 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
63 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
64         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
65
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit = 32;
69
70 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE         256
74 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
77 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
78 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
79
80 /* write/read MMIO register */
81 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
84 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
85 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
86 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
87
88 enum mac_version {
89         RTL_GIGA_MAC_VER_01 = 0,
90         RTL_GIGA_MAC_VER_02,
91         RTL_GIGA_MAC_VER_03,
92         RTL_GIGA_MAC_VER_04,
93         RTL_GIGA_MAC_VER_05,
94         RTL_GIGA_MAC_VER_06,
95         RTL_GIGA_MAC_VER_07,
96         RTL_GIGA_MAC_VER_08,
97         RTL_GIGA_MAC_VER_09,
98         RTL_GIGA_MAC_VER_10,
99         RTL_GIGA_MAC_VER_11,
100         RTL_GIGA_MAC_VER_12,
101         RTL_GIGA_MAC_VER_13,
102         RTL_GIGA_MAC_VER_14,
103         RTL_GIGA_MAC_VER_15,
104         RTL_GIGA_MAC_VER_16,
105         RTL_GIGA_MAC_VER_17,
106         RTL_GIGA_MAC_VER_18,
107         RTL_GIGA_MAC_VER_19,
108         RTL_GIGA_MAC_VER_20,
109         RTL_GIGA_MAC_VER_21,
110         RTL_GIGA_MAC_VER_22,
111         RTL_GIGA_MAC_VER_23,
112         RTL_GIGA_MAC_VER_24,
113         RTL_GIGA_MAC_VER_25,
114         RTL_GIGA_MAC_VER_26,
115         RTL_GIGA_MAC_VER_27,
116         RTL_GIGA_MAC_VER_28,
117         RTL_GIGA_MAC_VER_29,
118         RTL_GIGA_MAC_VER_30,
119         RTL_GIGA_MAC_VER_31,
120         RTL_GIGA_MAC_VER_32,
121         RTL_GIGA_MAC_VER_33,
122         RTL_GIGA_MAC_VER_34,
123         RTL_GIGA_MAC_VER_35,
124         RTL_GIGA_MAC_VER_36,
125         RTL_GIGA_MAC_VER_37,
126         RTL_GIGA_MAC_VER_38,
127         RTL_GIGA_MAC_VER_39,
128         RTL_GIGA_MAC_VER_40,
129         RTL_GIGA_MAC_VER_41,
130         RTL_GIGA_MAC_VER_42,
131         RTL_GIGA_MAC_VER_43,
132         RTL_GIGA_MAC_VER_44,
133         RTL_GIGA_MAC_VER_45,
134         RTL_GIGA_MAC_VER_46,
135         RTL_GIGA_MAC_VER_47,
136         RTL_GIGA_MAC_VER_48,
137         RTL_GIGA_MAC_VER_49,
138         RTL_GIGA_MAC_VER_50,
139         RTL_GIGA_MAC_VER_51,
140         RTL_GIGA_MAC_NONE   = 0xff,
141 };
142
143 #define JUMBO_1K        ETH_DATA_LEN
144 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
145 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
146 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
147 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
148
149 static const struct {
150         const char *name;
151         const char *fw_name;
152 } rtl_chip_infos[] = {
153         /* PCI devices. */
154         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
155         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
156         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
157         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
158         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
159         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
160         /* PCI-E devices. */
161         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
162         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
163         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
164         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
165         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
166         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
167         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
168         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
169         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
170         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
171         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
172         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
173         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
174         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
175         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
176         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
177         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
178         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
179         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
180         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
181         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
182         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
183         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
184         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
185         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
186         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
187         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
188         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
189         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
190         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
191         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
192         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
193         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
194         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
195         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
196         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
197         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
198         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
199         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
200         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
201         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
202         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
203         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
204         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
205         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
206 };
207
208 enum cfg_version {
209         RTL_CFG_0 = 0x00,
210         RTL_CFG_1,
211         RTL_CFG_2
212 };
213
214 static const struct pci_device_id rtl8169_pci_tbl[] = {
215         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
216         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
217         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
218         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
219         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
220         { PCI_DEVICE(PCI_VENDOR_ID_NCUBE,       0x8168), 0, 0, RTL_CFG_1 },
221         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
222         { PCI_VENDOR_ID_DLINK,                  0x4300,
223                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
224         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
225         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
226         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
227         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
228         { PCI_VENDOR_ID_LINKSYS,                0x1032,
229                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
230         { 0x0001,                               0x8168,
231                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
232         {0,},
233 };
234
235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
236
237 static int use_dac = -1;
238 static struct {
239         u32 msg_enable;
240 } debug = { -1 };
241
242 enum rtl_registers {
243         MAC0            = 0,    /* Ethernet hardware address. */
244         MAC4            = 4,
245         MAR0            = 8,    /* Multicast filter. */
246         CounterAddrLow          = 0x10,
247         CounterAddrHigh         = 0x14,
248         TxDescStartAddrLow      = 0x20,
249         TxDescStartAddrHigh     = 0x24,
250         TxHDescStartAddrLow     = 0x28,
251         TxHDescStartAddrHigh    = 0x2c,
252         FLASH           = 0x30,
253         ERSR            = 0x36,
254         ChipCmd         = 0x37,
255         TxPoll          = 0x38,
256         IntrMask        = 0x3c,
257         IntrStatus      = 0x3e,
258
259         TxConfig        = 0x40,
260 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
261 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
262
263         RxConfig        = 0x44,
264 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
265 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
266 #define RXCFG_FIFO_SHIFT                13
267                                         /* No threshold before first PCI xfer */
268 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
269 #define RX_EARLY_OFF                    (1 << 11)
270 #define RXCFG_DMA_SHIFT                 8
271                                         /* Unlimited maximum PCI burst. */
272 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
273
274         RxMissed        = 0x4c,
275         Cfg9346         = 0x50,
276         Config0         = 0x51,
277         Config1         = 0x52,
278         Config2         = 0x53,
279 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
280
281         Config3         = 0x54,
282         Config4         = 0x55,
283         Config5         = 0x56,
284         MultiIntr       = 0x5c,
285         PHYAR           = 0x60,
286         PHYstatus       = 0x6c,
287         RxMaxSize       = 0xda,
288         CPlusCmd        = 0xe0,
289         IntrMitigate    = 0xe2,
290
291 #define RTL_COALESCE_MASK       0x0f
292 #define RTL_COALESCE_SHIFT      4
293 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
294 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
295
296         RxDescAddrLow   = 0xe4,
297         RxDescAddrHigh  = 0xe8,
298         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
299
300 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
301
302         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
303
304 #define TxPacketMax     (8064 >> 7)
305 #define EarlySize       0x27
306
307         FuncEvent       = 0xf0,
308         FuncEventMask   = 0xf4,
309         FuncPresetState = 0xf8,
310         IBCR0           = 0xf8,
311         IBCR2           = 0xf9,
312         IBIMR0          = 0xfa,
313         IBISR0          = 0xfb,
314         FuncForceEvent  = 0xfc,
315 };
316
317 enum rtl8168_8101_registers {
318         CSIDR                   = 0x64,
319         CSIAR                   = 0x68,
320 #define CSIAR_FLAG                      0x80000000
321 #define CSIAR_WRITE_CMD                 0x80000000
322 #define CSIAR_BYTE_ENABLE               0x0000f000
323 #define CSIAR_ADDR_MASK                 0x00000fff
324         PMCH                    = 0x6f,
325         EPHYAR                  = 0x80,
326 #define EPHYAR_FLAG                     0x80000000
327 #define EPHYAR_WRITE_CMD                0x80000000
328 #define EPHYAR_REG_MASK                 0x1f
329 #define EPHYAR_REG_SHIFT                16
330 #define EPHYAR_DATA_MASK                0xffff
331         DLLPR                   = 0xd0,
332 #define PFM_EN                          (1 << 6)
333 #define TX_10M_PS_EN                    (1 << 7)
334         DBG_REG                 = 0xd1,
335 #define FIX_NAK_1                       (1 << 4)
336 #define FIX_NAK_2                       (1 << 3)
337         TWSI                    = 0xd2,
338         MCU                     = 0xd3,
339 #define NOW_IS_OOB                      (1 << 7)
340 #define TX_EMPTY                        (1 << 5)
341 #define RX_EMPTY                        (1 << 4)
342 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
343 #define EN_NDP                          (1 << 3)
344 #define EN_OOB_RESET                    (1 << 2)
345 #define LINK_LIST_RDY                   (1 << 1)
346         EFUSEAR                 = 0xdc,
347 #define EFUSEAR_FLAG                    0x80000000
348 #define EFUSEAR_WRITE_CMD               0x80000000
349 #define EFUSEAR_READ_CMD                0x00000000
350 #define EFUSEAR_REG_MASK                0x03ff
351 #define EFUSEAR_REG_SHIFT               8
352 #define EFUSEAR_DATA_MASK               0xff
353         MISC_1                  = 0xf2,
354 #define PFM_D3COLD_EN                   (1 << 6)
355 };
356
357 enum rtl8168_registers {
358         LED_FREQ                = 0x1a,
359         EEE_LED                 = 0x1b,
360         ERIDR                   = 0x70,
361         ERIAR                   = 0x74,
362 #define ERIAR_FLAG                      0x80000000
363 #define ERIAR_WRITE_CMD                 0x80000000
364 #define ERIAR_READ_CMD                  0x00000000
365 #define ERIAR_ADDR_BYTE_ALIGN           4
366 #define ERIAR_TYPE_SHIFT                16
367 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
368 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
369 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
370 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
371 #define ERIAR_MASK_SHIFT                12
372 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
373 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
374 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
375 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
377         EPHY_RXER_NUM           = 0x7c,
378         OCPDR                   = 0xb0, /* OCP GPHY access */
379 #define OCPDR_WRITE_CMD                 0x80000000
380 #define OCPDR_READ_CMD                  0x00000000
381 #define OCPDR_REG_MASK                  0x7f
382 #define OCPDR_GPHY_REG_SHIFT            16
383 #define OCPDR_DATA_MASK                 0xffff
384         OCPAR                   = 0xb4,
385 #define OCPAR_FLAG                      0x80000000
386 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
387 #define OCPAR_GPHY_READ_CMD             0x0000f060
388         GPHY_OCP                = 0xb8,
389         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
390         MISC                    = 0xf0, /* 8168e only. */
391 #define TXPLA_RST                       (1 << 29)
392 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
393 #define PWM_EN                          (1 << 22)
394 #define RXDV_GATED_EN                   (1 << 19)
395 #define EARLY_TALLY_EN                  (1 << 16)
396 };
397
398 enum rtl_register_content {
399         /* InterruptStatusBits */
400         SYSErr          = 0x8000,
401         PCSTimeout      = 0x4000,
402         SWInt           = 0x0100,
403         TxDescUnavail   = 0x0080,
404         RxFIFOOver      = 0x0040,
405         LinkChg         = 0x0020,
406         RxOverflow      = 0x0010,
407         TxErr           = 0x0008,
408         TxOK            = 0x0004,
409         RxErr           = 0x0002,
410         RxOK            = 0x0001,
411
412         /* RxStatusDesc */
413         RxBOVF  = (1 << 24),
414         RxFOVF  = (1 << 23),
415         RxRWT   = (1 << 22),
416         RxRES   = (1 << 21),
417         RxRUNT  = (1 << 20),
418         RxCRC   = (1 << 19),
419
420         /* ChipCmdBits */
421         StopReq         = 0x80,
422         CmdReset        = 0x10,
423         CmdRxEnb        = 0x08,
424         CmdTxEnb        = 0x04,
425         RxBufEmpty      = 0x01,
426
427         /* TXPoll register p.5 */
428         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
429         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
430         FSWInt          = 0x01,         /* Forced software interrupt */
431
432         /* Cfg9346Bits */
433         Cfg9346_Lock    = 0x00,
434         Cfg9346_Unlock  = 0xc0,
435
436         /* rx_mode_bits */
437         AcceptErr       = 0x20,
438         AcceptRunt      = 0x10,
439         AcceptBroadcast = 0x08,
440         AcceptMulticast = 0x04,
441         AcceptMyPhys    = 0x02,
442         AcceptAllPhys   = 0x01,
443 #define RX_CONFIG_ACCEPT_MASK           0x3f
444
445         /* TxConfigBits */
446         TxInterFrameGapShift = 24,
447         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
448
449         /* Config1 register p.24 */
450         LEDS1           = (1 << 7),
451         LEDS0           = (1 << 6),
452         Speed_down      = (1 << 4),
453         MEMMAP          = (1 << 3),
454         IOMAP           = (1 << 2),
455         VPD             = (1 << 1),
456         PMEnable        = (1 << 0),     /* Power Management Enable */
457
458         /* Config2 register p. 25 */
459         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
460         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
461         PCI_Clock_66MHz = 0x01,
462         PCI_Clock_33MHz = 0x00,
463
464         /* Config3 register p.25 */
465         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
466         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
467         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
468         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
469         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
470
471         /* Config4 register */
472         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
473
474         /* Config5 register p.27 */
475         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
476         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
477         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
478         Spi_en          = (1 << 3),
479         LanWake         = (1 << 1),     /* LanWake enable/disable */
480         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
481         ASPM_en         = (1 << 0),     /* ASPM enable */
482
483         /* CPlusCmd p.31 */
484         EnableBist      = (1 << 15),    // 8168 8101
485         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
486         Normal_mode     = (1 << 13),    // unused
487         Force_half_dup  = (1 << 12),    // 8168 8101
488         Force_rxflow_en = (1 << 11),    // 8168 8101
489         Force_txflow_en = (1 << 10),    // 8168 8101
490         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
491         ASF             = (1 << 8),     // 8168 8101
492         PktCntrDisable  = (1 << 7),     // 8168 8101
493         Mac_dbgo_sel    = 0x001c,       // 8168
494         RxVlan          = (1 << 6),
495         RxChkSum        = (1 << 5),
496         PCIDAC          = (1 << 4),
497         PCIMulRW        = (1 << 3),
498 #define INTT_MASK       GENMASK(1, 0)
499         INTT_0          = 0x0000,       // 8168
500         INTT_1          = 0x0001,       // 8168
501         INTT_2          = 0x0002,       // 8168
502         INTT_3          = 0x0003,       // 8168
503
504         /* rtl8169_PHYstatus */
505         TBI_Enable      = 0x80,
506         TxFlowCtrl      = 0x40,
507         RxFlowCtrl      = 0x20,
508         _1000bpsF       = 0x10,
509         _100bps         = 0x08,
510         _10bps          = 0x04,
511         LinkStatus      = 0x02,
512         FullDup         = 0x01,
513
514         /* _TBICSRBit */
515         TBILinkOK       = 0x02000000,
516
517         /* ResetCounterCommand */
518         CounterReset    = 0x1,
519
520         /* DumpCounterCommand */
521         CounterDump     = 0x8,
522
523         /* magic enable v2 */
524         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
525 };
526
527 enum rtl_desc_bit {
528         /* First doubleword. */
529         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
530         RingEnd         = (1 << 30), /* End of descriptor ring */
531         FirstFrag       = (1 << 29), /* First segment of a packet */
532         LastFrag        = (1 << 28), /* Final segment of a packet */
533 };
534
535 /* Generic case. */
536 enum rtl_tx_desc_bit {
537         /* First doubleword. */
538         TD_LSO          = (1 << 27),            /* Large Send Offload */
539 #define TD_MSS_MAX                      0x07ffu /* MSS value */
540
541         /* Second doubleword. */
542         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
543 };
544
545 /* 8169, 8168b and 810x except 8102e. */
546 enum rtl_tx_desc_bit_0 {
547         /* First doubleword. */
548 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
549         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
550         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
551         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
552 };
553
554 /* 8102e, 8168c and beyond. */
555 enum rtl_tx_desc_bit_1 {
556         /* First doubleword. */
557         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
558         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
559 #define GTTCPHO_SHIFT                   18
560 #define GTTCPHO_MAX                     0x7fU
561
562         /* Second doubleword. */
563 #define TCPHO_SHIFT                     18
564 #define TCPHO_MAX                       0x3ffU
565 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
566         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
567         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
568         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
569         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
570 };
571
572 enum rtl_rx_desc_bit {
573         /* Rx private */
574         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
575         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
576
577 #define RxProtoUDP      (PID1)
578 #define RxProtoTCP      (PID0)
579 #define RxProtoIP       (PID1 | PID0)
580 #define RxProtoMask     RxProtoIP
581
582         IPFail          = (1 << 16), /* IP checksum failed */
583         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
584         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
585         RxVlanTag       = (1 << 16), /* VLAN tag available */
586 };
587
588 #define RsvdMask        0x3fffc000
589 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
590
591 struct TxDesc {
592         __le32 opts1;
593         __le32 opts2;
594         __le64 addr;
595 };
596
597 struct RxDesc {
598         __le32 opts1;
599         __le32 opts2;
600         __le64 addr;
601 };
602
603 struct ring_info {
604         struct sk_buff  *skb;
605         u32             len;
606         u8              __pad[sizeof(void *) - sizeof(u32)];
607 };
608
609 struct rtl8169_counters {
610         __le64  tx_packets;
611         __le64  rx_packets;
612         __le64  tx_errors;
613         __le32  rx_errors;
614         __le16  rx_missed;
615         __le16  align_errors;
616         __le32  tx_one_collision;
617         __le32  tx_multi_collision;
618         __le64  rx_unicast;
619         __le64  rx_broadcast;
620         __le32  rx_multicast;
621         __le16  tx_aborted;
622         __le16  tx_underun;
623 };
624
625 struct rtl8169_tc_offsets {
626         bool    inited;
627         __le64  tx_errors;
628         __le32  tx_multi_collision;
629         __le16  tx_aborted;
630 };
631
632 enum rtl_flag {
633         RTL_FLAG_TASK_ENABLED = 0,
634         RTL_FLAG_TASK_RESET_PENDING,
635         RTL_FLAG_MAX
636 };
637
638 struct rtl8169_stats {
639         u64                     packets;
640         u64                     bytes;
641         struct u64_stats_sync   syncp;
642 };
643
644 struct rtl8169_private {
645         void __iomem *mmio_addr;        /* memory map physical address */
646         struct pci_dev *pci_dev;
647         struct net_device *dev;
648         struct napi_struct napi;
649         u32 msg_enable;
650         u16 mac_version;
651         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
652         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
653         u32 dirty_tx;
654         struct rtl8169_stats rx_stats;
655         struct rtl8169_stats tx_stats;
656         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
657         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
658         dma_addr_t TxPhyAddr;
659         dma_addr_t RxPhyAddr;
660         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
661         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
662         u16 cp_cmd;
663
664         u16 event_slow;
665         const struct rtl_coalesce_info *coalesce_info;
666         struct clk *clk;
667
668         struct mdio_ops {
669                 void (*write)(struct rtl8169_private *, int, int);
670                 int (*read)(struct rtl8169_private *, int);
671         } mdio_ops;
672
673         struct jumbo_ops {
674                 void (*enable)(struct rtl8169_private *);
675                 void (*disable)(struct rtl8169_private *);
676         } jumbo_ops;
677
678         void (*hw_start)(struct rtl8169_private *tp);
679         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
680
681         struct {
682                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
683                 struct mutex mutex;
684                 struct work_struct work;
685         } wk;
686
687         unsigned supports_gmii:1;
688         struct mii_bus *mii_bus;
689         dma_addr_t counters_phys_addr;
690         struct rtl8169_counters *counters;
691         struct rtl8169_tc_offsets tc_offset;
692         u32 saved_wolopts;
693
694         struct rtl_fw {
695                 const struct firmware *fw;
696
697 #define RTL_VER_SIZE            32
698
699                 char version[RTL_VER_SIZE];
700
701                 struct rtl_fw_phy_action {
702                         __le32 *code;
703                         size_t size;
704                 } phy_action;
705         } *rtl_fw;
706 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
707
708         u32 ocp_base;
709 };
710
711 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
712 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
713 module_param(use_dac, int, 0);
714 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
715 module_param_named(debug, debug.msg_enable, int, 0);
716 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
717 MODULE_LICENSE("GPL");
718 MODULE_FIRMWARE(FIRMWARE_8168D_1);
719 MODULE_FIRMWARE(FIRMWARE_8168D_2);
720 MODULE_FIRMWARE(FIRMWARE_8168E_1);
721 MODULE_FIRMWARE(FIRMWARE_8168E_2);
722 MODULE_FIRMWARE(FIRMWARE_8168E_3);
723 MODULE_FIRMWARE(FIRMWARE_8105E_1);
724 MODULE_FIRMWARE(FIRMWARE_8168F_1);
725 MODULE_FIRMWARE(FIRMWARE_8168F_2);
726 MODULE_FIRMWARE(FIRMWARE_8402_1);
727 MODULE_FIRMWARE(FIRMWARE_8411_1);
728 MODULE_FIRMWARE(FIRMWARE_8411_2);
729 MODULE_FIRMWARE(FIRMWARE_8106E_1);
730 MODULE_FIRMWARE(FIRMWARE_8106E_2);
731 MODULE_FIRMWARE(FIRMWARE_8168G_2);
732 MODULE_FIRMWARE(FIRMWARE_8168G_3);
733 MODULE_FIRMWARE(FIRMWARE_8168H_1);
734 MODULE_FIRMWARE(FIRMWARE_8168H_2);
735 MODULE_FIRMWARE(FIRMWARE_8107E_1);
736 MODULE_FIRMWARE(FIRMWARE_8107E_2);
737
738 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
739 {
740         return &tp->pci_dev->dev;
741 }
742
743 static void rtl_lock_work(struct rtl8169_private *tp)
744 {
745         mutex_lock(&tp->wk.mutex);
746 }
747
748 static void rtl_unlock_work(struct rtl8169_private *tp)
749 {
750         mutex_unlock(&tp->wk.mutex);
751 }
752
753 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
754 {
755         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
756                                            PCI_EXP_DEVCTL_READRQ, force);
757 }
758
759 struct rtl_cond {
760         bool (*check)(struct rtl8169_private *);
761         const char *msg;
762 };
763
764 static void rtl_udelay(unsigned int d)
765 {
766         udelay(d);
767 }
768
769 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
770                           void (*delay)(unsigned int), unsigned int d, int n,
771                           bool high)
772 {
773         int i;
774
775         for (i = 0; i < n; i++) {
776                 delay(d);
777                 if (c->check(tp) == high)
778                         return true;
779         }
780         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
781                   c->msg, !high, n, d);
782         return false;
783 }
784
785 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
786                                       const struct rtl_cond *c,
787                                       unsigned int d, int n)
788 {
789         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
790 }
791
792 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
793                                      const struct rtl_cond *c,
794                                      unsigned int d, int n)
795 {
796         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
797 }
798
799 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
800                                       const struct rtl_cond *c,
801                                       unsigned int d, int n)
802 {
803         return rtl_loop_wait(tp, c, msleep, d, n, true);
804 }
805
806 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
807                                      const struct rtl_cond *c,
808                                      unsigned int d, int n)
809 {
810         return rtl_loop_wait(tp, c, msleep, d, n, false);
811 }
812
813 #define DECLARE_RTL_COND(name)                          \
814 static bool name ## _check(struct rtl8169_private *);   \
815                                                         \
816 static const struct rtl_cond name = {                   \
817         .check  = name ## _check,                       \
818         .msg    = #name                                 \
819 };                                                      \
820                                                         \
821 static bool name ## _check(struct rtl8169_private *tp)
822
823 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
824 {
825         if (reg & 0xffff0001) {
826                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
827                 return true;
828         }
829         return false;
830 }
831
832 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
833 {
834         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
835 }
836
837 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
838 {
839         if (rtl_ocp_reg_failure(tp, reg))
840                 return;
841
842         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
843
844         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
845 }
846
847 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
848 {
849         if (rtl_ocp_reg_failure(tp, reg))
850                 return 0;
851
852         RTL_W32(tp, GPHY_OCP, reg << 15);
853
854         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
855                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
856 }
857
858 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
859 {
860         if (rtl_ocp_reg_failure(tp, reg))
861                 return;
862
863         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
864 }
865
866 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
867 {
868         if (rtl_ocp_reg_failure(tp, reg))
869                 return 0;
870
871         RTL_W32(tp, OCPDR, reg << 15);
872
873         return RTL_R32(tp, OCPDR);
874 }
875
876 #define OCP_STD_PHY_BASE        0xa400
877
878 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
879 {
880         if (reg == 0x1f) {
881                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
882                 return;
883         }
884
885         if (tp->ocp_base != OCP_STD_PHY_BASE)
886                 reg -= 0x10;
887
888         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
889 }
890
891 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
892 {
893         if (tp->ocp_base != OCP_STD_PHY_BASE)
894                 reg -= 0x10;
895
896         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
897 }
898
899 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
900 {
901         if (reg == 0x1f) {
902                 tp->ocp_base = value << 4;
903                 return;
904         }
905
906         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
907 }
908
909 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
910 {
911         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
912 }
913
914 DECLARE_RTL_COND(rtl_phyar_cond)
915 {
916         return RTL_R32(tp, PHYAR) & 0x80000000;
917 }
918
919 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
920 {
921         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
922
923         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
924         /*
925          * According to hardware specs a 20us delay is required after write
926          * complete indication, but before sending next command.
927          */
928         udelay(20);
929 }
930
931 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
932 {
933         int value;
934
935         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
936
937         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
938                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
939
940         /*
941          * According to hardware specs a 20us delay is required after read
942          * complete indication, but before sending next command.
943          */
944         udelay(20);
945
946         return value;
947 }
948
949 DECLARE_RTL_COND(rtl_ocpar_cond)
950 {
951         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
952 }
953
954 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
955 {
956         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
957         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
958         RTL_W32(tp, EPHY_RXER_NUM, 0);
959
960         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
961 }
962
963 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
964 {
965         r8168dp_1_mdio_access(tp, reg,
966                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
967 }
968
969 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
970 {
971         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
972
973         mdelay(1);
974         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
975         RTL_W32(tp, EPHY_RXER_NUM, 0);
976
977         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
978                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
979 }
980
981 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
982
983 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
984 {
985         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
986 }
987
988 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
989 {
990         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
991 }
992
993 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
994 {
995         r8168dp_2_mdio_start(tp);
996
997         r8169_mdio_write(tp, reg, value);
998
999         r8168dp_2_mdio_stop(tp);
1000 }
1001
1002 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1003 {
1004         int value;
1005
1006         r8168dp_2_mdio_start(tp);
1007
1008         value = r8169_mdio_read(tp, reg);
1009
1010         r8168dp_2_mdio_stop(tp);
1011
1012         return value;
1013 }
1014
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1016 {
1017         tp->mdio_ops.write(tp, location, val);
1018 }
1019
1020 static int rtl_readphy(struct rtl8169_private *tp, int location)
1021 {
1022         return tp->mdio_ops.read(tp, location);
1023 }
1024
1025 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1026 {
1027         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1028 }
1029
1030 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1031 {
1032         int val;
1033
1034         val = rtl_readphy(tp, reg_addr);
1035         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1036 }
1037
1038 DECLARE_RTL_COND(rtl_ephyar_cond)
1039 {
1040         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1041 }
1042
1043 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1044 {
1045         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1046                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1047
1048         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1049
1050         udelay(10);
1051 }
1052
1053 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1054 {
1055         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1056
1057         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1058                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1059 }
1060
1061 DECLARE_RTL_COND(rtl_eriar_cond)
1062 {
1063         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1064 }
1065
1066 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1067                           u32 val, int type)
1068 {
1069         BUG_ON((addr & 3) || (mask == 0));
1070         RTL_W32(tp, ERIDR, val);
1071         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1072
1073         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1074 }
1075
1076 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1077 {
1078         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1079
1080         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1081                 RTL_R32(tp, ERIDR) : ~0;
1082 }
1083
1084 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1085                          u32 m, int type)
1086 {
1087         u32 val;
1088
1089         val = rtl_eri_read(tp, addr, type);
1090         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1091 }
1092
1093 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1094 {
1095         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1096         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1097                 RTL_R32(tp, OCPDR) : ~0;
1098 }
1099
1100 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1101 {
1102         return rtl_eri_read(tp, reg, ERIAR_OOB);
1103 }
1104
1105 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1106 {
1107         switch (tp->mac_version) {
1108         case RTL_GIGA_MAC_VER_27:
1109         case RTL_GIGA_MAC_VER_28:
1110         case RTL_GIGA_MAC_VER_31:
1111                 return r8168dp_ocp_read(tp, mask, reg);
1112         case RTL_GIGA_MAC_VER_49:
1113         case RTL_GIGA_MAC_VER_50:
1114         case RTL_GIGA_MAC_VER_51:
1115                 return r8168ep_ocp_read(tp, mask, reg);
1116         default:
1117                 BUG();
1118                 return ~0;
1119         }
1120 }
1121
1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1123                               u32 data)
1124 {
1125         RTL_W32(tp, OCPDR, data);
1126         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1127         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1128 }
1129
1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1131                               u32 data)
1132 {
1133         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1134                       data, ERIAR_OOB);
1135 }
1136
1137 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1138 {
1139         switch (tp->mac_version) {
1140         case RTL_GIGA_MAC_VER_27:
1141         case RTL_GIGA_MAC_VER_28:
1142         case RTL_GIGA_MAC_VER_31:
1143                 r8168dp_ocp_write(tp, mask, reg, data);
1144                 break;
1145         case RTL_GIGA_MAC_VER_49:
1146         case RTL_GIGA_MAC_VER_50:
1147         case RTL_GIGA_MAC_VER_51:
1148                 r8168ep_ocp_write(tp, mask, reg, data);
1149                 break;
1150         default:
1151                 BUG();
1152                 break;
1153         }
1154 }
1155
1156 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1157 {
1158         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1159
1160         ocp_write(tp, 0x1, 0x30, 0x00000001);
1161 }
1162
1163 #define OOB_CMD_RESET           0x00
1164 #define OOB_CMD_DRIVER_START    0x05
1165 #define OOB_CMD_DRIVER_STOP     0x06
1166
1167 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1168 {
1169         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1170 }
1171
1172 DECLARE_RTL_COND(rtl_ocp_read_cond)
1173 {
1174         u16 reg;
1175
1176         reg = rtl8168_get_ocp_reg(tp);
1177
1178         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1179 }
1180
1181 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1182 {
1183         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1184 }
1185
1186 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1187 {
1188         return RTL_R8(tp, IBISR0) & 0x20;
1189 }
1190
1191 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1192 {
1193         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1194         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1195         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1196         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1197 }
1198
1199 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1200 {
1201         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1202         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1203 }
1204
1205 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1206 {
1207         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1208         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1209         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1210 }
1211
1212 static void rtl8168_driver_start(struct rtl8169_private *tp)
1213 {
1214         switch (tp->mac_version) {
1215         case RTL_GIGA_MAC_VER_27:
1216         case RTL_GIGA_MAC_VER_28:
1217         case RTL_GIGA_MAC_VER_31:
1218                 rtl8168dp_driver_start(tp);
1219                 break;
1220         case RTL_GIGA_MAC_VER_49:
1221         case RTL_GIGA_MAC_VER_50:
1222         case RTL_GIGA_MAC_VER_51:
1223                 rtl8168ep_driver_start(tp);
1224                 break;
1225         default:
1226                 BUG();
1227                 break;
1228         }
1229 }
1230
1231 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1232 {
1233         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1234         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1235 }
1236
1237 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1238 {
1239         rtl8168ep_stop_cmac(tp);
1240         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1241         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1242         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1243 }
1244
1245 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1246 {
1247         switch (tp->mac_version) {
1248         case RTL_GIGA_MAC_VER_27:
1249         case RTL_GIGA_MAC_VER_28:
1250         case RTL_GIGA_MAC_VER_31:
1251                 rtl8168dp_driver_stop(tp);
1252                 break;
1253         case RTL_GIGA_MAC_VER_49:
1254         case RTL_GIGA_MAC_VER_50:
1255         case RTL_GIGA_MAC_VER_51:
1256                 rtl8168ep_driver_stop(tp);
1257                 break;
1258         default:
1259                 BUG();
1260                 break;
1261         }
1262 }
1263
1264 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1265 {
1266         u16 reg = rtl8168_get_ocp_reg(tp);
1267
1268         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1269 }
1270
1271 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1272 {
1273         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1274 }
1275
1276 static bool r8168_check_dash(struct rtl8169_private *tp)
1277 {
1278         switch (tp->mac_version) {
1279         case RTL_GIGA_MAC_VER_27:
1280         case RTL_GIGA_MAC_VER_28:
1281         case RTL_GIGA_MAC_VER_31:
1282                 return r8168dp_check_dash(tp);
1283         case RTL_GIGA_MAC_VER_49:
1284         case RTL_GIGA_MAC_VER_50:
1285         case RTL_GIGA_MAC_VER_51:
1286                 return r8168ep_check_dash(tp);
1287         default:
1288                 return false;
1289         }
1290 }
1291
1292 struct exgmac_reg {
1293         u16 addr;
1294         u16 mask;
1295         u32 val;
1296 };
1297
1298 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1299                                    const struct exgmac_reg *r, int len)
1300 {
1301         while (len-- > 0) {
1302                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1303                 r++;
1304         }
1305 }
1306
1307 DECLARE_RTL_COND(rtl_efusear_cond)
1308 {
1309         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1310 }
1311
1312 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1313 {
1314         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1315
1316         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1317                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1318 }
1319
1320 static u16 rtl_get_events(struct rtl8169_private *tp)
1321 {
1322         return RTL_R16(tp, IntrStatus);
1323 }
1324
1325 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1326 {
1327         RTL_W16(tp, IntrStatus, bits);
1328         mmiowb();
1329 }
1330
1331 static void rtl_irq_disable(struct rtl8169_private *tp)
1332 {
1333         RTL_W16(tp, IntrMask, 0);
1334         mmiowb();
1335 }
1336
1337 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1338 {
1339         RTL_W16(tp, IntrMask, bits);
1340 }
1341
1342 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1343 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1344 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1345
1346 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1347 {
1348         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1349 }
1350
1351 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1352 {
1353         rtl_irq_disable(tp);
1354         rtl_ack_events(tp, 0xffff);
1355         /* PCI commit */
1356         RTL_R8(tp, ChipCmd);
1357 }
1358
1359 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1360 {
1361         struct net_device *dev = tp->dev;
1362         struct phy_device *phydev = dev->phydev;
1363
1364         if (!netif_running(dev))
1365                 return;
1366
1367         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1368             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1369                 if (phydev->speed == SPEED_1000) {
1370                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1371                                       ERIAR_EXGMAC);
1372                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1373                                       ERIAR_EXGMAC);
1374                 } else if (phydev->speed == SPEED_100) {
1375                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1376                                       ERIAR_EXGMAC);
1377                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1378                                       ERIAR_EXGMAC);
1379                 } else {
1380                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1381                                       ERIAR_EXGMAC);
1382                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1383                                       ERIAR_EXGMAC);
1384                 }
1385                 /* Reset packet filter */
1386                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1387                              ERIAR_EXGMAC);
1388                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1389                              ERIAR_EXGMAC);
1390         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1391                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1392                 if (phydev->speed == SPEED_1000) {
1393                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1394                                       ERIAR_EXGMAC);
1395                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1396                                       ERIAR_EXGMAC);
1397                 } else {
1398                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1399                                       ERIAR_EXGMAC);
1400                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1401                                       ERIAR_EXGMAC);
1402                 }
1403         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1404                 if (phydev->speed == SPEED_10) {
1405                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1406                                       ERIAR_EXGMAC);
1407                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1408                                       ERIAR_EXGMAC);
1409                 } else {
1410                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1411                                       ERIAR_EXGMAC);
1412                 }
1413         }
1414 }
1415
1416 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1417
1418 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1419 {
1420         u8 options;
1421         u32 wolopts = 0;
1422
1423         options = RTL_R8(tp, Config1);
1424         if (!(options & PMEnable))
1425                 return 0;
1426
1427         options = RTL_R8(tp, Config3);
1428         if (options & LinkUp)
1429                 wolopts |= WAKE_PHY;
1430         switch (tp->mac_version) {
1431         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1432         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1433                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1434                         wolopts |= WAKE_MAGIC;
1435                 break;
1436         default:
1437                 if (options & MagicPacket)
1438                         wolopts |= WAKE_MAGIC;
1439                 break;
1440         }
1441
1442         options = RTL_R8(tp, Config5);
1443         if (options & UWF)
1444                 wolopts |= WAKE_UCAST;
1445         if (options & BWF)
1446                 wolopts |= WAKE_BCAST;
1447         if (options & MWF)
1448                 wolopts |= WAKE_MCAST;
1449
1450         return wolopts;
1451 }
1452
1453 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1454 {
1455         struct rtl8169_private *tp = netdev_priv(dev);
1456
1457         rtl_lock_work(tp);
1458         wol->supported = WAKE_ANY;
1459         wol->wolopts = tp->saved_wolopts;
1460         rtl_unlock_work(tp);
1461 }
1462
1463 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1464 {
1465         unsigned int i, tmp;
1466         static const struct {
1467                 u32 opt;
1468                 u16 reg;
1469                 u8  mask;
1470         } cfg[] = {
1471                 { WAKE_PHY,   Config3, LinkUp },
1472                 { WAKE_UCAST, Config5, UWF },
1473                 { WAKE_BCAST, Config5, BWF },
1474                 { WAKE_MCAST, Config5, MWF },
1475                 { WAKE_ANY,   Config5, LanWake },
1476                 { WAKE_MAGIC, Config3, MagicPacket }
1477         };
1478         u8 options;
1479
1480         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1481
1482         switch (tp->mac_version) {
1483         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1484         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1485                 tmp = ARRAY_SIZE(cfg) - 1;
1486                 if (wolopts & WAKE_MAGIC)
1487                         rtl_w0w1_eri(tp,
1488                                      0x0dc,
1489                                      ERIAR_MASK_0100,
1490                                      MagicPacket_v2,
1491                                      0x0000,
1492                                      ERIAR_EXGMAC);
1493                 else
1494                         rtl_w0w1_eri(tp,
1495                                      0x0dc,
1496                                      ERIAR_MASK_0100,
1497                                      0x0000,
1498                                      MagicPacket_v2,
1499                                      ERIAR_EXGMAC);
1500                 break;
1501         default:
1502                 tmp = ARRAY_SIZE(cfg);
1503                 break;
1504         }
1505
1506         for (i = 0; i < tmp; i++) {
1507                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1508                 if (wolopts & cfg[i].opt)
1509                         options |= cfg[i].mask;
1510                 RTL_W8(tp, cfg[i].reg, options);
1511         }
1512
1513         switch (tp->mac_version) {
1514         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1515                 options = RTL_R8(tp, Config1) & ~PMEnable;
1516                 if (wolopts)
1517                         options |= PMEnable;
1518                 RTL_W8(tp, Config1, options);
1519                 break;
1520         default:
1521                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1522                 if (wolopts)
1523                         options |= PME_SIGNAL;
1524                 RTL_W8(tp, Config2, options);
1525                 break;
1526         }
1527
1528         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1529 }
1530
1531 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1532 {
1533         struct rtl8169_private *tp = netdev_priv(dev);
1534         struct device *d = tp_to_dev(tp);
1535
1536         if (wol->wolopts & ~WAKE_ANY)
1537                 return -EINVAL;
1538
1539         pm_runtime_get_noresume(d);
1540
1541         rtl_lock_work(tp);
1542
1543         tp->saved_wolopts = wol->wolopts;
1544
1545         if (pm_runtime_active(d))
1546                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1547
1548         rtl_unlock_work(tp);
1549
1550         device_set_wakeup_enable(d, tp->saved_wolopts);
1551
1552         pm_runtime_put_noidle(d);
1553
1554         return 0;
1555 }
1556
1557 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1558 {
1559         return rtl_chip_infos[tp->mac_version].fw_name;
1560 }
1561
1562 static void rtl8169_get_drvinfo(struct net_device *dev,
1563                                 struct ethtool_drvinfo *info)
1564 {
1565         struct rtl8169_private *tp = netdev_priv(dev);
1566         struct rtl_fw *rtl_fw = tp->rtl_fw;
1567
1568         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1569         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1570         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1571         if (!IS_ERR_OR_NULL(rtl_fw))
1572                 strlcpy(info->fw_version, rtl_fw->version,
1573                         sizeof(info->fw_version));
1574 }
1575
1576 static int rtl8169_get_regs_len(struct net_device *dev)
1577 {
1578         return R8169_REGS_SIZE;
1579 }
1580
1581 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1582         netdev_features_t features)
1583 {
1584         struct rtl8169_private *tp = netdev_priv(dev);
1585
1586         if (dev->mtu > TD_MSS_MAX)
1587                 features &= ~NETIF_F_ALL_TSO;
1588
1589         if (dev->mtu > JUMBO_1K &&
1590             tp->mac_version > RTL_GIGA_MAC_VER_06)
1591                 features &= ~NETIF_F_IP_CSUM;
1592
1593         return features;
1594 }
1595
1596 static int rtl8169_set_features(struct net_device *dev,
1597                                 netdev_features_t features)
1598 {
1599         struct rtl8169_private *tp = netdev_priv(dev);
1600         u32 rx_config;
1601
1602         rtl_lock_work(tp);
1603
1604         rx_config = RTL_R32(tp, RxConfig);
1605         if (features & NETIF_F_RXALL)
1606                 rx_config |= (AcceptErr | AcceptRunt);
1607         else
1608                 rx_config &= ~(AcceptErr | AcceptRunt);
1609
1610         RTL_W32(tp, RxConfig, rx_config);
1611
1612         if (features & NETIF_F_RXCSUM)
1613                 tp->cp_cmd |= RxChkSum;
1614         else
1615                 tp->cp_cmd &= ~RxChkSum;
1616
1617         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1618                 tp->cp_cmd |= RxVlan;
1619         else
1620                 tp->cp_cmd &= ~RxVlan;
1621
1622         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1623         RTL_R16(tp, CPlusCmd);
1624
1625         rtl_unlock_work(tp);
1626
1627         return 0;
1628 }
1629
1630 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1631 {
1632         return (skb_vlan_tag_present(skb)) ?
1633                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1634 }
1635
1636 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1637 {
1638         u32 opts2 = le32_to_cpu(desc->opts2);
1639
1640         if (opts2 & RxVlanTag)
1641                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1642 }
1643
1644 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1645                              void *p)
1646 {
1647         struct rtl8169_private *tp = netdev_priv(dev);
1648         u32 __iomem *data = tp->mmio_addr;
1649         u32 *dw = p;
1650         int i;
1651
1652         rtl_lock_work(tp);
1653         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1654                 memcpy_fromio(dw++, data++, 4);
1655         rtl_unlock_work(tp);
1656 }
1657
1658 static u32 rtl8169_get_msglevel(struct net_device *dev)
1659 {
1660         struct rtl8169_private *tp = netdev_priv(dev);
1661
1662         return tp->msg_enable;
1663 }
1664
1665 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1666 {
1667         struct rtl8169_private *tp = netdev_priv(dev);
1668
1669         tp->msg_enable = value;
1670 }
1671
1672 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1673         "tx_packets",
1674         "rx_packets",
1675         "tx_errors",
1676         "rx_errors",
1677         "rx_missed",
1678         "align_errors",
1679         "tx_single_collisions",
1680         "tx_multi_collisions",
1681         "unicast",
1682         "broadcast",
1683         "multicast",
1684         "tx_aborted",
1685         "tx_underrun",
1686 };
1687
1688 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1689 {
1690         switch (sset) {
1691         case ETH_SS_STATS:
1692                 return ARRAY_SIZE(rtl8169_gstrings);
1693         default:
1694                 return -EOPNOTSUPP;
1695         }
1696 }
1697
1698 DECLARE_RTL_COND(rtl_counters_cond)
1699 {
1700         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1701 }
1702
1703 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1704 {
1705         dma_addr_t paddr = tp->counters_phys_addr;
1706         u32 cmd;
1707
1708         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1709         RTL_R32(tp, CounterAddrHigh);
1710         cmd = (u64)paddr & DMA_BIT_MASK(32);
1711         RTL_W32(tp, CounterAddrLow, cmd);
1712         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1713
1714         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1715 }
1716
1717 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1718 {
1719         /*
1720          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1721          * tally counters.
1722          */
1723         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1724                 return true;
1725
1726         return rtl8169_do_counters(tp, CounterReset);
1727 }
1728
1729 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1730 {
1731         /*
1732          * Some chips are unable to dump tally counters when the receiver
1733          * is disabled.
1734          */
1735         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1736                 return true;
1737
1738         return rtl8169_do_counters(tp, CounterDump);
1739 }
1740
1741 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1742 {
1743         struct rtl8169_counters *counters = tp->counters;
1744         bool ret = false;
1745
1746         /*
1747          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1748          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1749          * reset by a power cycle, while the counter values collected by the
1750          * driver are reset at every driver unload/load cycle.
1751          *
1752          * To make sure the HW values returned by @get_stats64 match the SW
1753          * values, we collect the initial values at first open(*) and use them
1754          * as offsets to normalize the values returned by @get_stats64.
1755          *
1756          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1757          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1758          * set at open time by rtl_hw_start.
1759          */
1760
1761         if (tp->tc_offset.inited)
1762                 return true;
1763
1764         /* If both, reset and update fail, propagate to caller. */
1765         if (rtl8169_reset_counters(tp))
1766                 ret = true;
1767
1768         if (rtl8169_update_counters(tp))
1769                 ret = true;
1770
1771         tp->tc_offset.tx_errors = counters->tx_errors;
1772         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1773         tp->tc_offset.tx_aborted = counters->tx_aborted;
1774         tp->tc_offset.inited = true;
1775
1776         return ret;
1777 }
1778
1779 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1780                                       struct ethtool_stats *stats, u64 *data)
1781 {
1782         struct rtl8169_private *tp = netdev_priv(dev);
1783         struct device *d = tp_to_dev(tp);
1784         struct rtl8169_counters *counters = tp->counters;
1785
1786         ASSERT_RTNL();
1787
1788         pm_runtime_get_noresume(d);
1789
1790         if (pm_runtime_active(d))
1791                 rtl8169_update_counters(tp);
1792
1793         pm_runtime_put_noidle(d);
1794
1795         data[0] = le64_to_cpu(counters->tx_packets);
1796         data[1] = le64_to_cpu(counters->rx_packets);
1797         data[2] = le64_to_cpu(counters->tx_errors);
1798         data[3] = le32_to_cpu(counters->rx_errors);
1799         data[4] = le16_to_cpu(counters->rx_missed);
1800         data[5] = le16_to_cpu(counters->align_errors);
1801         data[6] = le32_to_cpu(counters->tx_one_collision);
1802         data[7] = le32_to_cpu(counters->tx_multi_collision);
1803         data[8] = le64_to_cpu(counters->rx_unicast);
1804         data[9] = le64_to_cpu(counters->rx_broadcast);
1805         data[10] = le32_to_cpu(counters->rx_multicast);
1806         data[11] = le16_to_cpu(counters->tx_aborted);
1807         data[12] = le16_to_cpu(counters->tx_underun);
1808 }
1809
1810 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1811 {
1812         switch(stringset) {
1813         case ETH_SS_STATS:
1814                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1815                 break;
1816         }
1817 }
1818
1819 /*
1820  * Interrupt coalescing
1821  *
1822  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1823  * >     8169, 8168 and 810x line of chipsets
1824  *
1825  * 8169, 8168, and 8136(810x) serial chipsets support it.
1826  *
1827  * > 2 - the Tx timer unit at gigabit speed
1828  *
1829  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1830  * (0xe0) bit 1 and bit 0.
1831  *
1832  * For 8169
1833  * bit[1:0] \ speed        1000M           100M            10M
1834  * 0 0                     320ns           2.56us          40.96us
1835  * 0 1                     2.56us          20.48us         327.7us
1836  * 1 0                     5.12us          40.96us         655.4us
1837  * 1 1                     10.24us         81.92us         1.31ms
1838  *
1839  * For the other
1840  * bit[1:0] \ speed        1000M           100M            10M
1841  * 0 0                     5us             2.56us          40.96us
1842  * 0 1                     40us            20.48us         327.7us
1843  * 1 0                     80us            40.96us         655.4us
1844  * 1 1                     160us           81.92us         1.31ms
1845  */
1846
1847 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1848 struct rtl_coalesce_scale {
1849         /* Rx / Tx */
1850         u32 nsecs[2];
1851 };
1852
1853 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1854 struct rtl_coalesce_info {
1855         u32 speed;
1856         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1857 };
1858
1859 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1860 #define rxtx_x1822(r, t) {              \
1861         {{(r),          (t)}},          \
1862         {{(r)*8,        (t)*8}},        \
1863         {{(r)*8*2,      (t)*8*2}},      \
1864         {{(r)*8*2*2,    (t)*8*2*2}},    \
1865 }
1866 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1867         /* speed        delays:     rx00   tx00 */
1868         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1869         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1870         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1871         { 0 },
1872 };
1873
1874 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1875         /* speed        delays:     rx00   tx00 */
1876         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1877         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1878         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1879         { 0 },
1880 };
1881 #undef rxtx_x1822
1882
1883 /* get rx/tx scale vector corresponding to current speed */
1884 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1885 {
1886         struct rtl8169_private *tp = netdev_priv(dev);
1887         struct ethtool_link_ksettings ecmd;
1888         const struct rtl_coalesce_info *ci;
1889         int rc;
1890
1891         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1892         if (rc < 0)
1893                 return ERR_PTR(rc);
1894
1895         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1896                 if (ecmd.base.speed == ci->speed) {
1897                         return ci;
1898                 }
1899         }
1900
1901         return ERR_PTR(-ELNRNG);
1902 }
1903
1904 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1905 {
1906         struct rtl8169_private *tp = netdev_priv(dev);
1907         const struct rtl_coalesce_info *ci;
1908         const struct rtl_coalesce_scale *scale;
1909         struct {
1910                 u32 *max_frames;
1911                 u32 *usecs;
1912         } coal_settings [] = {
1913                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1914                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1915         }, *p = coal_settings;
1916         int i;
1917         u16 w;
1918
1919         memset(ec, 0, sizeof(*ec));
1920
1921         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1922         ci = rtl_coalesce_info(dev);
1923         if (IS_ERR(ci))
1924                 return PTR_ERR(ci);
1925
1926         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1927
1928         /* read IntrMitigate and adjust according to scale */
1929         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1930                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1931                 w >>= RTL_COALESCE_SHIFT;
1932                 *p->usecs = w & RTL_COALESCE_MASK;
1933         }
1934
1935         for (i = 0; i < 2; i++) {
1936                 p = coal_settings + i;
1937                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1938
1939                 /*
1940                  * ethtool_coalesce says it is illegal to set both usecs and
1941                  * max_frames to 0.
1942                  */
1943                 if (!*p->usecs && !*p->max_frames)
1944                         *p->max_frames = 1;
1945         }
1946
1947         return 0;
1948 }
1949
1950 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1951 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1952                         struct net_device *dev, u32 nsec, u16 *cp01)
1953 {
1954         const struct rtl_coalesce_info *ci;
1955         u16 i;
1956
1957         ci = rtl_coalesce_info(dev);
1958         if (IS_ERR(ci))
1959                 return ERR_CAST(ci);
1960
1961         for (i = 0; i < 4; i++) {
1962                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1963                                         ci->scalev[i].nsecs[1]);
1964                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1965                         *cp01 = i;
1966                         return &ci->scalev[i];
1967                 }
1968         }
1969
1970         return ERR_PTR(-EINVAL);
1971 }
1972
1973 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1974 {
1975         struct rtl8169_private *tp = netdev_priv(dev);
1976         const struct rtl_coalesce_scale *scale;
1977         struct {
1978                 u32 frames;
1979                 u32 usecs;
1980         } coal_settings [] = {
1981                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1982                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1983         }, *p = coal_settings;
1984         u16 w = 0, cp01;
1985         int i;
1986
1987         scale = rtl_coalesce_choose_scale(dev,
1988                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1989         if (IS_ERR(scale))
1990                 return PTR_ERR(scale);
1991
1992         for (i = 0; i < 2; i++, p++) {
1993                 u32 units;
1994
1995                 /*
1996                  * accept max_frames=1 we returned in rtl_get_coalesce.
1997                  * accept it not only when usecs=0 because of e.g. the following scenario:
1998                  *
1999                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2000                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2001                  * - then user does `ethtool -C eth0 rx-usecs 100`
2002                  *
2003                  * since ethtool sends to kernel whole ethtool_coalesce
2004                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2005                  * we'll reject it below in `frames % 4 != 0`.
2006                  */
2007                 if (p->frames == 1) {
2008                         p->frames = 0;
2009                 }
2010
2011                 units = p->usecs * 1000 / scale->nsecs[i];
2012                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2013                         return -EINVAL;
2014
2015                 w <<= RTL_COALESCE_SHIFT;
2016                 w |= units;
2017                 w <<= RTL_COALESCE_SHIFT;
2018                 w |= p->frames >> 2;
2019         }
2020
2021         rtl_lock_work(tp);
2022
2023         RTL_W16(tp, IntrMitigate, swab16(w));
2024
2025         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2026         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2027         RTL_R16(tp, CPlusCmd);
2028
2029         rtl_unlock_work(tp);
2030
2031         return 0;
2032 }
2033
2034 static const struct ethtool_ops rtl8169_ethtool_ops = {
2035         .get_drvinfo            = rtl8169_get_drvinfo,
2036         .get_regs_len           = rtl8169_get_regs_len,
2037         .get_link               = ethtool_op_get_link,
2038         .get_coalesce           = rtl_get_coalesce,
2039         .set_coalesce           = rtl_set_coalesce,
2040         .get_msglevel           = rtl8169_get_msglevel,
2041         .set_msglevel           = rtl8169_set_msglevel,
2042         .get_regs               = rtl8169_get_regs,
2043         .get_wol                = rtl8169_get_wol,
2044         .set_wol                = rtl8169_set_wol,
2045         .get_strings            = rtl8169_get_strings,
2046         .get_sset_count         = rtl8169_get_sset_count,
2047         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2048         .get_ts_info            = ethtool_op_get_ts_info,
2049         .nway_reset             = phy_ethtool_nway_reset,
2050         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2051         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2052 };
2053
2054 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2055                                     u8 default_version)
2056 {
2057         /*
2058          * The driver currently handles the 8168Bf and the 8168Be identically
2059          * but they can be identified more specifically through the test below
2060          * if needed:
2061          *
2062          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2063          *
2064          * Same thing for the 8101Eb and the 8101Ec:
2065          *
2066          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2067          */
2068         static const struct rtl_mac_info {
2069                 u32 mask;
2070                 u32 val;
2071                 int mac_version;
2072         } mac_info[] = {
2073                 /* 8168EP family. */
2074                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2075                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2076                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2077
2078                 /* 8168H family. */
2079                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2080                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2081
2082                 /* 8168G family. */
2083                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2084                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2085                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2086                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2087
2088                 /* 8168F family. */
2089                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2090                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2091                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2092
2093                 /* 8168E family. */
2094                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2095                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2096                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2097
2098                 /* 8168D family. */
2099                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2100                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2101
2102                 /* 8168DP family. */
2103                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2104                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2105                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2106
2107                 /* 8168C family. */
2108                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2109                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2110                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2111                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2112                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2113                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2114                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2115
2116                 /* 8168B family. */
2117                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2118                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2119                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2120
2121                 /* 8101 family. */
2122                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2123                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2124                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2125                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2126                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2127                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2128                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2129                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2130                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2131                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2132                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2133                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2134                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2135                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2136                 /* FIXME: where did these entries come from ? -- FR */
2137                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2138                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2139
2140                 /* 8110 family. */
2141                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2142                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2143                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2144                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2145                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2146                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2147
2148                 /* Catch-all */
2149                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2150         };
2151         const struct rtl_mac_info *p = mac_info;
2152         u32 reg;
2153
2154         reg = RTL_R32(tp, TxConfig);
2155         while ((reg & p->mask) != p->val)
2156                 p++;
2157         tp->mac_version = p->mac_version;
2158
2159         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2160                 dev_notice(tp_to_dev(tp),
2161                            "unknown MAC, using family default\n");
2162                 tp->mac_version = default_version;
2163         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2164                 tp->mac_version = tp->supports_gmii ?
2165                                   RTL_GIGA_MAC_VER_42 :
2166                                   RTL_GIGA_MAC_VER_43;
2167         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2168                 tp->mac_version = tp->supports_gmii ?
2169                                   RTL_GIGA_MAC_VER_45 :
2170                                   RTL_GIGA_MAC_VER_47;
2171         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2172                 tp->mac_version = tp->supports_gmii ?
2173                                   RTL_GIGA_MAC_VER_46 :
2174                                   RTL_GIGA_MAC_VER_48;
2175         }
2176 }
2177
2178 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2179 {
2180         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2181 }
2182
2183 struct phy_reg {
2184         u16 reg;
2185         u16 val;
2186 };
2187
2188 static void rtl_writephy_batch(struct rtl8169_private *tp,
2189                                const struct phy_reg *regs, int len)
2190 {
2191         while (len-- > 0) {
2192                 rtl_writephy(tp, regs->reg, regs->val);
2193                 regs++;
2194         }
2195 }
2196
2197 #define PHY_READ                0x00000000
2198 #define PHY_DATA_OR             0x10000000
2199 #define PHY_DATA_AND            0x20000000
2200 #define PHY_BJMPN               0x30000000
2201 #define PHY_MDIO_CHG            0x40000000
2202 #define PHY_CLEAR_READCOUNT     0x70000000
2203 #define PHY_WRITE               0x80000000
2204 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2205 #define PHY_COMP_EQ_SKIPN       0xa0000000
2206 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2207 #define PHY_WRITE_PREVIOUS      0xc0000000
2208 #define PHY_SKIPN               0xd0000000
2209 #define PHY_DELAY_MS            0xe0000000
2210
2211 struct fw_info {
2212         u32     magic;
2213         char    version[RTL_VER_SIZE];
2214         __le32  fw_start;
2215         __le32  fw_len;
2216         u8      chksum;
2217 } __packed;
2218
2219 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2220
2221 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2222 {
2223         const struct firmware *fw = rtl_fw->fw;
2224         struct fw_info *fw_info = (struct fw_info *)fw->data;
2225         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2226         char *version = rtl_fw->version;
2227         bool rc = false;
2228
2229         if (fw->size < FW_OPCODE_SIZE)
2230                 goto out;
2231
2232         if (!fw_info->magic) {
2233                 size_t i, size, start;
2234                 u8 checksum = 0;
2235
2236                 if (fw->size < sizeof(*fw_info))
2237                         goto out;
2238
2239                 for (i = 0; i < fw->size; i++)
2240                         checksum += fw->data[i];
2241                 if (checksum != 0)
2242                         goto out;
2243
2244                 start = le32_to_cpu(fw_info->fw_start);
2245                 if (start > fw->size)
2246                         goto out;
2247
2248                 size = le32_to_cpu(fw_info->fw_len);
2249                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2250                         goto out;
2251
2252                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2253
2254                 pa->code = (__le32 *)(fw->data + start);
2255                 pa->size = size;
2256         } else {
2257                 if (fw->size % FW_OPCODE_SIZE)
2258                         goto out;
2259
2260                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2261
2262                 pa->code = (__le32 *)fw->data;
2263                 pa->size = fw->size / FW_OPCODE_SIZE;
2264         }
2265         version[RTL_VER_SIZE - 1] = 0;
2266
2267         rc = true;
2268 out:
2269         return rc;
2270 }
2271
2272 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2273                            struct rtl_fw_phy_action *pa)
2274 {
2275         bool rc = false;
2276         size_t index;
2277
2278         for (index = 0; index < pa->size; index++) {
2279                 u32 action = le32_to_cpu(pa->code[index]);
2280                 u32 regno = (action & 0x0fff0000) >> 16;
2281
2282                 switch(action & 0xf0000000) {
2283                 case PHY_READ:
2284                 case PHY_DATA_OR:
2285                 case PHY_DATA_AND:
2286                 case PHY_MDIO_CHG:
2287                 case PHY_CLEAR_READCOUNT:
2288                 case PHY_WRITE:
2289                 case PHY_WRITE_PREVIOUS:
2290                 case PHY_DELAY_MS:
2291                         break;
2292
2293                 case PHY_BJMPN:
2294                         if (regno > index) {
2295                                 netif_err(tp, ifup, tp->dev,
2296                                           "Out of range of firmware\n");
2297                                 goto out;
2298                         }
2299                         break;
2300                 case PHY_READCOUNT_EQ_SKIP:
2301                         if (index + 2 >= pa->size) {
2302                                 netif_err(tp, ifup, tp->dev,
2303                                           "Out of range of firmware\n");
2304                                 goto out;
2305                         }
2306                         break;
2307                 case PHY_COMP_EQ_SKIPN:
2308                 case PHY_COMP_NEQ_SKIPN:
2309                 case PHY_SKIPN:
2310                         if (index + 1 + regno >= pa->size) {
2311                                 netif_err(tp, ifup, tp->dev,
2312                                           "Out of range of firmware\n");
2313                                 goto out;
2314                         }
2315                         break;
2316
2317                 default:
2318                         netif_err(tp, ifup, tp->dev,
2319                                   "Invalid action 0x%08x\n", action);
2320                         goto out;
2321                 }
2322         }
2323         rc = true;
2324 out:
2325         return rc;
2326 }
2327
2328 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2329 {
2330         struct net_device *dev = tp->dev;
2331         int rc = -EINVAL;
2332
2333         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2334                 netif_err(tp, ifup, dev, "invalid firmware\n");
2335                 goto out;
2336         }
2337
2338         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2339                 rc = 0;
2340 out:
2341         return rc;
2342 }
2343
2344 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2345 {
2346         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2347         struct mdio_ops org, *ops = &tp->mdio_ops;
2348         u32 predata, count;
2349         size_t index;
2350
2351         predata = count = 0;
2352         org.write = ops->write;
2353         org.read = ops->read;
2354
2355         for (index = 0; index < pa->size; ) {
2356                 u32 action = le32_to_cpu(pa->code[index]);
2357                 u32 data = action & 0x0000ffff;
2358                 u32 regno = (action & 0x0fff0000) >> 16;
2359
2360                 if (!action)
2361                         break;
2362
2363                 switch(action & 0xf0000000) {
2364                 case PHY_READ:
2365                         predata = rtl_readphy(tp, regno);
2366                         count++;
2367                         index++;
2368                         break;
2369                 case PHY_DATA_OR:
2370                         predata |= data;
2371                         index++;
2372                         break;
2373                 case PHY_DATA_AND:
2374                         predata &= data;
2375                         index++;
2376                         break;
2377                 case PHY_BJMPN:
2378                         index -= regno;
2379                         break;
2380                 case PHY_MDIO_CHG:
2381                         if (data == 0) {
2382                                 ops->write = org.write;
2383                                 ops->read = org.read;
2384                         } else if (data == 1) {
2385                                 ops->write = mac_mcu_write;
2386                                 ops->read = mac_mcu_read;
2387                         }
2388
2389                         index++;
2390                         break;
2391                 case PHY_CLEAR_READCOUNT:
2392                         count = 0;
2393                         index++;
2394                         break;
2395                 case PHY_WRITE:
2396                         rtl_writephy(tp, regno, data);
2397                         index++;
2398                         break;
2399                 case PHY_READCOUNT_EQ_SKIP:
2400                         index += (count == data) ? 2 : 1;
2401                         break;
2402                 case PHY_COMP_EQ_SKIPN:
2403                         if (predata == data)
2404                                 index += regno;
2405                         index++;
2406                         break;
2407                 case PHY_COMP_NEQ_SKIPN:
2408                         if (predata != data)
2409                                 index += regno;
2410                         index++;
2411                         break;
2412                 case PHY_WRITE_PREVIOUS:
2413                         rtl_writephy(tp, regno, predata);
2414                         index++;
2415                         break;
2416                 case PHY_SKIPN:
2417                         index += regno + 1;
2418                         break;
2419                 case PHY_DELAY_MS:
2420                         mdelay(data);
2421                         index++;
2422                         break;
2423
2424                 default:
2425                         BUG();
2426                 }
2427         }
2428
2429         ops->write = org.write;
2430         ops->read = org.read;
2431 }
2432
2433 static void rtl_release_firmware(struct rtl8169_private *tp)
2434 {
2435         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2436                 release_firmware(tp->rtl_fw->fw);
2437                 kfree(tp->rtl_fw);
2438         }
2439         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2440 }
2441
2442 static void rtl_apply_firmware(struct rtl8169_private *tp)
2443 {
2444         struct rtl_fw *rtl_fw = tp->rtl_fw;
2445
2446         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2447         if (!IS_ERR_OR_NULL(rtl_fw))
2448                 rtl_phy_write_fw(tp, rtl_fw);
2449 }
2450
2451 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2452 {
2453         if (rtl_readphy(tp, reg) != val)
2454                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2455         else
2456                 rtl_apply_firmware(tp);
2457 }
2458
2459 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2460 {
2461         static const struct phy_reg phy_reg_init[] = {
2462                 { 0x1f, 0x0001 },
2463                 { 0x06, 0x006e },
2464                 { 0x08, 0x0708 },
2465                 { 0x15, 0x4000 },
2466                 { 0x18, 0x65c7 },
2467
2468                 { 0x1f, 0x0001 },
2469                 { 0x03, 0x00a1 },
2470                 { 0x02, 0x0008 },
2471                 { 0x01, 0x0120 },
2472                 { 0x00, 0x1000 },
2473                 { 0x04, 0x0800 },
2474                 { 0x04, 0x0000 },
2475
2476                 { 0x03, 0xff41 },
2477                 { 0x02, 0xdf60 },
2478                 { 0x01, 0x0140 },
2479                 { 0x00, 0x0077 },
2480                 { 0x04, 0x7800 },
2481                 { 0x04, 0x7000 },
2482
2483                 { 0x03, 0x802f },
2484                 { 0x02, 0x4f02 },
2485                 { 0x01, 0x0409 },
2486                 { 0x00, 0xf0f9 },
2487                 { 0x04, 0x9800 },
2488                 { 0x04, 0x9000 },
2489
2490                 { 0x03, 0xdf01 },
2491                 { 0x02, 0xdf20 },
2492                 { 0x01, 0xff95 },
2493                 { 0x00, 0xba00 },
2494                 { 0x04, 0xa800 },
2495                 { 0x04, 0xa000 },
2496
2497                 { 0x03, 0xff41 },
2498                 { 0x02, 0xdf20 },
2499                 { 0x01, 0x0140 },
2500                 { 0x00, 0x00bb },
2501                 { 0x04, 0xb800 },
2502                 { 0x04, 0xb000 },
2503
2504                 { 0x03, 0xdf41 },
2505                 { 0x02, 0xdc60 },
2506                 { 0x01, 0x6340 },
2507                 { 0x00, 0x007d },
2508                 { 0x04, 0xd800 },
2509                 { 0x04, 0xd000 },
2510
2511                 { 0x03, 0xdf01 },
2512                 { 0x02, 0xdf20 },
2513                 { 0x01, 0x100a },
2514                 { 0x00, 0xa0ff },
2515                 { 0x04, 0xf800 },
2516                 { 0x04, 0xf000 },
2517
2518                 { 0x1f, 0x0000 },
2519                 { 0x0b, 0x0000 },
2520                 { 0x00, 0x9200 }
2521         };
2522
2523         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2524 }
2525
2526 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2527 {
2528         static const struct phy_reg phy_reg_init[] = {
2529                 { 0x1f, 0x0002 },
2530                 { 0x01, 0x90d0 },
2531                 { 0x1f, 0x0000 }
2532         };
2533
2534         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2535 }
2536
2537 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2538 {
2539         struct pci_dev *pdev = tp->pci_dev;
2540
2541         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2542             (pdev->subsystem_device != 0xe000))
2543                 return;
2544
2545         rtl_writephy(tp, 0x1f, 0x0001);
2546         rtl_writephy(tp, 0x10, 0xf01b);
2547         rtl_writephy(tp, 0x1f, 0x0000);
2548 }
2549
2550 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2551 {
2552         static const struct phy_reg phy_reg_init[] = {
2553                 { 0x1f, 0x0001 },
2554                 { 0x04, 0x0000 },
2555                 { 0x03, 0x00a1 },
2556                 { 0x02, 0x0008 },
2557                 { 0x01, 0x0120 },
2558                 { 0x00, 0x1000 },
2559                 { 0x04, 0x0800 },
2560                 { 0x04, 0x9000 },
2561                 { 0x03, 0x802f },
2562                 { 0x02, 0x4f02 },
2563                 { 0x01, 0x0409 },
2564                 { 0x00, 0xf099 },
2565                 { 0x04, 0x9800 },
2566                 { 0x04, 0xa000 },
2567                 { 0x03, 0xdf01 },
2568                 { 0x02, 0xdf20 },
2569                 { 0x01, 0xff95 },
2570                 { 0x00, 0xba00 },
2571                 { 0x04, 0xa800 },
2572                 { 0x04, 0xf000 },
2573                 { 0x03, 0xdf01 },
2574                 { 0x02, 0xdf20 },
2575                 { 0x01, 0x101a },
2576                 { 0x00, 0xa0ff },
2577                 { 0x04, 0xf800 },
2578                 { 0x04, 0x0000 },
2579                 { 0x1f, 0x0000 },
2580
2581                 { 0x1f, 0x0001 },
2582                 { 0x10, 0xf41b },
2583                 { 0x14, 0xfb54 },
2584                 { 0x18, 0xf5c7 },
2585                 { 0x1f, 0x0000 },
2586
2587                 { 0x1f, 0x0001 },
2588                 { 0x17, 0x0cc0 },
2589                 { 0x1f, 0x0000 }
2590         };
2591
2592         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593
2594         rtl8169scd_hw_phy_config_quirk(tp);
2595 }
2596
2597 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2598 {
2599         static const struct phy_reg phy_reg_init[] = {
2600                 { 0x1f, 0x0001 },
2601                 { 0x04, 0x0000 },
2602                 { 0x03, 0x00a1 },
2603                 { 0x02, 0x0008 },
2604                 { 0x01, 0x0120 },
2605                 { 0x00, 0x1000 },
2606                 { 0x04, 0x0800 },
2607                 { 0x04, 0x9000 },
2608                 { 0x03, 0x802f },
2609                 { 0x02, 0x4f02 },
2610                 { 0x01, 0x0409 },
2611                 { 0x00, 0xf099 },
2612                 { 0x04, 0x9800 },
2613                 { 0x04, 0xa000 },
2614                 { 0x03, 0xdf01 },
2615                 { 0x02, 0xdf20 },
2616                 { 0x01, 0xff95 },
2617                 { 0x00, 0xba00 },
2618                 { 0x04, 0xa800 },
2619                 { 0x04, 0xf000 },
2620                 { 0x03, 0xdf01 },
2621                 { 0x02, 0xdf20 },
2622                 { 0x01, 0x101a },
2623                 { 0x00, 0xa0ff },
2624                 { 0x04, 0xf800 },
2625                 { 0x04, 0x0000 },
2626                 { 0x1f, 0x0000 },
2627
2628                 { 0x1f, 0x0001 },
2629                 { 0x0b, 0x8480 },
2630                 { 0x1f, 0x0000 },
2631
2632                 { 0x1f, 0x0001 },
2633                 { 0x18, 0x67c7 },
2634                 { 0x04, 0x2000 },
2635                 { 0x03, 0x002f },
2636                 { 0x02, 0x4360 },
2637                 { 0x01, 0x0109 },
2638                 { 0x00, 0x3022 },
2639                 { 0x04, 0x2800 },
2640                 { 0x1f, 0x0000 },
2641
2642                 { 0x1f, 0x0001 },
2643                 { 0x17, 0x0cc0 },
2644                 { 0x1f, 0x0000 }
2645         };
2646
2647         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2648 }
2649
2650 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2651 {
2652         static const struct phy_reg phy_reg_init[] = {
2653                 { 0x10, 0xf41b },
2654                 { 0x1f, 0x0000 }
2655         };
2656
2657         rtl_writephy(tp, 0x1f, 0x0001);
2658         rtl_patchphy(tp, 0x16, 1 << 0);
2659
2660         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2661 }
2662
2663 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2664 {
2665         static const struct phy_reg phy_reg_init[] = {
2666                 { 0x1f, 0x0001 },
2667                 { 0x10, 0xf41b },
2668                 { 0x1f, 0x0000 }
2669         };
2670
2671         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2672 }
2673
2674 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2675 {
2676         static const struct phy_reg phy_reg_init[] = {
2677                 { 0x1f, 0x0000 },
2678                 { 0x1d, 0x0f00 },
2679                 { 0x1f, 0x0002 },
2680                 { 0x0c, 0x1ec8 },
2681                 { 0x1f, 0x0000 }
2682         };
2683
2684         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2685 }
2686
2687 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2688 {
2689         static const struct phy_reg phy_reg_init[] = {
2690                 { 0x1f, 0x0001 },
2691                 { 0x1d, 0x3d98 },
2692                 { 0x1f, 0x0000 }
2693         };
2694
2695         rtl_writephy(tp, 0x1f, 0x0000);
2696         rtl_patchphy(tp, 0x14, 1 << 5);
2697         rtl_patchphy(tp, 0x0d, 1 << 5);
2698
2699         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2700 }
2701
2702 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2703 {
2704         static const struct phy_reg phy_reg_init[] = {
2705                 { 0x1f, 0x0001 },
2706                 { 0x12, 0x2300 },
2707                 { 0x1f, 0x0002 },
2708                 { 0x00, 0x88d4 },
2709                 { 0x01, 0x82b1 },
2710                 { 0x03, 0x7002 },
2711                 { 0x08, 0x9e30 },
2712                 { 0x09, 0x01f0 },
2713                 { 0x0a, 0x5500 },
2714                 { 0x0c, 0x00c8 },
2715                 { 0x1f, 0x0003 },
2716                 { 0x12, 0xc096 },
2717                 { 0x16, 0x000a },
2718                 { 0x1f, 0x0000 },
2719                 { 0x1f, 0x0000 },
2720                 { 0x09, 0x2000 },
2721                 { 0x09, 0x0000 }
2722         };
2723
2724         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2725
2726         rtl_patchphy(tp, 0x14, 1 << 5);
2727         rtl_patchphy(tp, 0x0d, 1 << 5);
2728         rtl_writephy(tp, 0x1f, 0x0000);
2729 }
2730
2731 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2732 {
2733         static const struct phy_reg phy_reg_init[] = {
2734                 { 0x1f, 0x0001 },
2735                 { 0x12, 0x2300 },
2736                 { 0x03, 0x802f },
2737                 { 0x02, 0x4f02 },
2738                 { 0x01, 0x0409 },
2739                 { 0x00, 0xf099 },
2740                 { 0x04, 0x9800 },
2741                 { 0x04, 0x9000 },
2742                 { 0x1d, 0x3d98 },
2743                 { 0x1f, 0x0002 },
2744                 { 0x0c, 0x7eb8 },
2745                 { 0x06, 0x0761 },
2746                 { 0x1f, 0x0003 },
2747                 { 0x16, 0x0f0a },
2748                 { 0x1f, 0x0000 }
2749         };
2750
2751         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2752
2753         rtl_patchphy(tp, 0x16, 1 << 0);
2754         rtl_patchphy(tp, 0x14, 1 << 5);
2755         rtl_patchphy(tp, 0x0d, 1 << 5);
2756         rtl_writephy(tp, 0x1f, 0x0000);
2757 }
2758
2759 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2760 {
2761         static const struct phy_reg phy_reg_init[] = {
2762                 { 0x1f, 0x0001 },
2763                 { 0x12, 0x2300 },
2764                 { 0x1d, 0x3d98 },
2765                 { 0x1f, 0x0002 },
2766                 { 0x0c, 0x7eb8 },
2767                 { 0x06, 0x5461 },
2768                 { 0x1f, 0x0003 },
2769                 { 0x16, 0x0f0a },
2770                 { 0x1f, 0x0000 }
2771         };
2772
2773         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2774
2775         rtl_patchphy(tp, 0x16, 1 << 0);
2776         rtl_patchphy(tp, 0x14, 1 << 5);
2777         rtl_patchphy(tp, 0x0d, 1 << 5);
2778         rtl_writephy(tp, 0x1f, 0x0000);
2779 }
2780
2781 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2782 {
2783         rtl8168c_3_hw_phy_config(tp);
2784 }
2785
2786 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2787 {
2788         static const struct phy_reg phy_reg_init_0[] = {
2789                 /* Channel Estimation */
2790                 { 0x1f, 0x0001 },
2791                 { 0x06, 0x4064 },
2792                 { 0x07, 0x2863 },
2793                 { 0x08, 0x059c },
2794                 { 0x09, 0x26b4 },
2795                 { 0x0a, 0x6a19 },
2796                 { 0x0b, 0xdcc8 },
2797                 { 0x10, 0xf06d },
2798                 { 0x14, 0x7f68 },
2799                 { 0x18, 0x7fd9 },
2800                 { 0x1c, 0xf0ff },
2801                 { 0x1d, 0x3d9c },
2802                 { 0x1f, 0x0003 },
2803                 { 0x12, 0xf49f },
2804                 { 0x13, 0x070b },
2805                 { 0x1a, 0x05ad },
2806                 { 0x14, 0x94c0 },
2807
2808                 /*
2809                  * Tx Error Issue
2810                  * Enhance line driver power
2811                  */
2812                 { 0x1f, 0x0002 },
2813                 { 0x06, 0x5561 },
2814                 { 0x1f, 0x0005 },
2815                 { 0x05, 0x8332 },
2816                 { 0x06, 0x5561 },
2817
2818                 /*
2819                  * Can not link to 1Gbps with bad cable
2820                  * Decrease SNR threshold form 21.07dB to 19.04dB
2821                  */
2822                 { 0x1f, 0x0001 },
2823                 { 0x17, 0x0cc0 },
2824
2825                 { 0x1f, 0x0000 },
2826                 { 0x0d, 0xf880 }
2827         };
2828
2829         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2830
2831         /*
2832          * Rx Error Issue
2833          * Fine Tune Switching regulator parameter
2834          */
2835         rtl_writephy(tp, 0x1f, 0x0002);
2836         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2837         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2838
2839         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2840                 static const struct phy_reg phy_reg_init[] = {
2841                         { 0x1f, 0x0002 },
2842                         { 0x05, 0x669a },
2843                         { 0x1f, 0x0005 },
2844                         { 0x05, 0x8330 },
2845                         { 0x06, 0x669a },
2846                         { 0x1f, 0x0002 }
2847                 };
2848                 int val;
2849
2850                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851
2852                 val = rtl_readphy(tp, 0x0d);
2853
2854                 if ((val & 0x00ff) != 0x006c) {
2855                         static const u32 set[] = {
2856                                 0x0065, 0x0066, 0x0067, 0x0068,
2857                                 0x0069, 0x006a, 0x006b, 0x006c
2858                         };
2859                         int i;
2860
2861                         rtl_writephy(tp, 0x1f, 0x0002);
2862
2863                         val &= 0xff00;
2864                         for (i = 0; i < ARRAY_SIZE(set); i++)
2865                                 rtl_writephy(tp, 0x0d, val | set[i]);
2866                 }
2867         } else {
2868                 static const struct phy_reg phy_reg_init[] = {
2869                         { 0x1f, 0x0002 },
2870                         { 0x05, 0x6662 },
2871                         { 0x1f, 0x0005 },
2872                         { 0x05, 0x8330 },
2873                         { 0x06, 0x6662 }
2874                 };
2875
2876                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2877         }
2878
2879         /* RSET couple improve */
2880         rtl_writephy(tp, 0x1f, 0x0002);
2881         rtl_patchphy(tp, 0x0d, 0x0300);
2882         rtl_patchphy(tp, 0x0f, 0x0010);
2883
2884         /* Fine tune PLL performance */
2885         rtl_writephy(tp, 0x1f, 0x0002);
2886         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2887         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2888
2889         rtl_writephy(tp, 0x1f, 0x0005);
2890         rtl_writephy(tp, 0x05, 0x001b);
2891
2892         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2893
2894         rtl_writephy(tp, 0x1f, 0x0000);
2895 }
2896
2897 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2898 {
2899         static const struct phy_reg phy_reg_init_0[] = {
2900                 /* Channel Estimation */
2901                 { 0x1f, 0x0001 },
2902                 { 0x06, 0x4064 },
2903                 { 0x07, 0x2863 },
2904                 { 0x08, 0x059c },
2905                 { 0x09, 0x26b4 },
2906                 { 0x0a, 0x6a19 },
2907                 { 0x0b, 0xdcc8 },
2908                 { 0x10, 0xf06d },
2909                 { 0x14, 0x7f68 },
2910                 { 0x18, 0x7fd9 },
2911                 { 0x1c, 0xf0ff },
2912                 { 0x1d, 0x3d9c },
2913                 { 0x1f, 0x0003 },
2914                 { 0x12, 0xf49f },
2915                 { 0x13, 0x070b },
2916                 { 0x1a, 0x05ad },
2917                 { 0x14, 0x94c0 },
2918
2919                 /*
2920                  * Tx Error Issue
2921                  * Enhance line driver power
2922                  */
2923                 { 0x1f, 0x0002 },
2924                 { 0x06, 0x5561 },
2925                 { 0x1f, 0x0005 },
2926                 { 0x05, 0x8332 },
2927                 { 0x06, 0x5561 },
2928
2929                 /*
2930                  * Can not link to 1Gbps with bad cable
2931                  * Decrease SNR threshold form 21.07dB to 19.04dB
2932                  */
2933                 { 0x1f, 0x0001 },
2934                 { 0x17, 0x0cc0 },
2935
2936                 { 0x1f, 0x0000 },
2937                 { 0x0d, 0xf880 }
2938         };
2939
2940         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2941
2942         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2943                 static const struct phy_reg phy_reg_init[] = {
2944                         { 0x1f, 0x0002 },
2945                         { 0x05, 0x669a },
2946                         { 0x1f, 0x0005 },
2947                         { 0x05, 0x8330 },
2948                         { 0x06, 0x669a },
2949
2950                         { 0x1f, 0x0002 }
2951                 };
2952                 int val;
2953
2954                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2955
2956                 val = rtl_readphy(tp, 0x0d);
2957                 if ((val & 0x00ff) != 0x006c) {
2958                         static const u32 set[] = {
2959                                 0x0065, 0x0066, 0x0067, 0x0068,
2960                                 0x0069, 0x006a, 0x006b, 0x006c
2961                         };
2962                         int i;
2963
2964                         rtl_writephy(tp, 0x1f, 0x0002);
2965
2966                         val &= 0xff00;
2967                         for (i = 0; i < ARRAY_SIZE(set); i++)
2968                                 rtl_writephy(tp, 0x0d, val | set[i]);
2969                 }
2970         } else {
2971                 static const struct phy_reg phy_reg_init[] = {
2972                         { 0x1f, 0x0002 },
2973                         { 0x05, 0x2642 },
2974                         { 0x1f, 0x0005 },
2975                         { 0x05, 0x8330 },
2976                         { 0x06, 0x2642 }
2977                 };
2978
2979                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2980         }
2981
2982         /* Fine tune PLL performance */
2983         rtl_writephy(tp, 0x1f, 0x0002);
2984         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2985         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2986
2987         /* Switching regulator Slew rate */
2988         rtl_writephy(tp, 0x1f, 0x0002);
2989         rtl_patchphy(tp, 0x0f, 0x0017);
2990
2991         rtl_writephy(tp, 0x1f, 0x0005);
2992         rtl_writephy(tp, 0x05, 0x001b);
2993
2994         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2995
2996         rtl_writephy(tp, 0x1f, 0x0000);
2997 }
2998
2999 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3000 {
3001         static const struct phy_reg phy_reg_init[] = {
3002                 { 0x1f, 0x0002 },
3003                 { 0x10, 0x0008 },
3004                 { 0x0d, 0x006c },
3005
3006                 { 0x1f, 0x0000 },
3007                 { 0x0d, 0xf880 },
3008
3009                 { 0x1f, 0x0001 },
3010                 { 0x17, 0x0cc0 },
3011
3012                 { 0x1f, 0x0001 },
3013                 { 0x0b, 0xa4d8 },
3014                 { 0x09, 0x281c },
3015                 { 0x07, 0x2883 },
3016                 { 0x0a, 0x6b35 },
3017                 { 0x1d, 0x3da4 },
3018                 { 0x1c, 0xeffd },
3019                 { 0x14, 0x7f52 },
3020                 { 0x18, 0x7fc6 },
3021                 { 0x08, 0x0601 },
3022                 { 0x06, 0x4063 },
3023                 { 0x10, 0xf074 },
3024                 { 0x1f, 0x0003 },
3025                 { 0x13, 0x0789 },
3026                 { 0x12, 0xf4bd },
3027                 { 0x1a, 0x04fd },
3028                 { 0x14, 0x84b0 },
3029                 { 0x1f, 0x0000 },
3030                 { 0x00, 0x9200 },
3031
3032                 { 0x1f, 0x0005 },
3033                 { 0x01, 0x0340 },
3034                 { 0x1f, 0x0001 },
3035                 { 0x04, 0x4000 },
3036                 { 0x03, 0x1d21 },
3037                 { 0x02, 0x0c32 },
3038                 { 0x01, 0x0200 },
3039                 { 0x00, 0x5554 },
3040                 { 0x04, 0x4800 },
3041                 { 0x04, 0x4000 },
3042                 { 0x04, 0xf000 },
3043                 { 0x03, 0xdf01 },
3044                 { 0x02, 0xdf20 },
3045                 { 0x01, 0x101a },
3046                 { 0x00, 0xa0ff },
3047                 { 0x04, 0xf800 },
3048                 { 0x04, 0xf000 },
3049                 { 0x1f, 0x0000 },
3050
3051                 { 0x1f, 0x0007 },
3052                 { 0x1e, 0x0023 },
3053                 { 0x16, 0x0000 },
3054                 { 0x1f, 0x0000 }
3055         };
3056
3057         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3058 }
3059
3060 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3061 {
3062         static const struct phy_reg phy_reg_init[] = {
3063                 { 0x1f, 0x0001 },
3064                 { 0x17, 0x0cc0 },
3065
3066                 { 0x1f, 0x0007 },
3067                 { 0x1e, 0x002d },
3068                 { 0x18, 0x0040 },
3069                 { 0x1f, 0x0000 }
3070         };
3071
3072         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3073         rtl_patchphy(tp, 0x0d, 1 << 5);
3074 }
3075
3076 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3077 {
3078         static const struct phy_reg phy_reg_init[] = {
3079                 /* Enable Delay cap */
3080                 { 0x1f, 0x0005 },
3081                 { 0x05, 0x8b80 },
3082                 { 0x06, 0xc896 },
3083                 { 0x1f, 0x0000 },
3084
3085                 /* Channel estimation fine tune */
3086                 { 0x1f, 0x0001 },
3087                 { 0x0b, 0x6c20 },
3088                 { 0x07, 0x2872 },
3089                 { 0x1c, 0xefff },
3090                 { 0x1f, 0x0003 },
3091                 { 0x14, 0x6420 },
3092                 { 0x1f, 0x0000 },
3093
3094                 /* Update PFM & 10M TX idle timer */
3095                 { 0x1f, 0x0007 },
3096                 { 0x1e, 0x002f },
3097                 { 0x15, 0x1919 },
3098                 { 0x1f, 0x0000 },
3099
3100                 { 0x1f, 0x0007 },
3101                 { 0x1e, 0x00ac },
3102                 { 0x18, 0x0006 },
3103                 { 0x1f, 0x0000 }
3104         };
3105
3106         rtl_apply_firmware(tp);
3107
3108         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109
3110         /* DCO enable for 10M IDLE Power */
3111         rtl_writephy(tp, 0x1f, 0x0007);
3112         rtl_writephy(tp, 0x1e, 0x0023);
3113         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3114         rtl_writephy(tp, 0x1f, 0x0000);
3115
3116         /* For impedance matching */
3117         rtl_writephy(tp, 0x1f, 0x0002);
3118         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3119         rtl_writephy(tp, 0x1f, 0x0000);
3120
3121         /* PHY auto speed down */
3122         rtl_writephy(tp, 0x1f, 0x0007);
3123         rtl_writephy(tp, 0x1e, 0x002d);
3124         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3125         rtl_writephy(tp, 0x1f, 0x0000);
3126         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3127
3128         rtl_writephy(tp, 0x1f, 0x0005);
3129         rtl_writephy(tp, 0x05, 0x8b86);
3130         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3131         rtl_writephy(tp, 0x1f, 0x0000);
3132
3133         rtl_writephy(tp, 0x1f, 0x0005);
3134         rtl_writephy(tp, 0x05, 0x8b85);
3135         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3136         rtl_writephy(tp, 0x1f, 0x0007);
3137         rtl_writephy(tp, 0x1e, 0x0020);
3138         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3139         rtl_writephy(tp, 0x1f, 0x0006);
3140         rtl_writephy(tp, 0x00, 0x5a00);
3141         rtl_writephy(tp, 0x1f, 0x0000);
3142         rtl_writephy(tp, 0x0d, 0x0007);
3143         rtl_writephy(tp, 0x0e, 0x003c);
3144         rtl_writephy(tp, 0x0d, 0x4007);
3145         rtl_writephy(tp, 0x0e, 0x0000);
3146         rtl_writephy(tp, 0x0d, 0x0000);
3147 }
3148
3149 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3150 {
3151         const u16 w[] = {
3152                 addr[0] | (addr[1] << 8),
3153                 addr[2] | (addr[3] << 8),
3154                 addr[4] | (addr[5] << 8)
3155         };
3156         const struct exgmac_reg e[] = {
3157                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3158                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3159                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3160                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3161         };
3162
3163         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3164 }
3165
3166 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3167 {
3168         static const struct phy_reg phy_reg_init[] = {
3169                 /* Enable Delay cap */
3170                 { 0x1f, 0x0004 },
3171                 { 0x1f, 0x0007 },
3172                 { 0x1e, 0x00ac },
3173                 { 0x18, 0x0006 },
3174                 { 0x1f, 0x0002 },
3175                 { 0x1f, 0x0000 },
3176                 { 0x1f, 0x0000 },
3177
3178                 /* Channel estimation fine tune */
3179                 { 0x1f, 0x0003 },
3180                 { 0x09, 0xa20f },
3181                 { 0x1f, 0x0000 },
3182                 { 0x1f, 0x0000 },
3183
3184                 /* Green Setting */
3185                 { 0x1f, 0x0005 },
3186                 { 0x05, 0x8b5b },
3187                 { 0x06, 0x9222 },
3188                 { 0x05, 0x8b6d },
3189                 { 0x06, 0x8000 },
3190                 { 0x05, 0x8b76 },
3191                 { 0x06, 0x8000 },
3192                 { 0x1f, 0x0000 }
3193         };
3194
3195         rtl_apply_firmware(tp);
3196
3197         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3198
3199         /* For 4-corner performance improve */
3200         rtl_writephy(tp, 0x1f, 0x0005);
3201         rtl_writephy(tp, 0x05, 0x8b80);
3202         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3203         rtl_writephy(tp, 0x1f, 0x0000);
3204
3205         /* PHY auto speed down */
3206         rtl_writephy(tp, 0x1f, 0x0004);
3207         rtl_writephy(tp, 0x1f, 0x0007);
3208         rtl_writephy(tp, 0x1e, 0x002d);
3209         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3210         rtl_writephy(tp, 0x1f, 0x0002);
3211         rtl_writephy(tp, 0x1f, 0x0000);
3212         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3213
3214         /* improve 10M EEE waveform */
3215         rtl_writephy(tp, 0x1f, 0x0005);
3216         rtl_writephy(tp, 0x05, 0x8b86);
3217         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3218         rtl_writephy(tp, 0x1f, 0x0000);
3219
3220         /* Improve 2-pair detection performance */
3221         rtl_writephy(tp, 0x1f, 0x0005);
3222         rtl_writephy(tp, 0x05, 0x8b85);
3223         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3224         rtl_writephy(tp, 0x1f, 0x0000);
3225
3226         /* EEE setting */
3227         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3228         rtl_writephy(tp, 0x1f, 0x0005);
3229         rtl_writephy(tp, 0x05, 0x8b85);
3230         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3231         rtl_writephy(tp, 0x1f, 0x0004);
3232         rtl_writephy(tp, 0x1f, 0x0007);
3233         rtl_writephy(tp, 0x1e, 0x0020);
3234         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3235         rtl_writephy(tp, 0x1f, 0x0002);
3236         rtl_writephy(tp, 0x1f, 0x0000);
3237         rtl_writephy(tp, 0x0d, 0x0007);
3238         rtl_writephy(tp, 0x0e, 0x003c);
3239         rtl_writephy(tp, 0x0d, 0x4007);
3240         rtl_writephy(tp, 0x0e, 0x0006);
3241         rtl_writephy(tp, 0x0d, 0x0000);
3242
3243         /* Green feature */
3244         rtl_writephy(tp, 0x1f, 0x0003);
3245         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3246         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3247         rtl_writephy(tp, 0x1f, 0x0000);
3248         rtl_writephy(tp, 0x1f, 0x0005);
3249         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);