r8169: Enable MSI-X on RTL8106e
[muen/linux.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/crc32.h>
22 #include <linux/in.h>
23 #include <linux/io.h>
24 #include <linux/ip.h>
25 #include <linux/tcp.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
33
34 #define MODULENAME "r8169"
35
36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
55
56 #define R8169_MSG_DEFAULT \
57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
58
59 #define TX_SLOTS_AVAIL(tp) \
60         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
61
62 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
63 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
64         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
65
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit = 32;
69
70 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE         256
74 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
77 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
78 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
79
80 #define RTL8169_TX_TIMEOUT      (6*HZ)
81
82 /* write/read MMIO register */
83 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
84 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
85 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
86 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
87 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
88 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
89
90 enum mac_version {
91         RTL_GIGA_MAC_VER_01 = 0,
92         RTL_GIGA_MAC_VER_02,
93         RTL_GIGA_MAC_VER_03,
94         RTL_GIGA_MAC_VER_04,
95         RTL_GIGA_MAC_VER_05,
96         RTL_GIGA_MAC_VER_06,
97         RTL_GIGA_MAC_VER_07,
98         RTL_GIGA_MAC_VER_08,
99         RTL_GIGA_MAC_VER_09,
100         RTL_GIGA_MAC_VER_10,
101         RTL_GIGA_MAC_VER_11,
102         RTL_GIGA_MAC_VER_12,
103         RTL_GIGA_MAC_VER_13,
104         RTL_GIGA_MAC_VER_14,
105         RTL_GIGA_MAC_VER_15,
106         RTL_GIGA_MAC_VER_16,
107         RTL_GIGA_MAC_VER_17,
108         RTL_GIGA_MAC_VER_18,
109         RTL_GIGA_MAC_VER_19,
110         RTL_GIGA_MAC_VER_20,
111         RTL_GIGA_MAC_VER_21,
112         RTL_GIGA_MAC_VER_22,
113         RTL_GIGA_MAC_VER_23,
114         RTL_GIGA_MAC_VER_24,
115         RTL_GIGA_MAC_VER_25,
116         RTL_GIGA_MAC_VER_26,
117         RTL_GIGA_MAC_VER_27,
118         RTL_GIGA_MAC_VER_28,
119         RTL_GIGA_MAC_VER_29,
120         RTL_GIGA_MAC_VER_30,
121         RTL_GIGA_MAC_VER_31,
122         RTL_GIGA_MAC_VER_32,
123         RTL_GIGA_MAC_VER_33,
124         RTL_GIGA_MAC_VER_34,
125         RTL_GIGA_MAC_VER_35,
126         RTL_GIGA_MAC_VER_36,
127         RTL_GIGA_MAC_VER_37,
128         RTL_GIGA_MAC_VER_38,
129         RTL_GIGA_MAC_VER_39,
130         RTL_GIGA_MAC_VER_40,
131         RTL_GIGA_MAC_VER_41,
132         RTL_GIGA_MAC_VER_42,
133         RTL_GIGA_MAC_VER_43,
134         RTL_GIGA_MAC_VER_44,
135         RTL_GIGA_MAC_VER_45,
136         RTL_GIGA_MAC_VER_46,
137         RTL_GIGA_MAC_VER_47,
138         RTL_GIGA_MAC_VER_48,
139         RTL_GIGA_MAC_VER_49,
140         RTL_GIGA_MAC_VER_50,
141         RTL_GIGA_MAC_VER_51,
142         RTL_GIGA_MAC_NONE   = 0xff,
143 };
144
145 #define JUMBO_1K        ETH_DATA_LEN
146 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
147 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
148 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
149 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
150
151 static const struct {
152         const char *name;
153         const char *fw_name;
154 } rtl_chip_infos[] = {
155         /* PCI devices. */
156         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
157         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
158         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
159         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
160         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
161         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
162         /* PCI-E devices. */
163         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
164         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
165         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
166         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
167         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
168         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
169         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
170         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
171         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
172         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
173         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
174         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
175         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
176         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
177         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
178         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
179         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
180         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
181         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
182         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
183         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
184         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
185         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
186         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
187         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
188         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
189         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
190         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
191         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
192         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
193         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
194         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
195         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
196         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
197         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
198         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
199         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
200         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
201         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
202         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
203         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
204         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
205         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
206         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
207         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
208 };
209
210 enum cfg_version {
211         RTL_CFG_0 = 0x00,
212         RTL_CFG_1,
213         RTL_CFG_2
214 };
215
216 static const struct pci_device_id rtl8169_pci_tbl[] = {
217         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
218         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
219         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
220         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
221         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
222         { PCI_DEVICE(PCI_VENDOR_ID_NCUBE,       0x8168), 0, 0, RTL_CFG_1 },
223         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
224         { PCI_VENDOR_ID_DLINK,                  0x4300,
225                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
226         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
227         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
228         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
229         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
230         { PCI_VENDOR_ID_LINKSYS,                0x1032,
231                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
232         { 0x0001,                               0x8168,
233                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
234         {0,},
235 };
236
237 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
238
239 static int use_dac = -1;
240 static struct {
241         u32 msg_enable;
242 } debug = { -1 };
243
244 enum rtl_registers {
245         MAC0            = 0,    /* Ethernet hardware address. */
246         MAC4            = 4,
247         MAR0            = 8,    /* Multicast filter. */
248         CounterAddrLow          = 0x10,
249         CounterAddrHigh         = 0x14,
250         TxDescStartAddrLow      = 0x20,
251         TxDescStartAddrHigh     = 0x24,
252         TxHDescStartAddrLow     = 0x28,
253         TxHDescStartAddrHigh    = 0x2c,
254         FLASH           = 0x30,
255         ERSR            = 0x36,
256         ChipCmd         = 0x37,
257         TxPoll          = 0x38,
258         IntrMask        = 0x3c,
259         IntrStatus      = 0x3e,
260
261         TxConfig        = 0x40,
262 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
263 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
264
265         RxConfig        = 0x44,
266 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
267 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
268 #define RXCFG_FIFO_SHIFT                13
269                                         /* No threshold before first PCI xfer */
270 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
271 #define RX_EARLY_OFF                    (1 << 11)
272 #define RXCFG_DMA_SHIFT                 8
273                                         /* Unlimited maximum PCI burst. */
274 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
275
276         RxMissed        = 0x4c,
277         Cfg9346         = 0x50,
278         Config0         = 0x51,
279         Config1         = 0x52,
280         Config2         = 0x53,
281 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
282
283         Config3         = 0x54,
284         Config4         = 0x55,
285         Config5         = 0x56,
286         MultiIntr       = 0x5c,
287         PHYAR           = 0x60,
288         PHYstatus       = 0x6c,
289         RxMaxSize       = 0xda,
290         CPlusCmd        = 0xe0,
291         IntrMitigate    = 0xe2,
292
293 #define RTL_COALESCE_MASK       0x0f
294 #define RTL_COALESCE_SHIFT      4
295 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
296 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
297
298         RxDescAddrLow   = 0xe4,
299         RxDescAddrHigh  = 0xe8,
300         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
301
302 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
303
304         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
305
306 #define TxPacketMax     (8064 >> 7)
307 #define EarlySize       0x27
308
309         FuncEvent       = 0xf0,
310         FuncEventMask   = 0xf4,
311         FuncPresetState = 0xf8,
312         IBCR0           = 0xf8,
313         IBCR2           = 0xf9,
314         IBIMR0          = 0xfa,
315         IBISR0          = 0xfb,
316         FuncForceEvent  = 0xfc,
317 };
318
319 enum rtl8168_8101_registers {
320         CSIDR                   = 0x64,
321         CSIAR                   = 0x68,
322 #define CSIAR_FLAG                      0x80000000
323 #define CSIAR_WRITE_CMD                 0x80000000
324 #define CSIAR_BYTE_ENABLE               0x0000f000
325 #define CSIAR_ADDR_MASK                 0x00000fff
326         PMCH                    = 0x6f,
327         EPHYAR                  = 0x80,
328 #define EPHYAR_FLAG                     0x80000000
329 #define EPHYAR_WRITE_CMD                0x80000000
330 #define EPHYAR_REG_MASK                 0x1f
331 #define EPHYAR_REG_SHIFT                16
332 #define EPHYAR_DATA_MASK                0xffff
333         DLLPR                   = 0xd0,
334 #define PFM_EN                          (1 << 6)
335 #define TX_10M_PS_EN                    (1 << 7)
336         DBG_REG                 = 0xd1,
337 #define FIX_NAK_1                       (1 << 4)
338 #define FIX_NAK_2                       (1 << 3)
339         TWSI                    = 0xd2,
340         MCU                     = 0xd3,
341 #define NOW_IS_OOB                      (1 << 7)
342 #define TX_EMPTY                        (1 << 5)
343 #define RX_EMPTY                        (1 << 4)
344 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
345 #define EN_NDP                          (1 << 3)
346 #define EN_OOB_RESET                    (1 << 2)
347 #define LINK_LIST_RDY                   (1 << 1)
348         EFUSEAR                 = 0xdc,
349 #define EFUSEAR_FLAG                    0x80000000
350 #define EFUSEAR_WRITE_CMD               0x80000000
351 #define EFUSEAR_READ_CMD                0x00000000
352 #define EFUSEAR_REG_MASK                0x03ff
353 #define EFUSEAR_REG_SHIFT               8
354 #define EFUSEAR_DATA_MASK               0xff
355         MISC_1                  = 0xf2,
356 #define PFM_D3COLD_EN                   (1 << 6)
357 };
358
359 enum rtl8168_registers {
360         LED_FREQ                = 0x1a,
361         EEE_LED                 = 0x1b,
362         ERIDR                   = 0x70,
363         ERIAR                   = 0x74,
364 #define ERIAR_FLAG                      0x80000000
365 #define ERIAR_WRITE_CMD                 0x80000000
366 #define ERIAR_READ_CMD                  0x00000000
367 #define ERIAR_ADDR_BYTE_ALIGN           4
368 #define ERIAR_TYPE_SHIFT                16
369 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
370 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
371 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_MASK_SHIFT                12
374 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
375 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
377 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
378 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
379         EPHY_RXER_NUM           = 0x7c,
380         OCPDR                   = 0xb0, /* OCP GPHY access */
381 #define OCPDR_WRITE_CMD                 0x80000000
382 #define OCPDR_READ_CMD                  0x00000000
383 #define OCPDR_REG_MASK                  0x7f
384 #define OCPDR_GPHY_REG_SHIFT            16
385 #define OCPDR_DATA_MASK                 0xffff
386         OCPAR                   = 0xb4,
387 #define OCPAR_FLAG                      0x80000000
388 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
389 #define OCPAR_GPHY_READ_CMD             0x0000f060
390         GPHY_OCP                = 0xb8,
391         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
392         MISC                    = 0xf0, /* 8168e only. */
393 #define TXPLA_RST                       (1 << 29)
394 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
395 #define PWM_EN                          (1 << 22)
396 #define RXDV_GATED_EN                   (1 << 19)
397 #define EARLY_TALLY_EN                  (1 << 16)
398 };
399
400 enum rtl_register_content {
401         /* InterruptStatusBits */
402         SYSErr          = 0x8000,
403         PCSTimeout      = 0x4000,
404         SWInt           = 0x0100,
405         TxDescUnavail   = 0x0080,
406         RxFIFOOver      = 0x0040,
407         LinkChg         = 0x0020,
408         RxOverflow      = 0x0010,
409         TxErr           = 0x0008,
410         TxOK            = 0x0004,
411         RxErr           = 0x0002,
412         RxOK            = 0x0001,
413
414         /* RxStatusDesc */
415         RxBOVF  = (1 << 24),
416         RxFOVF  = (1 << 23),
417         RxRWT   = (1 << 22),
418         RxRES   = (1 << 21),
419         RxRUNT  = (1 << 20),
420         RxCRC   = (1 << 19),
421
422         /* ChipCmdBits */
423         StopReq         = 0x80,
424         CmdReset        = 0x10,
425         CmdRxEnb        = 0x08,
426         CmdTxEnb        = 0x04,
427         RxBufEmpty      = 0x01,
428
429         /* TXPoll register p.5 */
430         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
431         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
432         FSWInt          = 0x01,         /* Forced software interrupt */
433
434         /* Cfg9346Bits */
435         Cfg9346_Lock    = 0x00,
436         Cfg9346_Unlock  = 0xc0,
437
438         /* rx_mode_bits */
439         AcceptErr       = 0x20,
440         AcceptRunt      = 0x10,
441         AcceptBroadcast = 0x08,
442         AcceptMulticast = 0x04,
443         AcceptMyPhys    = 0x02,
444         AcceptAllPhys   = 0x01,
445 #define RX_CONFIG_ACCEPT_MASK           0x3f
446
447         /* TxConfigBits */
448         TxInterFrameGapShift = 24,
449         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
450
451         /* Config1 register p.24 */
452         LEDS1           = (1 << 7),
453         LEDS0           = (1 << 6),
454         Speed_down      = (1 << 4),
455         MEMMAP          = (1 << 3),
456         IOMAP           = (1 << 2),
457         VPD             = (1 << 1),
458         PMEnable        = (1 << 0),     /* Power Management Enable */
459
460         /* Config2 register p. 25 */
461         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
462         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
463         PCI_Clock_66MHz = 0x01,
464         PCI_Clock_33MHz = 0x00,
465
466         /* Config3 register p.25 */
467         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
468         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
469         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
470         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
471         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
472
473         /* Config4 register */
474         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
475
476         /* Config5 register p.27 */
477         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
478         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
479         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
480         Spi_en          = (1 << 3),
481         LanWake         = (1 << 1),     /* LanWake enable/disable */
482         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
483         ASPM_en         = (1 << 0),     /* ASPM enable */
484
485         /* CPlusCmd p.31 */
486         EnableBist      = (1 << 15),    // 8168 8101
487         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
488         Normal_mode     = (1 << 13),    // unused
489         Force_half_dup  = (1 << 12),    // 8168 8101
490         Force_rxflow_en = (1 << 11),    // 8168 8101
491         Force_txflow_en = (1 << 10),    // 8168 8101
492         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
493         ASF             = (1 << 8),     // 8168 8101
494         PktCntrDisable  = (1 << 7),     // 8168 8101
495         Mac_dbgo_sel    = 0x001c,       // 8168
496         RxVlan          = (1 << 6),
497         RxChkSum        = (1 << 5),
498         PCIDAC          = (1 << 4),
499         PCIMulRW        = (1 << 3),
500 #define INTT_MASK       GENMASK(1, 0)
501         INTT_0          = 0x0000,       // 8168
502         INTT_1          = 0x0001,       // 8168
503         INTT_2          = 0x0002,       // 8168
504         INTT_3          = 0x0003,       // 8168
505
506         /* rtl8169_PHYstatus */
507         TBI_Enable      = 0x80,
508         TxFlowCtrl      = 0x40,
509         RxFlowCtrl      = 0x20,
510         _1000bpsF       = 0x10,
511         _100bps         = 0x08,
512         _10bps          = 0x04,
513         LinkStatus      = 0x02,
514         FullDup         = 0x01,
515
516         /* _TBICSRBit */
517         TBILinkOK       = 0x02000000,
518
519         /* ResetCounterCommand */
520         CounterReset    = 0x1,
521
522         /* DumpCounterCommand */
523         CounterDump     = 0x8,
524
525         /* magic enable v2 */
526         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
527 };
528
529 enum rtl_desc_bit {
530         /* First doubleword. */
531         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
532         RingEnd         = (1 << 30), /* End of descriptor ring */
533         FirstFrag       = (1 << 29), /* First segment of a packet */
534         LastFrag        = (1 << 28), /* Final segment of a packet */
535 };
536
537 /* Generic case. */
538 enum rtl_tx_desc_bit {
539         /* First doubleword. */
540         TD_LSO          = (1 << 27),            /* Large Send Offload */
541 #define TD_MSS_MAX                      0x07ffu /* MSS value */
542
543         /* Second doubleword. */
544         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
545 };
546
547 /* 8169, 8168b and 810x except 8102e. */
548 enum rtl_tx_desc_bit_0 {
549         /* First doubleword. */
550 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
551         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
552         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
553         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
554 };
555
556 /* 8102e, 8168c and beyond. */
557 enum rtl_tx_desc_bit_1 {
558         /* First doubleword. */
559         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
560         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
561 #define GTTCPHO_SHIFT                   18
562 #define GTTCPHO_MAX                     0x7fU
563
564         /* Second doubleword. */
565 #define TCPHO_SHIFT                     18
566 #define TCPHO_MAX                       0x3ffU
567 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
568         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
569         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
570         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
571         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
572 };
573
574 enum rtl_rx_desc_bit {
575         /* Rx private */
576         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
577         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
578
579 #define RxProtoUDP      (PID1)
580 #define RxProtoTCP      (PID0)
581 #define RxProtoIP       (PID1 | PID0)
582 #define RxProtoMask     RxProtoIP
583
584         IPFail          = (1 << 16), /* IP checksum failed */
585         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
586         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
587         RxVlanTag       = (1 << 16), /* VLAN tag available */
588 };
589
590 #define RsvdMask        0x3fffc000
591 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
592
593 struct TxDesc {
594         __le32 opts1;
595         __le32 opts2;
596         __le64 addr;
597 };
598
599 struct RxDesc {
600         __le32 opts1;
601         __le32 opts2;
602         __le64 addr;
603 };
604
605 struct ring_info {
606         struct sk_buff  *skb;
607         u32             len;
608         u8              __pad[sizeof(void *) - sizeof(u32)];
609 };
610
611 struct rtl8169_counters {
612         __le64  tx_packets;
613         __le64  rx_packets;
614         __le64  tx_errors;
615         __le32  rx_errors;
616         __le16  rx_missed;
617         __le16  align_errors;
618         __le32  tx_one_collision;
619         __le32  tx_multi_collision;
620         __le64  rx_unicast;
621         __le64  rx_broadcast;
622         __le32  rx_multicast;
623         __le16  tx_aborted;
624         __le16  tx_underun;
625 };
626
627 struct rtl8169_tc_offsets {
628         bool    inited;
629         __le64  tx_errors;
630         __le32  tx_multi_collision;
631         __le16  tx_aborted;
632 };
633
634 enum rtl_flag {
635         RTL_FLAG_TASK_ENABLED = 0,
636         RTL_FLAG_TASK_SLOW_PENDING,
637         RTL_FLAG_TASK_RESET_PENDING,
638         RTL_FLAG_MAX
639 };
640
641 struct rtl8169_stats {
642         u64                     packets;
643         u64                     bytes;
644         struct u64_stats_sync   syncp;
645 };
646
647 struct rtl8169_private {
648         void __iomem *mmio_addr;        /* memory map physical address */
649         struct pci_dev *pci_dev;
650         struct net_device *dev;
651         struct napi_struct napi;
652         u32 msg_enable;
653         u16 mac_version;
654         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
655         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
656         u32 dirty_tx;
657         struct rtl8169_stats rx_stats;
658         struct rtl8169_stats tx_stats;
659         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
660         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
661         dma_addr_t TxPhyAddr;
662         dma_addr_t RxPhyAddr;
663         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
664         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
665         u16 cp_cmd;
666
667         u16 event_slow;
668         const struct rtl_coalesce_info *coalesce_info;
669         struct clk *clk;
670
671         struct mdio_ops {
672                 void (*write)(struct rtl8169_private *, int, int);
673                 int (*read)(struct rtl8169_private *, int);
674         } mdio_ops;
675
676         struct jumbo_ops {
677                 void (*enable)(struct rtl8169_private *);
678                 void (*disable)(struct rtl8169_private *);
679         } jumbo_ops;
680
681         void (*hw_start)(struct rtl8169_private *tp);
682         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
683
684         struct {
685                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
686                 struct mutex mutex;
687                 struct work_struct work;
688         } wk;
689
690         unsigned supports_gmii:1;
691         struct mii_bus *mii_bus;
692         dma_addr_t counters_phys_addr;
693         struct rtl8169_counters *counters;
694         struct rtl8169_tc_offsets tc_offset;
695         u32 saved_wolopts;
696
697         struct rtl_fw {
698                 const struct firmware *fw;
699
700 #define RTL_VER_SIZE            32
701
702                 char version[RTL_VER_SIZE];
703
704                 struct rtl_fw_phy_action {
705                         __le32 *code;
706                         size_t size;
707                 } phy_action;
708         } *rtl_fw;
709 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
710
711         u32 ocp_base;
712 };
713
714 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
715 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
716 module_param(use_dac, int, 0);
717 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
718 module_param_named(debug, debug.msg_enable, int, 0);
719 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
720 MODULE_LICENSE("GPL");
721 MODULE_FIRMWARE(FIRMWARE_8168D_1);
722 MODULE_FIRMWARE(FIRMWARE_8168D_2);
723 MODULE_FIRMWARE(FIRMWARE_8168E_1);
724 MODULE_FIRMWARE(FIRMWARE_8168E_2);
725 MODULE_FIRMWARE(FIRMWARE_8168E_3);
726 MODULE_FIRMWARE(FIRMWARE_8105E_1);
727 MODULE_FIRMWARE(FIRMWARE_8168F_1);
728 MODULE_FIRMWARE(FIRMWARE_8168F_2);
729 MODULE_FIRMWARE(FIRMWARE_8402_1);
730 MODULE_FIRMWARE(FIRMWARE_8411_1);
731 MODULE_FIRMWARE(FIRMWARE_8411_2);
732 MODULE_FIRMWARE(FIRMWARE_8106E_1);
733 MODULE_FIRMWARE(FIRMWARE_8106E_2);
734 MODULE_FIRMWARE(FIRMWARE_8168G_2);
735 MODULE_FIRMWARE(FIRMWARE_8168G_3);
736 MODULE_FIRMWARE(FIRMWARE_8168H_1);
737 MODULE_FIRMWARE(FIRMWARE_8168H_2);
738 MODULE_FIRMWARE(FIRMWARE_8107E_1);
739 MODULE_FIRMWARE(FIRMWARE_8107E_2);
740
741 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
742 {
743         return &tp->pci_dev->dev;
744 }
745
746 static void rtl_lock_work(struct rtl8169_private *tp)
747 {
748         mutex_lock(&tp->wk.mutex);
749 }
750
751 static void rtl_unlock_work(struct rtl8169_private *tp)
752 {
753         mutex_unlock(&tp->wk.mutex);
754 }
755
756 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
757 {
758         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
759                                            PCI_EXP_DEVCTL_READRQ, force);
760 }
761
762 struct rtl_cond {
763         bool (*check)(struct rtl8169_private *);
764         const char *msg;
765 };
766
767 static void rtl_udelay(unsigned int d)
768 {
769         udelay(d);
770 }
771
772 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
773                           void (*delay)(unsigned int), unsigned int d, int n,
774                           bool high)
775 {
776         int i;
777
778         for (i = 0; i < n; i++) {
779                 delay(d);
780                 if (c->check(tp) == high)
781                         return true;
782         }
783         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
784                   c->msg, !high, n, d);
785         return false;
786 }
787
788 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
789                                       const struct rtl_cond *c,
790                                       unsigned int d, int n)
791 {
792         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
793 }
794
795 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
796                                      const struct rtl_cond *c,
797                                      unsigned int d, int n)
798 {
799         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
800 }
801
802 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
803                                       const struct rtl_cond *c,
804                                       unsigned int d, int n)
805 {
806         return rtl_loop_wait(tp, c, msleep, d, n, true);
807 }
808
809 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
810                                      const struct rtl_cond *c,
811                                      unsigned int d, int n)
812 {
813         return rtl_loop_wait(tp, c, msleep, d, n, false);
814 }
815
816 #define DECLARE_RTL_COND(name)                          \
817 static bool name ## _check(struct rtl8169_private *);   \
818                                                         \
819 static const struct rtl_cond name = {                   \
820         .check  = name ## _check,                       \
821         .msg    = #name                                 \
822 };                                                      \
823                                                         \
824 static bool name ## _check(struct rtl8169_private *tp)
825
826 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
827 {
828         if (reg & 0xffff0001) {
829                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
830                 return true;
831         }
832         return false;
833 }
834
835 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
836 {
837         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
838 }
839
840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
841 {
842         if (rtl_ocp_reg_failure(tp, reg))
843                 return;
844
845         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
846
847         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
848 }
849
850 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
851 {
852         if (rtl_ocp_reg_failure(tp, reg))
853                 return 0;
854
855         RTL_W32(tp, GPHY_OCP, reg << 15);
856
857         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
858                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
859 }
860
861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
862 {
863         if (rtl_ocp_reg_failure(tp, reg))
864                 return;
865
866         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
867 }
868
869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
870 {
871         if (rtl_ocp_reg_failure(tp, reg))
872                 return 0;
873
874         RTL_W32(tp, OCPDR, reg << 15);
875
876         return RTL_R32(tp, OCPDR);
877 }
878
879 #define OCP_STD_PHY_BASE        0xa400
880
881 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
882 {
883         if (reg == 0x1f) {
884                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
885                 return;
886         }
887
888         if (tp->ocp_base != OCP_STD_PHY_BASE)
889                 reg -= 0x10;
890
891         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
892 }
893
894 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
895 {
896         if (tp->ocp_base != OCP_STD_PHY_BASE)
897                 reg -= 0x10;
898
899         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
900 }
901
902 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
903 {
904         if (reg == 0x1f) {
905                 tp->ocp_base = value << 4;
906                 return;
907         }
908
909         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
910 }
911
912 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
913 {
914         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
915 }
916
917 DECLARE_RTL_COND(rtl_phyar_cond)
918 {
919         return RTL_R32(tp, PHYAR) & 0x80000000;
920 }
921
922 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
923 {
924         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
925
926         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
927         /*
928          * According to hardware specs a 20us delay is required after write
929          * complete indication, but before sending next command.
930          */
931         udelay(20);
932 }
933
934 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
935 {
936         int value;
937
938         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
939
940         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
941                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
942
943         /*
944          * According to hardware specs a 20us delay is required after read
945          * complete indication, but before sending next command.
946          */
947         udelay(20);
948
949         return value;
950 }
951
952 DECLARE_RTL_COND(rtl_ocpar_cond)
953 {
954         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
955 }
956
957 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
958 {
959         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
960         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
961         RTL_W32(tp, EPHY_RXER_NUM, 0);
962
963         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
964 }
965
966 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
967 {
968         r8168dp_1_mdio_access(tp, reg,
969                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
970 }
971
972 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
973 {
974         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
975
976         mdelay(1);
977         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
978         RTL_W32(tp, EPHY_RXER_NUM, 0);
979
980         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
981                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
982 }
983
984 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
985
986 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
987 {
988         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
989 }
990
991 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
992 {
993         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
994 }
995
996 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
997 {
998         r8168dp_2_mdio_start(tp);
999
1000         r8169_mdio_write(tp, reg, value);
1001
1002         r8168dp_2_mdio_stop(tp);
1003 }
1004
1005 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1006 {
1007         int value;
1008
1009         r8168dp_2_mdio_start(tp);
1010
1011         value = r8169_mdio_read(tp, reg);
1012
1013         r8168dp_2_mdio_stop(tp);
1014
1015         return value;
1016 }
1017
1018 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1019 {
1020         tp->mdio_ops.write(tp, location, val);
1021 }
1022
1023 static int rtl_readphy(struct rtl8169_private *tp, int location)
1024 {
1025         return tp->mdio_ops.read(tp, location);
1026 }
1027
1028 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1029 {
1030         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1031 }
1032
1033 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034 {
1035         int val;
1036
1037         val = rtl_readphy(tp, reg_addr);
1038         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1039 }
1040
1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1042 {
1043         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1044 }
1045
1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1047 {
1048         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1052
1053         udelay(10);
1054 }
1055
1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1057 {
1058         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1059
1060         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1062 }
1063
1064 DECLARE_RTL_COND(rtl_eriar_cond)
1065 {
1066         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1067 }
1068
1069 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1070                           u32 val, int type)
1071 {
1072         BUG_ON((addr & 3) || (mask == 0));
1073         RTL_W32(tp, ERIDR, val);
1074         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1075
1076         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1077 }
1078
1079 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1080 {
1081         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1082
1083         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084                 RTL_R32(tp, ERIDR) : ~0;
1085 }
1086
1087 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1088                          u32 m, int type)
1089 {
1090         u32 val;
1091
1092         val = rtl_eri_read(tp, addr, type);
1093         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1094 }
1095
1096 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1097 {
1098         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1099         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1100                 RTL_R32(tp, OCPDR) : ~0;
1101 }
1102
1103 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1104 {
1105         return rtl_eri_read(tp, reg, ERIAR_OOB);
1106 }
1107
1108 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1109 {
1110         switch (tp->mac_version) {
1111         case RTL_GIGA_MAC_VER_27:
1112         case RTL_GIGA_MAC_VER_28:
1113         case RTL_GIGA_MAC_VER_31:
1114                 return r8168dp_ocp_read(tp, mask, reg);
1115         case RTL_GIGA_MAC_VER_49:
1116         case RTL_GIGA_MAC_VER_50:
1117         case RTL_GIGA_MAC_VER_51:
1118                 return r8168ep_ocp_read(tp, mask, reg);
1119         default:
1120                 BUG();
1121                 return ~0;
1122         }
1123 }
1124
1125 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1126                               u32 data)
1127 {
1128         RTL_W32(tp, OCPDR, data);
1129         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1130         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1131 }
1132
1133 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134                               u32 data)
1135 {
1136         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137                       data, ERIAR_OOB);
1138 }
1139
1140 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1141 {
1142         switch (tp->mac_version) {
1143         case RTL_GIGA_MAC_VER_27:
1144         case RTL_GIGA_MAC_VER_28:
1145         case RTL_GIGA_MAC_VER_31:
1146                 r8168dp_ocp_write(tp, mask, reg, data);
1147                 break;
1148         case RTL_GIGA_MAC_VER_49:
1149         case RTL_GIGA_MAC_VER_50:
1150         case RTL_GIGA_MAC_VER_51:
1151                 r8168ep_ocp_write(tp, mask, reg, data);
1152                 break;
1153         default:
1154                 BUG();
1155                 break;
1156         }
1157 }
1158
1159 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1160 {
1161         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1162
1163         ocp_write(tp, 0x1, 0x30, 0x00000001);
1164 }
1165
1166 #define OOB_CMD_RESET           0x00
1167 #define OOB_CMD_DRIVER_START    0x05
1168 #define OOB_CMD_DRIVER_STOP     0x06
1169
1170 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171 {
1172         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1173 }
1174
1175 DECLARE_RTL_COND(rtl_ocp_read_cond)
1176 {
1177         u16 reg;
1178
1179         reg = rtl8168_get_ocp_reg(tp);
1180
1181         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1182 }
1183
1184 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1185 {
1186         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1187 }
1188
1189 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190 {
1191         return RTL_R8(tp, IBISR0) & 0x20;
1192 }
1193
1194 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195 {
1196         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1197         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1198         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1199         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1200 }
1201
1202 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203 {
1204         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1205         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1206 }
1207
1208 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1209 {
1210         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1211         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1212         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1213 }
1214
1215 static void rtl8168_driver_start(struct rtl8169_private *tp)
1216 {
1217         switch (tp->mac_version) {
1218         case RTL_GIGA_MAC_VER_27:
1219         case RTL_GIGA_MAC_VER_28:
1220         case RTL_GIGA_MAC_VER_31:
1221                 rtl8168dp_driver_start(tp);
1222                 break;
1223         case RTL_GIGA_MAC_VER_49:
1224         case RTL_GIGA_MAC_VER_50:
1225         case RTL_GIGA_MAC_VER_51:
1226                 rtl8168ep_driver_start(tp);
1227                 break;
1228         default:
1229                 BUG();
1230                 break;
1231         }
1232 }
1233
1234 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1235 {
1236         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1237         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1238 }
1239
1240 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1241 {
1242         rtl8168ep_stop_cmac(tp);
1243         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1244         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1245         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1246 }
1247
1248 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1249 {
1250         switch (tp->mac_version) {
1251         case RTL_GIGA_MAC_VER_27:
1252         case RTL_GIGA_MAC_VER_28:
1253         case RTL_GIGA_MAC_VER_31:
1254                 rtl8168dp_driver_stop(tp);
1255                 break;
1256         case RTL_GIGA_MAC_VER_49:
1257         case RTL_GIGA_MAC_VER_50:
1258         case RTL_GIGA_MAC_VER_51:
1259                 rtl8168ep_driver_stop(tp);
1260                 break;
1261         default:
1262                 BUG();
1263                 break;
1264         }
1265 }
1266
1267 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1268 {
1269         u16 reg = rtl8168_get_ocp_reg(tp);
1270
1271         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1272 }
1273
1274 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1275 {
1276         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1277 }
1278
1279 static bool r8168_check_dash(struct rtl8169_private *tp)
1280 {
1281         switch (tp->mac_version) {
1282         case RTL_GIGA_MAC_VER_27:
1283         case RTL_GIGA_MAC_VER_28:
1284         case RTL_GIGA_MAC_VER_31:
1285                 return r8168dp_check_dash(tp);
1286         case RTL_GIGA_MAC_VER_49:
1287         case RTL_GIGA_MAC_VER_50:
1288         case RTL_GIGA_MAC_VER_51:
1289                 return r8168ep_check_dash(tp);
1290         default:
1291                 return false;
1292         }
1293 }
1294
1295 struct exgmac_reg {
1296         u16 addr;
1297         u16 mask;
1298         u32 val;
1299 };
1300
1301 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1302                                    const struct exgmac_reg *r, int len)
1303 {
1304         while (len-- > 0) {
1305                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1306                 r++;
1307         }
1308 }
1309
1310 DECLARE_RTL_COND(rtl_efusear_cond)
1311 {
1312         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1313 }
1314
1315 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1316 {
1317         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1318
1319         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1320                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1321 }
1322
1323 static u16 rtl_get_events(struct rtl8169_private *tp)
1324 {
1325         return RTL_R16(tp, IntrStatus);
1326 }
1327
1328 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1329 {
1330         RTL_W16(tp, IntrStatus, bits);
1331         mmiowb();
1332 }
1333
1334 static void rtl_irq_disable(struct rtl8169_private *tp)
1335 {
1336         RTL_W16(tp, IntrMask, 0);
1337         mmiowb();
1338 }
1339
1340 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1341 {
1342         RTL_W16(tp, IntrMask, bits);
1343 }
1344
1345 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1346 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1347 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1348
1349 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1350 {
1351         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1352 }
1353
1354 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1355 {
1356         rtl_irq_disable(tp);
1357         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1358         RTL_R8(tp, ChipCmd);
1359 }
1360
1361 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1362 {
1363         struct net_device *dev = tp->dev;
1364         struct phy_device *phydev = dev->phydev;
1365
1366         if (!netif_running(dev))
1367                 return;
1368
1369         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1370             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1371                 if (phydev->speed == SPEED_1000) {
1372                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1373                                       ERIAR_EXGMAC);
1374                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1375                                       ERIAR_EXGMAC);
1376                 } else if (phydev->speed == SPEED_100) {
1377                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1378                                       ERIAR_EXGMAC);
1379                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1380                                       ERIAR_EXGMAC);
1381                 } else {
1382                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1383                                       ERIAR_EXGMAC);
1384                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1385                                       ERIAR_EXGMAC);
1386                 }
1387                 /* Reset packet filter */
1388                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1389                              ERIAR_EXGMAC);
1390                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1391                              ERIAR_EXGMAC);
1392         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1393                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1394                 if (phydev->speed == SPEED_1000) {
1395                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1396                                       ERIAR_EXGMAC);
1397                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1398                                       ERIAR_EXGMAC);
1399                 } else {
1400                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1401                                       ERIAR_EXGMAC);
1402                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1403                                       ERIAR_EXGMAC);
1404                 }
1405         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1406                 if (phydev->speed == SPEED_10) {
1407                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1408                                       ERIAR_EXGMAC);
1409                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1410                                       ERIAR_EXGMAC);
1411                 } else {
1412                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1413                                       ERIAR_EXGMAC);
1414                 }
1415         }
1416 }
1417
1418 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1419
1420 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1421 {
1422         u8 options;
1423         u32 wolopts = 0;
1424
1425         options = RTL_R8(tp, Config1);
1426         if (!(options & PMEnable))
1427                 return 0;
1428
1429         options = RTL_R8(tp, Config3);
1430         if (options & LinkUp)
1431                 wolopts |= WAKE_PHY;
1432         switch (tp->mac_version) {
1433         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1434         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1435                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1436                         wolopts |= WAKE_MAGIC;
1437                 break;
1438         default:
1439                 if (options & MagicPacket)
1440                         wolopts |= WAKE_MAGIC;
1441                 break;
1442         }
1443
1444         options = RTL_R8(tp, Config5);
1445         if (options & UWF)
1446                 wolopts |= WAKE_UCAST;
1447         if (options & BWF)
1448                 wolopts |= WAKE_BCAST;
1449         if (options & MWF)
1450                 wolopts |= WAKE_MCAST;
1451
1452         return wolopts;
1453 }
1454
1455 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1456 {
1457         struct rtl8169_private *tp = netdev_priv(dev);
1458
1459         rtl_lock_work(tp);
1460         wol->supported = WAKE_ANY;
1461         wol->wolopts = tp->saved_wolopts;
1462         rtl_unlock_work(tp);
1463 }
1464
1465 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1466 {
1467         unsigned int i, tmp;
1468         static const struct {
1469                 u32 opt;
1470                 u16 reg;
1471                 u8  mask;
1472         } cfg[] = {
1473                 { WAKE_PHY,   Config3, LinkUp },
1474                 { WAKE_UCAST, Config5, UWF },
1475                 { WAKE_BCAST, Config5, BWF },
1476                 { WAKE_MCAST, Config5, MWF },
1477                 { WAKE_ANY,   Config5, LanWake },
1478                 { WAKE_MAGIC, Config3, MagicPacket }
1479         };
1480         u8 options;
1481
1482         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1483
1484         switch (tp->mac_version) {
1485         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1486         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1487                 tmp = ARRAY_SIZE(cfg) - 1;
1488                 if (wolopts & WAKE_MAGIC)
1489                         rtl_w0w1_eri(tp,
1490                                      0x0dc,
1491                                      ERIAR_MASK_0100,
1492                                      MagicPacket_v2,
1493                                      0x0000,
1494                                      ERIAR_EXGMAC);
1495                 else
1496                         rtl_w0w1_eri(tp,
1497                                      0x0dc,
1498                                      ERIAR_MASK_0100,
1499                                      0x0000,
1500                                      MagicPacket_v2,
1501                                      ERIAR_EXGMAC);
1502                 break;
1503         default:
1504                 tmp = ARRAY_SIZE(cfg);
1505                 break;
1506         }
1507
1508         for (i = 0; i < tmp; i++) {
1509                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1510                 if (wolopts & cfg[i].opt)
1511                         options |= cfg[i].mask;
1512                 RTL_W8(tp, cfg[i].reg, options);
1513         }
1514
1515         switch (tp->mac_version) {
1516         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1517                 options = RTL_R8(tp, Config1) & ~PMEnable;
1518                 if (wolopts)
1519                         options |= PMEnable;
1520                 RTL_W8(tp, Config1, options);
1521                 break;
1522         default:
1523                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1524                 if (wolopts)
1525                         options |= PME_SIGNAL;
1526                 RTL_W8(tp, Config2, options);
1527                 break;
1528         }
1529
1530         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1531 }
1532
1533 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1534 {
1535         struct rtl8169_private *tp = netdev_priv(dev);
1536         struct device *d = tp_to_dev(tp);
1537
1538         if (wol->wolopts & ~WAKE_ANY)
1539                 return -EINVAL;
1540
1541         pm_runtime_get_noresume(d);
1542
1543         rtl_lock_work(tp);
1544
1545         tp->saved_wolopts = wol->wolopts;
1546
1547         if (pm_runtime_active(d))
1548                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1549
1550         rtl_unlock_work(tp);
1551
1552         device_set_wakeup_enable(d, tp->saved_wolopts);
1553
1554         pm_runtime_put_noidle(d);
1555
1556         return 0;
1557 }
1558
1559 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1560 {
1561         return rtl_chip_infos[tp->mac_version].fw_name;
1562 }
1563
1564 static void rtl8169_get_drvinfo(struct net_device *dev,
1565                                 struct ethtool_drvinfo *info)
1566 {
1567         struct rtl8169_private *tp = netdev_priv(dev);
1568         struct rtl_fw *rtl_fw = tp->rtl_fw;
1569
1570         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1571         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1572         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1573         if (!IS_ERR_OR_NULL(rtl_fw))
1574                 strlcpy(info->fw_version, rtl_fw->version,
1575                         sizeof(info->fw_version));
1576 }
1577
1578 static int rtl8169_get_regs_len(struct net_device *dev)
1579 {
1580         return R8169_REGS_SIZE;
1581 }
1582
1583 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1584         netdev_features_t features)
1585 {
1586         struct rtl8169_private *tp = netdev_priv(dev);
1587
1588         if (dev->mtu > TD_MSS_MAX)
1589                 features &= ~NETIF_F_ALL_TSO;
1590
1591         if (dev->mtu > JUMBO_1K &&
1592             tp->mac_version > RTL_GIGA_MAC_VER_06)
1593                 features &= ~NETIF_F_IP_CSUM;
1594
1595         return features;
1596 }
1597
1598 static int rtl8169_set_features(struct net_device *dev,
1599                                 netdev_features_t features)
1600 {
1601         struct rtl8169_private *tp = netdev_priv(dev);
1602         u32 rx_config;
1603
1604         rtl_lock_work(tp);
1605
1606         rx_config = RTL_R32(tp, RxConfig);
1607         if (features & NETIF_F_RXALL)
1608                 rx_config |= (AcceptErr | AcceptRunt);
1609         else
1610                 rx_config &= ~(AcceptErr | AcceptRunt);
1611
1612         RTL_W32(tp, RxConfig, rx_config);
1613
1614         if (features & NETIF_F_RXCSUM)
1615                 tp->cp_cmd |= RxChkSum;
1616         else
1617                 tp->cp_cmd &= ~RxChkSum;
1618
1619         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1620                 tp->cp_cmd |= RxVlan;
1621         else
1622                 tp->cp_cmd &= ~RxVlan;
1623
1624         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1625         RTL_R16(tp, CPlusCmd);
1626
1627         rtl_unlock_work(tp);
1628
1629         return 0;
1630 }
1631
1632 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1633 {
1634         return (skb_vlan_tag_present(skb)) ?
1635                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1636 }
1637
1638 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1639 {
1640         u32 opts2 = le32_to_cpu(desc->opts2);
1641
1642         if (opts2 & RxVlanTag)
1643                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1644 }
1645
1646 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1647                              void *p)
1648 {
1649         struct rtl8169_private *tp = netdev_priv(dev);
1650         u32 __iomem *data = tp->mmio_addr;
1651         u32 *dw = p;
1652         int i;
1653
1654         rtl_lock_work(tp);
1655         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1656                 memcpy_fromio(dw++, data++, 4);
1657         rtl_unlock_work(tp);
1658 }
1659
1660 static u32 rtl8169_get_msglevel(struct net_device *dev)
1661 {
1662         struct rtl8169_private *tp = netdev_priv(dev);
1663
1664         return tp->msg_enable;
1665 }
1666
1667 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1668 {
1669         struct rtl8169_private *tp = netdev_priv(dev);
1670
1671         tp->msg_enable = value;
1672 }
1673
1674 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1675         "tx_packets",
1676         "rx_packets",
1677         "tx_errors",
1678         "rx_errors",
1679         "rx_missed",
1680         "align_errors",
1681         "tx_single_collisions",
1682         "tx_multi_collisions",
1683         "unicast",
1684         "broadcast",
1685         "multicast",
1686         "tx_aborted",
1687         "tx_underrun",
1688 };
1689
1690 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1691 {
1692         switch (sset) {
1693         case ETH_SS_STATS:
1694                 return ARRAY_SIZE(rtl8169_gstrings);
1695         default:
1696                 return -EOPNOTSUPP;
1697         }
1698 }
1699
1700 DECLARE_RTL_COND(rtl_counters_cond)
1701 {
1702         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1703 }
1704
1705 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1706 {
1707         dma_addr_t paddr = tp->counters_phys_addr;
1708         u32 cmd;
1709
1710         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1711         RTL_R32(tp, CounterAddrHigh);
1712         cmd = (u64)paddr & DMA_BIT_MASK(32);
1713         RTL_W32(tp, CounterAddrLow, cmd);
1714         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1715
1716         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1717 }
1718
1719 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1720 {
1721         /*
1722          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1723          * tally counters.
1724          */
1725         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1726                 return true;
1727
1728         return rtl8169_do_counters(tp, CounterReset);
1729 }
1730
1731 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1732 {
1733         /*
1734          * Some chips are unable to dump tally counters when the receiver
1735          * is disabled.
1736          */
1737         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1738                 return true;
1739
1740         return rtl8169_do_counters(tp, CounterDump);
1741 }
1742
1743 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1744 {
1745         struct rtl8169_counters *counters = tp->counters;
1746         bool ret = false;
1747
1748         /*
1749          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1750          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1751          * reset by a power cycle, while the counter values collected by the
1752          * driver are reset at every driver unload/load cycle.
1753          *
1754          * To make sure the HW values returned by @get_stats64 match the SW
1755          * values, we collect the initial values at first open(*) and use them
1756          * as offsets to normalize the values returned by @get_stats64.
1757          *
1758          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1759          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1760          * set at open time by rtl_hw_start.
1761          */
1762
1763         if (tp->tc_offset.inited)
1764                 return true;
1765
1766         /* If both, reset and update fail, propagate to caller. */
1767         if (rtl8169_reset_counters(tp))
1768                 ret = true;
1769
1770         if (rtl8169_update_counters(tp))
1771                 ret = true;
1772
1773         tp->tc_offset.tx_errors = counters->tx_errors;
1774         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1775         tp->tc_offset.tx_aborted = counters->tx_aborted;
1776         tp->tc_offset.inited = true;
1777
1778         return ret;
1779 }
1780
1781 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1782                                       struct ethtool_stats *stats, u64 *data)
1783 {
1784         struct rtl8169_private *tp = netdev_priv(dev);
1785         struct device *d = tp_to_dev(tp);
1786         struct rtl8169_counters *counters = tp->counters;
1787
1788         ASSERT_RTNL();
1789
1790         pm_runtime_get_noresume(d);
1791
1792         if (pm_runtime_active(d))
1793                 rtl8169_update_counters(tp);
1794
1795         pm_runtime_put_noidle(d);
1796
1797         data[0] = le64_to_cpu(counters->tx_packets);
1798         data[1] = le64_to_cpu(counters->rx_packets);
1799         data[2] = le64_to_cpu(counters->tx_errors);
1800         data[3] = le32_to_cpu(counters->rx_errors);
1801         data[4] = le16_to_cpu(counters->rx_missed);
1802         data[5] = le16_to_cpu(counters->align_errors);
1803         data[6] = le32_to_cpu(counters->tx_one_collision);
1804         data[7] = le32_to_cpu(counters->tx_multi_collision);
1805         data[8] = le64_to_cpu(counters->rx_unicast);
1806         data[9] = le64_to_cpu(counters->rx_broadcast);
1807         data[10] = le32_to_cpu(counters->rx_multicast);
1808         data[11] = le16_to_cpu(counters->tx_aborted);
1809         data[12] = le16_to_cpu(counters->tx_underun);
1810 }
1811
1812 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1813 {
1814         switch(stringset) {
1815         case ETH_SS_STATS:
1816                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1817                 break;
1818         }
1819 }
1820
1821 /*
1822  * Interrupt coalescing
1823  *
1824  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1825  * >     8169, 8168 and 810x line of chipsets
1826  *
1827  * 8169, 8168, and 8136(810x) serial chipsets support it.
1828  *
1829  * > 2 - the Tx timer unit at gigabit speed
1830  *
1831  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1832  * (0xe0) bit 1 and bit 0.
1833  *
1834  * For 8169
1835  * bit[1:0] \ speed        1000M           100M            10M
1836  * 0 0                     320ns           2.56us          40.96us
1837  * 0 1                     2.56us          20.48us         327.7us
1838  * 1 0                     5.12us          40.96us         655.4us
1839  * 1 1                     10.24us         81.92us         1.31ms
1840  *
1841  * For the other
1842  * bit[1:0] \ speed        1000M           100M            10M
1843  * 0 0                     5us             2.56us          40.96us
1844  * 0 1                     40us            20.48us         327.7us
1845  * 1 0                     80us            40.96us         655.4us
1846  * 1 1                     160us           81.92us         1.31ms
1847  */
1848
1849 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1850 struct rtl_coalesce_scale {
1851         /* Rx / Tx */
1852         u32 nsecs[2];
1853 };
1854
1855 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1856 struct rtl_coalesce_info {
1857         u32 speed;
1858         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1859 };
1860
1861 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1862 #define rxtx_x1822(r, t) {              \
1863         {{(r),          (t)}},          \
1864         {{(r)*8,        (t)*8}},        \
1865         {{(r)*8*2,      (t)*8*2}},      \
1866         {{(r)*8*2*2,    (t)*8*2*2}},    \
1867 }
1868 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1869         /* speed        delays:     rx00   tx00 */
1870         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1871         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1872         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1873         { 0 },
1874 };
1875
1876 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1877         /* speed        delays:     rx00   tx00 */
1878         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1879         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1880         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1881         { 0 },
1882 };
1883 #undef rxtx_x1822
1884
1885 /* get rx/tx scale vector corresponding to current speed */
1886 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1887 {
1888         struct rtl8169_private *tp = netdev_priv(dev);
1889         struct ethtool_link_ksettings ecmd;
1890         const struct rtl_coalesce_info *ci;
1891         int rc;
1892
1893         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1894         if (rc < 0)
1895                 return ERR_PTR(rc);
1896
1897         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1898                 if (ecmd.base.speed == ci->speed) {
1899                         return ci;
1900                 }
1901         }
1902
1903         return ERR_PTR(-ELNRNG);
1904 }
1905
1906 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1907 {
1908         struct rtl8169_private *tp = netdev_priv(dev);
1909         const struct rtl_coalesce_info *ci;
1910         const struct rtl_coalesce_scale *scale;
1911         struct {
1912                 u32 *max_frames;
1913                 u32 *usecs;
1914         } coal_settings [] = {
1915                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1916                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1917         }, *p = coal_settings;
1918         int i;
1919         u16 w;
1920
1921         memset(ec, 0, sizeof(*ec));
1922
1923         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1924         ci = rtl_coalesce_info(dev);
1925         if (IS_ERR(ci))
1926                 return PTR_ERR(ci);
1927
1928         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1929
1930         /* read IntrMitigate and adjust according to scale */
1931         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1932                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1933                 w >>= RTL_COALESCE_SHIFT;
1934                 *p->usecs = w & RTL_COALESCE_MASK;
1935         }
1936
1937         for (i = 0; i < 2; i++) {
1938                 p = coal_settings + i;
1939                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1940
1941                 /*
1942                  * ethtool_coalesce says it is illegal to set both usecs and
1943                  * max_frames to 0.
1944                  */
1945                 if (!*p->usecs && !*p->max_frames)
1946                         *p->max_frames = 1;
1947         }
1948
1949         return 0;
1950 }
1951
1952 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1953 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1954                         struct net_device *dev, u32 nsec, u16 *cp01)
1955 {
1956         const struct rtl_coalesce_info *ci;
1957         u16 i;
1958
1959         ci = rtl_coalesce_info(dev);
1960         if (IS_ERR(ci))
1961                 return ERR_CAST(ci);
1962
1963         for (i = 0; i < 4; i++) {
1964                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1965                                         ci->scalev[i].nsecs[1]);
1966                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1967                         *cp01 = i;
1968                         return &ci->scalev[i];
1969                 }
1970         }
1971
1972         return ERR_PTR(-EINVAL);
1973 }
1974
1975 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1976 {
1977         struct rtl8169_private *tp = netdev_priv(dev);
1978         const struct rtl_coalesce_scale *scale;
1979         struct {
1980                 u32 frames;
1981                 u32 usecs;
1982         } coal_settings [] = {
1983                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1984                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1985         }, *p = coal_settings;
1986         u16 w = 0, cp01;
1987         int i;
1988
1989         scale = rtl_coalesce_choose_scale(dev,
1990                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1991         if (IS_ERR(scale))
1992                 return PTR_ERR(scale);
1993
1994         for (i = 0; i < 2; i++, p++) {
1995                 u32 units;
1996
1997                 /*
1998                  * accept max_frames=1 we returned in rtl_get_coalesce.
1999                  * accept it not only when usecs=0 because of e.g. the following scenario:
2000                  *
2001                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2002                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2003                  * - then user does `ethtool -C eth0 rx-usecs 100`
2004                  *
2005                  * since ethtool sends to kernel whole ethtool_coalesce
2006                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2007                  * we'll reject it below in `frames % 4 != 0`.
2008                  */
2009                 if (p->frames == 1) {
2010                         p->frames = 0;
2011                 }
2012
2013                 units = p->usecs * 1000 / scale->nsecs[i];
2014                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2015                         return -EINVAL;
2016
2017                 w <<= RTL_COALESCE_SHIFT;
2018                 w |= units;
2019                 w <<= RTL_COALESCE_SHIFT;
2020                 w |= p->frames >> 2;
2021         }
2022
2023         rtl_lock_work(tp);
2024
2025         RTL_W16(tp, IntrMitigate, swab16(w));
2026
2027         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2028         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2029         RTL_R16(tp, CPlusCmd);
2030
2031         rtl_unlock_work(tp);
2032
2033         return 0;
2034 }
2035
2036 static const struct ethtool_ops rtl8169_ethtool_ops = {
2037         .get_drvinfo            = rtl8169_get_drvinfo,
2038         .get_regs_len           = rtl8169_get_regs_len,
2039         .get_link               = ethtool_op_get_link,
2040         .get_coalesce           = rtl_get_coalesce,
2041         .set_coalesce           = rtl_set_coalesce,
2042         .get_msglevel           = rtl8169_get_msglevel,
2043         .set_msglevel           = rtl8169_set_msglevel,
2044         .get_regs               = rtl8169_get_regs,
2045         .get_wol                = rtl8169_get_wol,
2046         .set_wol                = rtl8169_set_wol,
2047         .get_strings            = rtl8169_get_strings,
2048         .get_sset_count         = rtl8169_get_sset_count,
2049         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2050         .get_ts_info            = ethtool_op_get_ts_info,
2051         .nway_reset             = phy_ethtool_nway_reset,
2052         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2053         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2054 };
2055
2056 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2057                                     u8 default_version)
2058 {
2059         /*
2060          * The driver currently handles the 8168Bf and the 8168Be identically
2061          * but they can be identified more specifically through the test below
2062          * if needed:
2063          *
2064          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2065          *
2066          * Same thing for the 8101Eb and the 8101Ec:
2067          *
2068          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2069          */
2070         static const struct rtl_mac_info {
2071                 u32 mask;
2072                 u32 val;
2073                 int mac_version;
2074         } mac_info[] = {
2075                 /* 8168EP family. */
2076                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2077                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2078                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2079
2080                 /* 8168H family. */
2081                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2082                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2083
2084                 /* 8168G family. */
2085                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2086                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2087                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2088                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2089
2090                 /* 8168F family. */
2091                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2092                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2093                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2094
2095                 /* 8168E family. */
2096                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2097                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2098                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2099
2100                 /* 8168D family. */
2101                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2102                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2103
2104                 /* 8168DP family. */
2105                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2106                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2107                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2108
2109                 /* 8168C family. */
2110                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2111                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2112                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2113                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2114                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2115                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2116                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2117
2118                 /* 8168B family. */
2119                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2120                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2121                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2122
2123                 /* 8101 family. */
2124                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2125                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2126                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2127                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2128                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2129                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2130                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2131                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2132                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2133                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2134                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2135                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2136                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2137                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2138                 /* FIXME: where did these entries come from ? -- FR */
2139                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2140                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2141
2142                 /* 8110 family. */
2143                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2144                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2145                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2146                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2147                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2148                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2149
2150                 /* Catch-all */
2151                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2152         };
2153         const struct rtl_mac_info *p = mac_info;
2154         u32 reg;
2155
2156         reg = RTL_R32(tp, TxConfig);
2157         while ((reg & p->mask) != p->val)
2158                 p++;
2159         tp->mac_version = p->mac_version;
2160
2161         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2162                 dev_notice(tp_to_dev(tp),
2163                            "unknown MAC, using family default\n");
2164                 tp->mac_version = default_version;
2165         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2166                 tp->mac_version = tp->supports_gmii ?
2167                                   RTL_GIGA_MAC_VER_42 :
2168                                   RTL_GIGA_MAC_VER_43;
2169         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2170                 tp->mac_version = tp->supports_gmii ?
2171                                   RTL_GIGA_MAC_VER_45 :
2172                                   RTL_GIGA_MAC_VER_47;
2173         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2174                 tp->mac_version = tp->supports_gmii ?
2175                                   RTL_GIGA_MAC_VER_46 :
2176                                   RTL_GIGA_MAC_VER_48;
2177         }
2178 }
2179
2180 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2181 {
2182         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2183 }
2184
2185 struct phy_reg {
2186         u16 reg;
2187         u16 val;
2188 };
2189
2190 static void rtl_writephy_batch(struct rtl8169_private *tp,
2191                                const struct phy_reg *regs, int len)
2192 {
2193         while (len-- > 0) {
2194                 rtl_writephy(tp, regs->reg, regs->val);
2195                 regs++;
2196         }
2197 }
2198
2199 #define PHY_READ                0x00000000
2200 #define PHY_DATA_OR             0x10000000
2201 #define PHY_DATA_AND            0x20000000
2202 #define PHY_BJMPN               0x30000000
2203 #define PHY_MDIO_CHG            0x40000000
2204 #define PHY_CLEAR_READCOUNT     0x70000000
2205 #define PHY_WRITE               0x80000000
2206 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2207 #define PHY_COMP_EQ_SKIPN       0xa0000000
2208 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2209 #define PHY_WRITE_PREVIOUS      0xc0000000
2210 #define PHY_SKIPN               0xd0000000
2211 #define PHY_DELAY_MS            0xe0000000
2212
2213 struct fw_info {
2214         u32     magic;
2215         char    version[RTL_VER_SIZE];
2216         __le32  fw_start;
2217         __le32  fw_len;
2218         u8      chksum;
2219 } __packed;
2220
2221 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2222
2223 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2224 {
2225         const struct firmware *fw = rtl_fw->fw;
2226         struct fw_info *fw_info = (struct fw_info *)fw->data;
2227         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2228         char *version = rtl_fw->version;
2229         bool rc = false;
2230
2231         if (fw->size < FW_OPCODE_SIZE)
2232                 goto out;
2233
2234         if (!fw_info->magic) {
2235                 size_t i, size, start;
2236                 u8 checksum = 0;
2237
2238                 if (fw->size < sizeof(*fw_info))
2239                         goto out;
2240
2241                 for (i = 0; i < fw->size; i++)
2242                         checksum += fw->data[i];
2243                 if (checksum != 0)
2244                         goto out;
2245
2246                 start = le32_to_cpu(fw_info->fw_start);
2247                 if (start > fw->size)
2248                         goto out;
2249
2250                 size = le32_to_cpu(fw_info->fw_len);
2251                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2252                         goto out;
2253
2254                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2255
2256                 pa->code = (__le32 *)(fw->data + start);
2257                 pa->size = size;
2258         } else {
2259                 if (fw->size % FW_OPCODE_SIZE)
2260                         goto out;
2261
2262                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2263
2264                 pa->code = (__le32 *)fw->data;
2265                 pa->size = fw->size / FW_OPCODE_SIZE;
2266         }
2267         version[RTL_VER_SIZE - 1] = 0;
2268
2269         rc = true;
2270 out:
2271         return rc;
2272 }
2273
2274 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2275                            struct rtl_fw_phy_action *pa)
2276 {
2277         bool rc = false;
2278         size_t index;
2279
2280         for (index = 0; index < pa->size; index++) {
2281                 u32 action = le32_to_cpu(pa->code[index]);
2282                 u32 regno = (action & 0x0fff0000) >> 16;
2283
2284                 switch(action & 0xf0000000) {
2285                 case PHY_READ:
2286                 case PHY_DATA_OR:
2287                 case PHY_DATA_AND:
2288                 case PHY_MDIO_CHG:
2289                 case PHY_CLEAR_READCOUNT:
2290                 case PHY_WRITE:
2291                 case PHY_WRITE_PREVIOUS:
2292                 case PHY_DELAY_MS:
2293                         break;
2294
2295                 case PHY_BJMPN:
2296                         if (regno > index) {
2297                                 netif_err(tp, ifup, tp->dev,
2298                                           "Out of range of firmware\n");
2299                                 goto out;
2300                         }
2301                         break;
2302                 case PHY_READCOUNT_EQ_SKIP:
2303                         if (index + 2 >= pa->size) {
2304                                 netif_err(tp, ifup, tp->dev,
2305                                           "Out of range of firmware\n");
2306                                 goto out;
2307                         }
2308                         break;
2309                 case PHY_COMP_EQ_SKIPN:
2310                 case PHY_COMP_NEQ_SKIPN:
2311                 case PHY_SKIPN:
2312                         if (index + 1 + regno >= pa->size) {
2313                                 netif_err(tp, ifup, tp->dev,
2314                                           "Out of range of firmware\n");
2315                                 goto out;
2316                         }
2317                         break;
2318
2319                 default:
2320                         netif_err(tp, ifup, tp->dev,
2321                                   "Invalid action 0x%08x\n", action);
2322                         goto out;
2323                 }
2324         }
2325         rc = true;
2326 out:
2327         return rc;
2328 }
2329
2330 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2331 {
2332         struct net_device *dev = tp->dev;
2333         int rc = -EINVAL;
2334
2335         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2336                 netif_err(tp, ifup, dev, "invalid firmware\n");
2337                 goto out;
2338         }
2339
2340         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2341                 rc = 0;
2342 out:
2343         return rc;
2344 }
2345
2346 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2347 {
2348         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2349         struct mdio_ops org, *ops = &tp->mdio_ops;
2350         u32 predata, count;
2351         size_t index;
2352
2353         predata = count = 0;
2354         org.write = ops->write;
2355         org.read = ops->read;
2356
2357         for (index = 0; index < pa->size; ) {
2358                 u32 action = le32_to_cpu(pa->code[index]);
2359                 u32 data = action & 0x0000ffff;
2360                 u32 regno = (action & 0x0fff0000) >> 16;
2361
2362                 if (!action)
2363                         break;
2364
2365                 switch(action & 0xf0000000) {
2366                 case PHY_READ:
2367                         predata = rtl_readphy(tp, regno);
2368                         count++;
2369                         index++;
2370                         break;
2371                 case PHY_DATA_OR:
2372                         predata |= data;
2373                         index++;
2374                         break;
2375                 case PHY_DATA_AND:
2376                         predata &= data;
2377                         index++;
2378                         break;
2379                 case PHY_BJMPN:
2380                         index -= regno;
2381                         break;
2382                 case PHY_MDIO_CHG:
2383                         if (data == 0) {
2384                                 ops->write = org.write;
2385                                 ops->read = org.read;
2386                         } else if (data == 1) {
2387                                 ops->write = mac_mcu_write;
2388                                 ops->read = mac_mcu_read;
2389                         }
2390
2391                         index++;
2392                         break;
2393                 case PHY_CLEAR_READCOUNT:
2394                         count = 0;
2395                         index++;
2396                         break;
2397                 case PHY_WRITE:
2398                         rtl_writephy(tp, regno, data);
2399                         index++;
2400                         break;
2401                 case PHY_READCOUNT_EQ_SKIP:
2402                         index += (count == data) ? 2 : 1;
2403                         break;
2404                 case PHY_COMP_EQ_SKIPN:
2405                         if (predata == data)
2406                                 index += regno;
2407                         index++;
2408                         break;
2409                 case PHY_COMP_NEQ_SKIPN:
2410                         if (predata != data)
2411                                 index += regno;
2412                         index++;
2413                         break;
2414                 case PHY_WRITE_PREVIOUS:
2415                         rtl_writephy(tp, regno, predata);
2416                         index++;
2417                         break;
2418                 case PHY_SKIPN:
2419                         index += regno + 1;
2420                         break;
2421                 case PHY_DELAY_MS:
2422                         mdelay(data);
2423                         index++;
2424                         break;
2425
2426                 default:
2427                         BUG();
2428                 }
2429         }
2430
2431         ops->write = org.write;
2432         ops->read = org.read;
2433 }
2434
2435 static void rtl_release_firmware(struct rtl8169_private *tp)
2436 {
2437         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2438                 release_firmware(tp->rtl_fw->fw);
2439                 kfree(tp->rtl_fw);
2440         }
2441         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2442 }
2443
2444 static void rtl_apply_firmware(struct rtl8169_private *tp)
2445 {
2446         struct rtl_fw *rtl_fw = tp->rtl_fw;
2447
2448         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2449         if (!IS_ERR_OR_NULL(rtl_fw))
2450                 rtl_phy_write_fw(tp, rtl_fw);
2451 }
2452
2453 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2454 {
2455         if (rtl_readphy(tp, reg) != val)
2456                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2457         else
2458                 rtl_apply_firmware(tp);
2459 }
2460
2461 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2462 {
2463         static const struct phy_reg phy_reg_init[] = {
2464                 { 0x1f, 0x0001 },
2465                 { 0x06, 0x006e },
2466                 { 0x08, 0x0708 },
2467                 { 0x15, 0x4000 },
2468                 { 0x18, 0x65c7 },
2469
2470                 { 0x1f, 0x0001 },
2471                 { 0x03, 0x00a1 },
2472                 { 0x02, 0x0008 },
2473                 { 0x01, 0x0120 },
2474                 { 0x00, 0x1000 },
2475                 { 0x04, 0x0800 },
2476                 { 0x04, 0x0000 },
2477
2478                 { 0x03, 0xff41 },
2479                 { 0x02, 0xdf60 },
2480                 { 0x01, 0x0140 },
2481                 { 0x00, 0x0077 },
2482                 { 0x04, 0x7800 },
2483                 { 0x04, 0x7000 },
2484
2485                 { 0x03, 0x802f },
2486                 { 0x02, 0x4f02 },
2487                 { 0x01, 0x0409 },
2488                 { 0x00, 0xf0f9 },
2489                 { 0x04, 0x9800 },
2490                 { 0x04, 0x9000 },
2491
2492                 { 0x03, 0xdf01 },
2493                 { 0x02, 0xdf20 },
2494                 { 0x01, 0xff95 },
2495                 { 0x00, 0xba00 },
2496                 { 0x04, 0xa800 },
2497                 { 0x04, 0xa000 },
2498
2499                 { 0x03, 0xff41 },
2500                 { 0x02, 0xdf20 },
2501                 { 0x01, 0x0140 },
2502                 { 0x00, 0x00bb },
2503                 { 0x04, 0xb800 },
2504                 { 0x04, 0xb000 },
2505
2506                 { 0x03, 0xdf41 },
2507                 { 0x02, 0xdc60 },
2508                 { 0x01, 0x6340 },
2509                 { 0x00, 0x007d },
2510                 { 0x04, 0xd800 },
2511                 { 0x04, 0xd000 },
2512
2513                 { 0x03, 0xdf01 },
2514                 { 0x02, 0xdf20 },
2515                 { 0x01, 0x100a },
2516                 { 0x00, 0xa0ff },
2517                 { 0x04, 0xf800 },
2518                 { 0x04, 0xf000 },
2519
2520                 { 0x1f, 0x0000 },
2521                 { 0x0b, 0x0000 },
2522                 { 0x00, 0x9200 }
2523         };
2524
2525         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2526 }
2527
2528 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2529 {
2530         static const struct phy_reg phy_reg_init[] = {
2531                 { 0x1f, 0x0002 },
2532                 { 0x01, 0x90d0 },
2533                 { 0x1f, 0x0000 }
2534         };
2535
2536         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2537 }
2538
2539 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2540 {
2541         struct pci_dev *pdev = tp->pci_dev;
2542
2543         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2544             (pdev->subsystem_device != 0xe000))
2545                 return;
2546
2547         rtl_writephy(tp, 0x1f, 0x0001);
2548         rtl_writephy(tp, 0x10, 0xf01b);
2549         rtl_writephy(tp, 0x1f, 0x0000);
2550 }
2551
2552 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2553 {
2554         static const struct phy_reg phy_reg_init[] = {
2555                 { 0x1f, 0x0001 },
2556                 { 0x04, 0x0000 },
2557                 { 0x03, 0x00a1 },
2558                 { 0x02, 0x0008 },
2559                 { 0x01, 0x0120 },
2560                 { 0x00, 0x1000 },
2561                 { 0x04, 0x0800 },
2562                 { 0x04, 0x9000 },
2563                 { 0x03, 0x802f },
2564                 { 0x02, 0x4f02 },
2565                 { 0x01, 0x0409 },
2566                 { 0x00, 0xf099 },
2567                 { 0x04, 0x9800 },
2568                 { 0x04, 0xa000 },
2569                 { 0x03, 0xdf01 },
2570                 { 0x02, 0xdf20 },
2571                 { 0x01, 0xff95 },
2572                 { 0x00, 0xba00 },
2573                 { 0x04, 0xa800 },
2574                 { 0x04, 0xf000 },
2575                 { 0x03, 0xdf01 },
2576                 { 0x02, 0xdf20 },
2577                 { 0x01, 0x101a },
2578                 { 0x00, 0xa0ff },
2579                 { 0x04, 0xf800 },
2580                 { 0x04, 0x0000 },
2581                 { 0x1f, 0x0000 },
2582
2583                 { 0x1f, 0x0001 },
2584                 { 0x10, 0xf41b },
2585                 { 0x14, 0xfb54 },
2586                 { 0x18, 0xf5c7 },
2587                 { 0x1f, 0x0000 },
2588
2589                 { 0x1f, 0x0001 },
2590                 { 0x17, 0x0cc0 },
2591                 { 0x1f, 0x0000 }
2592         };
2593
2594         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2595
2596         rtl8169scd_hw_phy_config_quirk(tp);
2597 }
2598
2599 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2600 {
2601         static const struct phy_reg phy_reg_init[] = {
2602                 { 0x1f, 0x0001 },
2603                 { 0x04, 0x0000 },
2604                 { 0x03, 0x00a1 },
2605                 { 0x02, 0x0008 },
2606                 { 0x01, 0x0120 },
2607                 { 0x00, 0x1000 },
2608                 { 0x04, 0x0800 },
2609                 { 0x04, 0x9000 },
2610                 { 0x03, 0x802f },
2611                 { 0x02, 0x4f02 },
2612                 { 0x01, 0x0409 },
2613                 { 0x00, 0xf099 },
2614                 { 0x04, 0x9800 },
2615                 { 0x04, 0xa000 },
2616                 { 0x03, 0xdf01 },
2617                 { 0x02, 0xdf20 },
2618                 { 0x01, 0xff95 },
2619                 { 0x00, 0xba00 },
2620                 { 0x04, 0xa800 },
2621                 { 0x04, 0xf000 },
2622                 { 0x03, 0xdf01 },
2623                 { 0x02, 0xdf20 },
2624                 { 0x01, 0x101a },
2625                 { 0x00, 0xa0ff },
2626                 { 0x04, 0xf800 },
2627                 { 0x04, 0x0000 },
2628                 { 0x1f, 0x0000 },
2629
2630                 { 0x1f, 0x0001 },
2631                 { 0x0b, 0x8480 },
2632                 { 0x1f, 0x0000 },
2633
2634                 { 0x1f, 0x0001 },
2635                 { 0x18, 0x67c7 },
2636                 { 0x04, 0x2000 },
2637                 { 0x03, 0x002f },
2638                 { 0x02, 0x4360 },
2639                 { 0x01, 0x0109 },
2640                 { 0x00, 0x3022 },
2641                 { 0x04, 0x2800 },
2642                 { 0x1f, 0x0000 },
2643
2644                 { 0x1f, 0x0001 },
2645                 { 0x17, 0x0cc0 },
2646                 { 0x1f, 0x0000 }
2647         };
2648
2649         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2650 }
2651
2652 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2653 {
2654         static const struct phy_reg phy_reg_init[] = {
2655                 { 0x10, 0xf41b },
2656                 { 0x1f, 0x0000 }
2657         };
2658
2659         rtl_writephy(tp, 0x1f, 0x0001);
2660         rtl_patchphy(tp, 0x16, 1 << 0);
2661
2662         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2663 }
2664
2665 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2666 {
2667         static const struct phy_reg phy_reg_init[] = {
2668                 { 0x1f, 0x0001 },
2669                 { 0x10, 0xf41b },
2670                 { 0x1f, 0x0000 }
2671         };
2672
2673         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2674 }
2675
2676 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2677 {
2678         static const struct phy_reg phy_reg_init[] = {
2679                 { 0x1f, 0x0000 },
2680                 { 0x1d, 0x0f00 },
2681                 { 0x1f, 0x0002 },
2682                 { 0x0c, 0x1ec8 },
2683                 { 0x1f, 0x0000 }
2684         };
2685
2686         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2687 }
2688
2689 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2690 {
2691         static const struct phy_reg phy_reg_init[] = {
2692                 { 0x1f, 0x0001 },
2693                 { 0x1d, 0x3d98 },
2694                 { 0x1f, 0x0000 }
2695         };
2696
2697         rtl_writephy(tp, 0x1f, 0x0000);
2698         rtl_patchphy(tp, 0x14, 1 << 5);
2699         rtl_patchphy(tp, 0x0d, 1 << 5);
2700
2701         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2702 }
2703
2704 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2705 {
2706         static const struct phy_reg phy_reg_init[] = {
2707                 { 0x1f, 0x0001 },
2708                 { 0x12, 0x2300 },
2709                 { 0x1f, 0x0002 },
2710                 { 0x00, 0x88d4 },
2711                 { 0x01, 0x82b1 },
2712                 { 0x03, 0x7002 },
2713                 { 0x08, 0x9e30 },
2714                 { 0x09, 0x01f0 },
2715                 { 0x0a, 0x5500 },
2716                 { 0x0c, 0x00c8 },
2717                 { 0x1f, 0x0003 },
2718                 { 0x12, 0xc096 },
2719                 { 0x16, 0x000a },
2720                 { 0x1f, 0x0000 },
2721                 { 0x1f, 0x0000 },
2722                 { 0x09, 0x2000 },
2723                 { 0x09, 0x0000 }
2724         };
2725
2726         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2727
2728         rtl_patchphy(tp, 0x14, 1 << 5);
2729         rtl_patchphy(tp, 0x0d, 1 << 5);
2730         rtl_writephy(tp, 0x1f, 0x0000);
2731 }
2732
2733 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2734 {
2735         static const struct phy_reg phy_reg_init[] = {
2736                 { 0x1f, 0x0001 },
2737                 { 0x12, 0x2300 },
2738                 { 0x03, 0x802f },
2739                 { 0x02, 0x4f02 },
2740                 { 0x01, 0x0409 },
2741                 { 0x00, 0xf099 },
2742                 { 0x04, 0x9800 },
2743                 { 0x04, 0x9000 },
2744                 { 0x1d, 0x3d98 },
2745                 { 0x1f, 0x0002 },
2746                 { 0x0c, 0x7eb8 },
2747                 { 0x06, 0x0761 },
2748                 { 0x1f, 0x0003 },
2749                 { 0x16, 0x0f0a },
2750                 { 0x1f, 0x0000 }
2751         };
2752
2753         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2754
2755         rtl_patchphy(tp, 0x16, 1 << 0);
2756         rtl_patchphy(tp, 0x14, 1 << 5);
2757         rtl_patchphy(tp, 0x0d, 1 << 5);
2758         rtl_writephy(tp, 0x1f, 0x0000);
2759 }
2760
2761 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2762 {
2763         static const struct phy_reg phy_reg_init[] = {
2764                 { 0x1f, 0x0001 },
2765                 { 0x12, 0x2300 },
2766                 { 0x1d, 0x3d98 },
2767                 { 0x1f, 0x0002 },
2768                 { 0x0c, 0x7eb8 },
2769                 { 0x06, 0x5461 },
2770                 { 0x1f, 0x0003 },
2771                 { 0x16, 0x0f0a },
2772                 { 0x1f, 0x0000 }
2773         };
2774
2775         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2776
2777         rtl_patchphy(tp, 0x16, 1 << 0);
2778         rtl_patchphy(tp, 0x14, 1 << 5);
2779         rtl_patchphy(tp, 0x0d, 1 << 5);
2780         rtl_writephy(tp, 0x1f, 0x0000);
2781 }
2782
2783 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2784 {
2785         rtl8168c_3_hw_phy_config(tp);
2786 }
2787
2788 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2789 {
2790         static const struct phy_reg phy_reg_init_0[] = {
2791                 /* Channel Estimation */
2792                 { 0x1f, 0x0001 },
2793                 { 0x06, 0x4064 },
2794                 { 0x07, 0x2863 },
2795                 { 0x08, 0x059c },
2796                 { 0x09, 0x26b4 },
2797                 { 0x0a, 0x6a19 },
2798                 { 0x0b, 0xdcc8 },
2799                 { 0x10, 0xf06d },
2800                 { 0x14, 0x7f68 },
2801                 { 0x18, 0x7fd9 },
2802                 { 0x1c, 0xf0ff },
2803                 { 0x1d, 0x3d9c },
2804                 { 0x1f, 0x0003 },
2805                 { 0x12, 0xf49f },
2806                 { 0x13, 0x070b },
2807                 { 0x1a, 0x05ad },
2808                 { 0x14, 0x94c0 },
2809
2810                 /*
2811                  * Tx Error Issue
2812                  * Enhance line driver power
2813                  */
2814                 { 0x1f, 0x0002 },
2815                 { 0x06, 0x5561 },
2816                 { 0x1f, 0x0005 },
2817                 { 0x05, 0x8332 },
2818                 { 0x06, 0x5561 },
2819
2820                 /*
2821                  * Can not link to 1Gbps with bad cable
2822                  * Decrease SNR threshold form 21.07dB to 19.04dB
2823                  */
2824                 { 0x1f, 0x0001 },
2825                 { 0x17, 0x0cc0 },
2826
2827                 { 0x1f, 0x0000 },
2828                 { 0x0d, 0xf880 }
2829         };
2830
2831         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2832
2833         /*
2834          * Rx Error Issue
2835          * Fine Tune Switching regulator parameter
2836          */
2837         rtl_writephy(tp, 0x1f, 0x0002);
2838         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2839         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2840
2841         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2842                 static const struct phy_reg phy_reg_init[] = {
2843                         { 0x1f, 0x0002 },
2844                         { 0x05, 0x669a },
2845                         { 0x1f, 0x0005 },
2846                         { 0x05, 0x8330 },
2847                         { 0x06, 0x669a },
2848                         { 0x1f, 0x0002 }
2849                 };
2850                 int val;
2851
2852                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2853
2854                 val = rtl_readphy(tp, 0x0d);
2855
2856                 if ((val & 0x00ff) != 0x006c) {
2857                         static const u32 set[] = {
2858                                 0x0065, 0x0066, 0x0067, 0x0068,
2859                                 0x0069, 0x006a, 0x006b, 0x006c
2860                         };
2861                         int i;
2862
2863                         rtl_writephy(tp, 0x1f, 0x0002);
2864
2865                         val &= 0xff00;
2866                         for (i = 0; i < ARRAY_SIZE(set); i++)
2867                                 rtl_writephy(tp, 0x0d, val | set[i]);
2868                 }
2869         } else {
2870                 static const struct phy_reg phy_reg_init[] = {
2871                         { 0x1f, 0x0002 },
2872                         { 0x05, 0x6662 },
2873                         { 0x1f, 0x0005 },
2874                         { 0x05, 0x8330 },
2875                         { 0x06, 0x6662 }
2876                 };
2877
2878                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2879         }
2880
2881         /* RSET couple improve */
2882         rtl_writephy(tp, 0x1f, 0x0002);
2883         rtl_patchphy(tp, 0x0d, 0x0300);
2884         rtl_patchphy(tp, 0x0f, 0x0010);
2885
2886         /* Fine tune PLL performance */
2887         rtl_writephy(tp, 0x1f, 0x0002);
2888         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2889         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2890
2891         rtl_writephy(tp, 0x1f, 0x0005);
2892         rtl_writephy(tp, 0x05, 0x001b);
2893
2894         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2895
2896         rtl_writephy(tp, 0x1f, 0x0000);
2897 }
2898
2899 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2900 {
2901         static const struct phy_reg phy_reg_init_0[] = {
2902                 /* Channel Estimation */
2903                 { 0x1f, 0x0001 },
2904                 { 0x06, 0x4064 },
2905                 { 0x07, 0x2863 },
2906                 { 0x08, 0x059c },
2907                 { 0x09, 0x26b4 },
2908                 { 0x0a, 0x6a19 },
2909                 { 0x0b, 0xdcc8 },
2910                 { 0x10, 0xf06d },
2911                 { 0x14, 0x7f68 },
2912                 { 0x18, 0x7fd9 },
2913                 { 0x1c, 0xf0ff },
2914                 { 0x1d, 0x3d9c },
2915                 { 0x1f, 0x0003 },
2916                 { 0x12, 0xf49f },
2917                 { 0x13, 0x070b },
2918                 { 0x1a, 0x05ad },
2919                 { 0x14, 0x94c0 },
2920
2921                 /*
2922                  * Tx Error Issue
2923                  * Enhance line driver power
2924                  */
2925                 { 0x1f, 0x0002 },
2926                 { 0x06, 0x5561 },
2927                 { 0x1f, 0x0005 },
2928                 { 0x05, 0x8332 },
2929                 { 0x06, 0x5561 },
2930
2931                 /*
2932                  * Can not link to 1Gbps with bad cable
2933                  * Decrease SNR threshold form 21.07dB to 19.04dB
2934                  */
2935                 { 0x1f, 0x0001 },
2936                 { 0x17, 0x0cc0 },
2937
2938                 { 0x1f, 0x0000 },
2939                 { 0x0d, 0xf880 }
2940         };
2941
2942         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2943
2944         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2945                 static const struct phy_reg phy_reg_init[] = {
2946                         { 0x1f, 0x0002 },
2947                         { 0x05, 0x669a },
2948                         { 0x1f, 0x0005 },
2949                         { 0x05, 0x8330 },
2950                         { 0x06, 0x669a },
2951
2952                         { 0x1f, 0x0002 }
2953                 };
2954                 int val;
2955
2956                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2957
2958                 val = rtl_readphy(tp, 0x0d);
2959                 if ((val & 0x00ff) != 0x006c) {
2960                         static const u32 set[] = {
2961                                 0x0065, 0x0066, 0x0067, 0x0068,
2962                                 0x0069, 0x006a, 0x006b, 0x006c
2963                         };
2964                         int i;
2965
2966                         rtl_writephy(tp, 0x1f, 0x0002);
2967
2968                         val &= 0xff00;
2969                         for (i = 0; i < ARRAY_SIZE(set); i++)
2970                                 rtl_writephy(tp, 0x0d, val | set[i]);
2971                 }
2972         } else {
2973                 static const struct phy_reg phy_reg_init[] = {
2974                         { 0x1f, 0x0002 },
2975                         { 0x05, 0x2642 },
2976                         { 0x1f, 0x0005 },
2977                         { 0x05, 0x8330 },
2978                         { 0x06, 0x2642 }
2979                 };
2980
2981                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2982         }
2983
2984         /* Fine tune PLL performance */
2985         rtl_writephy(tp, 0x1f, 0x0002);
2986         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2987         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2988
2989         /* Switching regulator Slew rate */
2990         rtl_writephy(tp, 0x1f, 0x0002);
2991         rtl_patchphy(tp, 0x0f, 0x0017);
2992
2993         rtl_writephy(tp, 0x1f, 0x0005);
2994         rtl_writephy(tp, 0x05, 0x001b);
2995
2996         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2997
2998         rtl_writephy(tp, 0x1f, 0x0000);
2999 }
3000
3001 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3002 {
3003         static const struct phy_reg phy_reg_init[] = {
3004                 { 0x1f, 0x0002 },
3005                 { 0x10, 0x0008 },
3006                 { 0x0d, 0x006c },
3007
3008                 { 0x1f, 0x0000 },
3009                 { 0x0d, 0xf880 },
3010
3011                 { 0x1f, 0x0001 },
3012                 { 0x17, 0x0cc0 },
3013
3014                 { 0x1f, 0x0001 },
3015                 { 0x0b, 0xa4d8 },
3016                 { 0x09, 0x281c },
3017                 { 0x07, 0x2883 },
3018                 { 0x0a, 0x6b35 },
3019                 { 0x1d, 0x3da4 },
3020                 { 0x1c, 0xeffd },
3021                 { 0x14, 0x7f52 },
3022                 { 0x18, 0x7fc6 },
3023                 { 0x08, 0x0601 },
3024                 { 0x06, 0x4063 },
3025                 { 0x10, 0xf074 },
3026                 { 0x1f, 0x0003 },
3027                 { 0x13, 0x0789 },
3028                 { 0x12, 0xf4bd },
3029                 { 0x1a, 0x04fd },
3030                 { 0x14, 0x84b0 },
3031                 { 0x1f, 0x0000 },
3032                 { 0x00, 0x9200 },
3033
3034                 { 0x1f, 0x0005 },
3035                 { 0x01, 0x0340 },
3036                 { 0x1f, 0x0001 },
3037                 { 0x04, 0x4000 },
3038                 { 0x03, 0x1d21 },
3039                 { 0x02, 0x0c32 },
3040                 { 0x01, 0x0200 },
3041                 { 0x00, 0x5554 },
3042                 { 0x04, 0x4800 },
3043                 { 0x04, 0x4000 },
3044                 { 0x04, 0xf000 },
3045                 { 0x03, 0xdf01 },
3046                 { 0x02, 0xdf20 },
3047                 { 0x01, 0x101a },
3048                 { 0x00, 0xa0ff },
3049                 { 0x04, 0xf800 },
3050                 { 0x04, 0xf000 },
3051                 { 0x1f, 0x0000 },
3052
3053                 { 0x1f, 0x0007 },
3054                 { 0x1e, 0x0023 },
3055                 { 0x16, 0x0000 },
3056                 { 0x1f, 0x0000 }
3057         };
3058
3059         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3060 }
3061
3062 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3063 {
3064         static const struct phy_reg phy_reg_init[] = {
3065                 { 0x1f, 0x0001 },
3066                 { 0x17, 0x0cc0 },
3067
3068                 { 0x1f, 0x0007 },
3069                 { 0x1e, 0x002d },
3070                 { 0x18, 0x0040 },
3071                 { 0x1f, 0x0000 }
3072         };
3073
3074         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3075         rtl_patchphy(tp, 0x0d, 1 << 5);
3076 }
3077
3078 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3079 {
3080         static const struct phy_reg phy_reg_init[] = {
3081                 /* Enable Delay cap */
3082                 { 0x1f, 0x0005 },
3083                 { 0x05, 0x8b80 },
3084                 { 0x06, 0xc896 },
3085                 { 0x1f, 0x0000 },
3086
3087                 /* Channel estimation fine tune */
3088                 { 0x1f, 0x0001 },
3089                 { 0x0b, 0x6c20 },
3090                 { 0x07, 0x2872 },
3091                 { 0x1c, 0xefff },
3092                 { 0x1f, 0x0003 },
3093                 { 0x14, 0x6420 },
3094                 { 0x1f, 0x0000 },
3095
3096                 /* Update PFM & 10M TX idle timer */
3097                 { 0x1f, 0x0007 },
3098                 { 0x1e, 0x002f },
3099                 { 0x15, 0x1919 },
3100                 { 0x1f, 0x0000 },
3101
3102                 { 0x1f, 0x0007 },
3103                 { 0x1e, 0x00ac },
3104                 { 0x18, 0x0006 },
3105                 { 0x1f, 0x0000 }
3106         };
3107
3108         rtl_apply_firmware(tp);
3109
3110         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3111
3112         /* DCO enable for 10M IDLE Power */
3113         rtl_writephy(tp, 0x1f, 0x0007);
3114         rtl_writephy(tp, 0x1e, 0x0023);
3115         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3116         rtl_writephy(tp, 0x1f, 0x0000);
3117
3118         /* For impedance matching */
3119         rtl_writephy(tp, 0x1f, 0x0002);
3120         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3121         rtl_writephy(tp, 0x1f, 0x0000);
3122
3123         /* PHY auto speed down */
3124         rtl_writephy(tp, 0x1f, 0x0007);
3125         rtl_writephy(tp, 0x1e, 0x002d);
3126         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3127         rtl_writephy(tp, 0x1f, 0x0000);
3128         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3129
3130         rtl_writephy(tp, 0x1f, 0x0005);
3131         rtl_writephy(tp, 0x05, 0x8b86);
3132         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3133         rtl_writephy(tp, 0x1f, 0x0000);
3134
3135         rtl_writephy(tp, 0x1f, 0x0005);
3136         rtl_writephy(tp, 0x05, 0x8b85);
3137         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3138         rtl_writephy(tp, 0x1f, 0x0007);
3139         rtl_writephy(tp, 0x1e, 0x0020);
3140         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3141         rtl_writephy(tp, 0x1f, 0x0006);
3142         rtl_writephy(tp, 0x00, 0x5a00);
3143         rtl_writephy(tp, 0x1f, 0x0000);
3144         rtl_writephy(tp, 0x0d, 0x0007);
3145         rtl_writephy(tp, 0x0e, 0x003c);
3146         rtl_writephy(tp, 0x0d, 0x4007);
3147         rtl_writephy(tp, 0x0e, 0x0000);
3148         rtl_writephy(tp, 0x0d, 0x0000);
3149 }
3150
3151 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3152 {
3153         const u16 w[] = {
3154                 addr[0] | (addr[1] << 8),
3155                 addr[2] | (addr[3] << 8),
3156                 addr[4] | (addr[5] << 8)
3157         };
3158         const struct exgmac_reg e[] = {
3159                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3160                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3161                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3162                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3163         };
3164
3165         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3166 }
3167
3168 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3169 {
3170         static const struct phy_reg phy_reg_init[] = {
3171                 /* Enable Delay cap */
3172                 { 0x1f, 0x0004 },
3173                 { 0x1f, 0x0007 },
3174                 { 0x1e, 0x00ac },
3175                 { 0x18, 0x0006 },
3176                 { 0x1f, 0x0002 },
3177                 { 0x1f, 0x0000 },
3178                 { 0x1f, 0x0000 },
3179
3180                 /* Channel estimation fine tune */
3181                 { 0x1f, 0x0003 },
3182                 { 0x09, 0xa20f },
3183                 { 0x1f, 0x0000 },
3184                 { 0x1f, 0x0000 },
3185
3186                 /* Green Setting */
3187                 { 0x1f, 0x0005 },
3188                 { 0x05, 0x8b5b },
3189                 { 0x06, 0x9222 },
3190                 { 0x05, 0x8b6d },
3191                 { 0x06, 0x8000 },
3192                 { 0x05, 0x8b76 },
3193                 { 0x06, 0x8000 },
3194                 { 0x1f, 0x0000 }
3195         };
3196
3197         rtl_apply_firmware(tp);
3198
3199         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3200
3201         /* For 4-corner performance improve */
3202         rtl_writephy(tp, 0x1f, 0x0005);
3203         rtl_writephy(tp, 0x05, 0x8b80);
3204         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3205         rtl_writephy(tp, 0x1f, 0x0000);
3206
3207         /* PHY auto speed down */
3208         rtl_writephy(tp, 0x1f, 0x0004);
3209         rtl_writephy(tp, 0x1f, 0x0007);
3210         rtl_writephy(tp, 0x1e, 0x002d);
3211         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3212         rtl_writephy(tp, 0x1f, 0x0002);
3213         rtl_writephy(tp, 0x1f, 0x0000);
3214         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3215
3216         /* improve 10M EEE waveform */
3217         rtl_writephy(tp, 0x1f, 0x0005);
3218         rtl_writephy(tp, 0x05, 0x8b86);
3219         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3220         rtl_writephy(tp, 0x1f, 0x0000);
3221
3222         /* Improve 2-pair detection performance */
3223         rtl_writephy(tp, 0x1f, 0x0005);
3224         rtl_writephy(tp, 0x05, 0x8b85);
3225         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3226         rtl_writephy(tp, 0x1f, 0x0000);
3227
3228         /* EEE setting */
3229         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3230         rtl_writephy(tp, 0x1f, 0x0005);
3231         rtl_writephy(tp, 0x05, 0x8b85);
3232         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3233         rtl_writephy(tp, 0x1f, 0x0004);
3234         rtl_writephy(tp, 0x1f, 0x0007);
3235         rtl_writephy(tp, 0x1e, 0x0020);
3236         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3237         rtl_writephy(tp, 0x1f, 0x0002);
3238         rtl_writephy(tp, 0x1f, 0x0000);
3239         rtl_writephy(tp, 0x0d, 0x0007);
3240         rtl_writephy(tp, 0x0e, 0x003c);
3241         rtl_writephy(tp, 0x0d, 0x4007);
3242         rtl_writephy(tp, 0x0e, 0x0006);
3243         rtl_writephy(tp, 0x0d, 0x0000);
3244
3245         /* Green feature */
3246         rtl_writephy(tp, 0x1f, 0x0003);
3247         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3248         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3249         rtl_writephy(tp, 0x1f, 0x0000);
3250