drivers/net/ethernet/socionext/netsec.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <linux/types.h>
   4 #include <linux/clk.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/pm_runtime.h>
   7 #include <linux/acpi.h>
   8 #include <linux/of_mdio.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12
  13 #include <net/tcp.h>
  14 #include <net/ip6_checksum.h>
  15
  16 #define NETSEC_REG_SOFT_RST                     0x104
  17 #define NETSEC_REG_COM_INIT                     0x120
  18
  19 #define NETSEC_REG_TOP_STATUS                   0x200
  20 #define NETSEC_IRQ_RX                           BIT(1)
  21 #define NETSEC_IRQ_TX                           BIT(0)
  22
  23 #define NETSEC_REG_TOP_INTEN                    0x204
  24 #define NETSEC_REG_INTEN_SET                    0x234
  25 #define NETSEC_REG_INTEN_CLR                    0x238
  26
  27 #define NETSEC_REG_NRM_TX_STATUS                0x400
  28 #define NETSEC_REG_NRM_TX_INTEN                 0x404
  29 #define NETSEC_REG_NRM_TX_INTEN_SET             0x428
  30 #define NETSEC_REG_NRM_TX_INTEN_CLR             0x42c
  31 #define NRM_TX_ST_NTOWNR        BIT(17)
  32 #define NRM_TX_ST_TR_ERR        BIT(16)
  33 #define NRM_TX_ST_TXDONE        BIT(15)
  34 #define NRM_TX_ST_TMREXP        BIT(14)
  35
  36 #define NETSEC_REG_NRM_RX_STATUS                0x440
  37 #define NETSEC_REG_NRM_RX_INTEN                 0x444
  38 #define NETSEC_REG_NRM_RX_INTEN_SET             0x468
  39 #define NETSEC_REG_NRM_RX_INTEN_CLR             0x46c
  40 #define NRM_RX_ST_RC_ERR        BIT(16)
  41 #define NRM_RX_ST_PKTCNT        BIT(15)
  42 #define NRM_RX_ST_TMREXP        BIT(14)
  43
  44 #define NETSEC_REG_PKT_CMD_BUF                  0xd0
  45
  46 #define NETSEC_REG_CLK_EN                       0x100
  47
  48 #define NETSEC_REG_PKT_CTRL                     0x140
  49
  50 #define NETSEC_REG_DMA_TMR_CTRL                 0x20c
  51 #define NETSEC_REG_F_TAIKI_MC_VER               0x22c
  52 #define NETSEC_REG_F_TAIKI_VER                  0x230
  53 #define NETSEC_REG_DMA_HM_CTRL                  0x214
  54 #define NETSEC_REG_DMA_MH_CTRL                  0x220
  55 #define NETSEC_REG_ADDR_DIS_CORE                0x218
  56 #define NETSEC_REG_DMAC_HM_CMD_BUF              0x210
  57 #define NETSEC_REG_DMAC_MH_CMD_BUF              0x21c
  58
  59 #define NETSEC_REG_NRM_TX_PKTCNT                0x410
  60
  61 #define NETSEC_REG_NRM_TX_DONE_PKTCNT           0x414
  62 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT     0x418
  63
  64 #define NETSEC_REG_NRM_TX_TMR                   0x41c
  65
  66 #define NETSEC_REG_NRM_RX_PKTCNT                0x454
  67 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT          0x458
  68 #define NETSEC_REG_NRM_TX_TXINT_TMR             0x420
  69 #define NETSEC_REG_NRM_RX_RXINT_TMR             0x460
  70
  71 #define NETSEC_REG_NRM_RX_TMR                   0x45c
  72
  73 #define NETSEC_REG_NRM_TX_DESC_START_UP         0x434
  74 #define NETSEC_REG_NRM_TX_DESC_START_LW         0x408
  75 #define NETSEC_REG_NRM_RX_DESC_START_UP         0x474
  76 #define NETSEC_REG_NRM_RX_DESC_START_LW         0x448
  77
  78 #define NETSEC_REG_NRM_TX_CONFIG                0x430
  79 #define NETSEC_REG_NRM_RX_CONFIG                0x470
  80
  81 #define MAC_REG_STATUS                          0x1024
  82 #define MAC_REG_DATA                            0x11c0
  83 #define MAC_REG_CMD                             0x11c4
  84 #define MAC_REG_FLOW_TH                         0x11cc
  85 #define MAC_REG_INTF_SEL                        0x11d4
  86 #define MAC_REG_DESC_INIT                       0x11fc
  87 #define MAC_REG_DESC_SOFT_RST                   0x1204
  88 #define NETSEC_REG_MODE_TRANS_COMP_STATUS       0x500
  89
  90 #define GMAC_REG_MCR                            0x0000
  91 #define GMAC_REG_MFFR                           0x0004
  92 #define GMAC_REG_GAR                            0x0010
  93 #define GMAC_REG_GDR                            0x0014
  94 #define GMAC_REG_FCR                            0x0018
  95 #define GMAC_REG_BMR                            0x1000
  96 #define GMAC_REG_RDLAR                          0x100c
  97 #define GMAC_REG_TDLAR                          0x1010
  98 #define GMAC_REG_OMR                            0x1018
  99
 100 #define MHZ(n)          ((n) * 1000 * 1000)
 101
 102 #define NETSEC_TX_SHIFT_OWN_FIELD               31
 103 #define NETSEC_TX_SHIFT_LD_FIELD                30
 104 #define NETSEC_TX_SHIFT_DRID_FIELD              24
 105 #define NETSEC_TX_SHIFT_PT_FIELD                21
 106 #define NETSEC_TX_SHIFT_TDRID_FIELD             16
 107 #define NETSEC_TX_SHIFT_CC_FIELD                15
 108 #define NETSEC_TX_SHIFT_FS_FIELD                9
 109 #define NETSEC_TX_LAST                          8
 110 #define NETSEC_TX_SHIFT_CO                      7
 111 #define NETSEC_TX_SHIFT_SO                      6
 112 #define NETSEC_TX_SHIFT_TRS_FIELD               4
 113
 114 #define NETSEC_RX_PKT_OWN_FIELD                 31
 115 #define NETSEC_RX_PKT_LD_FIELD                  30
 116 #define NETSEC_RX_PKT_SDRID_FIELD               24
 117 #define NETSEC_RX_PKT_FR_FIELD                  23
 118 #define NETSEC_RX_PKT_ER_FIELD                  21
 119 #define NETSEC_RX_PKT_ERR_FIELD                 16
 120 #define NETSEC_RX_PKT_TDRID_FIELD               12
 121 #define NETSEC_RX_PKT_FS_FIELD                  9
 122 #define NETSEC_RX_PKT_LS_FIELD                  8
 123 #define NETSEC_RX_PKT_CO_FIELD                  6
 124
 125 #define NETSEC_RX_PKT_ERR_MASK                  3
 126
 127 #define NETSEC_MAX_TX_PKT_LEN                   1518
 128 #define NETSEC_MAX_TX_JUMBO_PKT_LEN             9018
 129
 130 #define NETSEC_RING_GMAC                        15
 131 #define NETSEC_RING_MAX                         2
 132
 133 #define NETSEC_TCP_SEG_LEN_MAX                  1460
 134 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX            8960
 135
 136 #define NETSEC_RX_CKSUM_NOTAVAIL                0
 137 #define NETSEC_RX_CKSUM_OK                      1
 138 #define NETSEC_RX_CKSUM_NG                      2
 139
 140 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END        BIT(20)
 141 #define NETSEC_IRQ_TRANSITION_COMPLETE          BIT(4)
 142
 143 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T          BIT(20)
 144 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N          BIT(19)
 145
 146 #define NETSEC_INT_PKTCNT_MAX                   2047
 147
 148 #define NETSEC_FLOW_START_TH_MAX                95
 149 #define NETSEC_FLOW_STOP_TH_MAX                 95
 150 #define NETSEC_FLOW_PAUSE_TIME_MIN              5
 151
 152 #define NETSEC_CLK_EN_REG_DOM_ALL               0x3f
 153
 154 #define NETSEC_PKT_CTRL_REG_MODE_NRM            BIT(28)
 155 #define NETSEC_PKT_CTRL_REG_EN_JUMBO            BIT(27)
 156 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER       BIT(3)
 157 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE   BIT(2)
 158 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER           BIT(1)
 159 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH        BIT(0)
 160
 161 #define NETSEC_CLK_EN_REG_DOM_G                 BIT(5)
 162 #define NETSEC_CLK_EN_REG_DOM_C                 BIT(1)
 163 #define NETSEC_CLK_EN_REG_DOM_D                 BIT(0)
 164
 165 #define NETSEC_COM_INIT_REG_DB                  BIT(2)
 166 #define NETSEC_COM_INIT_REG_CLS                 BIT(1)
 167 #define NETSEC_COM_INIT_REG_ALL                 (NETSEC_COM_INIT_REG_CLS | \
 168                                                  NETSEC_COM_INIT_REG_DB)
 169
 170 #define NETSEC_SOFT_RST_REG_RESET               0
 171 #define NETSEC_SOFT_RST_REG_RUN                 BIT(31)
 172
 173 #define NETSEC_DMA_CTRL_REG_STOP                1
 174 #define MH_CTRL__MODE_TRANS                     BIT(20)
 175
 176 #define NETSEC_GMAC_CMD_ST_READ                 0
 177 #define NETSEC_GMAC_CMD_ST_WRITE                BIT(28)
 178 #define NETSEC_GMAC_CMD_ST_BUSY                 BIT(31)
 179
 180 #define NETSEC_GMAC_BMR_REG_COMMON              0x00412080
 181 #define NETSEC_GMAC_BMR_REG_RESET               0x00020181
 182 #define NETSEC_GMAC_BMR_REG_SWR                 0x00000001
 183
 184 #define NETSEC_GMAC_OMR_REG_ST                  BIT(13)
 185 #define NETSEC_GMAC_OMR_REG_SR                  BIT(1)
 186
 187 #define NETSEC_GMAC_MCR_REG_IBN                 BIT(30)
 188 #define NETSEC_GMAC_MCR_REG_CST                 BIT(25)
 189 #define NETSEC_GMAC_MCR_REG_JE                  BIT(20)
 190 #define NETSEC_MCR_PS                           BIT(15)
 191 #define NETSEC_GMAC_MCR_REG_FES                 BIT(14)
 192 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON  0x0000280c
 193 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON  0x0001a00c
 194
 195 #define NETSEC_FCR_RFE                          BIT(2)
 196 #define NETSEC_FCR_TFE                          BIT(1)
 197
 198 #define NETSEC_GMAC_GAR_REG_GW                  BIT(1)
 199 #define NETSEC_GMAC_GAR_REG_GB                  BIT(0)
 200
 201 #define NETSEC_GMAC_GAR_REG_SHIFT_PA            11
 202 #define NETSEC_GMAC_GAR_REG_SHIFT_GR            6
 203 #define GMAC_REG_SHIFT_CR_GAR                   2
 204
 205 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ        2
 206 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ        3
 207 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ       0
 208 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ      1
 209 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ      4
 210 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ      5
 211
 212 #define NETSEC_GMAC_RDLAR_REG_COMMON            0x18000
 213 #define NETSEC_GMAC_TDLAR_REG_COMMON            0x1c000
 214
 215 #define NETSEC_REG_NETSEC_VER_F_TAIKI           0x50000
 216
 217 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP      BIT(31)
 218 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST      BIT(30)
 219 #define NETSEC_REG_DESC_TMR_MODE                4
 220 #define NETSEC_REG_DESC_ENDIAN                  0
 221
 222 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST       1
 223 #define NETSEC_MAC_DESC_INIT_REG_INIT           1
 224
 225 #define NETSEC_EEPROM_MAC_ADDRESS               0x00
 226 #define NETSEC_EEPROM_HM_ME_ADDRESS_H           0x08
 227 #define NETSEC_EEPROM_HM_ME_ADDRESS_L           0x0C
 228 #define NETSEC_EEPROM_HM_ME_SIZE                0x10
 229 #define NETSEC_EEPROM_MH_ME_ADDRESS_H           0x14
 230 #define NETSEC_EEPROM_MH_ME_ADDRESS_L           0x18
 231 #define NETSEC_EEPROM_MH_ME_SIZE                0x1C
 232 #define NETSEC_EEPROM_PKT_ME_ADDRESS            0x20
 233 #define NETSEC_EEPROM_PKT_ME_SIZE               0x24
 234
 235 #define DESC_NUM        256
 236
 237 #define DESC_SZ sizeof(struct netsec_de)
 238
 239 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x)        ((x) & 0xffff0000)
 240
 241 enum ring_id {
 242         NETSEC_RING_TX = 0,
 243         NETSEC_RING_RX
 244 };
 245
 246 struct netsec_desc {
 247         struct sk_buff *skb;
 248         dma_addr_t dma_addr;
 249         void *addr;
 250         u16 len;
 251 };
 252
 253 struct netsec_desc_ring {
 254         dma_addr_t desc_dma;
 255         struct netsec_desc *desc;
 256         void *vaddr;
 257         u16 pkt_cnt;
 258         u16 head, tail;
 259 };
 260
 261 struct netsec_priv {
 262         struct netsec_desc_ring desc_ring[NETSEC_RING_MAX];
 263         struct ethtool_coalesce et_coalesce;
 264         spinlock_t reglock; /* protect reg access */
 265         struct napi_struct napi;
 266         phy_interface_t phy_interface;
 267         struct net_device *ndev;
 268         struct device_node *phy_np;
 269         struct phy_device *phydev;
 270         struct mii_bus *mii_bus;
 271         void __iomem *ioaddr;
 272         void __iomem *eeprom_base;
 273         struct device *dev;
 274         struct clk *clk;
 275         u32 msg_enable;
 276         u32 freq;
 277         u32 phy_addr;
 278         bool rx_cksum_offload_flag;
 279 };
 280
 281 struct netsec_de { /* Netsec Descriptor layout */
 282         u32 attr;
 283         u32 data_buf_addr_up;
 284         u32 data_buf_addr_lw;
 285         u32 buf_len_info;
 286 };
 287
 288 struct netsec_tx_pkt_ctrl {
 289         u16 tcp_seg_len;
 290         bool tcp_seg_offload_flag;
 291         bool cksum_offload_flag;
 292 };
 293
 294 struct netsec_rx_pkt_info {
 295         int rx_cksum_result;
 296         int err_code;
 297         bool err_flag;
 298 };
 299
 300 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val)
 301 {
 302         writel(val, priv->ioaddr + reg_addr);
 303 }
 304
 305 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr)
 306 {
 307         return readl(priv->ioaddr + reg_addr);
 308 }
 309
 310 /************* MDIO BUS OPS FOLLOW *************/
 311
 312 #define TIMEOUT_SPINS_MAC               1000
 313 #define TIMEOUT_SECONDARY_MS_MAC        100
 314
 315 static u32 netsec_clk_type(u32 freq)
 316 {
 317         if (freq < MHZ(35))
 318                 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
 319         if (freq < MHZ(60))
 320                 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
 321         if (freq < MHZ(100))
 322                 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
 323         if (freq < MHZ(150))
 324                 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
 325         if (freq < MHZ(250))
 326                 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
 327
 328         return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
 329 }
 330
 331 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
 332 {
 333         u32 timeout = TIMEOUT_SPINS_MAC;
 334
 335         while (--timeout && netsec_read(priv, addr) & mask)
 336                 cpu_relax();
 337         if (timeout)
 338                 return 0;
 339
 340         timeout = TIMEOUT_SECONDARY_MS_MAC;
 341         while (--timeout && netsec_read(priv, addr) & mask)
 342                 usleep_range(1000, 2000);
 343
 344         if (timeout)
 345                 return 0;
 346
 347         netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
 348
 349         return -ETIMEDOUT;
 350 }
 351
 352 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value)
 353 {
 354         netsec_write(priv, MAC_REG_DATA, value);
 355         netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
 356         return netsec_wait_while_busy(priv,
 357                                       MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
 358 }
 359
 360 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read)
 361 {
 362         int ret;
 363
 364         netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
 365         ret = netsec_wait_while_busy(priv,
 366                                      MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
 367         if (ret)
 368                 return ret;
 369
 370         *read = netsec_read(priv, MAC_REG_DATA);
 371
 372         return 0;
 373 }
 374
 375 static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
 376                                       u32 addr, u32 mask)
 377 {
 378         u32 timeout = TIMEOUT_SPINS_MAC;
 379         int ret, data;
 380
 381         do {
 382                 ret = netsec_mac_read(priv, addr, &data);
 383                 if (ret)
 384                         break;
 385                 cpu_relax();
 386         } while (--timeout && (data & mask));
 387
 388         if (timeout)
 389                 return 0;
 390
 391         timeout = TIMEOUT_SECONDARY_MS_MAC;
 392         do {
 393                 usleep_range(1000, 2000);
 394
 395                 ret = netsec_mac_read(priv, addr, &data);
 396                 if (ret)
 397                         break;
 398                 cpu_relax();
 399         } while (--timeout && (data & mask));
 400
 401         if (timeout && !ret)
 402                 return 0;
 403
 404         netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
 405
 406         return -ETIMEDOUT;
 407 }
 408
 409 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
 410 {
 411         struct phy_device *phydev = priv->ndev->phydev;
 412         u32 value = 0;
 413
 414         value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
 415                                  NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
 416
 417         if (phydev->speed != SPEED_1000)
 418                 value |= NETSEC_MCR_PS;
 419
 420         if (priv->phy_interface != PHY_INTERFACE_MODE_GMII &&
 421             phydev->speed == SPEED_100)
 422                 value |= NETSEC_GMAC_MCR_REG_FES;
 423
 424         value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
 425
 426         if (phy_interface_mode_is_rgmii(priv->phy_interface))
 427                 value |= NETSEC_GMAC_MCR_REG_IBN;
 428
 429         if (netsec_mac_write(priv, GMAC_REG_MCR, value))
 430                 return -ETIMEDOUT;
 431
 432         return 0;
 433 }
 434
 435 static int netsec_phy_write(struct mii_bus *bus,
 436                             int phy_addr, int reg, u16 val)
 437 {
 438         struct netsec_priv *priv = bus->priv;
 439
 440         if (netsec_mac_write(priv, GMAC_REG_GDR, val))
 441                 return -ETIMEDOUT;
 442         if (netsec_mac_write(priv, GMAC_REG_GAR,
 443                              phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
 444                              reg << NETSEC_GMAC_GAR_REG_SHIFT_GR |
 445                              NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
 446                              (netsec_clk_type(priv->freq) <<
 447                               GMAC_REG_SHIFT_CR_GAR)))
 448                 return -ETIMEDOUT;
 449
 450         return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
 451                                           NETSEC_GMAC_GAR_REG_GB);
 452 }
 453
 454 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
 455 {
 456         struct netsec_priv *priv = bus->priv;
 457         u32 data;
 458         int ret;
 459
 460         if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
 461                              phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
 462                              reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
 463                              (netsec_clk_type(priv->freq) <<
 464                               GMAC_REG_SHIFT_CR_GAR)))
 465                 return -ETIMEDOUT;
 466
 467         ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
 468                                          NETSEC_GMAC_GAR_REG_GB);
 469         if (ret)
 470                 return ret;
 471
 472         ret = netsec_mac_read(priv, GMAC_REG_GDR, &data);
 473         if (ret)
 474                 return ret;
 475
 476         return data;
 477 }
 478
 479 /************* ETHTOOL_OPS FOLLOW *************/
 480
 481 static void netsec_et_get_drvinfo(struct net_device *net_device,
 482                                   struct ethtool_drvinfo *info)
 483 {
 484         strlcpy(info->driver, "netsec", sizeof(info->driver));
 485         strlcpy(info->bus_info, dev_name(net_device->dev.parent),
 486                 sizeof(info->bus_info));
 487 }
 488
 489 static int netsec_et_get_coalesce(struct net_device *net_device,
 490                                   struct ethtool_coalesce *et_coalesce)
 491 {
 492         struct netsec_priv *priv = netdev_priv(net_device);
 493
 494         *et_coalesce = priv->et_coalesce;
 495
 496         return 0;
 497 }
 498
 499 static int netsec_et_set_coalesce(struct net_device *net_device,
 500                                   struct ethtool_coalesce *et_coalesce)
 501 {
 502         struct netsec_priv *priv = netdev_priv(net_device);
 503
 504         priv->et_coalesce = *et_coalesce;
 505
 506         if (priv->et_coalesce.tx_coalesce_usecs < 50)
 507                 priv->et_coalesce.tx_coalesce_usecs = 50;
 508         if (priv->et_coalesce.tx_max_coalesced_frames < 1)
 509                 priv->et_coalesce.tx_max_coalesced_frames = 1;
 510
 511         netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,
 512                      priv->et_coalesce.tx_max_coalesced_frames);
 513         netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,
 514                      priv->et_coalesce.tx_coalesce_usecs);
 515         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);
 516         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);
 517
 518         if (priv->et_coalesce.rx_coalesce_usecs < 50)
 519                 priv->et_coalesce.rx_coalesce_usecs = 50;
 520         if (priv->et_coalesce.rx_max_coalesced_frames < 1)
 521                 priv->et_coalesce.rx_max_coalesced_frames = 1;
 522
 523         netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,
 524                      priv->et_coalesce.rx_max_coalesced_frames);
 525         netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,
 526                      priv->et_coalesce.rx_coalesce_usecs);
 527         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);
 528         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);
 529
 530         return 0;
 531 }
 532
 533 static u32 netsec_et_get_msglevel(struct net_device *dev)
 534 {
 535         struct netsec_priv *priv = netdev_priv(dev);
 536
 537         return priv->msg_enable;
 538 }
 539
 540 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum)
 541 {
 542         struct netsec_priv *priv = netdev_priv(dev);
 543
 544         priv->msg_enable = datum;
 545 }
 546
 547 static const struct ethtool_ops netsec_ethtool_ops = {
 548         .get_drvinfo            = netsec_et_get_drvinfo,
 549         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
 550         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
 551         .get_link               = ethtool_op_get_link,
 552         .get_coalesce           = netsec_et_get_coalesce,
 553         .set_coalesce           = netsec_et_set_coalesce,
 554         .get_msglevel           = netsec_et_get_msglevel,
 555         .set_msglevel           = netsec_et_set_msglevel,
 556 };
 557
 558 /************* NETDEV_OPS FOLLOW *************/
 559
 560 static struct sk_buff *netsec_alloc_skb(struct netsec_priv *priv,
 561                                         struct netsec_desc *desc)
 562 {
 563         struct sk_buff *skb;
 564
 565         if (device_get_dma_attr(priv->dev) == DEV_DMA_COHERENT) {
 566                 skb = netdev_alloc_skb_ip_align(priv->ndev, desc->len);
 567         } else {
 568                 desc->len = L1_CACHE_ALIGN(desc->len);
 569                 skb = netdev_alloc_skb(priv->ndev, desc->len);
 570         }
 571         if (!skb)
 572                 return NULL;
 573
 574         desc->addr = skb->data;
 575         desc->dma_addr = dma_map_single(priv->dev, desc->addr, desc->len,
 576                                         DMA_FROM_DEVICE);
 577         if (dma_mapping_error(priv->dev, desc->dma_addr)) {
 578                 dev_kfree_skb_any(skb);
 579                 return NULL;
 580         }
 581         return skb;
 582 }
 583
 584 static void netsec_set_rx_de(struct netsec_priv *priv,
 585                              struct netsec_desc_ring *dring, u16 idx,
 586                              const struct netsec_desc *desc,
 587                              struct sk_buff *skb)
 588 {
 589         struct netsec_de *de = dring->vaddr + DESC_SZ * idx;
 590         u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
 591                    (1 << NETSEC_RX_PKT_FS_FIELD) |
 592                    (1 << NETSEC_RX_PKT_LS_FIELD);
 593
 594         if (idx == DESC_NUM - 1)
 595                 attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
 596
 597         de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
 598         de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
 599         de->buf_len_info = desc->len;
 600         de->attr = attr;
 601         dma_wmb();
 602
 603         dring->desc[idx].dma_addr = desc->dma_addr;
 604         dring->desc[idx].addr = desc->addr;
 605         dring->desc[idx].len = desc->len;
 606         dring->desc[idx].skb = skb;
 607 }
 608
 609 static struct sk_buff *netsec_get_rx_de(struct netsec_priv *priv,
 610                                         struct netsec_desc_ring *dring,
 611                                         u16 idx,
 612                                         struct netsec_rx_pkt_info *rxpi,
 613                                         struct netsec_desc *desc, u16 *len)
 614 {
 615         struct netsec_de de = {};
 616
 617         memcpy(&de, dring->vaddr + DESC_SZ * idx, DESC_SZ);
 618
 619         *len = de.buf_len_info >> 16;
 620
 621         rxpi->err_flag = (de.attr >> NETSEC_RX_PKT_ER_FIELD) & 1;
 622         rxpi->rx_cksum_result = (de.attr >> NETSEC_RX_PKT_CO_FIELD) & 3;
 623         rxpi->err_code = (de.attr >> NETSEC_RX_PKT_ERR_FIELD) &
 624                                                         NETSEC_RX_PKT_ERR_MASK;
 625         *desc = dring->desc[idx];
 626         return desc->skb;
 627 }
 628
 629 static struct sk_buff *netsec_get_rx_pkt_data(struct netsec_priv *priv,
 630                                               struct netsec_rx_pkt_info *rxpi,
 631                                               struct netsec_desc *desc,
 632                                               u16 *len)
 633 {
 634         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
 635         struct sk_buff *tmp_skb, *skb = NULL;
 636         struct netsec_desc td;
 637         int tail;
 638
 639         *rxpi = (struct netsec_rx_pkt_info){};
 640
 641         td.len = priv->ndev->mtu + 22;
 642
 643         tmp_skb = netsec_alloc_skb(priv, &td);
 644
 645         tail = dring->tail;
 646
 647         if (!tmp_skb) {
 648                 netsec_set_rx_de(priv, dring, tail, &dring->desc[tail],
 649                                  dring->desc[tail].skb);
 650         } else {
 651                 skb = netsec_get_rx_de(priv, dring, tail, rxpi, desc, len);
 652                 netsec_set_rx_de(priv, dring, tail, &td, tmp_skb);
 653         }
 654
 655         /* move tail ahead */
 656         dring->tail = (dring->tail + 1) % DESC_NUM;
 657
 658         return skb;
 659 }
 660
 661 static int netsec_clean_tx_dring(struct netsec_priv *priv, int budget)
 662 {
 663         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
 664         unsigned int pkts, bytes;
 665
 666         dring->pkt_cnt += netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
 667
 668         if (dring->pkt_cnt < budget)
 669                 budget = dring->pkt_cnt;
 670
 671         pkts = 0;
 672         bytes = 0;
 673
 674         while (pkts < budget) {
 675                 struct netsec_desc *desc;
 676                 struct netsec_de *entry;
 677                 int tail, eop;
 678
 679                 tail = dring->tail;
 680
 681                 /* move tail ahead */
 682                 dring->tail = (tail + 1) % DESC_NUM;
 683
 684                 desc = &dring->desc[tail];
 685                 entry = dring->vaddr + DESC_SZ * tail;
 686
 687                 eop = (entry->attr >> NETSEC_TX_LAST) & 1;
 688
 689                 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
 690                                  DMA_TO_DEVICE);
 691                 if (eop) {
 692                         pkts++;
 693                         bytes += desc->skb->len;
 694                         dev_kfree_skb(desc->skb);
 695                 }
 696                 *desc = (struct netsec_desc){};
 697         }
 698         dring->pkt_cnt -= budget;
 699
 700         priv->ndev->stats.tx_packets += budget;
 701         priv->ndev->stats.tx_bytes += bytes;
 702
 703         netdev_completed_queue(priv->ndev, budget, bytes);
 704
 705         return budget;
 706 }
 707
 708 static int netsec_process_tx(struct netsec_priv *priv, int budget)
 709 {
 710         struct net_device *ndev = priv->ndev;
 711         int new, done = 0;
 712
 713         do {
 714                 new = netsec_clean_tx_dring(priv, budget);
 715                 done += new;
 716                 budget -= new;
 717         } while (new);
 718
 719         if (done && netif_queue_stopped(ndev))
 720                 netif_wake_queue(ndev);
 721
 722         return done;
 723 }
 724
 725 static int netsec_process_rx(struct netsec_priv *priv, int budget)
 726 {
 727         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
 728         struct net_device *ndev = priv->ndev;
 729         struct netsec_rx_pkt_info rx_info;
 730         int done = 0;
 731         struct netsec_desc desc;
 732         struct sk_buff *skb;
 733         u16 len;
 734
 735         while (done < budget) {
 736                 u16 idx = dring->tail;
 737                 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx);
 738
 739                 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) {
 740                         /* reading the register clears the irq */
 741                         netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT);
 742                         break;
 743                 }
 744
 745                 /* This  barrier is needed to keep us from reading
 746                  * any other fields out of the netsec_de until we have
 747                  * verified the descriptor has been written back
 748                  */
 749                 dma_rmb();
 750                 done++;
 751                 skb = netsec_get_rx_pkt_data(priv, &rx_info, &desc, &len);
 752                 if (unlikely(!skb) || rx_info.err_flag) {
 753                         netif_err(priv, drv, priv->ndev,
 754                                   "%s: rx fail err(%d)\n",
 755                                   __func__, rx_info.err_code);
 756                         ndev->stats.rx_dropped++;
 757                         continue;
 758                 }
 759
 760                 dma_unmap_single(priv->dev, desc.dma_addr, desc.len,
 761                                  DMA_FROM_DEVICE);
 762                 skb_put(skb, len);
 763                 skb->protocol = eth_type_trans(skb, priv->ndev);
 764
 765                 if (priv->rx_cksum_offload_flag &&
 766                     rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK)
 767                         skb->ip_summed = CHECKSUM_UNNECESSARY;
 768
 769                 if (napi_gro_receive(&priv->napi, skb) != GRO_DROP) {
 770                         ndev->stats.rx_packets++;
 771                         ndev->stats.rx_bytes += len;
 772                 }
 773         }
 774
 775         return done;
 776 }
 777
 778 static int netsec_napi_poll(struct napi_struct *napi, int budget)
 779 {
 780         struct netsec_priv *priv;
 781         int tx, rx, done, todo;
 782
 783         priv = container_of(napi, struct netsec_priv, napi);
 784
 785         todo = budget;
 786         do {
 787                 if (!todo)
 788                         break;
 789
 790                 tx = netsec_process_tx(priv, todo);
 791                 todo -= tx;
 792
 793                 if (!todo)
 794                         break;
 795
 796                 rx = netsec_process_rx(priv, todo);
 797                 todo -= rx;
 798         } while (rx || tx);
 799
 800         done = budget - todo;
 801
 802         if (done < budget && napi_complete_done(napi, done)) {
 803                 unsigned long flags;
 804
 805                 spin_lock_irqsave(&priv->reglock, flags);
 806                 netsec_write(priv, NETSEC_REG_INTEN_SET,
 807                              NETSEC_IRQ_RX | NETSEC_IRQ_TX);
 808                 spin_unlock_irqrestore(&priv->reglock, flags);
 809         }
 810
 811         return done;
 812 }
 813
 814 static void netsec_set_tx_de(struct netsec_priv *priv,
 815                              struct netsec_desc_ring *dring,
 816                              const struct netsec_tx_pkt_ctrl *tx_ctrl,
 817                              const struct netsec_desc *desc,
 818                              struct sk_buff *skb)
 819 {
 820         int idx = dring->head;
 821         struct netsec_de *de;
 822         u32 attr;
 823
 824         de = dring->vaddr + (DESC_SZ * idx);
 825
 826         attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
 827                (1 << NETSEC_TX_SHIFT_PT_FIELD) |
 828                (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
 829                (1 << NETSEC_TX_SHIFT_FS_FIELD) |
 830                (1 << NETSEC_TX_LAST) |
 831                (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) |
 832                (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) |
 833                (1 << NETSEC_TX_SHIFT_TRS_FIELD);
 834         if (idx == DESC_NUM - 1)
 835                 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD);
 836
 837         de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
 838         de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
 839         de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len;
 840         de->attr = attr;
 841         dma_wmb();
 842
 843         dring->desc[idx] = *desc;
 844         dring->desc[idx].skb = skb;
 845
 846         /* move head ahead */
 847         dring->head = (dring->head + 1) % DESC_NUM;
 848 }
 849
 850 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb,
 851                                             struct net_device *ndev)
 852 {
 853         struct netsec_priv *priv = netdev_priv(ndev);
 854         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
 855         struct netsec_tx_pkt_ctrl tx_ctrl = {};
 856         struct netsec_desc tx_desc;
 857         u16 tso_seg_len = 0;
 858         int filled;
 859
 860         /* differentiate between full/emtpy ring */
 861         if (dring->head >= dring->tail)
 862                 filled = dring->head - dring->tail;
 863         else
 864                 filled = dring->head + DESC_NUM - dring->tail;
 865
 866         if (DESC_NUM - filled < 2) { /* if less than 2 available */
 867                 netif_err(priv, drv, priv->ndev, "%s: TxQFull!\n", __func__);
 868                 netif_stop_queue(priv->ndev);
 869                 dma_wmb();
 870                 return NETDEV_TX_BUSY;
 871         }
 872
 873         if (skb->ip_summed == CHECKSUM_PARTIAL)
 874                 tx_ctrl.cksum_offload_flag = true;
 875
 876         if (skb_is_gso(skb))
 877                 tso_seg_len = skb_shinfo(skb)->gso_size;
 878
 879         if (tso_seg_len > 0) {
 880                 if (skb->protocol == htons(ETH_P_IP)) {
 881                         ip_hdr(skb)->tot_len = 0;
 882                         tcp_hdr(skb)->check =
 883                                 ~tcp_v4_check(0, ip_hdr(skb)->saddr,
 884                                               ip_hdr(skb)->daddr, 0);
 885                 } else {
 886                         ipv6_hdr(skb)->payload_len = 0;
 887                         tcp_hdr(skb)->check =
 888                                 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
 889                                                  &ipv6_hdr(skb)->daddr,
 890                                                  0, IPPROTO_TCP, 0);
 891                 }
 892
 893                 tx_ctrl.tcp_seg_offload_flag = true;
 894                 tx_ctrl.tcp_seg_len = tso_seg_len;
 895         }
 896
 897         tx_desc.dma_addr = dma_map_single(priv->dev, skb->data,
 898                                           skb_headlen(skb), DMA_TO_DEVICE);
 899         if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) {
 900                 netif_err(priv, drv, priv->ndev,
 901                           "%s: DMA mapping failed\n", __func__);
 902                 ndev->stats.tx_dropped++;
 903                 dev_kfree_skb_any(skb);
 904                 return NETDEV_TX_OK;
 905         }
 906         tx_desc.addr = skb->data;
 907         tx_desc.len = skb_headlen(skb);
 908
 909         skb_tx_timestamp(skb);
 910         netdev_sent_queue(priv->ndev, skb->len);
 911
 912         netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb);
 913         netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
 914
 915         return NETDEV_TX_OK;
 916 }
 917
 918 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id)
 919 {
 920         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 921         struct netsec_desc *desc;
 922         u16 idx;
 923
 924         if (!dring->vaddr || !dring->desc)
 925                 return;
 926
 927         for (idx = 0; idx < DESC_NUM; idx++) {
 928                 desc = &dring->desc[idx];
 929                 if (!desc->addr)
 930                         continue;
 931
 932                 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
 933                                  id == NETSEC_RING_RX ? DMA_FROM_DEVICE :
 934                                                               DMA_TO_DEVICE);
 935                 dev_kfree_skb(desc->skb);
 936         }
 937
 938         memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM);
 939         memset(dring->vaddr, 0, DESC_SZ * DESC_NUM);
 940
 941         dring->head = 0;
 942         dring->tail = 0;
 943         dring->pkt_cnt = 0;
 944 }
 945
 946 static void netsec_free_dring(struct netsec_priv *priv, int id)
 947 {
 948         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 949
 950         if (dring->vaddr) {
 951                 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM,
 952                                   dring->vaddr, dring->desc_dma);
 953                 dring->vaddr = NULL;
 954         }
 955
 956         kfree(dring->desc);
 957         dring->desc = NULL;
 958 }
 959
 960 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
 961 {
 962         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 963         int ret = 0;
 964
 965         dring->vaddr = dma_zalloc_coherent(priv->dev, DESC_SZ * DESC_NUM,
 966                                            &dring->desc_dma, GFP_KERNEL);
 967         if (!dring->vaddr) {
 968                 ret = -ENOMEM;
 969                 goto err;
 970         }
 971
 972         dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL);
 973         if (!dring->desc) {
 974                 ret = -ENOMEM;
 975                 goto err;
 976         }
 977
 978         return 0;
 979 err:
 980         netsec_free_dring(priv, id);
 981
 982         return ret;
 983 }
 984
 985 static int netsec_setup_rx_dring(struct netsec_priv *priv)
 986 {
 987         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
 988         struct netsec_desc desc;
 989         struct sk_buff *skb;
 990         int n;
 991
 992         desc.len = priv->ndev->mtu + 22;
 993
 994         for (n = 0; n < DESC_NUM; n++) {
 995                 skb = netsec_alloc_skb(priv, &desc);
 996                 if (!skb) {
 997                         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
 998                         return -ENOMEM;
 999                 }
1000                 netsec_set_rx_de(priv, dring, n, &desc, skb);
1001         }
1002
1003         return 0;
1004 }
1005
1006 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
1007                                            u32 addr_h, u32 addr_l, u32 size)
1008 {
1009         u64 base = (u64)addr_h << 32 | addr_l;
1010         void __iomem *ucode;
1011         u32 i;
1012
1013         ucode = ioremap(base, size * sizeof(u32));
1014         if (!ucode)
1015                 return -ENOMEM;
1016
1017         for (i = 0; i < size; i++)
1018                 netsec_write(priv, reg, readl(ucode + i * 4));
1019
1020         iounmap(ucode);
1021         return 0;
1022 }
1023
1024 static int netsec_netdev_load_microcode(struct netsec_priv *priv)
1025 {
1026         u32 addr_h, addr_l, size;
1027         int err;
1028
1029         addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H);
1030         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L);
1031         size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE);
1032         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
1033                                               addr_h, addr_l, size);
1034         if (err)
1035                 return err;
1036
1037         addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H);
1038         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L);
1039         size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE);
1040         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
1041                                               addr_h, addr_l, size);
1042         if (err)
1043                 return err;
1044
1045         addr_h = 0;
1046         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS);
1047         size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE);
1048         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
1049                                               addr_h, addr_l, size);
1050         if (err)
1051                 return err;
1052
1053         return 0;
1054 }
1055
1056 static int netsec_reset_hardware(struct netsec_priv *priv,
1057                                  bool load_ucode)
1058 {
1059         u32 value;
1060         int err;
1061
1062         /* stop DMA engines */
1063         if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) {
1064                 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,
1065                              NETSEC_DMA_CTRL_REG_STOP);
1066                 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,
1067                              NETSEC_DMA_CTRL_REG_STOP);
1068
1069                 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) &
1070                        NETSEC_DMA_CTRL_REG_STOP)
1071                         cpu_relax();
1072
1073                 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) &
1074                        NETSEC_DMA_CTRL_REG_STOP)
1075                         cpu_relax();
1076         }
1077
1078         netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
1079         netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
1080         netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
1081
1082         while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0)
1083                 cpu_relax();
1084
1085         /* set desc_start addr */
1086         netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
1087                      upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1088         netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
1089                      lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1090
1091         netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
1092                      upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1093         netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
1094                      lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1095
1096         /* set normal tx dring ring config */
1097         netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,
1098                      1 << NETSEC_REG_DESC_ENDIAN);
1099         netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,
1100                      1 << NETSEC_REG_DESC_ENDIAN);
1101
1102         if (load_ucode) {
1103                 err = netsec_netdev_load_microcode(priv);
1104                 if (err) {
1105                         netif_err(priv, probe, priv->ndev,
1106                                   "%s: failed to load microcode (%d)\n",
1107                                   __func__, err);
1108                         return err;
1109                 }
1110         }
1111
1112         /* start DMA engines */
1113         netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
1114         netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
1115
1116         usleep_range(1000, 2000);
1117
1118         if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) &
1119               NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) {
1120                 netif_err(priv, probe, priv->ndev,
1121                           "microengine start failed\n");
1122                 return -ENXIO;
1123         }
1124         netsec_write(priv, NETSEC_REG_TOP_STATUS,
1125                      NETSEC_TOP_IRQ_REG_CODE_LOAD_END);
1126
1127         value = NETSEC_PKT_CTRL_REG_MODE_NRM;
1128         if (priv->ndev->mtu > ETH_DATA_LEN)
1129                 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO;
1130
1131         /* change to normal mode */
1132         netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
1133         netsec_write(priv, NETSEC_REG_PKT_CTRL, value);
1134
1135         while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
1136                 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0)
1137                 cpu_relax();
1138
1139         /* clear any pending EMPTY/ERR irq status */
1140         netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
1141
1142         /* Disable TX & RX intr */
1143         netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1144
1145         return 0;
1146 }
1147
1148 static int netsec_start_gmac(struct netsec_priv *priv)
1149 {
1150         struct phy_device *phydev = priv->ndev->phydev;
1151         u32 value = 0;
1152         int ret;
1153
1154         if (phydev->speed != SPEED_1000)
1155                 value = (NETSEC_GMAC_MCR_REG_CST |
1156                          NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
1157
1158         if (netsec_mac_write(priv, GMAC_REG_MCR, value))
1159                 return -ETIMEDOUT;
1160         if (netsec_mac_write(priv, GMAC_REG_BMR,
1161                              NETSEC_GMAC_BMR_REG_RESET))
1162                 return -ETIMEDOUT;
1163
1164         /* Wait soft reset */
1165         usleep_range(1000, 5000);
1166
1167         ret = netsec_mac_read(priv, GMAC_REG_BMR, &value);
1168         if (ret)
1169                 return ret;
1170         if (value & NETSEC_GMAC_BMR_REG_SWR)
1171                 return -EAGAIN;
1172
1173         netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);
1174         if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
1175                 return -ETIMEDOUT;
1176
1177         netsec_write(priv, MAC_REG_DESC_INIT, 1);
1178         if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
1179                 return -ETIMEDOUT;
1180
1181         if (netsec_mac_write(priv, GMAC_REG_BMR,
1182                              NETSEC_GMAC_BMR_REG_COMMON))
1183                 return -ETIMEDOUT;
1184         if (netsec_mac_write(priv, GMAC_REG_RDLAR,
1185                              NETSEC_GMAC_RDLAR_REG_COMMON))
1186                 return -ETIMEDOUT;
1187         if (netsec_mac_write(priv, GMAC_REG_TDLAR,
1188                              NETSEC_GMAC_TDLAR_REG_COMMON))
1189                 return -ETIMEDOUT;
1190         if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001))
1191                 return -ETIMEDOUT;
1192
1193         ret = netsec_mac_update_to_phy_state(priv);
1194         if (ret)
1195                 return ret;
1196
1197         ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1198         if (ret)
1199                 return ret;
1200
1201         value |= NETSEC_GMAC_OMR_REG_SR;
1202         value |= NETSEC_GMAC_OMR_REG_ST;
1203
1204         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1205         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1206
1207         netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce);
1208
1209         if (netsec_mac_write(priv, GMAC_REG_OMR, value))
1210                 return -ETIMEDOUT;
1211
1212         return 0;
1213 }
1214
1215 static int netsec_stop_gmac(struct netsec_priv *priv)
1216 {
1217         u32 value;
1218         int ret;
1219
1220         ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1221         if (ret)
1222                 return ret;
1223         value &= ~NETSEC_GMAC_OMR_REG_SR;
1224         value &= ~NETSEC_GMAC_OMR_REG_ST;
1225
1226         /* disable all interrupts */
1227         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1228         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1229
1230         return netsec_mac_write(priv, GMAC_REG_OMR, value);
1231 }
1232
1233 static void netsec_phy_adjust_link(struct net_device *ndev)
1234 {
1235         struct netsec_priv *priv = netdev_priv(ndev);
1236
1237         if (ndev->phydev->link)
1238                 netsec_start_gmac(priv);
1239         else
1240                 netsec_stop_gmac(priv);
1241
1242         phy_print_status(ndev->phydev);
1243 }
1244
1245 static irqreturn_t netsec_irq_handler(int irq, void *dev_id)
1246 {
1247         struct netsec_priv *priv = dev_id;
1248         u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS);
1249         unsigned long flags;
1250
1251         /* Disable interrupts */
1252         if (status & NETSEC_IRQ_TX) {
1253                 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS);
1254                 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);
1255         }
1256         if (status & NETSEC_IRQ_RX) {
1257                 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS);
1258                 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);
1259         }
1260
1261         spin_lock_irqsave(&priv->reglock, flags);
1262         netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1263         spin_unlock_irqrestore(&priv->reglock, flags);
1264
1265         napi_schedule(&priv->napi);
1266
1267         return IRQ_HANDLED;
1268 }
1269
1270 static int netsec_netdev_open(struct net_device *ndev)
1271 {
1272         struct netsec_priv *priv = netdev_priv(ndev);
1273         int ret;
1274
1275         pm_runtime_get_sync(priv->dev);
1276
1277         ret = netsec_setup_rx_dring(priv);
1278         if (ret) {
1279                 netif_err(priv, probe, priv->ndev,
1280                           "%s: fail setup ring\n", __func__);
1281                 goto err1;
1282         }
1283
1284         ret = request_irq(priv->ndev->irq, netsec_irq_handler,
1285                           IRQF_SHARED, "netsec", priv);
1286         if (ret) {
1287                 netif_err(priv, drv, priv->ndev, "request_irq failed\n");
1288                 goto err2;
1289         }
1290
1291         if (dev_of_node(priv->dev)) {
1292                 if (!of_phy_connect(priv->ndev, priv->phy_np,
1293                                     netsec_phy_adjust_link, 0,
1294                                     priv->phy_interface)) {
1295                         netif_err(priv, link, priv->ndev, "missing PHY\n");
1296                         ret = -ENODEV;
1297                         goto err3;
1298                 }
1299         } else {
1300                 ret = phy_connect_direct(priv->ndev, priv->phydev,
1301                                          netsec_phy_adjust_link,
1302                                          priv->phy_interface);
1303                 if (ret) {
1304                         netif_err(priv, link, priv->ndev,
1305                                   "phy_connect_direct() failed (%d)\n", ret);
1306                         goto err3;
1307                 }
1308         }
1309
1310         phy_start(ndev->phydev);
1311
1312         netsec_start_gmac(priv);
1313         napi_enable(&priv->napi);
1314         netif_start_queue(ndev);
1315
1316         /* Enable TX+RX intr. */
1317         netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1318
1319         return 0;
1320 err3:
1321         free_irq(priv->ndev->irq, priv);
1322 err2:
1323         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1324 err1:
1325         pm_runtime_put_sync(priv->dev);
1326         return ret;
1327 }
1328
1329 static int netsec_netdev_stop(struct net_device *ndev)
1330 {
1331         int ret;
1332         struct netsec_priv *priv = netdev_priv(ndev);
1333
1334         netif_stop_queue(priv->ndev);
1335         dma_wmb();
1336
1337         napi_disable(&priv->napi);
1338
1339         netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1340         netsec_stop_gmac(priv);
1341
1342         free_irq(priv->ndev->irq, priv);
1343
1344         netsec_uninit_pkt_dring(priv, NETSEC_RING_TX);
1345         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1346
1347         phy_stop(ndev->phydev);
1348         phy_disconnect(ndev->phydev);
1349
1350         ret = netsec_reset_hardware(priv, false);
1351
1352         pm_runtime_put_sync(priv->dev);
1353
1354         return ret;
1355 }
1356
1357 static int netsec_netdev_init(struct net_device *ndev)
1358 {
1359         struct netsec_priv *priv = netdev_priv(ndev);
1360         int ret;
1361         u16 data;
1362
1363         ret = netsec_alloc_dring(priv, NETSEC_RING_TX);
1364         if (ret)
1365                 return ret;
1366
1367         ret = netsec_alloc_dring(priv, NETSEC_RING_RX);
1368         if (ret)
1369                 goto err1;
1370
1371         /* set phy power down */
1372         data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR) |
1373                 BMCR_PDOWN;
1374         netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data);
1375
1376         ret = netsec_reset_hardware(priv, true);
1377         if (ret)
1378                 goto err2;
1379
1380         return 0;
1381 err2:
1382         netsec_free_dring(priv, NETSEC_RING_RX);
1383 err1:
1384         netsec_free_dring(priv, NETSEC_RING_TX);
1385         return ret;
1386 }
1387
1388 static void netsec_netdev_uninit(struct net_device *ndev)
1389 {
1390         struct netsec_priv *priv = netdev_priv(ndev);
1391
1392         netsec_free_dring(priv, NETSEC_RING_RX);
1393         netsec_free_dring(priv, NETSEC_RING_TX);
1394 }
1395
1396 static int netsec_netdev_set_features(struct net_device *ndev,
1397                                       netdev_features_t features)
1398 {
1399         struct netsec_priv *priv = netdev_priv(ndev);
1400
1401         priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM);
1402
1403         return 0;
1404 }
1405
1406 static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr,
1407                                int cmd)
1408 {
1409         return phy_mii_ioctl(ndev->phydev, ifr, cmd);
1410 }
1411
1412 static const struct net_device_ops netsec_netdev_ops = {
1413         .ndo_init               = netsec_netdev_init,
1414         .ndo_uninit             = netsec_netdev_uninit,
1415         .ndo_open               = netsec_netdev_open,
1416         .ndo_stop               = netsec_netdev_stop,
1417         .ndo_start_xmit         = netsec_netdev_start_xmit,
1418         .ndo_set_features       = netsec_netdev_set_features,
1419         .ndo_set_mac_address    = eth_mac_addr,
1420         .ndo_validate_addr      = eth_validate_addr,
1421         .ndo_do_ioctl           = netsec_netdev_ioctl,
1422 };
1423
1424 static int netsec_of_probe(struct platform_device *pdev,
1425                            struct netsec_priv *priv, u32 *phy_addr)
1426 {
1427         priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1428         if (!priv->phy_np) {
1429                 dev_err(&pdev->dev, "missing required property 'phy-handle'\n");
1430                 return -EINVAL;
1431         }
1432
1433         *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np);
1434
1435         priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */
1436         if (IS_ERR(priv->clk)) {
1437                 dev_err(&pdev->dev, "phy_ref_clk not found\n");
1438                 return PTR_ERR(priv->clk);
1439         }
1440         priv->freq = clk_get_rate(priv->clk);
1441
1442         return 0;
1443 }
1444
1445 static int netsec_acpi_probe(struct platform_device *pdev,
1446                              struct netsec_priv *priv, u32 *phy_addr)
1447 {
1448         int ret;
1449
1450         if (!IS_ENABLED(CONFIG_ACPI))
1451                 return -ENODEV;
1452
1453         ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr);
1454         if (ret) {
1455                 dev_err(&pdev->dev,
1456                         "missing required property 'phy-channel'\n");
1457                 return ret;
1458         }
1459
1460         ret = device_property_read_u32(&pdev->dev,
1461                                        "socionext,phy-clock-frequency",
1462                                        &priv->freq);
1463         if (ret)
1464                 dev_err(&pdev->dev,
1465                         "missing required property 'socionext,phy-clock-frequency'\n");
1466         return ret;
1467 }
1468
1469 static void netsec_unregister_mdio(struct netsec_priv *priv)
1470 {
1471         struct phy_device *phydev = priv->phydev;
1472
1473         if (!dev_of_node(priv->dev) && phydev) {
1474                 phy_device_remove(phydev);
1475                 phy_device_free(phydev);
1476         }
1477
1478         mdiobus_unregister(priv->mii_bus);
1479 }
1480
1481 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr)
1482 {
1483         struct mii_bus *bus;
1484         int ret;
1485
1486         bus = devm_mdiobus_alloc(priv->dev);
1487         if (!bus)
1488                 return -ENOMEM;
1489
1490         snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev));
1491         bus->priv = priv;
1492         bus->name = "SNI NETSEC MDIO";
1493         bus->read = netsec_phy_read;
1494         bus->write = netsec_phy_write;
1495         bus->parent = priv->dev;
1496         priv->mii_bus = bus;
1497
1498         if (dev_of_node(priv->dev)) {
1499                 struct device_node *mdio_node, *parent = dev_of_node(priv->dev);
1500
1501                 mdio_node = of_get_child_by_name(parent, "mdio");
1502                 if (mdio_node) {
1503                         parent = mdio_node;
1504                 } else {
1505                         /* older f/w doesn't populate the mdio subnode,
1506                          * allow relaxed upgrade of f/w in due time.
1507                          */
1508                         dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n");
1509                 }
1510
1511                 ret = of_mdiobus_register(bus, parent);
1512                 of_node_put(mdio_node);
1513
1514                 if (ret) {
1515                         dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1516                         return ret;
1517                 }
1518         } else {
1519                 /* Mask out all PHYs from auto probing. */
1520                 bus->phy_mask = ~0;
1521                 ret = mdiobus_register(bus);
1522                 if (ret) {
1523                         dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1524                         return ret;
1525                 }
1526
1527                 priv->phydev = get_phy_device(bus, phy_addr, false);
1528                 if (IS_ERR(priv->phydev)) {
1529                         ret = PTR_ERR(priv->phydev);
1530                         dev_err(priv->dev, "get_phy_device err(%d)\n", ret);
1531                         priv->phydev = NULL;
1532                         return -ENODEV;
1533                 }
1534
1535                 ret = phy_device_register(priv->phydev);
1536                 if (ret) {
1537                         mdiobus_unregister(bus);
1538                         dev_err(priv->dev,
1539                                 "phy_device_register err(%d)\n", ret);
1540                 }
1541         }
1542
1543         return ret;
1544 }
1545
1546 static int netsec_probe(struct platform_device *pdev)
1547 {
1548         struct resource *mmio_res, *eeprom_res, *irq_res;
1549         u8 *mac, macbuf[ETH_ALEN];
1550         struct netsec_priv *priv;
1551         u32 hw_ver, phy_addr = 0;
1552         struct net_device *ndev;
1553         int ret;
1554
1555         mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1556         if (!mmio_res) {
1557                 dev_err(&pdev->dev, "No MMIO resource found.\n");
1558                 return -ENODEV;
1559         }
1560
1561         eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1562         if (!eeprom_res) {
1563                 dev_info(&pdev->dev, "No EEPROM resource found.\n");
1564                 return -ENODEV;
1565         }
1566
1567         irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1568         if (!irq_res) {
1569                 dev_err(&pdev->dev, "No IRQ resource found.\n");
1570                 return -ENODEV;
1571         }
1572
1573         ndev = alloc_etherdev(sizeof(*priv));
1574         if (!ndev)
1575                 return -ENOMEM;
1576
1577         priv = netdev_priv(ndev);
1578
1579         spin_lock_init(&priv->reglock);
1580         SET_NETDEV_DEV(ndev, &pdev->dev);
1581         platform_set_drvdata(pdev, priv);
1582         ndev->irq = irq_res->start;
1583         priv->dev = &pdev->dev;
1584         priv->ndev = ndev;
1585
1586         priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV |
1587                            NETIF_MSG_LINK | NETIF_MSG_PROBE;
1588
1589         priv->phy_interface = device_get_phy_mode(&pdev->dev);
1590         if (priv->phy_interface < 0) {
1591                 dev_err(&pdev->dev, "missing required property 'phy-mode'\n");
1592                 ret = -ENODEV;
1593                 goto free_ndev;
1594         }
1595
1596         priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start,
1597                                     resource_size(mmio_res));
1598         if (!priv->ioaddr) {
1599                 dev_err(&pdev->dev, "devm_ioremap() failed\n");
1600                 ret = -ENXIO;
1601                 goto free_ndev;
1602         }
1603
1604         priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start,
1605                                          resource_size(eeprom_res));
1606         if (!priv->eeprom_base) {
1607                 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n");
1608                 ret = -ENXIO;
1609                 goto free_ndev;
1610         }
1611
1612         mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf));
1613         if (mac)
1614                 ether_addr_copy(ndev->dev_addr, mac);
1615
1616         if (priv->eeprom_base &&
1617             (!mac || !is_valid_ether_addr(ndev->dev_addr))) {
1618                 void __iomem *macp = priv->eeprom_base +
1619                                         NETSEC_EEPROM_MAC_ADDRESS;
1620
1621                 ndev->dev_addr[0] = readb(macp + 3);
1622                 ndev->dev_addr[1] = readb(macp + 2);
1623                 ndev->dev_addr[2] = readb(macp + 1);
1624                 ndev->dev_addr[3] = readb(macp + 0);
1625                 ndev->dev_addr[4] = readb(macp + 7);
1626                 ndev->dev_addr[5] = readb(macp + 6);
1627         }
1628
1629         if (!is_valid_ether_addr(ndev->dev_addr)) {
1630                 dev_warn(&pdev->dev, "No MAC address found, using random\n");
1631                 eth_hw_addr_random(ndev);
1632         }
1633
1634         if (dev_of_node(&pdev->dev))
1635                 ret = netsec_of_probe(pdev, priv, &phy_addr);
1636         else
1637                 ret = netsec_acpi_probe(pdev, priv, &phy_addr);
1638         if (ret)
1639                 goto free_ndev;
1640
1641         priv->phy_addr = phy_addr;
1642
1643         if (!priv->freq) {
1644                 dev_err(&pdev->dev, "missing PHY reference clock frequency\n");
1645                 ret = -ENODEV;
1646                 goto free_ndev;
1647         }
1648
1649         /* default for throughput */
1650         priv->et_coalesce.rx_coalesce_usecs = 500;
1651         priv->et_coalesce.rx_max_coalesced_frames = 8;
1652         priv->et_coalesce.tx_coalesce_usecs = 500;
1653         priv->et_coalesce.tx_max_coalesced_frames = 8;
1654
1655         ret = device_property_read_u32(&pdev->dev, "max-frame-size",
1656                                        &ndev->max_mtu);
1657         if (ret < 0)
1658                 ndev->max_mtu = ETH_DATA_LEN;
1659
1660         /* runtime_pm coverage just for probe, open/close also cover it */
1661         pm_runtime_enable(&pdev->dev);
1662         pm_runtime_get_sync(&pdev->dev);
1663
1664         hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER);
1665         /* this driver only supports F_TAIKI style NETSEC */
1666         if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) !=
1667             NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) {
1668                 ret = -ENODEV;
1669                 goto pm_disable;
1670         }
1671
1672         dev_info(&pdev->dev, "hardware revision %d.%d\n",
1673                  hw_ver >> 16, hw_ver & 0xffff);
1674
1675         netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT);
1676
1677         ndev->netdev_ops = &netsec_netdev_ops;
1678         ndev->ethtool_ops = &netsec_ethtool_ops;
1679
1680         ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO |
1681                                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1682         ndev->hw_features = ndev->features;
1683
1684         priv->rx_cksum_offload_flag = true;
1685
1686         ret = netsec_register_mdio(priv, phy_addr);
1687         if (ret)
1688                 goto unreg_napi;
1689
1690         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)))
1691                 dev_warn(&pdev->dev, "Failed to set DMA mask\n");
1692
1693         ret = register_netdev(ndev);
1694         if (ret) {
1695                 netif_err(priv, probe, ndev, "register_netdev() failed\n");
1696                 goto unreg_mii;
1697         }
1698
1699         pm_runtime_put_sync(&pdev->dev);
1700         return 0;
1701
1702 unreg_mii:
1703         netsec_unregister_mdio(priv);
1704 unreg_napi:
1705         netif_napi_del(&priv->napi);
1706 pm_disable:
1707         pm_runtime_put_sync(&pdev->dev);
1708         pm_runtime_disable(&pdev->dev);
1709 free_ndev:
1710         free_netdev(ndev);
1711         dev_err(&pdev->dev, "init failed\n");
1712
1713         return ret;
1714 }
1715
1716 static int netsec_remove(struct platform_device *pdev)
1717 {
1718         struct netsec_priv *priv = platform_get_drvdata(pdev);
1719
1720         unregister_netdev(priv->ndev);
1721
1722         netsec_unregister_mdio(priv);
1723
1724         netif_napi_del(&priv->napi);
1725
1726         pm_runtime_disable(&pdev->dev);
1727         free_netdev(priv->ndev);
1728
1729         return 0;
1730 }
1731
1732 #ifdef CONFIG_PM
1733 static int netsec_runtime_suspend(struct device *dev)
1734 {
1735         struct netsec_priv *priv = dev_get_drvdata(dev);
1736
1737         netsec_write(priv, NETSEC_REG_CLK_EN, 0);
1738
1739         clk_disable_unprepare(priv->clk);
1740
1741         return 0;
1742 }
1743
1744 static int netsec_runtime_resume(struct device *dev)
1745 {
1746         struct netsec_priv *priv = dev_get_drvdata(dev);
1747
1748         clk_prepare_enable(priv->clk);
1749
1750         netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |
1751                                                NETSEC_CLK_EN_REG_DOM_C |
1752                                                NETSEC_CLK_EN_REG_DOM_G);
1753         return 0;
1754 }
1755 #endif
1756
1757 static const struct dev_pm_ops netsec_pm_ops = {
1758         SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL)
1759 };
1760
1761 static const struct of_device_id netsec_dt_ids[] = {
1762         { .compatible = "socionext,synquacer-netsec" },
1763         { }
1764 };
1765 MODULE_DEVICE_TABLE(of, netsec_dt_ids);
1766
1767 #ifdef CONFIG_ACPI
1768 static const struct acpi_device_id netsec_acpi_ids[] = {
1769         { "SCX0001" },
1770         { }
1771 };
1772 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids);
1773 #endif
1774
1775 static struct platform_driver netsec_driver = {
1776         .probe  = netsec_probe,
1777         .remove = netsec_remove,
1778         .driver = {
1779                 .name = "netsec",
1780                 .pm = &netsec_pm_ops,
1781                 .of_match_table = netsec_dt_ids,
1782                 .acpi_match_table = ACPI_PTR(netsec_acpi_ids),
1783         },
1784 };
1785 module_platform_driver(netsec_driver);
1786
1787 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>");
1788 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
1789 MODULE_DESCRIPTION("NETSEC Ethernet driver");
1790 MODULE_LICENSE("GPL");