16dcbf36f8cc4bf5c6a2e6e34ea17367c1a6d035
[muen/linux.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2  * Texas Instruments Ethernet Switch Driver
3  *
4  * Copyright (C) 2012 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38 #include <linux/kmemleak.h>
39 #include <linux/sys_soc.h>
40
41 #include <linux/pinctrl/consumer.h>
42 #include <net/pkt_cls.h>
43
44 #include "cpsw.h"
45 #include "cpsw_ale.h"
46 #include "cpts.h"
47 #include "davinci_cpdma.h"
48
49 #include <net/pkt_sched.h>
50
51 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
52                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
53                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
54                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
55                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
56                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
57                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
58                          NETIF_MSG_RX_STATUS)
59
60 #define cpsw_info(priv, type, format, ...)              \
61 do {                                                            \
62         if (netif_msg_##type(priv) && net_ratelimit())          \
63                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
64 } while (0)
65
66 #define cpsw_err(priv, type, format, ...)               \
67 do {                                                            \
68         if (netif_msg_##type(priv) && net_ratelimit())          \
69                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
70 } while (0)
71
72 #define cpsw_dbg(priv, type, format, ...)               \
73 do {                                                            \
74         if (netif_msg_##type(priv) && net_ratelimit())          \
75                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
76 } while (0)
77
78 #define cpsw_notice(priv, type, format, ...)            \
79 do {                                                            \
80         if (netif_msg_##type(priv) && net_ratelimit())          \
81                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
82 } while (0)
83
84 #define ALE_ALL_PORTS           0x7
85
86 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
87 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
88 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
89
90 #define CPSW_VERSION_1          0x19010a
91 #define CPSW_VERSION_2          0x19010c
92 #define CPSW_VERSION_3          0x19010f
93 #define CPSW_VERSION_4          0x190112
94
95 #define HOST_PORT_NUM           0
96 #define CPSW_ALE_PORTS_NUM      3
97 #define SLIVER_SIZE             0x40
98
99 #define CPSW1_HOST_PORT_OFFSET  0x028
100 #define CPSW1_SLAVE_OFFSET      0x050
101 #define CPSW1_SLAVE_SIZE        0x040
102 #define CPSW1_CPDMA_OFFSET      0x100
103 #define CPSW1_STATERAM_OFFSET   0x200
104 #define CPSW1_HW_STATS          0x400
105 #define CPSW1_CPTS_OFFSET       0x500
106 #define CPSW1_ALE_OFFSET        0x600
107 #define CPSW1_SLIVER_OFFSET     0x700
108
109 #define CPSW2_HOST_PORT_OFFSET  0x108
110 #define CPSW2_SLAVE_OFFSET      0x200
111 #define CPSW2_SLAVE_SIZE        0x100
112 #define CPSW2_CPDMA_OFFSET      0x800
113 #define CPSW2_HW_STATS          0x900
114 #define CPSW2_STATERAM_OFFSET   0xa00
115 #define CPSW2_CPTS_OFFSET       0xc00
116 #define CPSW2_ALE_OFFSET        0xd00
117 #define CPSW2_SLIVER_OFFSET     0xd80
118 #define CPSW2_BD_OFFSET         0x2000
119
120 #define CPDMA_RXTHRESH          0x0c0
121 #define CPDMA_RXFREE            0x0e0
122 #define CPDMA_TXHDP             0x00
123 #define CPDMA_RXHDP             0x20
124 #define CPDMA_TXCP              0x40
125 #define CPDMA_RXCP              0x60
126
127 #define CPSW_POLL_WEIGHT        64
128 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE             4
129 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
130 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN +\
131                                  ETH_FCS_LEN +\
132                                  CPSW_RX_VLAN_ENCAP_HDR_SIZE)
133
134 #define RX_PRIORITY_MAPPING     0x76543210
135 #define TX_PRIORITY_MAPPING     0x33221100
136 #define CPDMA_TX_PRIORITY_MAP   0x76543210
137
138 #define CPSW_VLAN_AWARE         BIT(1)
139 #define CPSW_RX_VLAN_ENCAP      BIT(2)
140 #define CPSW_ALE_VLAN_AWARE     1
141
142 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
143 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
144 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
145
146 #define CPSW_INTPACEEN          (0x3f << 16)
147 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
148 #define CPSW_CMINTMAX_CNT       63
149 #define CPSW_CMINTMIN_CNT       2
150 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
151 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
152
153 #define cpsw_slave_index(cpsw, priv)                            \
154                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
155                 cpsw->data.active_slave)
156 #define IRQ_NUM                 2
157 #define CPSW_MAX_QUEUES         8
158 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
159 #define CPSW_FIFO_QUEUE_TYPE_SHIFT      16
160 #define CPSW_FIFO_SHAPE_EN_SHIFT        16
161 #define CPSW_FIFO_RATE_EN_SHIFT         20
162 #define CPSW_TC_NUM                     4
163 #define CPSW_FIFO_SHAPERS_NUM           (CPSW_TC_NUM - 1)
164 #define CPSW_PCT_MASK                   0x7f
165
166 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT       29
167 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK         GENMASK(2, 0)
168 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT        16
169 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT   8
170 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK     GENMASK(1, 0)
171 enum {
172         CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
173         CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
174         CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
175         CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
176 };
177
178 static int debug_level;
179 module_param(debug_level, int, 0);
180 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
181
182 static int ale_ageout = 10;
183 module_param(ale_ageout, int, 0);
184 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
185
186 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
187 module_param(rx_packet_max, int, 0);
188 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
189
190 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
191 module_param(descs_pool_size, int, 0444);
192 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
193
194 struct cpsw_wr_regs {
195         u32     id_ver;
196         u32     soft_reset;
197         u32     control;
198         u32     int_control;
199         u32     rx_thresh_en;
200         u32     rx_en;
201         u32     tx_en;
202         u32     misc_en;
203         u32     mem_allign1[8];
204         u32     rx_thresh_stat;
205         u32     rx_stat;
206         u32     tx_stat;
207         u32     misc_stat;
208         u32     mem_allign2[8];
209         u32     rx_imax;
210         u32     tx_imax;
211
212 };
213
214 struct cpsw_ss_regs {
215         u32     id_ver;
216         u32     control;
217         u32     soft_reset;
218         u32     stat_port_en;
219         u32     ptype;
220         u32     soft_idle;
221         u32     thru_rate;
222         u32     gap_thresh;
223         u32     tx_start_wds;
224         u32     flow_control;
225         u32     vlan_ltype;
226         u32     ts_ltype;
227         u32     dlr_ltype;
228 };
229
230 /* CPSW_PORT_V1 */
231 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
232 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
233 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
234 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
235 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
236 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
237 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
238 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
239
240 /* CPSW_PORT_V2 */
241 #define CPSW2_CONTROL       0x00 /* Control Register */
242 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
243 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
244 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
245 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
246 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
247 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
248
249 /* CPSW_PORT_V1 and V2 */
250 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
251 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
252 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
253
254 /* CPSW_PORT_V2 only */
255 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
256 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
257 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
258 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
259 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
260 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
261 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
262 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
263
264 /* Bit definitions for the CPSW2_CONTROL register */
265 #define PASS_PRI_TAGGED     BIT(24) /* Pass Priority Tagged */
266 #define VLAN_LTYPE2_EN      BIT(21) /* VLAN LTYPE 2 enable */
267 #define VLAN_LTYPE1_EN      BIT(20) /* VLAN LTYPE 1 enable */
268 #define DSCP_PRI_EN         BIT(16) /* DSCP Priority Enable */
269 #define TS_107              BIT(15) /* Tyme Sync Dest IP Address 107 */
270 #define TS_320              BIT(14) /* Time Sync Dest Port 320 enable */
271 #define TS_319              BIT(13) /* Time Sync Dest Port 319 enable */
272 #define TS_132              BIT(12) /* Time Sync Dest IP Addr 132 enable */
273 #define TS_131              BIT(11) /* Time Sync Dest IP Addr 131 enable */
274 #define TS_130              BIT(10) /* Time Sync Dest IP Addr 130 enable */
275 #define TS_129              BIT(9)  /* Time Sync Dest IP Addr 129 enable */
276 #define TS_TTL_NONZERO      BIT(8)  /* Time Sync Time To Live Non-zero enable */
277 #define TS_ANNEX_F_EN       BIT(6)  /* Time Sync Annex F enable */
278 #define TS_ANNEX_D_EN       BIT(4)  /* Time Sync Annex D enable */
279 #define TS_LTYPE2_EN        BIT(3)  /* Time Sync LTYPE 2 enable */
280 #define TS_LTYPE1_EN        BIT(2)  /* Time Sync LTYPE 1 enable */
281 #define TS_TX_EN            BIT(1)  /* Time Sync Transmit Enable */
282 #define TS_RX_EN            BIT(0)  /* Time Sync Receive Enable */
283
284 #define CTRL_V2_TS_BITS \
285         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
286          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
287
288 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
289 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
290 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
291
292
293 #define CTRL_V3_TS_BITS \
294         (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
295          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
296          TS_LTYPE1_EN)
297
298 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
299 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
300 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
301
302 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
303 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
304 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
305 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
306 #define TS_MSG_TYPE_EN_MASK      (0xffff)
307
308 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
309 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
310
311 /* Bit definitions for the CPSW1_TS_CTL register */
312 #define CPSW_V1_TS_RX_EN                BIT(0)
313 #define CPSW_V1_TS_TX_EN                BIT(4)
314 #define CPSW_V1_MSG_TYPE_OFS            16
315
316 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
317 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
318
319 #define CPSW_MAX_BLKS_TX                15
320 #define CPSW_MAX_BLKS_TX_SHIFT          4
321 #define CPSW_MAX_BLKS_RX                5
322
323 struct cpsw_host_regs {
324         u32     max_blks;
325         u32     blk_cnt;
326         u32     tx_in_ctl;
327         u32     port_vlan;
328         u32     tx_pri_map;
329         u32     cpdma_tx_pri_map;
330         u32     cpdma_rx_chan_map;
331 };
332
333 struct cpsw_sliver_regs {
334         u32     id_ver;
335         u32     mac_control;
336         u32     mac_status;
337         u32     soft_reset;
338         u32     rx_maxlen;
339         u32     __reserved_0;
340         u32     rx_pause;
341         u32     tx_pause;
342         u32     __reserved_1;
343         u32     rx_pri_map;
344 };
345
346 struct cpsw_hw_stats {
347         u32     rxgoodframes;
348         u32     rxbroadcastframes;
349         u32     rxmulticastframes;
350         u32     rxpauseframes;
351         u32     rxcrcerrors;
352         u32     rxaligncodeerrors;
353         u32     rxoversizedframes;
354         u32     rxjabberframes;
355         u32     rxundersizedframes;
356         u32     rxfragments;
357         u32     __pad_0[2];
358         u32     rxoctets;
359         u32     txgoodframes;
360         u32     txbroadcastframes;
361         u32     txmulticastframes;
362         u32     txpauseframes;
363         u32     txdeferredframes;
364         u32     txcollisionframes;
365         u32     txsinglecollframes;
366         u32     txmultcollframes;
367         u32     txexcessivecollisions;
368         u32     txlatecollisions;
369         u32     txunderrun;
370         u32     txcarriersenseerrors;
371         u32     txoctets;
372         u32     octetframes64;
373         u32     octetframes65t127;
374         u32     octetframes128t255;
375         u32     octetframes256t511;
376         u32     octetframes512t1023;
377         u32     octetframes1024tup;
378         u32     netoctets;
379         u32     rxsofoverruns;
380         u32     rxmofoverruns;
381         u32     rxdmaoverruns;
382 };
383
384 struct cpsw_slave_data {
385         struct device_node *phy_node;
386         char            phy_id[MII_BUS_ID_SIZE];
387         int             phy_if;
388         u8              mac_addr[ETH_ALEN];
389         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
390 };
391
392 struct cpsw_platform_data {
393         struct cpsw_slave_data  *slave_data;
394         u32     ss_reg_ofs;     /* Subsystem control register offset */
395         u32     channels;       /* number of cpdma channels (symmetric) */
396         u32     slaves;         /* number of slave cpgmac ports */
397         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
398         u32     ale_entries;    /* ale table size */
399         u32     bd_ram_size;  /*buffer descriptor ram size */
400         u32     mac_control;    /* Mac control register */
401         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
402         bool    dual_emac;      /* Enable Dual EMAC mode */
403 };
404
405 struct cpsw_slave {
406         void __iomem                    *regs;
407         struct cpsw_sliver_regs __iomem *sliver;
408         int                             slave_num;
409         u32                             mac_control;
410         struct cpsw_slave_data          *data;
411         struct phy_device               *phy;
412         struct net_device               *ndev;
413         u32                             port_vlan;
414 };
415
416 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
417 {
418         return readl_relaxed(slave->regs + offset);
419 }
420
421 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
422 {
423         writel_relaxed(val, slave->regs + offset);
424 }
425
426 struct cpsw_vector {
427         struct cpdma_chan *ch;
428         int budget;
429 };
430
431 struct cpsw_common {
432         struct device                   *dev;
433         struct cpsw_platform_data       data;
434         struct napi_struct              napi_rx;
435         struct napi_struct              napi_tx;
436         struct cpsw_ss_regs __iomem     *regs;
437         struct cpsw_wr_regs __iomem     *wr_regs;
438         u8 __iomem                      *hw_stats;
439         struct cpsw_host_regs __iomem   *host_port_regs;
440         u32                             version;
441         u32                             coal_intvl;
442         u32                             bus_freq_mhz;
443         int                             rx_packet_max;
444         struct cpsw_slave               *slaves;
445         struct cpdma_ctlr               *dma;
446         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
447         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
448         struct cpsw_ale                 *ale;
449         bool                            quirk_irq;
450         bool                            rx_irq_disabled;
451         bool                            tx_irq_disabled;
452         u32 irqs_table[IRQ_NUM];
453         struct cpts                     *cpts;
454         int                             rx_ch_num, tx_ch_num;
455         int                             speed;
456         int                             usage_count;
457 };
458
459 struct cpsw_priv {
460         struct net_device               *ndev;
461         struct device                   *dev;
462         u32                             msg_enable;
463         u8                              mac_addr[ETH_ALEN];
464         bool                            rx_pause;
465         bool                            tx_pause;
466         bool                            mqprio_hw;
467         int                             fifo_bw[CPSW_TC_NUM];
468         int                             shp_cfg_speed;
469         u32 emac_port;
470         struct cpsw_common *cpsw;
471 };
472
473 struct cpsw_stats {
474         char stat_string[ETH_GSTRING_LEN];
475         int type;
476         int sizeof_stat;
477         int stat_offset;
478 };
479
480 enum {
481         CPSW_STATS,
482         CPDMA_RX_STATS,
483         CPDMA_TX_STATS,
484 };
485
486 #define CPSW_STAT(m)            CPSW_STATS,                             \
487                                 FIELD_SIZEOF(struct cpsw_hw_stats, m), \
488                                 offsetof(struct cpsw_hw_stats, m)
489 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
490                                 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
491                                 offsetof(struct cpdma_chan_stats, m)
492 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
493                                 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
494                                 offsetof(struct cpdma_chan_stats, m)
495
496 static const struct cpsw_stats cpsw_gstrings_stats[] = {
497         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
498         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
499         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
500         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
501         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
502         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
503         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
504         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
505         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
506         { "Rx Fragments", CPSW_STAT(rxfragments) },
507         { "Rx Octets", CPSW_STAT(rxoctets) },
508         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
509         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
510         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
511         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
512         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
513         { "Collisions", CPSW_STAT(txcollisionframes) },
514         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
515         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
516         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
517         { "Late Collisions", CPSW_STAT(txlatecollisions) },
518         { "Tx Underrun", CPSW_STAT(txunderrun) },
519         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
520         { "Tx Octets", CPSW_STAT(txoctets) },
521         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
522         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
523         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
524         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
525         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
526         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
527         { "Net Octets", CPSW_STAT(netoctets) },
528         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
529         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
530         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
531 };
532
533 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
534         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
535         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
536         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
537         { "misqueued", CPDMA_RX_STAT(misqueued) },
538         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
539         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
540         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
541         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
542         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
543         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
544         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
545         { "requeue", CPDMA_RX_STAT(requeue) },
546         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
547 };
548
549 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
550 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
551
552 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
553 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
554 #define for_each_slave(priv, func, arg...)                              \
555         do {                                                            \
556                 struct cpsw_slave *slave;                               \
557                 struct cpsw_common *cpsw = (priv)->cpsw;                \
558                 int n;                                                  \
559                 if (cpsw->data.dual_emac)                               \
560                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
561                 else                                                    \
562                         for (n = cpsw->data.slaves,                     \
563                                         slave = cpsw->slaves;           \
564                                         n; n--)                         \
565                                 (func)(slave++, ##arg);                 \
566         } while (0)
567
568 static inline int cpsw_get_slave_port(u32 slave_num)
569 {
570         return slave_num + 1;
571 }
572
573 static void cpsw_add_mcast(struct cpsw_priv *priv, u8 *addr)
574 {
575         struct cpsw_common *cpsw = priv->cpsw;
576
577         if (cpsw->data.dual_emac) {
578                 struct cpsw_slave *slave = cpsw->slaves + priv->emac_port;
579                 int slave_port = cpsw_get_slave_port(slave->slave_num);
580
581                 cpsw_ale_add_mcast(cpsw->ale, addr,
582                                    1 << slave_port | ALE_PORT_HOST,
583                                    ALE_VLAN, slave->port_vlan, 0);
584                 return;
585         }
586
587         cpsw_ale_add_mcast(cpsw->ale, addr, ALE_ALL_PORTS, 0, 0, 0);
588 }
589
590 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
591 {
592         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
593         struct cpsw_ale *ale = cpsw->ale;
594         int i;
595
596         if (cpsw->data.dual_emac) {
597                 bool flag = false;
598
599                 /* Enabling promiscuous mode for one interface will be
600                  * common for both the interface as the interface shares
601                  * the same hardware resource.
602                  */
603                 for (i = 0; i < cpsw->data.slaves; i++)
604                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
605                                 flag = true;
606
607                 if (!enable && flag) {
608                         enable = true;
609                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
610                 }
611
612                 if (enable) {
613                         /* Enable Bypass */
614                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
615
616                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
617                 } else {
618                         /* Disable Bypass */
619                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
620                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
621                 }
622         } else {
623                 if (enable) {
624                         unsigned long timeout = jiffies + HZ;
625
626                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
627                         for (i = 0; i <= cpsw->data.slaves; i++) {
628                                 cpsw_ale_control_set(ale, i,
629                                                      ALE_PORT_NOLEARN, 1);
630                                 cpsw_ale_control_set(ale, i,
631                                                      ALE_PORT_NO_SA_UPDATE, 1);
632                         }
633
634                         /* Clear All Untouched entries */
635                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
636                         do {
637                                 cpu_relax();
638                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
639                                         break;
640                         } while (time_after(timeout, jiffies));
641                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
642
643                         /* Clear all mcast from ALE */
644                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
645
646                         /* Flood All Unicast Packets to Host port */
647                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
648                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
649                 } else {
650                         /* Don't Flood All Unicast Packets to Host port */
651                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
652
653                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
654                         for (i = 0; i <= cpsw->data.slaves; i++) {
655                                 cpsw_ale_control_set(ale, i,
656                                                      ALE_PORT_NOLEARN, 0);
657                                 cpsw_ale_control_set(ale, i,
658                                                      ALE_PORT_NO_SA_UPDATE, 0);
659                         }
660                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
661                 }
662         }
663 }
664
665 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
666 {
667         struct cpsw_priv *priv = netdev_priv(ndev);
668         struct cpsw_common *cpsw = priv->cpsw;
669         int vid;
670
671         if (cpsw->data.dual_emac)
672                 vid = cpsw->slaves[priv->emac_port].port_vlan;
673         else
674                 vid = cpsw->data.default_vlan;
675
676         if (ndev->flags & IFF_PROMISC) {
677                 /* Enable promiscuous mode */
678                 cpsw_set_promiscious(ndev, true);
679                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
680                 return;
681         } else {
682                 /* Disable promiscuous mode */
683                 cpsw_set_promiscious(ndev, false);
684         }
685
686         /* Restore allmulti on vlans if necessary */
687         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
688
689         /* Clear all mcast from ALE */
690         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
691
692         if (!netdev_mc_empty(ndev)) {
693                 struct netdev_hw_addr *ha;
694
695                 /* program multicast address list into ALE register */
696                 netdev_for_each_mc_addr(ha, ndev) {
697                         cpsw_add_mcast(priv, ha->addr);
698                 }
699         }
700 }
701
702 static void cpsw_intr_enable(struct cpsw_common *cpsw)
703 {
704         writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
705         writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
706
707         cpdma_ctlr_int_ctrl(cpsw->dma, true);
708         return;
709 }
710
711 static void cpsw_intr_disable(struct cpsw_common *cpsw)
712 {
713         writel_relaxed(0, &cpsw->wr_regs->tx_en);
714         writel_relaxed(0, &cpsw->wr_regs->rx_en);
715
716         cpdma_ctlr_int_ctrl(cpsw->dma, false);
717         return;
718 }
719
720 static void cpsw_tx_handler(void *token, int len, int status)
721 {
722         struct netdev_queue     *txq;
723         struct sk_buff          *skb = token;
724         struct net_device       *ndev = skb->dev;
725         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
726
727         /* Check whether the queue is stopped due to stalled tx dma, if the
728          * queue is stopped then start the queue as we have free desc for tx
729          */
730         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
731         if (unlikely(netif_tx_queue_stopped(txq)))
732                 netif_tx_wake_queue(txq);
733
734         cpts_tx_timestamp(cpsw->cpts, skb);
735         ndev->stats.tx_packets++;
736         ndev->stats.tx_bytes += len;
737         dev_kfree_skb_any(skb);
738 }
739
740 static void cpsw_rx_vlan_encap(struct sk_buff *skb)
741 {
742         struct cpsw_priv *priv = netdev_priv(skb->dev);
743         struct cpsw_common *cpsw = priv->cpsw;
744         u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
745         u16 vtag, vid, prio, pkt_type;
746
747         /* Remove VLAN header encapsulation word */
748         skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
749
750         pkt_type = (rx_vlan_encap_hdr >>
751                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
752                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
753         /* Ignore unknown & Priority-tagged packets*/
754         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
755             pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
756                 return;
757
758         vid = (rx_vlan_encap_hdr >>
759                CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
760                VLAN_VID_MASK;
761         /* Ignore vid 0 and pass packet as is */
762         if (!vid)
763                 return;
764         /* Ignore default vlans in dual mac mode */
765         if (cpsw->data.dual_emac &&
766             vid == cpsw->slaves[priv->emac_port].port_vlan)
767                 return;
768
769         prio = (rx_vlan_encap_hdr >>
770                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
771                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
772
773         vtag = (prio << VLAN_PRIO_SHIFT) | vid;
774         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
775
776         /* strip vlan tag for VLAN-tagged packet */
777         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
778                 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
779                 skb_pull(skb, VLAN_HLEN);
780         }
781 }
782
783 static void cpsw_rx_handler(void *token, int len, int status)
784 {
785         struct cpdma_chan       *ch;
786         struct sk_buff          *skb = token;
787         struct sk_buff          *new_skb;
788         struct net_device       *ndev = skb->dev;
789         int                     ret = 0, port;
790         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
791
792         if (cpsw->data.dual_emac) {
793                 port = CPDMA_RX_SOURCE_PORT(status);
794                 if (port) {
795                         ndev = cpsw->slaves[--port].ndev;
796                         skb->dev = ndev;
797                 }
798         }
799
800         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
801                 /* In dual emac mode check for all interfaces */
802                 if (cpsw->data.dual_emac && cpsw->usage_count &&
803                     (status >= 0)) {
804                         /* The packet received is for the interface which
805                          * is already down and the other interface is up
806                          * and running, instead of freeing which results
807                          * in reducing of the number of rx descriptor in
808                          * DMA engine, requeue skb back to cpdma.
809                          */
810                         new_skb = skb;
811                         goto requeue;
812                 }
813
814                 /* the interface is going down, skbs are purged */
815                 dev_kfree_skb_any(skb);
816                 return;
817         }
818
819         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
820         if (new_skb) {
821                 skb_copy_queue_mapping(new_skb, skb);
822                 skb_put(skb, len);
823                 if (status & CPDMA_RX_VLAN_ENCAP)
824                         cpsw_rx_vlan_encap(skb);
825                 cpts_rx_timestamp(cpsw->cpts, skb);
826                 skb->protocol = eth_type_trans(skb, ndev);
827                 netif_receive_skb(skb);
828                 ndev->stats.rx_bytes += len;
829                 ndev->stats.rx_packets++;
830                 kmemleak_not_leak(new_skb);
831         } else {
832                 ndev->stats.rx_dropped++;
833                 new_skb = skb;
834         }
835
836 requeue:
837         if (netif_dormant(ndev)) {
838                 dev_kfree_skb_any(new_skb);
839                 return;
840         }
841
842         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
843         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
844                                 skb_tailroom(new_skb), 0);
845         if (WARN_ON(ret < 0))
846                 dev_kfree_skb_any(new_skb);
847 }
848
849 static void cpsw_split_res(struct net_device *ndev)
850 {
851         struct cpsw_priv *priv = netdev_priv(ndev);
852         u32 consumed_rate = 0, bigest_rate = 0;
853         struct cpsw_common *cpsw = priv->cpsw;
854         struct cpsw_vector *txv = cpsw->txv;
855         int i, ch_weight, rlim_ch_num = 0;
856         int budget, bigest_rate_ch = 0;
857         u32 ch_rate, max_rate;
858         int ch_budget = 0;
859
860         for (i = 0; i < cpsw->tx_ch_num; i++) {
861                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
862                 if (!ch_rate)
863                         continue;
864
865                 rlim_ch_num++;
866                 consumed_rate += ch_rate;
867         }
868
869         if (cpsw->tx_ch_num == rlim_ch_num) {
870                 max_rate = consumed_rate;
871         } else if (!rlim_ch_num) {
872                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
873                 bigest_rate = 0;
874                 max_rate = consumed_rate;
875         } else {
876                 max_rate = cpsw->speed * 1000;
877
878                 /* if max_rate is less then expected due to reduced link speed,
879                  * split proportionally according next potential max speed
880                  */
881                 if (max_rate < consumed_rate)
882                         max_rate *= 10;
883
884                 if (max_rate < consumed_rate)
885                         max_rate *= 10;
886
887                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
888                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
889                             (cpsw->tx_ch_num - rlim_ch_num);
890                 bigest_rate = (max_rate - consumed_rate) /
891                               (cpsw->tx_ch_num - rlim_ch_num);
892         }
893
894         /* split tx weight/budget */
895         budget = CPSW_POLL_WEIGHT;
896         for (i = 0; i < cpsw->tx_ch_num; i++) {
897                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
898                 if (ch_rate) {
899                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
900                         if (!txv[i].budget)
901                                 txv[i].budget++;
902                         if (ch_rate > bigest_rate) {
903                                 bigest_rate_ch = i;
904                                 bigest_rate = ch_rate;
905                         }
906
907                         ch_weight = (ch_rate * 100) / max_rate;
908                         if (!ch_weight)
909                                 ch_weight++;
910                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
911                 } else {
912                         txv[i].budget = ch_budget;
913                         if (!bigest_rate_ch)
914                                 bigest_rate_ch = i;
915                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
916                 }
917
918                 budget -= txv[i].budget;
919         }
920
921         if (budget)
922                 txv[bigest_rate_ch].budget += budget;
923
924         /* split rx budget */
925         budget = CPSW_POLL_WEIGHT;
926         ch_budget = budget / cpsw->rx_ch_num;
927         for (i = 0; i < cpsw->rx_ch_num; i++) {
928                 cpsw->rxv[i].budget = ch_budget;
929                 budget -= ch_budget;
930         }
931
932         if (budget)
933                 cpsw->rxv[0].budget += budget;
934 }
935
936 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
937 {
938         struct cpsw_common *cpsw = dev_id;
939
940         writel(0, &cpsw->wr_regs->tx_en);
941         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
942
943         if (cpsw->quirk_irq) {
944                 disable_irq_nosync(cpsw->irqs_table[1]);
945                 cpsw->tx_irq_disabled = true;
946         }
947
948         napi_schedule(&cpsw->napi_tx);
949         return IRQ_HANDLED;
950 }
951
952 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
953 {
954         struct cpsw_common *cpsw = dev_id;
955
956         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
957         writel(0, &cpsw->wr_regs->rx_en);
958
959         if (cpsw->quirk_irq) {
960                 disable_irq_nosync(cpsw->irqs_table[0]);
961                 cpsw->rx_irq_disabled = true;
962         }
963
964         napi_schedule(&cpsw->napi_rx);
965         return IRQ_HANDLED;
966 }
967
968 static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
969 {
970         u32                     ch_map;
971         int                     num_tx, cur_budget, ch;
972         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
973         struct cpsw_vector      *txv;
974
975         /* process every unprocessed channel */
976         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
977         for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) {
978                 if (!(ch_map & 0x80))
979                         continue;
980
981                 txv = &cpsw->txv[ch];
982                 if (unlikely(txv->budget > budget - num_tx))
983                         cur_budget = budget - num_tx;
984                 else
985                         cur_budget = txv->budget;
986
987                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
988                 if (num_tx >= budget)
989                         break;
990         }
991
992         if (num_tx < budget) {
993                 napi_complete(napi_tx);
994                 writel(0xff, &cpsw->wr_regs->tx_en);
995         }
996
997         return num_tx;
998 }
999
1000 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
1001 {
1002         struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
1003         int num_tx;
1004
1005         num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
1006         if (num_tx < budget) {
1007                 napi_complete(napi_tx);
1008                 writel(0xff, &cpsw->wr_regs->tx_en);
1009                 if (cpsw->tx_irq_disabled) {
1010                         cpsw->tx_irq_disabled = false;
1011                         enable_irq(cpsw->irqs_table[1]);
1012                 }
1013         }
1014
1015         return num_tx;
1016 }
1017
1018 static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
1019 {
1020         u32                     ch_map;
1021         int                     num_rx, cur_budget, ch;
1022         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
1023         struct cpsw_vector      *rxv;
1024
1025         /* process every unprocessed channel */
1026         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
1027         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
1028                 if (!(ch_map & 0x01))
1029                         continue;
1030
1031                 rxv = &cpsw->rxv[ch];
1032                 if (unlikely(rxv->budget > budget - num_rx))
1033                         cur_budget = budget - num_rx;
1034                 else
1035                         cur_budget = rxv->budget;
1036
1037                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
1038                 if (num_rx >= budget)
1039                         break;
1040         }
1041
1042         if (num_rx < budget) {
1043                 napi_complete_done(napi_rx, num_rx);
1044                 writel(0xff, &cpsw->wr_regs->rx_en);
1045         }
1046
1047         return num_rx;
1048 }
1049
1050 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
1051 {
1052         struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1053         int num_rx;
1054
1055         num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
1056         if (num_rx < budget) {
1057                 napi_complete_done(napi_rx, num_rx);
1058                 writel(0xff, &cpsw->wr_regs->rx_en);
1059                 if (cpsw->rx_irq_disabled) {
1060                         cpsw->rx_irq_disabled = false;
1061                         enable_irq(cpsw->irqs_table[0]);
1062                 }
1063         }
1064
1065         return num_rx;
1066 }
1067
1068 static inline void soft_reset(const char *module, void __iomem *reg)
1069 {
1070         unsigned long timeout = jiffies + HZ;
1071
1072         writel_relaxed(1, reg);
1073         do {
1074                 cpu_relax();
1075         } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
1076
1077         WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
1078 }
1079
1080 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
1081                                struct cpsw_priv *priv)
1082 {
1083         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
1084         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
1085 }
1086
1087 static bool cpsw_shp_is_off(struct cpsw_priv *priv)
1088 {
1089         struct cpsw_common *cpsw = priv->cpsw;
1090         struct cpsw_slave *slave;
1091         u32 shift, mask, val;
1092
1093         val = readl_relaxed(&cpsw->regs->ptype);
1094
1095         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1096         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1097         mask = 7 << shift;
1098         val = val & mask;
1099
1100         return !val;
1101 }
1102
1103 static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on)
1104 {
1105         struct cpsw_common *cpsw = priv->cpsw;
1106         struct cpsw_slave *slave;
1107         u32 shift, mask, val;
1108
1109         val = readl_relaxed(&cpsw->regs->ptype);
1110
1111         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1112         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1113         mask = (1 << --fifo) << shift;
1114         val = on ? val | mask : val & ~mask;
1115
1116         writel_relaxed(val, &cpsw->regs->ptype);
1117 }
1118
1119 static void _cpsw_adjust_link(struct cpsw_slave *slave,
1120                               struct cpsw_priv *priv, bool *link)
1121 {
1122         struct phy_device       *phy = slave->phy;
1123         u32                     mac_control = 0;
1124         u32                     slave_port;
1125         struct cpsw_common *cpsw = priv->cpsw;
1126
1127         if (!phy)
1128                 return;
1129
1130         slave_port = cpsw_get_slave_port(slave->slave_num);
1131
1132         if (phy->link) {
1133                 mac_control = cpsw->data.mac_control;
1134
1135                 /* enable forwarding */
1136                 cpsw_ale_control_set(cpsw->ale, slave_port,
1137                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1138
1139                 if (phy->speed == 1000)
1140                         mac_control |= BIT(7);  /* GIGABITEN    */
1141                 if (phy->duplex)
1142                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
1143
1144                 /* set speed_in input in case RMII mode is used in 100Mbps */
1145                 if (phy->speed == 100)
1146                         mac_control |= BIT(15);
1147                 /* in band mode only works in 10Mbps RGMII mode */
1148                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1149                         mac_control |= BIT(18); /* In Band mode */
1150
1151                 if (priv->rx_pause)
1152                         mac_control |= BIT(3);
1153
1154                 if (priv->tx_pause)
1155                         mac_control |= BIT(4);
1156
1157                 *link = true;
1158
1159                 if (priv->shp_cfg_speed &&
1160                     priv->shp_cfg_speed != slave->phy->speed &&
1161                     !cpsw_shp_is_off(priv))
1162                         dev_warn(priv->dev,
1163                                  "Speed was changed, CBS shaper speeds are changed!");
1164         } else {
1165                 mac_control = 0;
1166                 /* disable forwarding */
1167                 cpsw_ale_control_set(cpsw->ale, slave_port,
1168                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1169         }
1170
1171         if (mac_control != slave->mac_control) {
1172                 phy_print_status(phy);
1173                 writel_relaxed(mac_control, &slave->sliver->mac_control);
1174         }
1175
1176         slave->mac_control = mac_control;
1177 }
1178
1179 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1180 {
1181         int i, speed;
1182
1183         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1184                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1185                         speed += cpsw->slaves[i].phy->speed;
1186
1187         return speed;
1188 }
1189
1190 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1191 {
1192         int i, rlim_ch_num;
1193         int speed, ch_rate;
1194
1195         /* re-split resources only in case speed was changed */
1196         speed = cpsw_get_common_speed(cpsw);
1197         if (speed == cpsw->speed || !speed)
1198                 return 0;
1199
1200         cpsw->speed = speed;
1201
1202         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1203                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1204                 if (!ch_rate)
1205                         break;
1206
1207                 rlim_ch_num++;
1208         }
1209
1210         /* cases not dependent on speed */
1211         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1212                 return 0;
1213
1214         return 1;
1215 }
1216
1217 static void cpsw_adjust_link(struct net_device *ndev)
1218 {
1219         struct cpsw_priv        *priv = netdev_priv(ndev);
1220         struct cpsw_common      *cpsw = priv->cpsw;
1221         bool                    link = false;
1222
1223         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1224
1225         if (link) {
1226                 if (cpsw_need_resplit(cpsw))
1227                         cpsw_split_res(ndev);
1228
1229                 netif_carrier_on(ndev);
1230                 if (netif_running(ndev))
1231                         netif_tx_wake_all_queues(ndev);
1232         } else {
1233                 netif_carrier_off(ndev);
1234                 netif_tx_stop_all_queues(ndev);
1235         }
1236 }
1237
1238 static int cpsw_get_coalesce(struct net_device *ndev,
1239                                 struct ethtool_coalesce *coal)
1240 {
1241         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1242
1243         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1244         return 0;
1245 }
1246
1247 static int cpsw_set_coalesce(struct net_device *ndev,
1248                                 struct ethtool_coalesce *coal)
1249 {
1250         struct cpsw_priv *priv = netdev_priv(ndev);
1251         u32 int_ctrl;
1252         u32 num_interrupts = 0;
1253         u32 prescale = 0;
1254         u32 addnl_dvdr = 1;
1255         u32 coal_intvl = 0;
1256         struct cpsw_common *cpsw = priv->cpsw;
1257
1258         coal_intvl = coal->rx_coalesce_usecs;
1259
1260         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1261         prescale = cpsw->bus_freq_mhz * 4;
1262
1263         if (!coal->rx_coalesce_usecs) {
1264                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1265                 goto update_return;
1266         }
1267
1268         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1269                 coal_intvl = CPSW_CMINTMIN_INTVL;
1270
1271         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1272                 /* Interrupt pacer works with 4us Pulse, we can
1273                  * throttle further by dilating the 4us pulse.
1274                  */
1275                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1276
1277                 if (addnl_dvdr > 1) {
1278                         prescale *= addnl_dvdr;
1279                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1280                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1281                                                 * addnl_dvdr);
1282                 } else {
1283                         addnl_dvdr = 1;
1284                         coal_intvl = CPSW_CMINTMAX_INTVL;
1285                 }
1286         }
1287
1288         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1289         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1290         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1291
1292         int_ctrl |= CPSW_INTPACEEN;
1293         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1294         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1295
1296 update_return:
1297         writel(int_ctrl, &cpsw->wr_regs->int_control);
1298
1299         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1300         cpsw->coal_intvl = coal_intvl;
1301
1302         return 0;
1303 }
1304
1305 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1306 {
1307         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1308
1309         switch (sset) {
1310         case ETH_SS_STATS:
1311                 return (CPSW_STATS_COMMON_LEN +
1312                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1313                        CPSW_STATS_CH_LEN);
1314         default:
1315                 return -EOPNOTSUPP;
1316         }
1317 }
1318
1319 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1320 {
1321         int ch_stats_len;
1322         int line;
1323         int i;
1324
1325         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1326         for (i = 0; i < ch_stats_len; i++) {
1327                 line = i % CPSW_STATS_CH_LEN;
1328                 snprintf(*p, ETH_GSTRING_LEN,
1329                          "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1330                          (long)(i / CPSW_STATS_CH_LEN),
1331                          cpsw_gstrings_ch_stats[line].stat_string);
1332                 *p += ETH_GSTRING_LEN;
1333         }
1334 }
1335
1336 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1337 {
1338         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1339         u8 *p = data;
1340         int i;
1341
1342         switch (stringset) {
1343         case ETH_SS_STATS:
1344                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1345                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1346                                ETH_GSTRING_LEN);
1347                         p += ETH_GSTRING_LEN;
1348                 }
1349
1350                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1351                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1352                 break;
1353         }
1354 }
1355
1356 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1357                                     struct ethtool_stats *stats, u64 *data)
1358 {
1359         u8 *p;
1360         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1361         struct cpdma_chan_stats ch_stats;
1362         int i, l, ch;
1363
1364         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1365         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1366                 data[l] = readl(cpsw->hw_stats +
1367                                 cpsw_gstrings_stats[l].stat_offset);
1368
1369         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1370                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1371                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1372                         p = (u8 *)&ch_stats +
1373                                 cpsw_gstrings_ch_stats[i].stat_offset;
1374                         data[l] = *(u32 *)p;
1375                 }
1376         }
1377
1378         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1379                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1380                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1381                         p = (u8 *)&ch_stats +
1382                                 cpsw_gstrings_ch_stats[i].stat_offset;
1383                         data[l] = *(u32 *)p;
1384                 }
1385         }
1386 }
1387
1388 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1389                                         struct sk_buff *skb,
1390                                         struct cpdma_chan *txch)
1391 {
1392         struct cpsw_common *cpsw = priv->cpsw;
1393
1394         skb_tx_timestamp(skb);
1395         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1396                                  priv->emac_port + cpsw->data.dual_emac);
1397 }
1398
1399 static inline void cpsw_add_dual_emac_def_ale_entries(
1400                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1401                 u32 slave_port)
1402 {
1403         struct cpsw_common *cpsw = priv->cpsw;
1404         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1405
1406         if (cpsw->version == CPSW_VERSION_1)
1407                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1408         else
1409                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1410         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1411                           port_mask, port_mask, 0);
1412         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1413                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1414         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1415                            HOST_PORT_NUM, ALE_VLAN |
1416                            ALE_SECURE, slave->port_vlan);
1417         cpsw_ale_control_set(cpsw->ale, slave_port,
1418                              ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1419 }
1420
1421 static void soft_reset_slave(struct cpsw_slave *slave)
1422 {
1423         char name[32];
1424
1425         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1426         soft_reset(name, &slave->sliver->soft_reset);
1427 }
1428
1429 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1430 {
1431         u32 slave_port;
1432         struct phy_device *phy;
1433         struct cpsw_common *cpsw = priv->cpsw;
1434
1435         soft_reset_slave(slave);
1436
1437         /* setup priority mapping */
1438         writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1439
1440         switch (cpsw->version) {
1441         case CPSW_VERSION_1:
1442                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1443                 /* Increase RX FIFO size to 5 for supporting fullduplex
1444                  * flow control mode
1445                  */
1446                 slave_write(slave,
1447                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1448                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1449                 break;
1450         case CPSW_VERSION_2:
1451         case CPSW_VERSION_3:
1452         case CPSW_VERSION_4:
1453                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1454                 /* Increase RX FIFO size to 5 for supporting fullduplex
1455                  * flow control mode
1456                  */
1457                 slave_write(slave,
1458                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1459                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1460                 break;
1461         }
1462
1463         /* setup max packet size, and mac address */
1464         writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1465         cpsw_set_slave_mac(slave, priv);
1466
1467         slave->mac_control = 0; /* no link yet */
1468
1469         slave_port = cpsw_get_slave_port(slave->slave_num);
1470
1471         if (cpsw->data.dual_emac)
1472                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1473         else
1474                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1475                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1476
1477         if (slave->data->phy_node) {
1478                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1479                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1480                 if (!phy) {
1481                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1482                                 slave->data->phy_node,
1483                                 slave->slave_num);
1484                         return;
1485                 }
1486         } else {
1487                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1488                                  &cpsw_adjust_link, slave->data->phy_if);
1489                 if (IS_ERR(phy)) {
1490                         dev_err(priv->dev,
1491                                 "phy \"%s\" not found on slave %d, err %ld\n",
1492                                 slave->data->phy_id, slave->slave_num,
1493                                 PTR_ERR(phy));
1494                         return;
1495                 }
1496         }
1497
1498         slave->phy = phy;
1499
1500         phy_attached_info(slave->phy);
1501
1502         phy_start(slave->phy);
1503
1504         /* Configure GMII_SEL register */
1505         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1506 }
1507
1508 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1509 {
1510         struct cpsw_common *cpsw = priv->cpsw;
1511         const int vlan = cpsw->data.default_vlan;
1512         u32 reg;
1513         int i;
1514         int unreg_mcast_mask;
1515
1516         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1517                CPSW2_PORT_VLAN;
1518
1519         writel(vlan, &cpsw->host_port_regs->port_vlan);
1520
1521         for (i = 0; i < cpsw->data.slaves; i++)
1522                 slave_write(cpsw->slaves + i, vlan, reg);
1523
1524         if (priv->ndev->flags & IFF_ALLMULTI)
1525                 unreg_mcast_mask = ALE_ALL_PORTS;
1526         else
1527                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1528
1529         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1530                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1531                           unreg_mcast_mask);
1532 }
1533
1534 static void cpsw_init_host_port(struct cpsw_priv *priv)
1535 {
1536         u32 fifo_mode;
1537         u32 control_reg;
1538         struct cpsw_common *cpsw = priv->cpsw;
1539
1540         /* soft reset the controller and initialize ale */
1541         soft_reset("cpsw", &cpsw->regs->soft_reset);
1542         cpsw_ale_start(cpsw->ale);
1543
1544         /* switch to vlan unaware mode */
1545         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1546                              CPSW_ALE_VLAN_AWARE);
1547         control_reg = readl(&cpsw->regs->control);
1548         control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
1549         writel(control_reg, &cpsw->regs->control);
1550         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1551                      CPSW_FIFO_NORMAL_MODE;
1552         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1553
1554         /* setup host port priority mapping */
1555         writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1556                        &cpsw->host_port_regs->cpdma_tx_pri_map);
1557         writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1558
1559         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1560                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1561
1562         if (!cpsw->data.dual_emac) {
1563                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1564                                    0, 0);
1565                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1566                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1567         }
1568 }
1569
1570 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1571 {
1572         struct cpsw_common *cpsw = priv->cpsw;
1573         struct sk_buff *skb;
1574         int ch_buf_num;
1575         int ch, i, ret;
1576
1577         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1578                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1579                 for (i = 0; i < ch_buf_num; i++) {
1580                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1581                                                           cpsw->rx_packet_max,
1582                                                           GFP_KERNEL);
1583                         if (!skb) {
1584                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1585                                 return -ENOMEM;
1586                         }
1587
1588                         skb_set_queue_mapping(skb, ch);
1589                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1590                                                 skb->data, skb_tailroom(skb),
1591                                                 0);
1592                         if (ret < 0) {
1593                                 cpsw_err(priv, ifup,
1594                                          "cannot submit skb to channel %d rx, error %d\n",
1595                                          ch, ret);
1596                                 kfree_skb(skb);
1597                                 return ret;
1598                         }
1599                         kmemleak_not_leak(skb);
1600                 }
1601
1602                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1603                           ch, ch_buf_num);
1604         }
1605
1606         return 0;
1607 }
1608
1609 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1610 {
1611         u32 slave_port;
1612
1613         slave_port = cpsw_get_slave_port(slave->slave_num);
1614
1615         if (!slave->phy)
1616                 return;
1617         phy_stop(slave->phy);
1618         phy_disconnect(slave->phy);
1619         slave->phy = NULL;
1620         cpsw_ale_control_set(cpsw->ale, slave_port,
1621                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1622         soft_reset_slave(slave);
1623 }
1624
1625 static int cpsw_tc_to_fifo(int tc, int num_tc)
1626 {
1627         if (tc == num_tc - 1)
1628                 return 0;
1629
1630         return CPSW_FIFO_SHAPERS_NUM - tc;
1631 }
1632
1633 static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw)
1634 {
1635         struct cpsw_common *cpsw = priv->cpsw;
1636         u32 val = 0, send_pct, shift;
1637         struct cpsw_slave *slave;
1638         int pct = 0, i;
1639
1640         if (bw > priv->shp_cfg_speed * 1000)
1641                 goto err;
1642
1643         /* shaping has to stay enabled for highest fifos linearly
1644          * and fifo bw no more then interface can allow
1645          */
1646         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1647         send_pct = slave_read(slave, SEND_PERCENT);
1648         for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) {
1649                 if (!bw) {
1650                         if (i >= fifo || !priv->fifo_bw[i])
1651                                 continue;
1652
1653                         dev_warn(priv->dev, "Prev FIFO%d is shaped", i);
1654                         continue;
1655                 }
1656
1657                 if (!priv->fifo_bw[i] && i > fifo) {
1658                         dev_err(priv->dev, "Upper FIFO%d is not shaped", i);
1659                         return -EINVAL;
1660                 }
1661
1662                 shift = (i - 1) * 8;
1663                 if (i == fifo) {
1664                         send_pct &= ~(CPSW_PCT_MASK << shift);
1665                         val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10);
1666                         if (!val)
1667                                 val = 1;
1668
1669                         send_pct |= val << shift;
1670                         pct += val;
1671                         continue;
1672                 }
1673
1674                 if (priv->fifo_bw[i])
1675                         pct += (send_pct >> shift) & CPSW_PCT_MASK;
1676         }
1677
1678         if (pct >= 100)
1679                 goto err;
1680
1681         slave_write(slave, send_pct, SEND_PERCENT);
1682         priv->fifo_bw[fifo] = bw;
1683
1684         dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo,
1685                  DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100));
1686
1687         return 0;
1688 err:
1689         dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration");
1690         return -EINVAL;
1691 }
1692
1693 static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw)
1694 {
1695         struct cpsw_common *cpsw = priv->cpsw;
1696         struct cpsw_slave *slave;
1697         u32 tx_in_ctl_rg, val;
1698         int ret;
1699
1700         ret = cpsw_set_fifo_bw(priv, fifo, bw);
1701         if (ret)
1702                 return ret;
1703
1704         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1705         tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
1706                        CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL;
1707
1708         if (!bw)
1709                 cpsw_fifo_shp_on(priv, fifo, bw);
1710
1711         val = slave_read(slave, tx_in_ctl_rg);
1712         if (cpsw_shp_is_off(priv)) {
1713                 /* disable FIFOs rate limited queues */
1714                 val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT);
1715
1716                 /* set type of FIFO queues to normal priority mode */
1717                 val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT);
1718
1719                 /* set type of FIFO queues to be rate limited */
1720                 if (bw)
1721                         val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT;
1722                 else
1723                         priv->shp_cfg_speed = 0;
1724         }
1725
1726         /* toggle a FIFO rate limited queue */
1727         if (bw)
1728                 val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1729         else
1730                 val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1731         slave_write(slave, val, tx_in_ctl_rg);
1732
1733         /* FIFO transmit shape enable */
1734         cpsw_fifo_shp_on(priv, fifo, bw);
1735         return 0;
1736 }
1737
1738 /* Defaults:
1739  * class A - prio 3
1740  * class B - prio 2
1741  * shaping for class A should be set first
1742  */
1743 static int cpsw_set_cbs(struct net_device *ndev,
1744                         struct tc_cbs_qopt_offload *qopt)
1745 {
1746         struct cpsw_priv *priv = netdev_priv(ndev);
1747         struct cpsw_common *cpsw = priv->cpsw;
1748         struct cpsw_slave *slave;
1749         int prev_speed = 0;
1750         int tc, ret, fifo;
1751         u32 bw = 0;
1752
1753         tc = netdev_txq_to_tc(priv->ndev, qopt->queue);
1754
1755         /* enable channels in backward order, as highest FIFOs must be rate
1756          * limited first and for compliance with CPDMA rate limited channels
1757          * that also used in bacward order. FIFO0 cannot be rate limited.
1758          */
1759         fifo = cpsw_tc_to_fifo(tc, ndev->num_tc);
1760         if (!fifo) {
1761                 dev_err(priv->dev, "Last tc%d can't be rate limited", tc);
1762                 return -EINVAL;
1763         }
1764
1765         /* do nothing, it's disabled anyway */
1766         if (!qopt->enable && !priv->fifo_bw[fifo])
1767                 return 0;
1768
1769         /* shapers can be set if link speed is known */
1770         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1771         if (slave->phy && slave->phy->link) {
1772                 if (priv->shp_cfg_speed &&
1773                     priv->shp_cfg_speed != slave->phy->speed)
1774                         prev_speed = priv->shp_cfg_speed;
1775
1776                 priv->shp_cfg_speed = slave->phy->speed;
1777         }
1778
1779         if (!priv->shp_cfg_speed) {
1780                 dev_err(priv->dev, "Link speed is not known");
1781                 return -1;
1782         }
1783
1784         ret = pm_runtime_get_sync(cpsw->dev);
1785         if (ret < 0) {
1786                 pm_runtime_put_noidle(cpsw->dev);
1787                 return ret;
1788         }
1789
1790         bw = qopt->enable ? qopt->idleslope : 0;
1791         ret = cpsw_set_fifo_rlimit(priv, fifo, bw);
1792         if (ret) {
1793                 priv->shp_cfg_speed = prev_speed;
1794                 prev_speed = 0;
1795         }
1796
1797         if (bw && prev_speed)
1798                 dev_warn(priv->dev,
1799                          "Speed was changed, CBS shaper speeds are changed!");
1800
1801         pm_runtime_put_sync(cpsw->dev);
1802         return ret;
1803 }
1804
1805 static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1806 {
1807         int fifo, bw;
1808
1809         for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) {
1810                 bw = priv->fifo_bw[fifo];
1811                 if (!bw)
1812                         continue;
1813
1814                 cpsw_set_fifo_rlimit(priv, fifo, bw);
1815         }
1816 }
1817
1818 static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1819 {
1820         struct cpsw_common *cpsw = priv->cpsw;
1821         u32 tx_prio_map = 0;
1822         int i, tc, fifo;
1823         u32 tx_prio_rg;
1824
1825         if (!priv->mqprio_hw)
1826                 return;
1827
1828         for (i = 0; i < 8; i++) {
1829                 tc = netdev_get_prio_tc_map(priv->ndev, i);
1830                 fifo = CPSW_FIFO_SHAPERS_NUM - tc;
1831                 tx_prio_map |= fifo << (4 * i);
1832         }
1833
1834         tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
1835                      CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
1836
1837         slave_write(slave, tx_prio_map, tx_prio_rg);
1838 }
1839
1840 /* restore resources after port reset */
1841 static void cpsw_restore(struct cpsw_priv *priv)
1842 {
1843         /* restore MQPRIO offload */
1844         for_each_slave(priv, cpsw_mqprio_resume, priv);
1845
1846         /* restore CBS offload */
1847         for_each_slave(priv, cpsw_cbs_resume, priv);
1848 }
1849
1850 static int cpsw_ndo_open(struct net_device *ndev)
1851 {
1852         struct cpsw_priv *priv = netdev_priv(ndev);
1853         struct cpsw_common *cpsw = priv->cpsw;
1854         int ret;
1855         u32 reg;
1856
1857         ret = pm_runtime_get_sync(cpsw->dev);
1858         if (ret < 0) {
1859                 pm_runtime_put_noidle(cpsw->dev);
1860                 return ret;
1861         }
1862
1863         netif_carrier_off(ndev);
1864
1865         /* Notify the stack of the actual queue counts. */
1866         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1867         if (ret) {
1868                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1869                 goto err_cleanup;
1870         }
1871
1872         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1873         if (ret) {
1874                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1875                 goto err_cleanup;
1876         }
1877
1878         reg = cpsw->version;
1879
1880         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1881                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1882                  CPSW_RTL_VERSION(reg));
1883
1884         /* Initialize host and slave ports */
1885         if (!cpsw->usage_count)
1886                 cpsw_init_host_port(priv);
1887         for_each_slave(priv, cpsw_slave_open, priv);
1888
1889         /* Add default VLAN */
1890         if (!cpsw->data.dual_emac)
1891                 cpsw_add_default_vlan(priv);
1892         else
1893                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1894                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1895
1896         /* initialize shared resources for every ndev */
1897         if (!cpsw->usage_count) {
1898                 /* disable priority elevation */
1899                 writel_relaxed(0, &cpsw->regs->ptype);
1900
1901                 /* enable statistics collection only on all ports */
1902                 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1903
1904                 /* Enable internal fifo flow control */
1905                 writel(0x7, &cpsw->regs->flow_control);
1906
1907                 napi_enable(&cpsw->napi_rx);
1908                 napi_enable(&cpsw->napi_tx);
1909
1910                 if (cpsw->tx_irq_disabled) {
1911                         cpsw->tx_irq_disabled = false;
1912                         enable_irq(cpsw->irqs_table[1]);
1913                 }
1914
1915                 if (cpsw->rx_irq_disabled) {
1916                         cpsw->rx_irq_disabled = false;
1917                         enable_irq(cpsw->irqs_table[0]);
1918                 }
1919
1920                 ret = cpsw_fill_rx_channels(priv);
1921                 if (ret < 0)
1922                         goto err_cleanup;
1923
1924                 if (cpts_register(cpsw->cpts))
1925                         dev_err(priv->dev, "error registering cpts device\n");
1926
1927         }
1928
1929         cpsw_restore(priv);
1930
1931         /* Enable Interrupt pacing if configured */
1932         if (cpsw->coal_intvl != 0) {
1933                 struct ethtool_coalesce coal;
1934
1935                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1936                 cpsw_set_coalesce(ndev, &coal);
1937         }
1938
1939         cpdma_ctlr_start(cpsw->dma);
1940         cpsw_intr_enable(cpsw);
1941         cpsw->usage_count++;
1942
1943         return 0;
1944
1945 err_cleanup:
1946         cpdma_ctlr_stop(cpsw->dma);
1947         for_each_slave(priv, cpsw_slave_stop, cpsw);
1948         pm_runtime_put_sync(cpsw->dev);
1949         netif_carrier_off(priv->ndev);
1950         return ret;
1951 }
1952
1953 static int cpsw_ndo_stop(struct net_device *ndev)
1954 {
1955         struct cpsw_priv *priv = netdev_priv(ndev);
1956         struct cpsw_common *cpsw = priv->cpsw;
1957
1958         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1959         netif_tx_stop_all_queues(priv->ndev);
1960         netif_carrier_off(priv->ndev);
1961
1962         if (cpsw->usage_count <= 1) {
1963                 napi_disable(&cpsw->napi_rx);
1964                 napi_disable(&cpsw->napi_tx);
1965                 cpts_unregister(cpsw->cpts);
1966                 cpsw_intr_disable(cpsw);
1967                 cpdma_ctlr_stop(cpsw->dma);
1968                 cpsw_ale_stop(cpsw->ale);
1969         }
1970         for_each_slave(priv, cpsw_slave_stop, cpsw);
1971
1972         if (cpsw_need_resplit(cpsw))
1973                 cpsw_split_res(ndev);
1974
1975         cpsw->usage_count--;
1976         pm_runtime_put_sync(cpsw->dev);
1977         return 0;
1978 }
1979
1980 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1981                                        struct net_device *ndev)
1982 {
1983         struct cpsw_priv *priv = netdev_priv(ndev);
1984         struct cpsw_common *cpsw = priv->cpsw;
1985         struct cpts *cpts = cpsw->cpts;
1986         struct netdev_queue *txq;
1987         struct cpdma_chan *txch;
1988         int ret, q_idx;
1989
1990         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1991                 cpsw_err(priv, tx_err, "packet pad failed\n");
1992                 ndev->stats.tx_dropped++;
1993                 return NET_XMIT_DROP;
1994         }
1995
1996         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1997             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1998                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1999
2000         q_idx = skb_get_queue_mapping(skb);
2001         if (q_idx >= cpsw->tx_ch_num)
2002                 q_idx = q_idx % cpsw->tx_ch_num;
2003
2004         txch = cpsw->txv[q_idx].ch;
2005         txq = netdev_get_tx_queue(ndev, q_idx);
2006         ret = cpsw_tx_packet_submit(priv, skb, txch);
2007         if (unlikely(ret != 0)) {
2008                 cpsw_err(priv, tx_err, "desc submit failed\n");
2009                 goto fail;
2010         }
2011
2012         /* If there is no more tx desc left free then we need to
2013          * tell the kernel to stop sending us tx frames.
2014          */
2015         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
2016                 netif_tx_stop_queue(txq);
2017
2018                 /* Barrier, so that stop_queue visible to other cpus */
2019                 smp_mb__after_atomic();
2020
2021                 if (cpdma_check_free_tx_desc(txch))
2022                         netif_tx_wake_queue(txq);
2023         }
2024
2025         return NETDEV_TX_OK;
2026 fail:
2027         ndev->stats.tx_dropped++;
2028         netif_tx_stop_queue(txq);
2029
2030         /* Barrier, so that stop_queue visible to other cpus */
2031         smp_mb__after_atomic();
2032
2033         if (cpdma_check_free_tx_desc(txch))
2034                 netif_tx_wake_queue(txq);
2035
2036         return NETDEV_TX_BUSY;
2037 }
2038
2039 #if IS_ENABLED(CONFIG_TI_CPTS)
2040
2041 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
2042 {
2043         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2044         u32 ts_en, seq_id;
2045
2046         if (!cpts_is_tx_enabled(cpsw->cpts) &&
2047             !cpts_is_rx_enabled(cpsw->cpts)) {
2048                 slave_write(slave, 0, CPSW1_TS_CTL);
2049                 return;
2050         }
2051
2052         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2053         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
2054
2055         if (cpts_is_tx_enabled(cpsw->cpts))
2056                 ts_en |= CPSW_V1_TS_TX_EN;
2057
2058         if (cpts_is_rx_enabled(cpsw->cpts))
2059                 ts_en |= CPSW_V1_TS_RX_EN;
2060
2061         slave_write(slave, ts_en, CPSW1_TS_CTL);
2062         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
2063 }
2064
2065 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
2066 {
2067         struct cpsw_slave *slave;
2068         struct cpsw_common *cpsw = priv->cpsw;
2069         u32 ctrl, mtype;
2070
2071         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2072
2073         ctrl = slave_read(slave, CPSW2_CONTROL);
2074         switch (cpsw->version) {
2075         case CPSW_VERSION_2:
2076                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2077
2078                 if (cpts_is_tx_enabled(cpsw->cpts))
2079                         ctrl |= CTRL_V2_TX_TS_BITS;
2080
2081                 if (cpts_is_rx_enabled(cpsw->cpts))
2082                         ctrl |= CTRL_V2_RX_TS_BITS;
2083                 break;
2084         case CPSW_VERSION_3:
2085         default:
2086                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
2087
2088                 if (cpts_is_tx_enabled(cpsw->cpts))
2089                         ctrl |= CTRL_V3_TX_TS_BITS;
2090
2091                 if (cpts_is_rx_enabled(cpsw->cpts))
2092                         ctrl |= CTRL_V3_RX_TS_BITS;
2093                 break;
2094         }
2095
2096         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
2097
2098         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
2099         slave_write(slave, ctrl, CPSW2_CONTROL);
2100         writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
2101 }
2102
2103 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2104 {
2105         struct cpsw_priv *priv = netdev_priv(dev);
2106         struct hwtstamp_config cfg;
2107         struct cpsw_common *cpsw = priv->cpsw;
2108         struct cpts *cpts = cpsw->cpts;
2109
2110         if (cpsw->version != CPSW_VERSION_1 &&
2111             cpsw->version != CPSW_VERSION_2 &&
2112             cpsw->version != CPSW_VERSION_3)
2113                 return -EOPNOTSUPP;
2114
2115         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2116                 return -EFAULT;
2117
2118         /* reserved for future extensions */
2119         if (cfg.flags)
2120                 return -EINVAL;
2121
2122         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2123                 return -ERANGE;
2124
2125         switch (cfg.rx_filter) {
2126         case HWTSTAMP_FILTER_NONE:
2127                 cpts_rx_enable(cpts, 0);
2128                 break;
2129         case HWTSTAMP_FILTER_ALL:
2130         case HWTSTAMP_FILTER_NTP_ALL:
2131                 return -ERANGE;
2132         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2133         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2134         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2135                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
2136                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2137                 break;
2138         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2139         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2140         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2141         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2142         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2143         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2144         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2145         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2146         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2147                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
2148                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2149                 break;
2150         default:
2151                 return -ERANGE;
2152         }
2153
2154         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
2155
2156         switch (cpsw->version) {
2157         case CPSW_VERSION_1:
2158                 cpsw_hwtstamp_v1(cpsw);
2159                 break;
2160         case CPSW_VERSION_2:
2161         case CPSW_VERSION_3:
2162                 cpsw_hwtstamp_v2(priv);
2163                 break;
2164         default:
2165                 WARN_ON(1);
2166         }
2167
2168         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2169 }
2170
2171 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2172 {
2173         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
2174         struct cpts *cpts = cpsw->cpts;
2175         struct hwtstamp_config cfg;
2176
2177         if (cpsw->version != CPSW_VERSION_1 &&
2178             cpsw->version != CPSW_VERSION_2 &&
2179             cpsw->version != CPSW_VERSION_3)
2180                 return -EOPNOTSUPP;
2181
2182         cfg.flags = 0;
2183         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
2184                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2185         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
2186                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
2187
2188         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2189 }
2190 #else
2191 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2192 {
2193         return -EOPNOTSUPP;
2194 }
2195
2196 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2197 {
2198         return -EOPNOTSUPP;
2199 }
2200 #endif /*CONFIG_TI_CPTS*/
2201
2202 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2203 {
2204         struct cpsw_priv *priv = netdev_priv(dev);
2205         struct cpsw_common *cpsw = priv->cpsw;
2206         int slave_no = cpsw_slave_index(cpsw, priv);
2207
2208         if (!netif_running(dev))
2209                 return -EINVAL;
2210
2211         switch (cmd) {
2212         case SIOCSHWTSTAMP:
2213                 return cpsw_hwtstamp_set(dev, req);
2214         case SIOCGHWTSTAMP:
2215                 return cpsw_hwtstamp_get(dev, req);
2216         }
2217
2218         if (!cpsw->slaves[slave_no].phy)
2219                 return -EOPNOTSUPP;
2220         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2221 }
2222
2223 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
2224 {
2225         struct cpsw_priv *priv = netdev_priv(ndev);
2226         struct cpsw_common *cpsw = priv->cpsw;
2227         int ch;
2228
2229         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
2230         ndev->stats.tx_errors++;
2231         cpsw_intr_disable(cpsw);
2232         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
2233                 cpdma_chan_stop(cpsw->txv[ch].ch);
2234                 cpdma_chan_start(cpsw->txv[ch].ch);
2235         }
2236
2237         cpsw_intr_enable(cpsw);
2238         netif_trans_update(ndev);
2239         netif_tx_wake_all_queues(ndev);
2240 }
2241
2242 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
2243 {
2244         struct cpsw_priv *priv = netdev_priv(ndev);
2245         struct sockaddr *addr = (struct sockaddr *)p;
2246         struct cpsw_common *cpsw = priv->cpsw;
2247         int flags = 0;
2248         u16 vid = 0;
2249         int ret;
2250
2251         if (!is_valid_ether_addr(addr->sa_data))
2252                 return -EADDRNOTAVAIL;
2253
2254         ret = pm_runtime_get_sync(cpsw->dev);
2255         if (ret < 0) {
2256                 pm_runtime_put_noidle(cpsw->dev);
2257                 return ret;
2258         }
2259
2260         if (cpsw->data.dual_emac) {
2261                 vid = cpsw->slaves[priv->emac_port].port_vlan;
2262                 flags = ALE_VLAN;
2263         }
2264
2265         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
2266                            flags, vid);
2267         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
2268                            flags, vid);
2269
2270         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
2271         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2272         for_each_slave(priv, cpsw_set_slave_mac, priv);
2273
2274         pm_runtime_put(cpsw->dev);
2275
2276         return 0;
2277 }
2278
2279 #ifdef CONFIG_NET_POLL_CONTROLLER
2280 static void cpsw_ndo_poll_controller(struct net_device *ndev)
2281 {
2282         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2283
2284         cpsw_intr_disable(cpsw);
2285         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2286         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2287         cpsw_intr_enable(cpsw);
2288 }
2289 #endif
2290
2291 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2292                                 unsigned short vid)
2293 {
2294         int ret;
2295         int unreg_mcast_mask = 0;
2296         u32 port_mask;
2297         struct cpsw_common *cpsw = priv->cpsw;
2298
2299         if (cpsw->data.dual_emac) {
2300                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
2301
2302                 if (priv->ndev->flags & IFF_ALLMULTI)
2303                         unreg_mcast_mask = port_mask;
2304         } else {
2305                 port_mask = ALE_ALL_PORTS;
2306
2307                 if (priv->ndev->flags & IFF_ALLMULTI)
2308                         unreg_mcast_mask = ALE_ALL_PORTS;
2309                 else
2310                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
2311         }
2312
2313         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
2314                                 unreg_mcast_mask);
2315         if (ret != 0)
2316                 return ret;
2317
2318         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
2319                                  HOST_PORT_NUM, ALE_VLAN, vid);
2320         if (ret != 0)
2321                 goto clean_vid;
2322
2323         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
2324                                  port_mask, ALE_VLAN, vid, 0);
2325         if (ret != 0)
2326                 goto clean_vlan_ucast;
2327         return 0;
2328
2329 clean_vlan_ucast:
2330         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2331                            HOST_PORT_NUM, ALE_VLAN, vid);
2332 clean_vid:
2333         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2334         return ret;
2335 }
2336
2337 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
2338                                     __be16 proto, u16 vid)
2339 {
2340         struct cpsw_priv *priv = netdev_priv(ndev);
2341         struct cpsw_common *cpsw = priv->cpsw;
2342         int ret;
2343
2344         if (vid == cpsw->data.default_vlan)
2345                 return 0;
2346
2347         ret = pm_runtime_get_sync(cpsw->dev);
2348         if (ret < 0) {
2349                 pm_runtime_put_noidle(cpsw->dev);
2350                 return ret;
2351         }
2352
2353         if (cpsw->data.dual_emac) {
2354                 /* In dual EMAC, reserved VLAN id should not be used for
2355                  * creating VLAN interfaces as this can break the dual
2356                  * EMAC port separation
2357                  */
2358                 int i;
2359
2360                 for (i = 0; i < cpsw->data.slaves; i++) {
2361                         if (vid == cpsw->slaves[i].port_vlan) {
2362                                 ret = -EINVAL;
2363                                 goto err;
2364                         }
2365                 }
2366         }
2367
2368         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2369         ret = cpsw_add_vlan_ale_entry(priv, vid);
2370 err:
2371         pm_runtime_put(cpsw->dev);
2372         return ret;
2373 }
2374
2375 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2376                                      __be16 proto, u16 vid)
2377 {
2378         struct cpsw_priv *priv = netdev_priv(ndev);
2379         struct cpsw_common *cpsw = priv->cpsw;
2380         int ret;
2381
2382         if (vid == cpsw->data.default_vlan)
2383                 return 0;
2384
2385         ret = pm_runtime_get_sync(cpsw->dev);
2386         if (ret < 0) {
2387                 pm_runtime_put_noidle(cpsw->dev);
2388                 return ret;
2389         }
2390
2391         if (cpsw->data.dual_emac) {
2392                 int i;
2393
2394                 for (i = 0; i < cpsw->data.slaves; i++) {
2395                         if (vid == cpsw->slaves[i].port_vlan)
2396                                 goto err;
2397                 }
2398         }
2399
2400         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2401         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2402         ret |= cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2403                                   HOST_PORT_NUM, ALE_VLAN, vid);
2404         ret |= cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2405                                   0, ALE_VLAN, vid);
2406 err:
2407         pm_runtime_put(cpsw->dev);
2408         return ret;
2409 }
2410
2411 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2412 {
2413         struct cpsw_priv *priv = netdev_priv(ndev);
2414         struct cpsw_common *cpsw = priv->cpsw;
2415         struct cpsw_slave *slave;
2416         u32 min_rate;
2417         u32 ch_rate;
2418         int i, ret;
2419
2420         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2421         if (ch_rate == rate)
2422                 return 0;
2423
2424         ch_rate = rate * 1000;
2425         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2426         if ((ch_rate < min_rate && ch_rate)) {
2427                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2428                         min_rate);
2429                 return -EINVAL;
2430         }
2431
2432         if (rate > cpsw->speed) {
2433                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2434                 return -EINVAL;
2435         }
2436
2437         ret = pm_runtime_get_sync(cpsw->dev);
2438         if (ret < 0) {
2439                 pm_runtime_put_noidle(cpsw->dev);
2440                 return ret;
2441         }
2442
2443         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2444         pm_runtime_put(cpsw->dev);
2445
2446         if (ret)
2447                 return ret;
2448
2449         /* update rates for slaves tx queues */
2450         for (i = 0; i < cpsw->data.slaves; i++) {
2451                 slave = &cpsw->slaves[i];
2452                 if (!slave->ndev)
2453                         continue;
2454
2455                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2456         }
2457
2458         cpsw_split_res(ndev);
2459         return ret;
2460 }
2461
2462 static int cpsw_set_mqprio(struct net_device *ndev, void *type_data)
2463 {
2464         struct tc_mqprio_qopt_offload *mqprio = type_data;
2465         struct cpsw_priv *priv = netdev_priv(ndev);
2466         struct cpsw_common *cpsw = priv->cpsw;
2467         int fifo, num_tc, count, offset;
2468         struct cpsw_slave *slave;
2469         u32 tx_prio_map = 0;
2470         int i, tc, ret;
2471
2472         num_tc = mqprio->qopt.num_tc;
2473         if (num_tc > CPSW_TC_NUM)
2474                 return -EINVAL;
2475
2476         if (mqprio->mode != TC_MQPRIO_MODE_DCB)
2477                 return -EINVAL;
2478
2479         ret = pm_runtime_get_sync(cpsw->dev);
2480         if (ret < 0) {
2481                 pm_runtime_put_noidle(cpsw->dev);
2482                 return ret;
2483         }
2484
2485         if (num_tc) {
2486                 for (i = 0; i < 8; i++) {
2487                         tc = mqprio->qopt.prio_tc_map[i];
2488                         fifo = cpsw_tc_to_fifo(tc, num_tc);
2489                         tx_prio_map |= fifo << (4 * i);
2490                 }
2491
2492                 netdev_set_num_tc(ndev, num_tc);
2493                 for (i = 0; i < num_tc; i++) {
2494                         count = mqprio->qopt.count[i];
2495                         offset = mqprio->qopt.offset[i];
2496                         netdev_set_tc_queue(ndev, i, count, offset);
2497                 }
2498         }
2499
2500         if (!mqprio->qopt.hw) {
2501                 /* restore default configuration */
2502                 netdev_reset_tc(ndev);
2503                 tx_prio_map = TX_PRIORITY_MAPPING;
2504         }
2505
2506         priv->mqprio_hw = mqprio->qopt.hw;
2507
2508         offset = cpsw->version == CPSW_VERSION_1 ?
2509                  CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
2510
2511         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2512         slave_write(slave, tx_prio_map, offset);
2513
2514         pm_runtime_put_sync(cpsw->dev);
2515
2516         return 0;
2517 }
2518
2519 static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
2520                              void *type_data)
2521 {
2522         switch (type) {
2523         case TC_SETUP_QDISC_CBS:
2524                 return cpsw_set_cbs(ndev, type_data);
2525
2526         case TC_SETUP_QDISC_MQPRIO:
2527                 return cpsw_set_mqprio(ndev, type_data);
2528
2529         default:
2530                 return -EOPNOTSUPP;
2531         }
2532 }
2533
2534 static const struct net_device_ops cpsw_netdev_ops = {
2535         .ndo_open               = cpsw_ndo_open,
2536         .ndo_stop               = cpsw_ndo_stop,
2537         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2538         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2539         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2540         .ndo_validate_addr      = eth_validate_addr,
2541         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2542         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2543         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2544 #ifdef CONFIG_NET_POLL_CONTROLLER
2545         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2546 #endif
2547         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2548         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2549         .ndo_setup_tc           = cpsw_ndo_setup_tc,
2550 };
2551
2552 static int cpsw_get_regs_len(struct net_device *ndev)
2553 {
2554         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2555
2556         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2557 }
2558
2559 static void cpsw_get_regs(struct net_device *ndev,
2560                           struct ethtool_regs *regs, void *p)
2561 {
2562         u32 *reg = p;
2563         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2564
2565         /* update CPSW IP version */
2566         regs->version = cpsw->version;
2567
2568         cpsw_ale_dump(cpsw->ale, reg);
2569 }
2570
2571 static void cpsw_get_drvinfo(struct net_device *ndev,
2572                              struct ethtool_drvinfo *info)
2573 {
2574         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2575         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2576
2577         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2578         strlcpy(info->version, "1.0", sizeof(info->version));
2579         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2580 }
2581
2582 static u32 cpsw_get_msglevel(struct net_device *ndev)
2583 {
2584         struct cpsw_priv *priv = netdev_priv(ndev);
2585         return priv->msg_enable;
2586 }
2587
2588 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2589 {
2590         struct cpsw_priv *priv = netdev_priv(ndev);
2591         priv->msg_enable = value;
2592 }
2593
2594 #if IS_ENABLED(CONFIG_TI_CPTS)
2595 static int cpsw_get_ts_info(struct net_device *ndev,
2596                             struct ethtool_ts_info *info)
2597 {
2598         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2599
2600         info->so_timestamping =
2601                 SOF_TIMESTAMPING_TX_HARDWARE |
2602                 SOF_TIMESTAMPING_TX_SOFTWARE |
2603                 SOF_TIMESTAMPING_RX_HARDWARE |
2604                 SOF_TIMESTAMPING_RX_SOFTWARE |
2605                 SOF_TIMESTAMPING_SOFTWARE |
2606                 SOF_TIMESTAMPING_RAW_HARDWARE;
2607         info->phc_index = cpsw->cpts->phc_index;
2608         info->tx_types =
2609                 (1 << HWTSTAMP_TX_OFF) |
2610                 (1 << HWTSTAMP_TX_ON);
2611         info->rx_filters =
2612                 (1 << HWTSTAMP_FILTER_NONE) |
2613                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2614                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2615         return 0;
2616 }
2617 #else
2618 static int cpsw_get_ts_info(struct net_device *ndev,
2619                             struct ethtool_ts_info *info)
2620 {
2621         info->so_timestamping =
2622                 SOF_TIMESTAMPING_TX_SOFTWARE |
2623                 SOF_TIMESTAMPING_RX_SOFTWARE |
2624                 SOF_TIMESTAMPING_SOFTWARE;
2625         info->phc_index = -1;
2626         info->tx_types = 0;
2627         info->rx_filters = 0;
2628         return 0;
2629 }
2630 #endif
2631
2632 static int cpsw_get_link_ksettings(struct net_device *ndev,
2633                                    struct ethtool_link_ksettings *ecmd)
2634 {
2635         struct cpsw_priv *priv = netdev_priv(ndev);
2636         struct cpsw_common *cpsw = priv->cpsw;
2637         int slave_no = cpsw_slave_index(cpsw, priv);
2638
2639         if (!cpsw->slaves[slave_no].phy)
2640                 return -EOPNOTSUPP;
2641
2642         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2643         return 0;
2644 }
2645
2646 static int cpsw_set_link_ksettings(struct net_device *ndev,
2647                                    const struct ethtool_link_ksettings *ecmd)
2648 {
2649         struct cpsw_priv *priv = netdev_priv(ndev);
2650         struct cpsw_common *cpsw = priv->cpsw;
2651         int slave_no = cpsw_slave_index(cpsw, priv);
2652
2653         if (cpsw->slaves[slave_no].phy)
2654                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2655                                                  ecmd);
2656         else
2657                 return -EOPNOTSUPP;
2658 }
2659
2660 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2661 {
2662         struct cpsw_priv *priv = netdev_priv(ndev);
2663         struct cpsw_common *cpsw = priv->cpsw;
2664         int slave_no = cpsw_slave_index(cpsw, priv);
2665
2666         wol->supported = 0;
2667         wol->wolopts = 0;
2668
2669         if (cpsw->slaves[slave_no].phy)
2670                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2671 }
2672
2673 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2674 {
2675         struct cpsw_priv *priv = netdev_priv(ndev);
2676         struct cpsw_common *cpsw = priv->cpsw;
2677         int slave_no = cpsw_slave_index(cpsw, priv);
2678
2679         if (cpsw->slaves[slave_no].phy)
2680                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2681         else
2682                 return -EOPNOTSUPP;
2683 }
2684
2685 static void cpsw_get_pauseparam(struct net_device *ndev,
2686                                 struct ethtool_pauseparam *pause)
2687 {
2688         struct cpsw_priv *priv = netdev_priv(ndev);
2689
2690         pause->autoneg = AUTONEG_DISABLE;
2691         pause->rx_pause = priv->rx_pause ? true : false;
2692         pause->tx_pause = priv->tx_pause ? true : false;
2693 }
2694
2695 static int cpsw_set_pauseparam(struct net_device *ndev,
2696                                struct ethtool_pauseparam *pause)
2697 {
2698         struct cpsw_priv *priv = netdev_priv(ndev);
2699         bool link;
2700
2701         priv->rx_pause = pause->rx_pause ? true : false;
2702         priv->tx_pause = pause->tx_pause ? true : false;
2703
2704         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2705         return 0;
2706 }
2707
2708 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2709 {
2710         struct cpsw_priv *priv = netdev_priv(ndev);
2711         struct cpsw_common *cpsw = priv->cpsw;
2712         int ret;
2713
2714         ret = pm_runtime_get_sync(cpsw->dev);
2715         if (ret < 0) {
2716                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2717                 pm_runtime_put_noidle(cpsw->dev);
2718         }
2719
2720         return ret;
2721 }
2722
2723 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2724 {
2725         struct cpsw_priv *priv = netdev_priv(ndev);
2726         int ret;
2727
2728         ret = pm_runtime_put(priv->cpsw->dev);
2729         if (ret < 0)
2730                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2731 }
2732
2733 static void cpsw_get_channels(struct net_device *ndev,
2734                               struct ethtool_channels *ch)
2735 {
2736         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2737
2738         ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2739         ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2740         ch->max_combined = 0;
2741         ch->max_other = 0;
2742         ch->other_count = 0;
2743         ch->rx_count = cpsw->rx_ch_num;
2744         ch->tx_count = cpsw->tx_ch_num;
2745         ch->combined_count = 0;
2746 }
2747
2748 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2749                                   struct ethtool_channels *ch)
2750 {
2751         if (cpsw->quirk_irq) {
2752                 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2753                 return -EOPNOTSUPP;
2754         }
2755
2756         if (ch->combined_count)
2757                 return -EINVAL;
2758
2759         /* verify we have at least one channel in each direction */
2760         if (!ch->rx_count || !ch->tx_count)
2761                 return -EINVAL;
2762
2763         if (ch->rx_count > cpsw->data.channels ||
2764             ch->tx_count > cpsw->data.channels)
2765                 return -EINVAL;
2766
2767         return 0;
2768 }
2769
2770 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2771 {
2772         struct cpsw_common *cpsw = priv->cpsw;
2773         void (*handler)(void *, int, int);
2774         struct netdev_queue *queue;
2775         struct cpsw_vector *vec;
2776         int ret, *ch, vch;
2777
2778         if (rx) {
2779                 ch = &cpsw->rx_ch_num;
2780                 vec = cpsw->rxv;
2781                 handler = cpsw_rx_handler;
2782         } else {
2783                 ch = &cpsw->tx_ch_num;
2784                 vec = cpsw->txv;
2785                 handler = cpsw_tx_handler;
2786         }
2787
2788         while (*ch < ch_num) {
2789                 vch = rx ? *ch : 7 - *ch;
2790                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
2791                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2792                 queue->tx_maxrate = 0;
2793
2794                 if (IS_ERR(vec[*ch].ch))
2795                         return PTR_ERR(vec[*ch].ch);
2796
2797                 if (!vec[*ch].ch)
2798                         return -EINVAL;
2799
2800                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2801                           (rx ? "rx" : "tx"));
2802                 (*ch)++;
2803         }
2804
2805         while (*ch > ch_num) {
2806                 (*ch)--;
2807
2808                 ret = cpdma_chan_destroy(vec[*ch].ch);
2809                 if (ret)
2810                         return ret;
2811
2812                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2813                           (rx ? "rx" : "tx"));
2814         }
2815
2816         return 0;
2817 }
2818
2819 static int cpsw_update_channels(struct cpsw_priv *priv,
2820                                 struct ethtool_channels *ch)
2821 {
2822         int ret;
2823
2824         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2825         if (ret)
2826                 return ret;
2827
2828         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2829         if (ret)
2830                 return ret;
2831
2832         return 0;
2833 }
2834
2835 static void cpsw_suspend_data_pass(struct net_device *ndev)
2836 {
2837         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2838         struct cpsw_slave *slave;
2839         int i;
2840
2841         /* Disable NAPI scheduling */
2842         cpsw_intr_disable(cpsw);
2843
2844         /* Stop all transmit queues for every network device.
2845          * Disable re-using rx descriptors with dormant_on.
2846          */
2847         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2848                 if (!(slave->ndev && netif_running(slave->ndev)))
2849                         continue;
2850
2851                 netif_tx_stop_all_queues(slave->ndev);
2852                 netif_dormant_on(slave->ndev);
2853         }
2854
2855         /* Handle rest of tx packets and stop cpdma channels */
2856         cpdma_ctlr_stop(cpsw->dma);
2857 }
2858
2859 static int cpsw_resume_data_pass(struct net_device *ndev)
2860 {
2861         struct cpsw_priv *priv = netdev_priv(ndev);
2862         struct cpsw_common *cpsw = priv->cpsw;
2863         struct cpsw_slave *slave;
2864         int i, ret;
2865
2866         /* Allow rx packets handling */
2867         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2868                 if (slave->ndev && netif_running(slave->ndev))
2869                         netif_dormant_off(slave->ndev);
2870
2871         /* After this receive is started */
2872         if (cpsw->usage_count) {
2873                 ret = cpsw_fill_rx_channels(priv);
2874                 if (ret)
2875                         return ret;
2876
2877                 cpdma_ctlr_start(cpsw->dma);
2878                 cpsw_intr_enable(cpsw);
2879         }
2880
2881         /* Resume transmit for every affected interface */
2882         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2883                 if (slave->ndev && netif_running(slave->ndev))
2884                         netif_tx_start_all_queues(slave->ndev);
2885
2886         return 0;
2887 }
2888
2889 static int cpsw_set_channels(struct net_device *ndev,
2890                              struct ethtool_channels *chs)
2891 {
2892         struct cpsw_priv *priv = netdev_priv(ndev);
2893         struct cpsw_common *cpsw = priv->cpsw;
2894         struct cpsw_slave *slave;
2895         int i, ret;
2896
2897         ret = cpsw_check_ch_settings(cpsw, chs);
2898         if (ret < 0)
2899                 return ret;
2900
2901         cpsw_suspend_data_pass(ndev);
2902         ret = cpsw_update_channels(priv, chs);
2903         if (ret)
2904                 goto err;
2905
2906         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2907                 if (!(slave->ndev && netif_running(slave->ndev)))
2908                         continue;
2909
2910                 /* Inform stack about new count of queues */
2911                 ret = netif_set_real_num_tx_queues(slave->ndev,
2912                                                    cpsw->tx_ch_num);
2913                 if (ret) {
2914                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2915                         goto err;
2916                 }
2917
2918                 ret = netif_set_real_num_rx_queues(slave->ndev,
2919                                                    cpsw->rx_ch_num);
2920                 if (ret) {
2921                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2922                         goto err;
2923                 }
2924         }
2925
2926         if (cpsw->usage_count)
2927                 cpsw_split_res(ndev);
2928
2929         ret = cpsw_resume_data_pass(ndev);
2930         if (!ret)
2931                 return 0;
2932 err:
2933         dev_err(priv->dev, "cannot update channels number, closing device\n");
2934         dev_close(ndev);
2935         return ret;
2936 }
2937
2938 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2939 {
2940         struct cpsw_priv *priv = netdev_priv(ndev);
2941         struct cpsw_common *cpsw = priv->cpsw;
2942         int slave_no = cpsw_slave_index(cpsw, priv);
2943
2944         if (cpsw->slaves[slave_no].phy)
2945                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2946         else
2947                 return -EOPNOTSUPP;
2948 }
2949
2950 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2951 {
2952         struct cpsw_priv *priv = netdev_priv(ndev);
2953         struct cpsw_common *cpsw = priv->cpsw;
2954         int slave_no = cpsw_slave_index(cpsw, priv);
2955
2956         if (cpsw->slaves[slave_no].phy)
2957                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2958         else
2959                 return -EOPNOTSUPP;
2960 }
2961
2962 static int cpsw_nway_reset(struct net_device *ndev)
2963 {
2964         struct cpsw_priv *priv = netdev_priv(ndev);
2965         struct cpsw_common *cpsw = priv->cpsw;
2966         int slave_no = cpsw_slave_index(cpsw, priv);
2967
2968         if (cpsw->slaves[slave_no].phy)
2969                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2970         else
2971                 return -EOPNOTSUPP;
2972 }
2973
2974 static void cpsw_get_ringparam(struct net_device *ndev,
2975                                struct ethtool_ringparam *ering)
2976 {
2977         struct cpsw_priv *priv = netdev_priv(ndev);
2978         struct cpsw_common *cpsw = priv->cpsw;
2979
2980         /* not supported */
2981         ering->tx_max_pending = 0;
2982         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2983         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2984         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2985 }
2986
2987 static int cpsw_set_ringparam(struct net_device *ndev,
2988                               struct ethtool_ringparam *ering)
2989 {
2990         struct cpsw_priv *priv = netdev_priv(ndev);
2991         struct cpsw_common *cpsw = priv->cpsw;
2992         int ret;
2993
2994         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2995
2996         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2997             ering->rx_pending < CPSW_MAX_QUEUES ||
2998             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2999                 return -EINVAL;
3000
3001         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
3002                 return 0;
3003
3004         cpsw_suspend_data_pass(ndev);
3005
3006         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
3007
3008         if (cpsw->usage_count)
3009                 cpdma_chan_split_pool(cpsw->dma);
3010
3011         ret = cpsw_resume_data_pass(ndev);
3012         if (!ret)
3013                 return 0;
3014
3015         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
3016         dev_close(ndev);
3017         return ret;
3018 }
3019
3020 static const struct ethtool_ops cpsw_ethtool_ops = {
3021         .get_drvinfo    = cpsw_get_drvinfo,
3022         .get_msglevel   = cpsw_get_msglevel,
3023         .set_msglevel   = cpsw_set_msglevel,
3024         .get_link       = ethtool_op_get_link,
3025         .get_ts_info    = cpsw_get_ts_info,
3026         .get_coalesce   = cpsw_get_coalesce,
3027         .set_coalesce   = cpsw_set_coalesce,
3028         .get_sset_count         = cpsw_get_sset_count,
3029         .get_strings            = cpsw_get_strings,
3030         .get_ethtool_stats      = cpsw_get_ethtool_stats,
3031         .get_pauseparam         = cpsw_get_pauseparam,
3032         .set_pauseparam         = cpsw_set_pauseparam,
3033         .get_wol        = cpsw_get_wol,
3034         .set_wol        = cpsw_set_wol,
3035         .get_regs_len   = cpsw_get_regs_len,
3036         .get_regs       = cpsw_get_regs,
3037         .begin          = cpsw_ethtool_op_begin,
3038         .complete       = cpsw_ethtool_op_complete,
3039         .get_channels   = cpsw_get_channels,
3040         .set_channels   = cpsw_set_channels,
3041         .get_link_ksettings     = cpsw_get_link_ksettings,
3042         .set_link_ksettings     = cpsw_set_link_ksettings,
3043         .get_eee        = cpsw_get_eee,
3044         .set_eee        = cpsw_set_eee,
3045         .nway_reset     = cpsw_nway_reset,
3046         .get_ringparam = cpsw_get_ringparam,
3047         .set_ringparam = cpsw_set_ringparam,
3048 };
3049
3050 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
3051                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
3052 {
3053         void __iomem            *regs = cpsw->regs;
3054         int                     slave_num = slave->slave_num;
3055         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
3056
3057         slave->data     = data;
3058         slave->regs     = regs + slave_reg_ofs;
3059         slave->sliver   = regs + sliver_reg_ofs;
3060         slave->port_vlan = data->dual_emac_res_vlan;
3061 }
3062
3063 static int cpsw_probe_dt(struct cpsw_platform_data *data,
3064                          struct platform_device *pdev)
3065 {
3066         struct device_node *node = pdev->dev.of_node;
3067         struct device_node *slave_node;
3068         int i = 0, ret;
3069         u32 prop;
3070
3071         if (!node)
3072                 return -EINVAL;
3073
3074         if (of_property_read_u32(node, "slaves", &prop)) {
3075                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
3076                 return -EINVAL;
3077         }
3078         data->slaves = prop;
3079
3080         if (of_property_read_u32(node, "active_slave", &prop)) {
3081                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
3082                 return -EINVAL;
3083         }
3084         data->active_slave = prop;
3085
3086         data->slave_data = devm_kcalloc(&pdev->dev,
3087                                         data->slaves,
3088                                         sizeof(struct cpsw_slave_data),
3089                                         GFP_KERNEL);
3090         if (!data->slave_data)
3091                 return -ENOMEM;
3092
3093         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
3094                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
3095                 return -EINVAL;
3096         }
3097         data->channels = prop;
3098
3099         if (of_property_read_u32(node, "ale_entries", &prop)) {
3100                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
3101                 return -EINVAL;
3102         }
3103         data->ale_entries = prop;
3104
3105         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
3106                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
3107                 return -EINVAL;
3108         }
3109         data->bd_ram_size = prop;
3110
3111         if (of_property_read_u32(node, "mac_control", &prop)) {
3112                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
3113                 return -EINVAL;
3114         }
3115         data->mac_control = prop;
3116
3117         if (of_property_read_bool(node, "dual_emac"))
3118                 data->dual_emac = 1;
3119
3120         /*
3121          * Populate all the child nodes here...
3122          */
3123         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
3124         /* We do not want to force this, as in some cases may not have child */
3125         if (ret)
3126                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
3127
3128         for_each_available_child_of_node(node, slave_node) {
3129                 struct cpsw_slave_data *slave_data = data->slave_data + i;
3130                 const void *mac_addr = NULL;
3131                 int lenp;
3132                 const __be32 *parp;
3133
3134                 /* This is no slave child node, continue */
3135                 if (strcmp(slave_node->name, "slave"))
3136                         continue;
3137
3138                 slave_data->phy_node = of_parse_phandle(slave_node,
3139                                                         "phy-handle", 0);
3140                 parp = of_get_property(slave_node, "phy_id", &lenp);
3141                 if (slave_data->phy_node) {
3142                         dev_dbg(&pdev->dev,
3143                                 "slave[%d] using phy-handle=\"%pOF\"\n",
3144                                 i, slave_data->phy_node);
3145                 } else if (of_phy_is_fixed_link(slave_node)) {
3146                         /* In the case of a fixed PHY, the DT node associated
3147                          * to the PHY is the Ethernet MAC DT node.
3148                          */
3149                         ret = of_phy_register_fixed_link(slave_node);
3150                         if (ret) {
3151                                 if (ret != -EPROBE_DEFER)
3152                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
3153                                 return ret;
3154                         }
3155                         slave_data->phy_node = of_node_get(slave_node);
3156                 } else if (parp) {
3157                         u32 phyid;
3158                         struct device_node *mdio_node;
3159                         struct platform_device *mdio;
3160
3161                         if (lenp != (sizeof(__be32) * 2)) {
3162                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
3163                                 goto no_phy_slave;
3164                         }
3165                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
3166                         phyid = be32_to_cpup(parp+1);
3167                         mdio = of_find_device_by_node(mdio_node);
3168                         of_node_put(mdio_node);
3169                         if (!mdio) {
3170                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
3171                                 return -EINVAL;
3172                         }
3173                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
3174                                  PHY_ID_FMT, mdio->name, phyid);
3175                         put_device(&mdio->dev);
3176                 } else {
3177                         dev_err(&pdev->dev,
3178                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
3179                                 i);
3180                         goto no_phy_slave;
3181                 }
3182                 slave_data->phy_if = of_get_phy_mode(slave_node);
3183                 if (slave_data->phy_if < 0) {
3184                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
3185                                 i);
3186                         return slave_data->phy_if;
3187                 }
3188
3189 no_phy_slave:
3190                 mac_addr = of_get_mac_address(slave_node);
3191                 if (mac_addr) {
3192                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
3193                 } else {
3194                         ret = ti_cm_get_macid(&pdev->dev, i,
3195                                               slave_data->mac_addr);
3196                         if (ret)
3197                                 return ret;
3198                 }
3199                 if (data->dual_emac) {
3200                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
3201                                                  &prop)) {
3202                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
3203                                 slave_data->dual_emac_res_vlan = i+1;
3204                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
3205                                         slave_data->dual_emac_res_vlan, i);
3206                         } else {
3207                                 slave_data->dual_emac_res_vlan = prop;
3208                         }
3209                 }
3210
3211                 i++;
3212                 if (i == data->slaves)
3213                         break;
3214         }
3215
3216         return 0;
3217 }
3218
3219 static void cpsw_remove_dt(struct platform_device *pdev)
3220 {
3221         struct net_device *ndev = platform_get_drvdata(pdev);
3222         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3223         struct cpsw_platform_data *data = &cpsw->data;
3224         struct device_node *node = pdev->dev.of_node;
3225         struct device_node *slave_node;
3226         int i = 0;
3227
3228         for_each_available_child_of_node(node, slave_node) {
3229                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
3230
3231                 if (strcmp(slave_node->name, "slave"))
3232                         continue;
3233
3234                 if (of_phy_is_fixed_link(slave_node))
3235                         of_phy_deregister_fixed_link(slave_node);
3236
3237                 of_node_put(slave_data->phy_node);
3238
3239                 i++;
3240                 if (i == data->slaves)
3241                         break;
3242         }
3243
3244         of_platform_depopulate(&pdev->dev);
3245 }
3246
3247 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
3248 {
3249         struct cpsw_common              *cpsw = priv->cpsw;
3250         struct cpsw_platform_data       *data = &cpsw->data;
3251         struct net_device               *ndev;
3252         struct cpsw_priv                *priv_sl2;
3253         int ret = 0;
3254
3255         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
3256         if (!ndev) {
3257                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
3258                 return -ENOMEM;
3259         }
3260
3261         priv_sl2 = netdev_priv(ndev);
3262         priv_sl2->cpsw = cpsw;
3263         priv_sl2->ndev = ndev;
3264         priv_sl2->dev  = &ndev->dev;
3265         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3266
3267         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
3268                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
3269                         ETH_ALEN);
3270                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
3271                          priv_sl2->mac_addr);
3272         } else {
3273                 eth_random_addr(priv_sl2->mac_addr);
3274                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
3275                          priv_sl2->mac_addr);
3276         }
3277         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
3278
3279         priv_sl2->emac_port = 1;
3280         cpsw->slaves[1].ndev = ndev;
3281         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3282
3283         ndev->netdev_ops = &cpsw_netdev_ops;
3284         ndev->ethtool_ops = &cpsw_ethtool_ops;
3285
3286         /* register the network device */
3287         SET_NETDEV_DEV(ndev, cpsw->dev);
3288         ret = register_netdev(ndev);
3289         if (ret) {
3290                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
3291                 free_netdev(ndev);
3292                 ret = -ENODEV;
3293         }
3294
3295         return ret;
3296 }
3297
3298 static const struct of_device_id cpsw_of_mtable[] = {
3299         { .compatible = "ti,cpsw"},
3300         { .compatible = "ti,am335x-cpsw"},
3301         { .compatible = "ti,am4372-cpsw"},
3302         { .compatible = "ti,dra7-cpsw"},
3303         { /* sentinel */ },
3304 };
3305 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
3306
3307 static const struct soc_device_attribute cpsw_soc_devices[] = {
3308   &