net: ethernet: ti: cpsw: unsync mcast entries while switch promisc mode
[muen/linux.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2  * Texas Instruments Ethernet Switch Driver
3  *
4  * Copyright (C) 2012 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38 #include <linux/kmemleak.h>
39 #include <linux/sys_soc.h>
40
41 #include <linux/pinctrl/consumer.h>
42 #include <net/pkt_cls.h>
43
44 #include "cpsw.h"
45 #include "cpsw_ale.h"
46 #include "cpts.h"
47 #include "davinci_cpdma.h"
48
49 #include <net/pkt_sched.h>
50
51 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
52                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
53                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
54                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
55                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
56                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
57                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
58                          NETIF_MSG_RX_STATUS)
59
60 #define cpsw_info(priv, type, format, ...)              \
61 do {                                                            \
62         if (netif_msg_##type(priv) && net_ratelimit())          \
63                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
64 } while (0)
65
66 #define cpsw_err(priv, type, format, ...)               \
67 do {                                                            \
68         if (netif_msg_##type(priv) && net_ratelimit())          \
69                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
70 } while (0)
71
72 #define cpsw_dbg(priv, type, format, ...)               \
73 do {                                                            \
74         if (netif_msg_##type(priv) && net_ratelimit())          \
75                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
76 } while (0)
77
78 #define cpsw_notice(priv, type, format, ...)            \
79 do {                                                            \
80         if (netif_msg_##type(priv) && net_ratelimit())          \
81                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
82 } while (0)
83
84 #define ALE_ALL_PORTS           0x7
85
86 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
87 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
88 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
89
90 #define CPSW_VERSION_1          0x19010a
91 #define CPSW_VERSION_2          0x19010c
92 #define CPSW_VERSION_3          0x19010f
93 #define CPSW_VERSION_4          0x190112
94
95 #define HOST_PORT_NUM           0
96 #define CPSW_ALE_PORTS_NUM      3
97 #define SLIVER_SIZE             0x40
98
99 #define CPSW1_HOST_PORT_OFFSET  0x028
100 #define CPSW1_SLAVE_OFFSET      0x050
101 #define CPSW1_SLAVE_SIZE        0x040
102 #define CPSW1_CPDMA_OFFSET      0x100
103 #define CPSW1_STATERAM_OFFSET   0x200
104 #define CPSW1_HW_STATS          0x400
105 #define CPSW1_CPTS_OFFSET       0x500
106 #define CPSW1_ALE_OFFSET        0x600
107 #define CPSW1_SLIVER_OFFSET     0x700
108
109 #define CPSW2_HOST_PORT_OFFSET  0x108
110 #define CPSW2_SLAVE_OFFSET      0x200
111 #define CPSW2_SLAVE_SIZE        0x100
112 #define CPSW2_CPDMA_OFFSET      0x800
113 #define CPSW2_HW_STATS          0x900
114 #define CPSW2_STATERAM_OFFSET   0xa00
115 #define CPSW2_CPTS_OFFSET       0xc00
116 #define CPSW2_ALE_OFFSET        0xd00
117 #define CPSW2_SLIVER_OFFSET     0xd80
118 #define CPSW2_BD_OFFSET         0x2000
119
120 #define CPDMA_RXTHRESH          0x0c0
121 #define CPDMA_RXFREE            0x0e0
122 #define CPDMA_TXHDP             0x00
123 #define CPDMA_RXHDP             0x20
124 #define CPDMA_TXCP              0x40
125 #define CPDMA_RXCP              0x60
126
127 #define CPSW_POLL_WEIGHT        64
128 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE             4
129 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
130 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN +\
131                                  ETH_FCS_LEN +\
132                                  CPSW_RX_VLAN_ENCAP_HDR_SIZE)
133
134 #define RX_PRIORITY_MAPPING     0x76543210
135 #define TX_PRIORITY_MAPPING     0x33221100
136 #define CPDMA_TX_PRIORITY_MAP   0x76543210
137
138 #define CPSW_VLAN_AWARE         BIT(1)
139 #define CPSW_RX_VLAN_ENCAP      BIT(2)
140 #define CPSW_ALE_VLAN_AWARE     1
141
142 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
143 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
144 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
145
146 #define CPSW_INTPACEEN          (0x3f << 16)
147 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
148 #define CPSW_CMINTMAX_CNT       63
149 #define CPSW_CMINTMIN_CNT       2
150 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
151 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
152
153 #define cpsw_slave_index(cpsw, priv)                            \
154                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
155                 cpsw->data.active_slave)
156 #define IRQ_NUM                 2
157 #define CPSW_MAX_QUEUES         8
158 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
159 #define CPSW_FIFO_QUEUE_TYPE_SHIFT      16
160 #define CPSW_FIFO_SHAPE_EN_SHIFT        16
161 #define CPSW_FIFO_RATE_EN_SHIFT         20
162 #define CPSW_TC_NUM                     4
163 #define CPSW_FIFO_SHAPERS_NUM           (CPSW_TC_NUM - 1)
164 #define CPSW_PCT_MASK                   0x7f
165
166 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT       29
167 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK         GENMASK(2, 0)
168 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT        16
169 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT   8
170 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK     GENMASK(1, 0)
171 enum {
172         CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
173         CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
174         CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
175         CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
176 };
177
178 static int debug_level;
179 module_param(debug_level, int, 0);
180 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
181
182 static int ale_ageout = 10;
183 module_param(ale_ageout, int, 0);
184 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
185
186 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
187 module_param(rx_packet_max, int, 0);
188 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
189
190 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
191 module_param(descs_pool_size, int, 0444);
192 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
193
194 struct cpsw_wr_regs {
195         u32     id_ver;
196         u32     soft_reset;
197         u32     control;
198         u32     int_control;
199         u32     rx_thresh_en;
200         u32     rx_en;
201         u32     tx_en;
202         u32     misc_en;
203         u32     mem_allign1[8];
204         u32     rx_thresh_stat;
205         u32     rx_stat;
206         u32     tx_stat;
207         u32     misc_stat;
208         u32     mem_allign2[8];
209         u32     rx_imax;
210         u32     tx_imax;
211
212 };
213
214 struct cpsw_ss_regs {
215         u32     id_ver;
216         u32     control;
217         u32     soft_reset;
218         u32     stat_port_en;
219         u32     ptype;
220         u32     soft_idle;
221         u32     thru_rate;
222         u32     gap_thresh;
223         u32     tx_start_wds;
224         u32     flow_control;
225         u32     vlan_ltype;
226         u32     ts_ltype;
227         u32     dlr_ltype;
228 };
229
230 /* CPSW_PORT_V1 */
231 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
232 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
233 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
234 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
235 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
236 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
237 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
238 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
239
240 /* CPSW_PORT_V2 */
241 #define CPSW2_CONTROL       0x00 /* Control Register */
242 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
243 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
244 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
245 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
246 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
247 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
248
249 /* CPSW_PORT_V1 and V2 */
250 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
251 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
252 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
253
254 /* CPSW_PORT_V2 only */
255 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
256 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
257 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
258 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
259 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
260 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
261 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
262 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
263
264 /* Bit definitions for the CPSW2_CONTROL register */
265 #define PASS_PRI_TAGGED     BIT(24) /* Pass Priority Tagged */
266 #define VLAN_LTYPE2_EN      BIT(21) /* VLAN LTYPE 2 enable */
267 #define VLAN_LTYPE1_EN      BIT(20) /* VLAN LTYPE 1 enable */
268 #define DSCP_PRI_EN         BIT(16) /* DSCP Priority Enable */
269 #define TS_107              BIT(15) /* Tyme Sync Dest IP Address 107 */
270 #define TS_320              BIT(14) /* Time Sync Dest Port 320 enable */
271 #define TS_319              BIT(13) /* Time Sync Dest Port 319 enable */
272 #define TS_132              BIT(12) /* Time Sync Dest IP Addr 132 enable */
273 #define TS_131              BIT(11) /* Time Sync Dest IP Addr 131 enable */
274 #define TS_130              BIT(10) /* Time Sync Dest IP Addr 130 enable */
275 #define TS_129              BIT(9)  /* Time Sync Dest IP Addr 129 enable */
276 #define TS_TTL_NONZERO      BIT(8)  /* Time Sync Time To Live Non-zero enable */
277 #define TS_ANNEX_F_EN       BIT(6)  /* Time Sync Annex F enable */
278 #define TS_ANNEX_D_EN       BIT(4)  /* Time Sync Annex D enable */
279 #define TS_LTYPE2_EN        BIT(3)  /* Time Sync LTYPE 2 enable */
280 #define TS_LTYPE1_EN        BIT(2)  /* Time Sync LTYPE 1 enable */
281 #define TS_TX_EN            BIT(1)  /* Time Sync Transmit Enable */
282 #define TS_RX_EN            BIT(0)  /* Time Sync Receive Enable */
283
284 #define CTRL_V2_TS_BITS \
285         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
286          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
287
288 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
289 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
290 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
291
292
293 #define CTRL_V3_TS_BITS \
294         (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
295          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
296          TS_LTYPE1_EN)
297
298 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
299 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
300 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
301
302 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
303 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
304 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
305 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
306 #define TS_MSG_TYPE_EN_MASK      (0xffff)
307
308 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
309 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
310
311 /* Bit definitions for the CPSW1_TS_CTL register */
312 #define CPSW_V1_TS_RX_EN                BIT(0)
313 #define CPSW_V1_TS_TX_EN                BIT(4)
314 #define CPSW_V1_MSG_TYPE_OFS            16
315
316 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
317 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
318
319 #define CPSW_MAX_BLKS_TX                15
320 #define CPSW_MAX_BLKS_TX_SHIFT          4
321 #define CPSW_MAX_BLKS_RX                5
322
323 struct cpsw_host_regs {
324         u32     max_blks;
325         u32     blk_cnt;
326         u32     tx_in_ctl;
327         u32     port_vlan;
328         u32     tx_pri_map;
329         u32     cpdma_tx_pri_map;
330         u32     cpdma_rx_chan_map;
331 };
332
333 struct cpsw_sliver_regs {
334         u32     id_ver;
335         u32     mac_control;
336         u32     mac_status;
337         u32     soft_reset;
338         u32     rx_maxlen;
339         u32     __reserved_0;
340         u32     rx_pause;
341         u32     tx_pause;
342         u32     __reserved_1;
343         u32     rx_pri_map;
344 };
345
346 struct cpsw_hw_stats {
347         u32     rxgoodframes;
348         u32     rxbroadcastframes;
349         u32     rxmulticastframes;
350         u32     rxpauseframes;
351         u32     rxcrcerrors;
352         u32     rxaligncodeerrors;
353         u32     rxoversizedframes;
354         u32     rxjabberframes;
355         u32     rxundersizedframes;
356         u32     rxfragments;
357         u32     __pad_0[2];
358         u32     rxoctets;
359         u32     txgoodframes;
360         u32     txbroadcastframes;
361         u32     txmulticastframes;
362         u32     txpauseframes;
363         u32     txdeferredframes;
364         u32     txcollisionframes;
365         u32     txsinglecollframes;
366         u32     txmultcollframes;
367         u32     txexcessivecollisions;
368         u32     txlatecollisions;
369         u32     txunderrun;
370         u32     txcarriersenseerrors;
371         u32     txoctets;
372         u32     octetframes64;
373         u32     octetframes65t127;
374         u32     octetframes128t255;
375         u32     octetframes256t511;
376         u32     octetframes512t1023;
377         u32     octetframes1024tup;
378         u32     netoctets;
379         u32     rxsofoverruns;
380         u32     rxmofoverruns;
381         u32     rxdmaoverruns;
382 };
383
384 struct cpsw_slave_data {
385         struct device_node *phy_node;
386         char            phy_id[MII_BUS_ID_SIZE];
387         int             phy_if;
388         u8              mac_addr[ETH_ALEN];
389         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
390 };
391
392 struct cpsw_platform_data {
393         struct cpsw_slave_data  *slave_data;
394         u32     ss_reg_ofs;     /* Subsystem control register offset */
395         u32     channels;       /* number of cpdma channels (symmetric) */
396         u32     slaves;         /* number of slave cpgmac ports */
397         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
398         u32     ale_entries;    /* ale table size */
399         u32     bd_ram_size;  /*buffer descriptor ram size */
400         u32     mac_control;    /* Mac control register */
401         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
402         bool    dual_emac;      /* Enable Dual EMAC mode */
403 };
404
405 struct cpsw_slave {
406         void __iomem                    *regs;
407         struct cpsw_sliver_regs __iomem *sliver;
408         int                             slave_num;
409         u32                             mac_control;
410         struct cpsw_slave_data          *data;
411         struct phy_device               *phy;
412         struct net_device               *ndev;
413         u32                             port_vlan;
414 };
415
416 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
417 {
418         return readl_relaxed(slave->regs + offset);
419 }
420
421 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
422 {
423         writel_relaxed(val, slave->regs + offset);
424 }
425
426 struct cpsw_vector {
427         struct cpdma_chan *ch;
428         int budget;
429 };
430
431 struct cpsw_common {
432         struct device                   *dev;
433         struct cpsw_platform_data       data;
434         struct napi_struct              napi_rx;
435         struct napi_struct              napi_tx;
436         struct cpsw_ss_regs __iomem     *regs;
437         struct cpsw_wr_regs __iomem     *wr_regs;
438         u8 __iomem                      *hw_stats;
439         struct cpsw_host_regs __iomem   *host_port_regs;
440         u32                             version;
441         u32                             coal_intvl;
442         u32                             bus_freq_mhz;
443         int                             rx_packet_max;
444         struct cpsw_slave               *slaves;
445         struct cpdma_ctlr               *dma;
446         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
447         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
448         struct cpsw_ale                 *ale;
449         bool                            quirk_irq;
450         bool                            rx_irq_disabled;
451         bool                            tx_irq_disabled;
452         u32 irqs_table[IRQ_NUM];
453         struct cpts                     *cpts;
454         int                             rx_ch_num, tx_ch_num;
455         int                             speed;
456         int                             usage_count;
457 };
458
459 struct cpsw_priv {
460         struct net_device               *ndev;
461         struct device                   *dev;
462         u32                             msg_enable;
463         u8                              mac_addr[ETH_ALEN];
464         bool                            rx_pause;
465         bool                            tx_pause;
466         bool                            mqprio_hw;
467         int                             fifo_bw[CPSW_TC_NUM];
468         int                             shp_cfg_speed;
469         u32 emac_port;
470         struct cpsw_common *cpsw;
471 };
472
473 struct cpsw_stats {
474         char stat_string[ETH_GSTRING_LEN];
475         int type;
476         int sizeof_stat;
477         int stat_offset;
478 };
479
480 enum {
481         CPSW_STATS,
482         CPDMA_RX_STATS,
483         CPDMA_TX_STATS,
484 };
485
486 #define CPSW_STAT(m)            CPSW_STATS,                             \
487                                 FIELD_SIZEOF(struct cpsw_hw_stats, m), \
488                                 offsetof(struct cpsw_hw_stats, m)
489 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
490                                 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
491                                 offsetof(struct cpdma_chan_stats, m)
492 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
493                                 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
494                                 offsetof(struct cpdma_chan_stats, m)
495
496 static const struct cpsw_stats cpsw_gstrings_stats[] = {
497         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
498         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
499         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
500         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
501         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
502         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
503         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
504         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
505         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
506         { "Rx Fragments", CPSW_STAT(rxfragments) },
507         { "Rx Octets", CPSW_STAT(rxoctets) },
508         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
509         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
510         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
511         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
512         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
513         { "Collisions", CPSW_STAT(txcollisionframes) },
514         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
515         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
516         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
517         { "Late Collisions", CPSW_STAT(txlatecollisions) },
518         { "Tx Underrun", CPSW_STAT(txunderrun) },
519         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
520         { "Tx Octets", CPSW_STAT(txoctets) },
521         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
522         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
523         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
524         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
525         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
526         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
527         { "Net Octets", CPSW_STAT(netoctets) },
528         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
529         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
530         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
531 };
532
533 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
534         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
535         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
536         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
537         { "misqueued", CPDMA_RX_STAT(misqueued) },
538         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
539         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
540         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
541         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
542         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
543         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
544         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
545         { "requeue", CPDMA_RX_STAT(requeue) },
546         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
547 };
548
549 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
550 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
551
552 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
553 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
554 #define for_each_slave(priv, func, arg...)                              \
555         do {                                                            \
556                 struct cpsw_slave *slave;                               \
557                 struct cpsw_common *cpsw = (priv)->cpsw;                \
558                 int n;                                                  \
559                 if (cpsw->data.dual_emac)                               \
560                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
561                 else                                                    \
562                         for (n = cpsw->data.slaves,                     \
563                                         slave = cpsw->slaves;           \
564                                         n; n--)                         \
565                                 (func)(slave++, ##arg);                 \
566         } while (0)
567
568 static inline int cpsw_get_slave_port(u32 slave_num)
569 {
570         return slave_num + 1;
571 }
572
573 static void cpsw_add_mcast(struct cpsw_priv *priv, const u8 *addr)
574 {
575         struct cpsw_common *cpsw = priv->cpsw;
576
577         if (cpsw->data.dual_emac) {
578                 struct cpsw_slave *slave = cpsw->slaves + priv->emac_port;
579
580                 cpsw_ale_add_mcast(cpsw->ale, addr, ALE_PORT_HOST,
581                                    ALE_VLAN, slave->port_vlan, 0);
582                 return;
583         }
584
585         cpsw_ale_add_mcast(cpsw->ale, addr, ALE_ALL_PORTS, 0, 0, 0);
586 }
587
588 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
589 {
590         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
591         struct cpsw_ale *ale = cpsw->ale;
592         int i;
593
594         if (cpsw->data.dual_emac) {
595                 bool flag = false;
596
597                 /* Enabling promiscuous mode for one interface will be
598                  * common for both the interface as the interface shares
599                  * the same hardware resource.
600                  */
601                 for (i = 0; i < cpsw->data.slaves; i++)
602                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
603                                 flag = true;
604
605                 if (!enable && flag) {
606                         enable = true;
607                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
608                 }
609
610                 if (enable) {
611                         /* Enable Bypass */
612                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
613
614                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
615                 } else {
616                         /* Disable Bypass */
617                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
618                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
619                 }
620         } else {
621                 if (enable) {
622                         unsigned long timeout = jiffies + HZ;
623
624                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
625                         for (i = 0; i <= cpsw->data.slaves; i++) {
626                                 cpsw_ale_control_set(ale, i,
627                                                      ALE_PORT_NOLEARN, 1);
628                                 cpsw_ale_control_set(ale, i,
629                                                      ALE_PORT_NO_SA_UPDATE, 1);
630                         }
631
632                         /* Clear All Untouched entries */
633                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
634                         do {
635                                 cpu_relax();
636                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
637                                         break;
638                         } while (time_after(timeout, jiffies));
639                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
640
641                         /* Clear all mcast from ALE */
642                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
643                         __dev_mc_unsync(ndev, NULL);
644
645                         /* Flood All Unicast Packets to Host port */
646                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
647                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
648                 } else {
649                         /* Don't Flood All Unicast Packets to Host port */
650                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
651
652                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
653                         for (i = 0; i <= cpsw->data.slaves; i++) {
654                                 cpsw_ale_control_set(ale, i,
655                                                      ALE_PORT_NOLEARN, 0);
656                                 cpsw_ale_control_set(ale, i,
657                                                      ALE_PORT_NO_SA_UPDATE, 0);
658                         }
659                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
660                 }
661         }
662 }
663
664 static int cpsw_add_mc_addr(struct net_device *ndev, const u8 *addr)
665 {
666         struct cpsw_priv *priv = netdev_priv(ndev);
667
668         cpsw_add_mcast(priv, addr);
669         return 0;
670 }
671
672 static int cpsw_del_mc_addr(struct net_device *ndev, const u8 *addr)
673 {
674         struct cpsw_priv *priv = netdev_priv(ndev);
675         struct cpsw_common *cpsw = priv->cpsw;
676         int vid, flags;
677
678         if (cpsw->data.dual_emac) {
679                 vid = cpsw->slaves[priv->emac_port].port_vlan;
680                 flags = ALE_VLAN;
681         } else {
682                 vid = 0;
683                 flags = 0;
684         }
685
686         cpsw_ale_del_mcast(cpsw->ale, addr, 0, flags, vid);
687         return 0;
688 }
689
690 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
691 {
692         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
693
694         if (ndev->flags & IFF_PROMISC) {
695                 /* Enable promiscuous mode */
696                 cpsw_set_promiscious(ndev, true);
697                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
698                 return;
699         } else {
700                 /* Disable promiscuous mode */
701                 cpsw_set_promiscious(ndev, false);
702         }
703
704         /* Restore allmulti on vlans if necessary */
705         cpsw_ale_set_allmulti(cpsw->ale, ndev->flags & IFF_ALLMULTI);
706
707         __dev_mc_sync(ndev, cpsw_add_mc_addr, cpsw_del_mc_addr);
708 }
709
710 static void cpsw_intr_enable(struct cpsw_common *cpsw)
711 {
712         writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
713         writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
714
715         cpdma_ctlr_int_ctrl(cpsw->dma, true);
716         return;
717 }
718
719 static void cpsw_intr_disable(struct cpsw_common *cpsw)
720 {
721         writel_relaxed(0, &cpsw->wr_regs->tx_en);
722         writel_relaxed(0, &cpsw->wr_regs->rx_en);
723
724         cpdma_ctlr_int_ctrl(cpsw->dma, false);
725         return;
726 }
727
728 static void cpsw_tx_handler(void *token, int len, int status)
729 {
730         struct netdev_queue     *txq;
731         struct sk_buff          *skb = token;
732         struct net_device       *ndev = skb->dev;
733         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
734
735         /* Check whether the queue is stopped due to stalled tx dma, if the
736          * queue is stopped then start the queue as we have free desc for tx
737          */
738         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
739         if (unlikely(netif_tx_queue_stopped(txq)))
740                 netif_tx_wake_queue(txq);
741
742         cpts_tx_timestamp(cpsw->cpts, skb);
743         ndev->stats.tx_packets++;
744         ndev->stats.tx_bytes += len;
745         dev_kfree_skb_any(skb);
746 }
747
748 static void cpsw_rx_vlan_encap(struct sk_buff *skb)
749 {
750         struct cpsw_priv *priv = netdev_priv(skb->dev);
751         struct cpsw_common *cpsw = priv->cpsw;
752         u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
753         u16 vtag, vid, prio, pkt_type;
754
755         /* Remove VLAN header encapsulation word */
756         skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
757
758         pkt_type = (rx_vlan_encap_hdr >>
759                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
760                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
761         /* Ignore unknown & Priority-tagged packets*/
762         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
763             pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
764                 return;
765
766         vid = (rx_vlan_encap_hdr >>
767                CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
768                VLAN_VID_MASK;
769         /* Ignore vid 0 and pass packet as is */
770         if (!vid)
771                 return;
772         /* Ignore default vlans in dual mac mode */
773         if (cpsw->data.dual_emac &&
774             vid == cpsw->slaves[priv->emac_port].port_vlan)
775                 return;
776
777         prio = (rx_vlan_encap_hdr >>
778                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
779                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
780
781         vtag = (prio << VLAN_PRIO_SHIFT) | vid;
782         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
783
784         /* strip vlan tag for VLAN-tagged packet */
785         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
786                 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
787                 skb_pull(skb, VLAN_HLEN);
788         }
789 }
790
791 static void cpsw_rx_handler(void *token, int len, int status)
792 {
793         struct cpdma_chan       *ch;
794         struct sk_buff          *skb = token;
795         struct sk_buff          *new_skb;
796         struct net_device       *ndev = skb->dev;
797         int                     ret = 0, port;
798         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
799
800         if (cpsw->data.dual_emac) {
801                 port = CPDMA_RX_SOURCE_PORT(status);
802                 if (port) {
803                         ndev = cpsw->slaves[--port].ndev;
804                         skb->dev = ndev;
805                 }
806         }
807
808         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
809                 /* In dual emac mode check for all interfaces */
810                 if (cpsw->data.dual_emac && cpsw->usage_count &&
811                     (status >= 0)) {
812                         /* The packet received is for the interface which
813                          * is already down and the other interface is up
814                          * and running, instead of freeing which results
815                          * in reducing of the number of rx descriptor in
816                          * DMA engine, requeue skb back to cpdma.
817                          */
818                         new_skb = skb;
819                         goto requeue;
820                 }
821
822                 /* the interface is going down, skbs are purged */
823                 dev_kfree_skb_any(skb);
824                 return;
825         }
826
827         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
828         if (new_skb) {
829                 skb_copy_queue_mapping(new_skb, skb);
830                 skb_put(skb, len);
831                 if (status & CPDMA_RX_VLAN_ENCAP)
832                         cpsw_rx_vlan_encap(skb);
833                 cpts_rx_timestamp(cpsw->cpts, skb);
834                 skb->protocol = eth_type_trans(skb, ndev);
835                 netif_receive_skb(skb);
836                 ndev->stats.rx_bytes += len;
837                 ndev->stats.rx_packets++;
838                 kmemleak_not_leak(new_skb);
839         } else {
840                 ndev->stats.rx_dropped++;
841                 new_skb = skb;
842         }
843
844 requeue:
845         if (netif_dormant(ndev)) {
846                 dev_kfree_skb_any(new_skb);
847                 return;
848         }
849
850         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
851         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
852                                 skb_tailroom(new_skb), 0);
853         if (WARN_ON(ret < 0))
854                 dev_kfree_skb_any(new_skb);
855 }
856
857 static void cpsw_split_res(struct net_device *ndev)
858 {
859         struct cpsw_priv *priv = netdev_priv(ndev);
860         u32 consumed_rate = 0, bigest_rate = 0;
861         struct cpsw_common *cpsw = priv->cpsw;
862         struct cpsw_vector *txv = cpsw->txv;
863         int i, ch_weight, rlim_ch_num = 0;
864         int budget, bigest_rate_ch = 0;
865         u32 ch_rate, max_rate;
866         int ch_budget = 0;
867
868         for (i = 0; i < cpsw->tx_ch_num; i++) {
869                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
870                 if (!ch_rate)
871                         continue;
872
873                 rlim_ch_num++;
874                 consumed_rate += ch_rate;
875         }
876
877         if (cpsw->tx_ch_num == rlim_ch_num) {
878                 max_rate = consumed_rate;
879         } else if (!rlim_ch_num) {
880                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
881                 bigest_rate = 0;
882                 max_rate = consumed_rate;
883         } else {
884                 max_rate = cpsw->speed * 1000;
885
886                 /* if max_rate is less then expected due to reduced link speed,
887                  * split proportionally according next potential max speed
888                  */
889                 if (max_rate < consumed_rate)
890                         max_rate *= 10;
891
892                 if (max_rate < consumed_rate)
893                         max_rate *= 10;
894
895                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
896                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
897                             (cpsw->tx_ch_num - rlim_ch_num);
898                 bigest_rate = (max_rate - consumed_rate) /
899                               (cpsw->tx_ch_num - rlim_ch_num);
900         }
901
902         /* split tx weight/budget */
903         budget = CPSW_POLL_WEIGHT;
904         for (i = 0; i < cpsw->tx_ch_num; i++) {
905                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
906                 if (ch_rate) {
907                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
908                         if (!txv[i].budget)
909                                 txv[i].budget++;
910                         if (ch_rate > bigest_rate) {
911                                 bigest_rate_ch = i;
912                                 bigest_rate = ch_rate;
913                         }
914
915                         ch_weight = (ch_rate * 100) / max_rate;
916                         if (!ch_weight)
917                                 ch_weight++;
918                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
919                 } else {
920                         txv[i].budget = ch_budget;
921                         if (!bigest_rate_ch)
922                                 bigest_rate_ch = i;
923                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
924                 }
925
926                 budget -= txv[i].budget;
927         }
928
929         if (budget)
930                 txv[bigest_rate_ch].budget += budget;
931
932         /* split rx budget */
933         budget = CPSW_POLL_WEIGHT;
934         ch_budget = budget / cpsw->rx_ch_num;
935         for (i = 0; i < cpsw->rx_ch_num; i++) {
936                 cpsw->rxv[i].budget = ch_budget;
937                 budget -= ch_budget;
938         }
939
940         if (budget)
941                 cpsw->rxv[0].budget += budget;
942 }
943
944 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
945 {
946         struct cpsw_common *cpsw = dev_id;
947
948         writel(0, &cpsw->wr_regs->tx_en);
949         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
950
951         if (cpsw->quirk_irq) {
952                 disable_irq_nosync(cpsw->irqs_table[1]);
953                 cpsw->tx_irq_disabled = true;
954         }
955
956         napi_schedule(&cpsw->napi_tx);
957         return IRQ_HANDLED;
958 }
959
960 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
961 {
962         struct cpsw_common *cpsw = dev_id;
963
964         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
965         writel(0, &cpsw->wr_regs->rx_en);
966
967         if (cpsw->quirk_irq) {
968                 disable_irq_nosync(cpsw->irqs_table[0]);
969                 cpsw->rx_irq_disabled = true;
970         }
971
972         napi_schedule(&cpsw->napi_rx);
973         return IRQ_HANDLED;
974 }
975
976 static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
977 {
978         u32                     ch_map;
979         int                     num_tx, cur_budget, ch;
980         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
981         struct cpsw_vector      *txv;
982
983         /* process every unprocessed channel */
984         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
985         for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) {
986                 if (!(ch_map & 0x80))
987                         continue;
988
989                 txv = &cpsw->txv[ch];
990                 if (unlikely(txv->budget > budget - num_tx))
991                         cur_budget = budget - num_tx;
992                 else
993                         cur_budget = txv->budget;
994
995                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
996                 if (num_tx >= budget)
997                         break;
998         }
999
1000         if (num_tx < budget) {
1001                 napi_complete(napi_tx);
1002                 writel(0xff, &cpsw->wr_regs->tx_en);
1003         }
1004
1005         return num_tx;
1006 }
1007
1008 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
1009 {
1010         struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
1011         int num_tx;
1012
1013         num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
1014         if (num_tx < budget) {
1015                 napi_complete(napi_tx);
1016                 writel(0xff, &cpsw->wr_regs->tx_en);
1017                 if (cpsw->tx_irq_disabled) {
1018                         cpsw->tx_irq_disabled = false;
1019                         enable_irq(cpsw->irqs_table[1]);
1020                 }
1021         }
1022
1023         return num_tx;
1024 }
1025
1026 static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
1027 {
1028         u32                     ch_map;
1029         int                     num_rx, cur_budget, ch;
1030         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
1031         struct cpsw_vector      *rxv;
1032
1033         /* process every unprocessed channel */
1034         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
1035         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
1036                 if (!(ch_map & 0x01))
1037                         continue;
1038
1039                 rxv = &cpsw->rxv[ch];
1040                 if (unlikely(rxv->budget > budget - num_rx))
1041                         cur_budget = budget - num_rx;
1042                 else
1043                         cur_budget = rxv->budget;
1044
1045                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
1046                 if (num_rx >= budget)
1047                         break;
1048         }
1049
1050         if (num_rx < budget) {
1051                 napi_complete_done(napi_rx, num_rx);
1052                 writel(0xff, &cpsw->wr_regs->rx_en);
1053         }
1054
1055         return num_rx;
1056 }
1057
1058 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
1059 {
1060         struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1061         int num_rx;
1062
1063         num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
1064         if (num_rx < budget) {
1065                 napi_complete_done(napi_rx, num_rx);
1066                 writel(0xff, &cpsw->wr_regs->rx_en);
1067                 if (cpsw->rx_irq_disabled) {
1068                         cpsw->rx_irq_disabled = false;
1069                         enable_irq(cpsw->irqs_table[0]);
1070                 }
1071         }
1072
1073         return num_rx;
1074 }
1075
1076 static inline void soft_reset(const char *module, void __iomem *reg)
1077 {
1078         unsigned long timeout = jiffies + HZ;
1079
1080         writel_relaxed(1, reg);
1081         do {
1082                 cpu_relax();
1083         } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
1084
1085         WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
1086 }
1087
1088 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
1089                                struct cpsw_priv *priv)
1090 {
1091         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
1092         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
1093 }
1094
1095 static bool cpsw_shp_is_off(struct cpsw_priv *priv)
1096 {
1097         struct cpsw_common *cpsw = priv->cpsw;
1098         struct cpsw_slave *slave;
1099         u32 shift, mask, val;
1100
1101         val = readl_relaxed(&cpsw->regs->ptype);
1102
1103         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1104         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1105         mask = 7 << shift;
1106         val = val & mask;
1107
1108         return !val;
1109 }
1110
1111 static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on)
1112 {
1113         struct cpsw_common *cpsw = priv->cpsw;
1114         struct cpsw_slave *slave;
1115         u32 shift, mask, val;
1116
1117         val = readl_relaxed(&cpsw->regs->ptype);
1118
1119         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1120         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1121         mask = (1 << --fifo) << shift;
1122         val = on ? val | mask : val & ~mask;
1123
1124         writel_relaxed(val, &cpsw->regs->ptype);
1125 }
1126
1127 static void _cpsw_adjust_link(struct cpsw_slave *slave,
1128                               struct cpsw_priv *priv, bool *link)
1129 {
1130         struct phy_device       *phy = slave->phy;
1131         u32                     mac_control = 0;
1132         u32                     slave_port;
1133         struct cpsw_common *cpsw = priv->cpsw;
1134
1135         if (!phy)
1136                 return;
1137
1138         slave_port = cpsw_get_slave_port(slave->slave_num);
1139
1140         if (phy->link) {
1141                 mac_control = cpsw->data.mac_control;
1142
1143                 /* enable forwarding */
1144                 cpsw_ale_control_set(cpsw->ale, slave_port,
1145                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1146
1147                 if (phy->speed == 1000)
1148                         mac_control |= BIT(7);  /* GIGABITEN    */
1149                 if (phy->duplex)
1150                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
1151
1152                 /* set speed_in input in case RMII mode is used in 100Mbps */
1153                 if (phy->speed == 100)
1154                         mac_control |= BIT(15);
1155                 /* in band mode only works in 10Mbps RGMII mode */
1156                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1157                         mac_control |= BIT(18); /* In Band mode */
1158
1159                 if (priv->rx_pause)
1160                         mac_control |= BIT(3);
1161
1162                 if (priv->tx_pause)
1163                         mac_control |= BIT(4);
1164
1165                 *link = true;
1166
1167                 if (priv->shp_cfg_speed &&
1168                     priv->shp_cfg_speed != slave->phy->speed &&
1169                     !cpsw_shp_is_off(priv))
1170                         dev_warn(priv->dev,
1171                                  "Speed was changed, CBS shaper speeds are changed!");
1172         } else {
1173                 mac_control = 0;
1174                 /* disable forwarding */
1175                 cpsw_ale_control_set(cpsw->ale, slave_port,
1176                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1177         }
1178
1179         if (mac_control != slave->mac_control) {
1180                 phy_print_status(phy);
1181                 writel_relaxed(mac_control, &slave->sliver->mac_control);
1182         }
1183
1184         slave->mac_control = mac_control;
1185 }
1186
1187 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1188 {
1189         int i, speed;
1190
1191         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1192                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1193                         speed += cpsw->slaves[i].phy->speed;
1194
1195         return speed;
1196 }
1197
1198 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1199 {
1200         int i, rlim_ch_num;
1201         int speed, ch_rate;
1202
1203         /* re-split resources only in case speed was changed */
1204         speed = cpsw_get_common_speed(cpsw);
1205         if (speed == cpsw->speed || !speed)
1206                 return 0;
1207
1208         cpsw->speed = speed;
1209
1210         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1211                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1212                 if (!ch_rate)
1213                         break;
1214
1215                 rlim_ch_num++;
1216         }
1217
1218         /* cases not dependent on speed */
1219         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1220                 return 0;
1221
1222         return 1;
1223 }
1224
1225 static void cpsw_adjust_link(struct net_device *ndev)
1226 {
1227         struct cpsw_priv        *priv = netdev_priv(ndev);
1228         struct cpsw_common      *cpsw = priv->cpsw;
1229         bool                    link = false;
1230
1231         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1232
1233         if (link) {
1234                 if (cpsw_need_resplit(cpsw))
1235                         cpsw_split_res(ndev);
1236
1237                 netif_carrier_on(ndev);
1238                 if (netif_running(ndev))
1239                         netif_tx_wake_all_queues(ndev);
1240         } else {
1241                 netif_carrier_off(ndev);
1242                 netif_tx_stop_all_queues(ndev);
1243         }
1244 }
1245
1246 static int cpsw_get_coalesce(struct net_device *ndev,
1247                                 struct ethtool_coalesce *coal)
1248 {
1249         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1250
1251         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1252         return 0;
1253 }
1254
1255 static int cpsw_set_coalesce(struct net_device *ndev,
1256                                 struct ethtool_coalesce *coal)
1257 {
1258         struct cpsw_priv *priv = netdev_priv(ndev);
1259         u32 int_ctrl;
1260         u32 num_interrupts = 0;
1261         u32 prescale = 0;
1262         u32 addnl_dvdr = 1;
1263         u32 coal_intvl = 0;
1264         struct cpsw_common *cpsw = priv->cpsw;
1265
1266         coal_intvl = coal->rx_coalesce_usecs;
1267
1268         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1269         prescale = cpsw->bus_freq_mhz * 4;
1270
1271         if (!coal->rx_coalesce_usecs) {
1272                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1273                 goto update_return;
1274         }
1275
1276         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1277                 coal_intvl = CPSW_CMINTMIN_INTVL;
1278
1279         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1280                 /* Interrupt pacer works with 4us Pulse, we can
1281                  * throttle further by dilating the 4us pulse.
1282                  */
1283                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1284
1285                 if (addnl_dvdr > 1) {
1286                         prescale *= addnl_dvdr;
1287                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1288                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1289                                                 * addnl_dvdr);
1290                 } else {
1291                         addnl_dvdr = 1;
1292                         coal_intvl = CPSW_CMINTMAX_INTVL;
1293                 }
1294         }
1295
1296         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1297         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1298         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1299
1300         int_ctrl |= CPSW_INTPACEEN;
1301         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1302         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1303
1304 update_return:
1305         writel(int_ctrl, &cpsw->wr_regs->int_control);
1306
1307         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1308         cpsw->coal_intvl = coal_intvl;
1309
1310         return 0;
1311 }
1312
1313 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1314 {
1315         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1316
1317         switch (sset) {
1318         case ETH_SS_STATS:
1319                 return (CPSW_STATS_COMMON_LEN +
1320                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1321                        CPSW_STATS_CH_LEN);
1322         default:
1323                 return -EOPNOTSUPP;
1324         }
1325 }
1326
1327 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1328 {
1329         int ch_stats_len;
1330         int line;
1331         int i;
1332
1333         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1334         for (i = 0; i < ch_stats_len; i++) {
1335                 line = i % CPSW_STATS_CH_LEN;
1336                 snprintf(*p, ETH_GSTRING_LEN,
1337                          "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1338                          (long)(i / CPSW_STATS_CH_LEN),
1339                          cpsw_gstrings_ch_stats[line].stat_string);
1340                 *p += ETH_GSTRING_LEN;
1341         }
1342 }
1343
1344 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1345 {
1346         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1347         u8 *p = data;
1348         int i;
1349
1350         switch (stringset) {
1351         case ETH_SS_STATS:
1352                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1353                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1354                                ETH_GSTRING_LEN);
1355                         p += ETH_GSTRING_LEN;
1356                 }
1357
1358                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1359                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1360                 break;
1361         }
1362 }
1363
1364 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1365                                     struct ethtool_stats *stats, u64 *data)
1366 {
1367         u8 *p;
1368         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1369         struct cpdma_chan_stats ch_stats;
1370         int i, l, ch;
1371
1372         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1373         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1374                 data[l] = readl(cpsw->hw_stats +
1375                                 cpsw_gstrings_stats[l].stat_offset);
1376
1377         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1378                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1379                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1380                         p = (u8 *)&ch_stats +
1381                                 cpsw_gstrings_ch_stats[i].stat_offset;
1382                         data[l] = *(u32 *)p;
1383                 }
1384         }
1385
1386         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1387                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1388                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1389                         p = (u8 *)&ch_stats +
1390                                 cpsw_gstrings_ch_stats[i].stat_offset;
1391                         data[l] = *(u32 *)p;
1392                 }
1393         }
1394 }
1395
1396 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1397                                         struct sk_buff *skb,
1398                                         struct cpdma_chan *txch)
1399 {
1400         struct cpsw_common *cpsw = priv->cpsw;
1401
1402         skb_tx_timestamp(skb);
1403         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1404                                  priv->emac_port + cpsw->data.dual_emac);
1405 }
1406
1407 static inline void cpsw_add_dual_emac_def_ale_entries(
1408                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1409                 u32 slave_port)
1410 {
1411         struct cpsw_common *cpsw = priv->cpsw;
1412         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1413
1414         if (cpsw->version == CPSW_VERSION_1)
1415                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1416         else
1417                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1418         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1419                           port_mask, port_mask, 0);
1420         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1421                            ALE_PORT_HOST, ALE_VLAN, slave->port_vlan, 0);
1422         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1423                            HOST_PORT_NUM, ALE_VLAN |
1424                            ALE_SECURE, slave->port_vlan);
1425         cpsw_ale_control_set(cpsw->ale, slave_port,
1426                              ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1427 }
1428
1429 static void soft_reset_slave(struct cpsw_slave *slave)
1430 {
1431         char name[32];
1432
1433         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1434         soft_reset(name, &slave->sliver->soft_reset);
1435 }
1436
1437 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1438 {
1439         u32 slave_port;
1440         struct phy_device *phy;
1441         struct cpsw_common *cpsw = priv->cpsw;
1442
1443         soft_reset_slave(slave);
1444
1445         /* setup priority mapping */
1446         writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1447
1448         switch (cpsw->version) {
1449         case CPSW_VERSION_1:
1450                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1451                 /* Increase RX FIFO size to 5 for supporting fullduplex
1452                  * flow control mode
1453                  */
1454                 slave_write(slave,
1455                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1456                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1457                 break;
1458         case CPSW_VERSION_2:
1459         case CPSW_VERSION_3:
1460         case CPSW_VERSION_4:
1461                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1462                 /* Increase RX FIFO size to 5 for supporting fullduplex
1463                  * flow control mode
1464                  */
1465                 slave_write(slave,
1466                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1467                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1468                 break;
1469         }
1470
1471         /* setup max packet size, and mac address */
1472         writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1473         cpsw_set_slave_mac(slave, priv);
1474
1475         slave->mac_control = 0; /* no link yet */
1476
1477         slave_port = cpsw_get_slave_port(slave->slave_num);
1478
1479         if (cpsw->data.dual_emac)
1480                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1481         else
1482                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1483                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1484
1485         if (slave->data->phy_node) {
1486                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1487                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1488                 if (!phy) {
1489                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1490                                 slave->data->phy_node,
1491                                 slave->slave_num);
1492                         return;
1493                 }
1494         } else {
1495                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1496                                  &cpsw_adjust_link, slave->data->phy_if);
1497                 if (IS_ERR(phy)) {
1498                         dev_err(priv->dev,
1499                                 "phy \"%s\" not found on slave %d, err %ld\n",
1500                                 slave->data->phy_id, slave->slave_num,
1501                                 PTR_ERR(phy));
1502                         return;
1503                 }
1504         }
1505
1506         slave->phy = phy;
1507
1508         phy_attached_info(slave->phy);
1509
1510         phy_start(slave->phy);
1511
1512         /* Configure GMII_SEL register */
1513         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1514 }
1515
1516 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1517 {
1518         struct cpsw_common *cpsw = priv->cpsw;
1519         const int vlan = cpsw->data.default_vlan;
1520         u32 reg;
1521         int i;
1522         int unreg_mcast_mask;
1523
1524         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1525                CPSW2_PORT_VLAN;
1526
1527         writel(vlan, &cpsw->host_port_regs->port_vlan);
1528
1529         for (i = 0; i < cpsw->data.slaves; i++)
1530                 slave_write(cpsw->slaves + i, vlan, reg);
1531
1532         if (priv->ndev->flags & IFF_ALLMULTI)
1533                 unreg_mcast_mask = ALE_ALL_PORTS;
1534         else
1535                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1536
1537         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1538                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1539                           unreg_mcast_mask);
1540 }
1541
1542 static void cpsw_init_host_port(struct cpsw_priv *priv)
1543 {
1544         u32 fifo_mode;
1545         u32 control_reg;
1546         struct cpsw_common *cpsw = priv->cpsw;
1547
1548         /* soft reset the controller and initialize ale */
1549         soft_reset("cpsw", &cpsw->regs->soft_reset);
1550         cpsw_ale_start(cpsw->ale);
1551
1552         /* switch to vlan unaware mode */
1553         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1554                              CPSW_ALE_VLAN_AWARE);
1555         control_reg = readl(&cpsw->regs->control);
1556         control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
1557         writel(control_reg, &cpsw->regs->control);
1558         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1559                      CPSW_FIFO_NORMAL_MODE;
1560         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1561
1562         /* setup host port priority mapping */
1563         writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1564                        &cpsw->host_port_regs->cpdma_tx_pri_map);
1565         writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1566
1567         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1568                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1569
1570         if (!cpsw->data.dual_emac) {
1571                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1572                                    0, 0);
1573                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1574                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1575         }
1576 }
1577
1578 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1579 {
1580         struct cpsw_common *cpsw = priv->cpsw;
1581         struct sk_buff *skb;
1582         int ch_buf_num;
1583         int ch, i, ret;
1584
1585         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1586                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1587                 for (i = 0; i < ch_buf_num; i++) {
1588                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1589                                                           cpsw->rx_packet_max,
1590                                                           GFP_KERNEL);
1591                         if (!skb) {
1592                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1593                                 return -ENOMEM;
1594                         }
1595
1596                         skb_set_queue_mapping(skb, ch);
1597                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1598                                                 skb->data, skb_tailroom(skb),
1599                                                 0);
1600                         if (ret < 0) {
1601                                 cpsw_err(priv, ifup,
1602                                          "cannot submit skb to channel %d rx, error %d\n",
1603                                          ch, ret);
1604                                 kfree_skb(skb);
1605                                 return ret;
1606                         }
1607                         kmemleak_not_leak(skb);
1608                 }
1609
1610                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1611                           ch, ch_buf_num);
1612         }
1613
1614         return 0;
1615 }
1616
1617 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1618 {
1619         u32 slave_port;
1620
1621         slave_port = cpsw_get_slave_port(slave->slave_num);
1622
1623         if (!slave->phy)
1624                 return;
1625         phy_stop(slave->phy);
1626         phy_disconnect(slave->phy);
1627         slave->phy = NULL;
1628         cpsw_ale_control_set(cpsw->ale, slave_port,
1629                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1630         soft_reset_slave(slave);
1631 }
1632
1633 static int cpsw_tc_to_fifo(int tc, int num_tc)
1634 {
1635         if (tc == num_tc - 1)
1636                 return 0;
1637
1638         return CPSW_FIFO_SHAPERS_NUM - tc;
1639 }
1640
1641 static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw)
1642 {
1643         struct cpsw_common *cpsw = priv->cpsw;
1644         u32 val = 0, send_pct, shift;
1645         struct cpsw_slave *slave;
1646         int pct = 0, i;
1647
1648         if (bw > priv->shp_cfg_speed * 1000)
1649                 goto err;
1650
1651         /* shaping has to stay enabled for highest fifos linearly
1652          * and fifo bw no more then interface can allow
1653          */
1654         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1655         send_pct = slave_read(slave, SEND_PERCENT);
1656         for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) {
1657                 if (!bw) {
1658                         if (i >= fifo || !priv->fifo_bw[i])
1659                                 continue;
1660
1661                         dev_warn(priv->dev, "Prev FIFO%d is shaped", i);
1662                         continue;
1663                 }
1664
1665                 if (!priv->fifo_bw[i] && i > fifo) {
1666                         dev_err(priv->dev, "Upper FIFO%d is not shaped", i);
1667                         return -EINVAL;
1668                 }
1669
1670                 shift = (i - 1) * 8;
1671                 if (i == fifo) {
1672                         send_pct &= ~(CPSW_PCT_MASK << shift);
1673                         val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10);
1674                         if (!val)
1675                                 val = 1;
1676
1677                         send_pct |= val << shift;
1678                         pct += val;
1679                         continue;
1680                 }
1681
1682                 if (priv->fifo_bw[i])
1683                         pct += (send_pct >> shift) & CPSW_PCT_MASK;
1684         }
1685
1686         if (pct >= 100)
1687                 goto err;
1688
1689         slave_write(slave, send_pct, SEND_PERCENT);
1690         priv->fifo_bw[fifo] = bw;
1691
1692         dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo,
1693                  DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100));
1694
1695         return 0;
1696 err:
1697         dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration");
1698         return -EINVAL;
1699 }
1700
1701 static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw)
1702 {
1703         struct cpsw_common *cpsw = priv->cpsw;
1704         struct cpsw_slave *slave;
1705         u32 tx_in_ctl_rg, val;
1706         int ret;
1707
1708         ret = cpsw_set_fifo_bw(priv, fifo, bw);
1709         if (ret)
1710                 return ret;
1711
1712         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1713         tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
1714                        CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL;
1715
1716         if (!bw)
1717                 cpsw_fifo_shp_on(priv, fifo, bw);
1718
1719         val = slave_read(slave, tx_in_ctl_rg);
1720         if (cpsw_shp_is_off(priv)) {
1721                 /* disable FIFOs rate limited queues */
1722                 val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT);
1723
1724                 /* set type of FIFO queues to normal priority mode */
1725                 val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT);
1726
1727                 /* set type of FIFO queues to be rate limited */
1728                 if (bw)
1729                         val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT;
1730                 else
1731                         priv->shp_cfg_speed = 0;
1732         }
1733
1734         /* toggle a FIFO rate limited queue */
1735         if (bw)
1736                 val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1737         else
1738                 val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1739         slave_write(slave, val, tx_in_ctl_rg);
1740
1741         /* FIFO transmit shape enable */
1742         cpsw_fifo_shp_on(priv, fifo, bw);
1743         return 0;
1744 }
1745
1746 /* Defaults:
1747  * class A - prio 3
1748  * class B - prio 2
1749  * shaping for class A should be set first
1750  */
1751 static int cpsw_set_cbs(struct net_device *ndev,
1752                         struct tc_cbs_qopt_offload *qopt)
1753 {
1754         struct cpsw_priv *priv = netdev_priv(ndev);
1755         struct cpsw_common *cpsw = priv->cpsw;
1756         struct cpsw_slave *slave;
1757         int prev_speed = 0;
1758         int tc, ret, fifo;
1759         u32 bw = 0;
1760
1761         tc = netdev_txq_to_tc(priv->ndev, qopt->queue);
1762
1763         /* enable channels in backward order, as highest FIFOs must be rate
1764          * limited first and for compliance with CPDMA rate limited channels
1765          * that also used in bacward order. FIFO0 cannot be rate limited.
1766          */
1767         fifo = cpsw_tc_to_fifo(tc, ndev->num_tc);
1768         if (!fifo) {
1769                 dev_err(priv->dev, "Last tc%d can't be rate limited", tc);
1770                 return -EINVAL;
1771         }
1772
1773         /* do nothing, it's disabled anyway */
1774         if (!qopt->enable && !priv->fifo_bw[fifo])
1775                 return 0;
1776
1777         /* shapers can be set if link speed is known */
1778         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1779         if (slave->phy && slave->phy->link) {
1780                 if (priv->shp_cfg_speed &&
1781                     priv->shp_cfg_speed != slave->phy->speed)
1782                         prev_speed = priv->shp_cfg_speed;
1783
1784                 priv->shp_cfg_speed = slave->phy->speed;
1785         }
1786
1787         if (!priv->shp_cfg_speed) {
1788                 dev_err(priv->dev, "Link speed is not known");
1789                 return -1;
1790         }
1791
1792         ret = pm_runtime_get_sync(cpsw->dev);
1793         if (ret < 0) {
1794                 pm_runtime_put_noidle(cpsw->dev);
1795                 return ret;
1796         }
1797
1798         bw = qopt->enable ? qopt->idleslope : 0;
1799         ret = cpsw_set_fifo_rlimit(priv, fifo, bw);
1800         if (ret) {
1801                 priv->shp_cfg_speed = prev_speed;
1802                 prev_speed = 0;
1803         }
1804
1805         if (bw && prev_speed)
1806                 dev_warn(priv->dev,
1807                          "Speed was changed, CBS shaper speeds are changed!");
1808
1809         pm_runtime_put_sync(cpsw->dev);
1810         return ret;
1811 }
1812
1813 static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1814 {
1815         int fifo, bw;
1816
1817         for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) {
1818                 bw = priv->fifo_bw[fifo];
1819                 if (!bw)
1820                         continue;
1821
1822                 cpsw_set_fifo_rlimit(priv, fifo, bw);
1823         }
1824 }
1825
1826 static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1827 {
1828         struct cpsw_common *cpsw = priv->cpsw;
1829         u32 tx_prio_map = 0;
1830         int i, tc, fifo;
1831         u32 tx_prio_rg;
1832
1833         if (!priv->mqprio_hw)
1834                 return;
1835
1836         for (i = 0; i < 8; i++) {
1837                 tc = netdev_get_prio_tc_map(priv->ndev, i);
1838                 fifo = CPSW_FIFO_SHAPERS_NUM - tc;
1839                 tx_prio_map |= fifo << (4 * i);
1840         }
1841
1842         tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
1843                      CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
1844
1845         slave_write(slave, tx_prio_map, tx_prio_rg);
1846 }
1847
1848 /* restore resources after port reset */
1849 static void cpsw_restore(struct cpsw_priv *priv)
1850 {
1851         /* restore MQPRIO offload */
1852         for_each_slave(priv, cpsw_mqprio_resume, priv);
1853
1854         /* restore CBS offload */
1855         for_each_slave(priv, cpsw_cbs_resume, priv);
1856 }
1857
1858 static int cpsw_ndo_open(struct net_device *ndev)
1859 {
1860         struct cpsw_priv *priv = netdev_priv(ndev);
1861         struct cpsw_common *cpsw = priv->cpsw;
1862         int ret;
1863         u32 reg;
1864
1865         ret = pm_runtime_get_sync(cpsw->dev);
1866         if (ret < 0) {
1867                 pm_runtime_put_noidle(cpsw->dev);
1868                 return ret;
1869         }
1870
1871         netif_carrier_off(ndev);
1872
1873         /* Notify the stack of the actual queue counts. */
1874         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1875         if (ret) {
1876                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1877                 goto err_cleanup;
1878         }
1879
1880         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1881         if (ret) {
1882                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1883                 goto err_cleanup;
1884         }
1885
1886         reg = cpsw->version;
1887
1888         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1889                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1890                  CPSW_RTL_VERSION(reg));
1891
1892         /* Initialize host and slave ports */
1893         if (!cpsw->usage_count)
1894                 cpsw_init_host_port(priv);
1895         for_each_slave(priv, cpsw_slave_open, priv);
1896
1897         /* Add default VLAN */
1898         if (!cpsw->data.dual_emac)
1899                 cpsw_add_default_vlan(priv);
1900         else
1901                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1902                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1903
1904         /* initialize shared resources for every ndev */
1905         if (!cpsw->usage_count) {
1906                 /* disable priority elevation */
1907                 writel_relaxed(0, &cpsw->regs->ptype);
1908
1909                 /* enable statistics collection only on all ports */
1910                 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1911
1912                 /* Enable internal fifo flow control */
1913                 writel(0x7, &cpsw->regs->flow_control);
1914
1915                 napi_enable(&cpsw->napi_rx);
1916                 napi_enable(&cpsw->napi_tx);
1917
1918                 if (cpsw->tx_irq_disabled) {
1919                         cpsw->tx_irq_disabled = false;
1920                         enable_irq(cpsw->irqs_table[1]);
1921                 }
1922
1923                 if (cpsw->rx_irq_disabled) {
1924                         cpsw->rx_irq_disabled = false;
1925                         enable_irq(cpsw->irqs_table[0]);
1926                 }
1927
1928                 ret = cpsw_fill_rx_channels(priv);
1929                 if (ret < 0)
1930                         goto err_cleanup;
1931
1932                 if (cpts_register(cpsw->cpts))
1933                         dev_err(priv->dev, "error registering cpts device\n");
1934
1935         }
1936
1937         cpsw_restore(priv);
1938
1939         /* Enable Interrupt pacing if configured */
1940         if (cpsw->coal_intvl != 0) {
1941                 struct ethtool_coalesce coal;
1942
1943                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1944                 cpsw_set_coalesce(ndev, &coal);
1945         }
1946
1947         cpdma_ctlr_start(cpsw->dma);
1948         cpsw_intr_enable(cpsw);
1949         cpsw->usage_count++;
1950
1951         return 0;
1952
1953 err_cleanup:
1954         cpdma_ctlr_stop(cpsw->dma);
1955         for_each_slave(priv, cpsw_slave_stop, cpsw);
1956         pm_runtime_put_sync(cpsw->dev);
1957         netif_carrier_off(priv->ndev);
1958         return ret;
1959 }
1960
1961 static int cpsw_ndo_stop(struct net_device *ndev)
1962 {
1963         struct cpsw_priv *priv = netdev_priv(ndev);
1964         struct cpsw_common *cpsw = priv->cpsw;
1965
1966         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1967         __dev_mc_unsync(priv->ndev, cpsw_del_mc_addr);
1968         netif_tx_stop_all_queues(priv->ndev);
1969         netif_carrier_off(priv->ndev);
1970
1971         if (cpsw->usage_count <= 1) {
1972                 napi_disable(&cpsw->napi_rx);
1973                 napi_disable(&cpsw->napi_tx);
1974                 cpts_unregister(cpsw->cpts);
1975                 cpsw_intr_disable(cpsw);
1976                 cpdma_ctlr_stop(cpsw->dma);
1977                 cpsw_ale_stop(cpsw->ale);
1978         }
1979         for_each_slave(priv, cpsw_slave_stop, cpsw);
1980
1981         if (cpsw_need_resplit(cpsw))
1982                 cpsw_split_res(ndev);
1983
1984         cpsw->usage_count--;
1985         pm_runtime_put_sync(cpsw->dev);
1986         return 0;
1987 }
1988
1989 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1990                                        struct net_device *ndev)
1991 {
1992         struct cpsw_priv *priv = netdev_priv(ndev);
1993         struct cpsw_common *cpsw = priv->cpsw;
1994         struct cpts *cpts = cpsw->cpts;
1995         struct netdev_queue *txq;
1996         struct cpdma_chan *txch;
1997         int ret, q_idx;
1998
1999         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
2000                 cpsw_err(priv, tx_err, "packet pad failed\n");
2001                 ndev->stats.tx_dropped++;
2002                 return NET_XMIT_DROP;
2003         }
2004
2005         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2006             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
2007                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2008
2009         q_idx = skb_get_queue_mapping(skb);
2010         if (q_idx >= cpsw->tx_ch_num)
2011                 q_idx = q_idx % cpsw->tx_ch_num;
2012
2013         txch = cpsw->txv[q_idx].ch;
2014         txq = netdev_get_tx_queue(ndev, q_idx);
2015         ret = cpsw_tx_packet_submit(priv, skb, txch);
2016         if (unlikely(ret != 0)) {
2017                 cpsw_err(priv, tx_err, "desc submit failed\n");
2018                 goto fail;
2019         }
2020
2021         /* If there is no more tx desc left free then we need to
2022          * tell the kernel to stop sending us tx frames.
2023          */
2024         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
2025                 netif_tx_stop_queue(txq);
2026
2027                 /* Barrier, so that stop_queue visible to other cpus */
2028                 smp_mb__after_atomic();
2029
2030                 if (cpdma_check_free_tx_desc(txch))
2031                         netif_tx_wake_queue(txq);
2032         }
2033
2034         return NETDEV_TX_OK;
2035 fail:
2036         ndev->stats.tx_dropped++;
2037         netif_tx_stop_queue(txq);
2038
2039         /* Barrier, so that stop_queue visible to other cpus */
2040         smp_mb__after_atomic();
2041
2042         if (cpdma_check_free_tx_desc(txch))
2043                 netif_tx_wake_queue(txq);
2044
2045         return NETDEV_TX_BUSY;
2046 }
2047
2048 #if IS_ENABLED(CONFIG_TI_CPTS)
2049
2050 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
2051 {
2052         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2053         u32 ts_en, seq_id;
2054
2055         if (!cpts_is_tx_enabled(cpsw->cpts) &&
2056             !cpts_is_rx_enabled(cpsw->cpts)) {
2057                 slave_write(slave, 0, CPSW1_TS_CTL);
2058                 return;
2059         }
2060
2061         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2062         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
2063
2064         if (cpts_is_tx_enabled(cpsw->cpts))
2065                 ts_en |= CPSW_V1_TS_TX_EN;
2066
2067         if (cpts_is_rx_enabled(cpsw->cpts))
2068                 ts_en |= CPSW_V1_TS_RX_EN;
2069
2070         slave_write(slave, ts_en, CPSW1_TS_CTL);
2071         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
2072 }
2073
2074 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
2075 {
2076         struct cpsw_slave *slave;
2077         struct cpsw_common *cpsw = priv->cpsw;
2078         u32 ctrl, mtype;
2079
2080         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2081
2082         ctrl = slave_read(slave, CPSW2_CONTROL);
2083         switch (cpsw->version) {
2084         case CPSW_VERSION_2:
2085                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2086
2087                 if (cpts_is_tx_enabled(cpsw->cpts))
2088                         ctrl |= CTRL_V2_TX_TS_BITS;
2089
2090                 if (cpts_is_rx_enabled(cpsw->cpts))
2091                         ctrl |= CTRL_V2_RX_TS_BITS;
2092                 break;
2093         case CPSW_VERSION_3:
2094         default:
2095                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
2096
2097                 if (cpts_is_tx_enabled(cpsw->cpts))
2098                         ctrl |= CTRL_V3_TX_TS_BITS;
2099
2100                 if (cpts_is_rx_enabled(cpsw->cpts))
2101                         ctrl |= CTRL_V3_RX_TS_BITS;
2102                 break;
2103         }
2104
2105         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
2106
2107         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
2108         slave_write(slave, ctrl, CPSW2_CONTROL);
2109         writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
2110 }
2111
2112 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2113 {
2114         struct cpsw_priv *priv = netdev_priv(dev);
2115         struct hwtstamp_config cfg;
2116         struct cpsw_common *cpsw = priv->cpsw;
2117         struct cpts *cpts = cpsw->cpts;
2118
2119         if (cpsw->version != CPSW_VERSION_1 &&
2120             cpsw->version != CPSW_VERSION_2 &&
2121             cpsw->version != CPSW_VERSION_3)
2122                 return -EOPNOTSUPP;
2123
2124         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2125                 return -EFAULT;
2126
2127         /* reserved for future extensions */
2128         if (cfg.flags)
2129                 return -EINVAL;
2130
2131         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2132                 return -ERANGE;
2133
2134         switch (cfg.rx_filter) {
2135         case HWTSTAMP_FILTER_NONE:
2136                 cpts_rx_enable(cpts, 0);
2137                 break;
2138         case HWTSTAMP_FILTER_ALL:
2139         case HWTSTAMP_FILTER_NTP_ALL:
2140                 return -ERANGE;
2141         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2142         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2143         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2144                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
2145                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2146                 break;
2147         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2148         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2149         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2150         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2151         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2152         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2153         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2154         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2155         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2156                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
2157                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2158                 break;
2159         default:
2160                 return -ERANGE;
2161         }
2162
2163         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
2164
2165         switch (cpsw->version) {
2166         case CPSW_VERSION_1:
2167                 cpsw_hwtstamp_v1(cpsw);
2168                 break;
2169         case CPSW_VERSION_2:
2170         case CPSW_VERSION_3:
2171                 cpsw_hwtstamp_v2(priv);
2172                 break;
2173         default:
2174                 WARN_ON(1);
2175         }
2176
2177         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2178 }
2179
2180 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2181 {
2182         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
2183         struct cpts *cpts = cpsw->cpts;
2184         struct hwtstamp_config cfg;
2185
2186         if (cpsw->version != CPSW_VERSION_1 &&
2187             cpsw->version != CPSW_VERSION_2 &&
2188             cpsw->version != CPSW_VERSION_3)
2189                 return -EOPNOTSUPP;
2190
2191         cfg.flags = 0;
2192         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
2193                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2194         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
2195                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
2196
2197         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2198 }
2199 #else
2200 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2201 {
2202         return -EOPNOTSUPP;
2203 }
2204
2205 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2206 {
2207         return -EOPNOTSUPP;
2208 }
2209 #endif /*CONFIG_TI_CPTS*/
2210
2211 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2212 {
2213         struct cpsw_priv *priv = netdev_priv(dev);
2214         struct cpsw_common *cpsw = priv->cpsw;
2215         int slave_no = cpsw_slave_index(cpsw, priv);
2216
2217         if (!netif_running(dev))
2218                 return -EINVAL;
2219
2220         switch (cmd) {
2221         case SIOCSHWTSTAMP:
2222                 return cpsw_hwtstamp_set(dev, req);
2223         case SIOCGHWTSTAMP:
2224                 return cpsw_hwtstamp_get(dev, req);
2225         }
2226
2227         if (!cpsw->slaves[slave_no].phy)
2228                 return -EOPNOTSUPP;
2229         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2230 }
2231
2232 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
2233 {
2234         struct cpsw_priv *priv = netdev_priv(ndev);
2235         struct cpsw_common *cpsw = priv->cpsw;
2236         int ch;
2237
2238         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
2239         ndev->stats.tx_errors++;
2240         cpsw_intr_disable(cpsw);
2241         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
2242                 cpdma_chan_stop(cpsw->txv[ch].ch);
2243                 cpdma_chan_start(cpsw->txv[ch].ch);
2244         }
2245
2246         cpsw_intr_enable(cpsw);
2247         netif_trans_update(ndev);
2248         netif_tx_wake_all_queues(ndev);
2249 }
2250
2251 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
2252 {
2253         struct cpsw_priv *priv = netdev_priv(ndev);
2254         struct sockaddr *addr = (struct sockaddr *)p;
2255         struct cpsw_common *cpsw = priv->cpsw;
2256         int flags = 0;
2257         u16 vid = 0;
2258         int ret;
2259
2260         if (!is_valid_ether_addr(addr->sa_data))
2261                 return -EADDRNOTAVAIL;
2262
2263         ret = pm_runtime_get_sync(cpsw->dev);
2264         if (ret < 0) {
2265                 pm_runtime_put_noidle(cpsw->dev);
2266                 return ret;
2267         }
2268
2269         if (cpsw->data.dual_emac) {
2270                 vid = cpsw->slaves[priv->emac_port].port_vlan;
2271                 flags = ALE_VLAN;
2272         }
2273
2274         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
2275                            flags, vid);
2276         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
2277                            flags, vid);
2278
2279         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
2280         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2281         for_each_slave(priv, cpsw_set_slave_mac, priv);
2282
2283         pm_runtime_put(cpsw->dev);
2284
2285         return 0;
2286 }
2287
2288 #ifdef CONFIG_NET_POLL_CONTROLLER
2289 static void cpsw_ndo_poll_controller(struct net_device *ndev)
2290 {
2291         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2292
2293         cpsw_intr_disable(cpsw);
2294         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2295         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2296         cpsw_intr_enable(cpsw);
2297 }
2298 #endif
2299
2300 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2301                                 unsigned short vid)
2302 {
2303         int ret;
2304         int unreg_mcast_mask = 0;
2305         int mcast_mask;
2306         u32 port_mask;
2307         struct cpsw_common *cpsw = priv->cpsw;
2308
2309         if (cpsw->data.dual_emac) {
2310                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
2311
2312                 mcast_mask = ALE_PORT_HOST;
2313                 if (priv->ndev->flags & IFF_ALLMULTI)
2314                         unreg_mcast_mask = mcast_mask;
2315         } else {
2316                 port_mask = ALE_ALL_PORTS;
2317                 mcast_mask = port_mask;
2318
2319                 if (priv->ndev->flags & IFF_ALLMULTI)
2320                         unreg_mcast_mask = ALE_ALL_PORTS;
2321                 else
2322                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
2323         }
2324
2325         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
2326                                 unreg_mcast_mask);
2327         if (ret != 0)
2328                 return ret;
2329
2330         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
2331                                  HOST_PORT_NUM, ALE_VLAN, vid);
2332         if (ret != 0)
2333                 goto clean_vid;
2334
2335         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
2336                                  mcast_mask, ALE_VLAN, vid, 0);
2337         if (ret != 0)
2338                 goto clean_vlan_ucast;
2339         return 0;
2340
2341 clean_vlan_ucast:
2342         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2343                            HOST_PORT_NUM, ALE_VLAN, vid);
2344 clean_vid:
2345         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2346         return ret;
2347 }
2348
2349 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
2350                                     __be16 proto, u16 vid)
2351 {
2352         struct cpsw_priv *priv = netdev_priv(ndev);
2353         struct cpsw_common *cpsw = priv->cpsw;
2354         int ret;
2355
2356         if (vid == cpsw->data.default_vlan)
2357                 return 0;
2358
2359         ret = pm_runtime_get_sync(cpsw->dev);
2360         if (ret < 0) {
2361                 pm_runtime_put_noidle(cpsw->dev);
2362                 return ret;
2363         }
2364
2365         if (cpsw->data.dual_emac) {
2366                 /* In dual EMAC, reserved VLAN id should not be used for
2367                  * creating VLAN interfaces as this can break the dual
2368                  * EMAC port separation
2369                  */
2370                 int i;
2371
2372                 for (i = 0; i < cpsw->data.slaves; i++) {
2373                         if (vid == cpsw->slaves[i].port_vlan) {
2374                                 ret = -EINVAL;
2375                                 goto err;
2376                         }
2377                 }
2378         }
2379
2380         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2381         ret = cpsw_add_vlan_ale_entry(priv, vid);
2382 err:
2383         pm_runtime_put(cpsw->dev);
2384         return ret;
2385 }
2386
2387 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2388                                      __be16 proto, u16 vid)
2389 {
2390         struct cpsw_priv *priv = netdev_priv(ndev);
2391         struct cpsw_common *cpsw = priv->cpsw;
2392         int ret;
2393
2394         if (vid == cpsw->data.default_vlan)
2395                 return 0;
2396
2397         ret = pm_runtime_get_sync(cpsw->dev);
2398         if (ret < 0) {
2399                 pm_runtime_put_noidle(cpsw->dev);
2400                 return ret;
2401         }
2402
2403         if (cpsw->data.dual_emac) {
2404                 int i;
2405
2406                 for (i = 0; i < cpsw->data.slaves; i++) {
2407                         if (vid == cpsw->slaves[i].port_vlan)
2408                                 goto err;
2409                 }
2410         }
2411
2412         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2413         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2414         ret |= cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2415                                   HOST_PORT_NUM, ALE_VLAN, vid);
2416         ret |= cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2417                                   0, ALE_VLAN, vid);
2418 err:
2419         pm_runtime_put(cpsw->dev);
2420         return ret;
2421 }
2422
2423 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2424 {
2425         struct cpsw_priv *priv = netdev_priv(ndev);
2426         struct cpsw_common *cpsw = priv->cpsw;
2427         struct cpsw_slave *slave;
2428         u32 min_rate;
2429         u32 ch_rate;
2430         int i, ret;
2431
2432         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2433         if (ch_rate == rate)
2434                 return 0;
2435
2436         ch_rate = rate * 1000;
2437         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2438         if ((ch_rate < min_rate && ch_rate)) {
2439                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2440                         min_rate);
2441                 return -EINVAL;
2442         }
2443
2444         if (rate > cpsw->speed) {
2445                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2446                 return -EINVAL;
2447         }
2448
2449         ret = pm_runtime_get_sync(cpsw->dev);
2450         if (ret < 0) {
2451                 pm_runtime_put_noidle(cpsw->dev);
2452                 return ret;
2453         }
2454
2455         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2456         pm_runtime_put(cpsw->dev);
2457
2458         if (ret)
2459                 return ret;
2460
2461         /* update rates for slaves tx queues */
2462         for (i = 0; i < cpsw->data.slaves; i++) {
2463                 slave = &cpsw->slaves[i];
2464                 if (!slave->ndev)
2465                         continue;
2466
2467                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2468         }
2469
2470         cpsw_split_res(ndev);
2471         return ret;
2472 }
2473
2474 static int cpsw_set_mqprio(struct net_device *ndev, void *type_data)
2475 {
2476         struct tc_mqprio_qopt_offload *mqprio = type_data;
2477         struct cpsw_priv *priv = netdev_priv(ndev);
2478         struct cpsw_common *cpsw = priv->cpsw;
2479         int fifo, num_tc, count, offset;
2480         struct cpsw_slave *slave;
2481         u32 tx_prio_map = 0;
2482         int i, tc, ret;
2483
2484         num_tc = mqprio->qopt.num_tc;
2485         if (num_tc > CPSW_TC_NUM)
2486                 return -EINVAL;
2487
2488         if (mqprio->mode != TC_MQPRIO_MODE_DCB)
2489                 return -EINVAL;
2490
2491         ret = pm_runtime_get_sync(cpsw->dev);
2492         if (ret < 0) {
2493                 pm_runtime_put_noidle(cpsw->dev);
2494                 return ret;
2495         }
2496
2497         if (num_tc) {
2498                 for (i = 0; i < 8; i++) {
2499                         tc = mqprio->qopt.prio_tc_map[i];
2500                         fifo = cpsw_tc_to_fifo(tc, num_tc);
2501                         tx_prio_map |= fifo << (4 * i);
2502                 }
2503
2504                 netdev_set_num_tc(ndev, num_tc);
2505                 for (i = 0; i < num_tc; i++) {
2506                         count = mqprio->qopt.count[i];
2507                         offset = mqprio->qopt.offset[i];
2508                         netdev_set_tc_queue(ndev, i, count, offset);
2509                 }
2510         }
2511
2512         if (!mqprio->qopt.hw) {
2513                 /* restore default configuration */
2514                 netdev_reset_tc(ndev);
2515                 tx_prio_map = TX_PRIORITY_MAPPING;
2516         }
2517
2518         priv->mqprio_hw = mqprio->qopt.hw;
2519
2520         offset = cpsw->version == CPSW_VERSION_1 ?
2521                  CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
2522
2523         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2524         slave_write(slave, tx_prio_map, offset);
2525
2526         pm_runtime_put_sync(cpsw->dev);
2527
2528         return 0;
2529 }
2530
2531 static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
2532                              void *type_data)
2533 {
2534         switch (type) {
2535         case TC_SETUP_QDISC_CBS:
2536                 return cpsw_set_cbs(ndev, type_data);
2537
2538         case TC_SETUP_QDISC_MQPRIO:
2539                 return cpsw_set_mqprio(ndev, type_data);
2540
2541         default:
2542                 return -EOPNOTSUPP;
2543         }
2544 }
2545
2546 static const struct net_device_ops cpsw_netdev_ops = {
2547         .ndo_open               = cpsw_ndo_open,
2548         .ndo_stop               = cpsw_ndo_stop,
2549         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2550         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2551         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2552         .ndo_validate_addr      = eth_validate_addr,
2553         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2554         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2555         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2556 #ifdef CONFIG_NET_POLL_CONTROLLER
2557         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2558 #endif
2559         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2560         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2561         .ndo_setup_tc           = cpsw_ndo_setup_tc,
2562 };
2563
2564 static int cpsw_get_regs_len(struct net_device *ndev)
2565 {
2566         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2567
2568         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2569 }
2570
2571 static void cpsw_get_regs(struct net_device *ndev,
2572                           struct ethtool_regs *regs, void *p)
2573 {
2574         u32 *reg = p;
2575         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2576
2577         /* update CPSW IP version */
2578         regs->version = cpsw->version;
2579
2580         cpsw_ale_dump(cpsw->ale, reg);
2581 }
2582
2583 static void cpsw_get_drvinfo(struct net_device *ndev,
2584                              struct ethtool_drvinfo *info)
2585 {
2586         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2587         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2588
2589         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2590         strlcpy(info->version, "1.0", sizeof(info->version));
2591         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2592 }
2593
2594 static u32 cpsw_get_msglevel(struct net_device *ndev)
2595 {
2596         struct cpsw_priv *priv = netdev_priv(ndev);
2597         return priv->msg_enable;
2598 }
2599
2600 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2601 {
2602         struct cpsw_priv *priv = netdev_priv(ndev);
2603         priv->msg_enable = value;
2604 }
2605
2606 #if IS_ENABLED(CONFIG_TI_CPTS)
2607 static int cpsw_get_ts_info(struct net_device *ndev,
2608                             struct ethtool_ts_info *info)
2609 {
2610         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2611
2612         info->so_timestamping =
2613                 SOF_TIMESTAMPING_TX_HARDWARE |
2614                 SOF_TIMESTAMPING_TX_SOFTWARE |
2615                 SOF_TIMESTAMPING_RX_HARDWARE |
2616                 SOF_TIMESTAMPING_RX_SOFTWARE |
2617                 SOF_TIMESTAMPING_SOFTWARE |
2618                 SOF_TIMESTAMPING_RAW_HARDWARE;
2619         info->phc_index = cpsw->cpts->phc_index;
2620         info->tx_types =
2621                 (1 << HWTSTAMP_TX_OFF) |
2622                 (1 << HWTSTAMP_TX_ON);
2623         info->rx_filters =
2624                 (1 << HWTSTAMP_FILTER_NONE) |
2625                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2626                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2627         return 0;
2628 }
2629 #else
2630 static int cpsw_get_ts_info(struct net_device *ndev,
2631                             struct ethtool_ts_info *info)
2632 {
2633         info->so_timestamping =
2634                 SOF_TIMESTAMPING_TX_SOFTWARE |
2635                 SOF_TIMESTAMPING_RX_SOFTWARE |
2636                 SOF_TIMESTAMPING_SOFTWARE;
2637         info->phc_index = -1;
2638         info->tx_types = 0;
2639         info->rx_filters = 0;
2640         return 0;
2641 }
2642 #endif
2643
2644 static int cpsw_get_link_ksettings(struct net_device *ndev,
2645                                    struct ethtool_link_ksettings *ecmd)
2646 {
2647         struct cpsw_priv *priv = netdev_priv(ndev);
2648         struct cpsw_common *cpsw = priv->cpsw;
2649         int slave_no = cpsw_slave_index(cpsw, priv);
2650
2651         if (!cpsw->slaves[slave_no].phy)
2652                 return -EOPNOTSUPP;
2653
2654         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2655         return 0;
2656 }
2657
2658 static int cpsw_set_link_ksettings(struct net_device *ndev,
2659                                    const struct ethtool_link_ksettings *ecmd)
2660 {
2661         struct cpsw_priv *priv = netdev_priv(ndev);
2662         struct cpsw_common *cpsw = priv->cpsw;
2663         int slave_no = cpsw_slave_index(cpsw, priv);
2664
2665         if (cpsw->slaves[slave_no].phy)
2666                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2667                                                  ecmd);
2668         else
2669                 return -EOPNOTSUPP;
2670 }
2671
2672 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2673 {
2674         struct cpsw_priv *priv = netdev_priv(ndev);
2675         struct cpsw_common *cpsw = priv->cpsw;
2676         int slave_no = cpsw_slave_index(cpsw, priv);
2677
2678         wol->supported = 0;
2679         wol->wolopts = 0;
2680
2681         if (cpsw->slaves[slave_no].phy)
2682                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2683 }
2684
2685 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2686 {
2687         struct cpsw_priv *priv = netdev_priv(ndev);
2688         struct cpsw_common *cpsw = priv->cpsw;
2689         int slave_no = cpsw_slave_index(cpsw, priv);
2690
2691         if (cpsw->slaves[slave_no].phy)
2692                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2693         else
2694                 return -EOPNOTSUPP;
2695 }
2696
2697 static void cpsw_get_pauseparam(struct net_device *ndev,
2698                                 struct ethtool_pauseparam *pause)
2699 {
2700         struct cpsw_priv *priv = netdev_priv(ndev);
2701
2702         pause->autoneg = AUTONEG_DISABLE;
2703         pause->rx_pause = priv->rx_pause ? true : false;
2704         pause->tx_pause = priv->tx_pause ? true : false;
2705 }
2706
2707 static int cpsw_set_pauseparam(struct net_device *ndev,
2708                                struct ethtool_pauseparam *pause)
2709 {
2710         struct cpsw_priv *priv = netdev_priv(ndev);
2711         bool link;
2712
2713         priv->rx_pause = pause->rx_pause ? true : false;
2714         priv->tx_pause = pause->tx_pause ? true : false;
2715
2716         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2717         return 0;
2718 }
2719
2720 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2721 {
2722         struct cpsw_priv *priv = netdev_priv(ndev);
2723         struct cpsw_common *cpsw = priv->cpsw;
2724         int ret;
2725
2726         ret = pm_runtime_get_sync(cpsw->dev);
2727         if (ret < 0) {
2728                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2729                 pm_runtime_put_noidle(cpsw->dev);
2730         }
2731
2732         return ret;
2733 }
2734
2735 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2736 {
2737         struct cpsw_priv *priv = netdev_priv(ndev);
2738         int ret;
2739
2740         ret = pm_runtime_put(priv->cpsw->dev);
2741         if (ret < 0)
2742                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2743 }
2744
2745 static void cpsw_get_channels(struct net_device *ndev,
2746                               struct ethtool_channels *ch)
2747 {
2748         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2749
2750         ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2751         ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2752         ch->max_combined = 0;
2753         ch->max_other = 0;
2754         ch->other_count = 0;
2755         ch->rx_count = cpsw->rx_ch_num;
2756         ch->tx_count = cpsw->tx_ch_num;
2757         ch->combined_count = 0;
2758 }
2759
2760 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2761                                   struct ethtool_channels *ch)
2762 {
2763         if (cpsw->quirk_irq) {
2764                 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2765                 return -EOPNOTSUPP;
2766         }
2767
2768         if (ch->combined_count)
2769                 return -EINVAL;
2770
2771         /* verify we have at least one channel in each direction */
2772         if (!ch->rx_count || !ch->tx_count)
2773                 return -EINVAL;
2774
2775         if (ch->rx_count > cpsw->data.channels ||
2776             ch->tx_count > cpsw->data.channels)
2777                 return -EINVAL;
2778
2779         return 0;
2780 }
2781
2782 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2783 {
2784         struct cpsw_common *cpsw = priv->cpsw;
2785         void (*handler)(void *, int, int);
2786         struct netdev_queue *queue;
2787         struct cpsw_vector *vec;
2788         int ret, *ch, vch;
2789
2790         if (rx) {
2791                 ch = &cpsw->rx_ch_num;
2792                 vec = cpsw->rxv;
2793                 handler = cpsw_rx_handler;
2794         } else {
2795                 ch = &cpsw->tx_ch_num;
2796                 vec = cpsw->txv;
2797                 handler = cpsw_tx_handler;
2798         }
2799
2800         while (*ch < ch_num) {
2801                 vch = rx ? *ch : 7 - *ch;
2802                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
2803                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2804                 queue->tx_maxrate = 0;
2805
2806                 if (IS_ERR(vec[*ch].ch))
2807                         return PTR_ERR(vec[*ch].ch);
2808
2809                 if (!vec[*ch].ch)
2810                         return -EINVAL;
2811
2812                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2813                           (rx ? "rx" : "tx"));
2814                 (*ch)++;
2815         }
2816
2817         while (*ch > ch_num) {
2818                 (*ch)--;
2819
2820                 ret = cpdma_chan_destroy(vec[*ch].ch);
2821                 if (ret)
2822                         return ret;
2823
2824                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2825                           (rx ? "rx" : "tx"));
2826         }
2827
2828         return 0;
2829 }
2830
2831 static int cpsw_update_channels(struct cpsw_priv *priv,
2832                                 struct ethtool_channels *ch)
2833 {
2834         int ret;
2835
2836         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2837         if (ret)
2838                 return ret;
2839
2840         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2841         if (ret)
2842                 return ret;
2843
2844         return 0;
2845 }
2846
2847 static void cpsw_suspend_data_pass(struct net_device *ndev)
2848 {
2849         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2850         struct cpsw_slave *slave;
2851         int i;
2852
2853         /* Disable NAPI scheduling */
2854         cpsw_intr_disable(cpsw);
2855
2856         /* Stop all transmit queues for every network device.
2857          * Disable re-using rx descriptors with dormant_on.
2858          */
2859         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2860                 if (!(slave->ndev && netif_running(slave->ndev)))
2861                         continue;
2862
2863                 netif_tx_stop_all_queues(slave->ndev);
2864                 netif_dormant_on(slave->ndev);
2865         }
2866
2867         /* Handle rest of tx packets and stop cpdma channels */
2868         cpdma_ctlr_stop(cpsw->dma);
2869 }
2870
2871 static int cpsw_resume_data_pass(struct net_device *ndev)
2872 {
2873         struct cpsw_priv *priv = netdev_priv(ndev);
2874         struct cpsw_common *cpsw = priv->cpsw;
2875         struct cpsw_slave *slave;
2876         int i, ret;
2877
2878         /* Allow rx packets handling */
2879         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2880                 if (slave->ndev && netif_running(slave->ndev))
2881                         netif_dormant_off(slave->ndev);
2882
2883         /* After this receive is started */
2884         if (cpsw->usage_count) {
2885                 ret = cpsw_fill_rx_channels(priv);
2886                 if (ret)
2887                         return ret;
2888
2889                 cpdma_ctlr_start(cpsw->dma);
2890                 cpsw_intr_enable(cpsw);
2891         }
2892
2893         /* Resume transmit for every affected interface */
2894         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2895                 if (slave->ndev && netif_running(slave->ndev))
2896                         netif_tx_start_all_queues(slave->ndev);
2897
2898         return 0;
2899 }
2900
2901 static int cpsw_set_channels(struct net_device *ndev,
2902                              struct ethtool_channels *chs)
2903 {
2904         struct cpsw_priv *priv = netdev_priv(ndev);
2905         struct cpsw_common *cpsw = priv->cpsw;
2906         struct cpsw_slave *slave;
2907         int i, ret;
2908
2909         ret = cpsw_check_ch_settings(cpsw, chs);
2910         if (ret < 0)
2911                 return ret;
2912
2913         cpsw_suspend_data_pass(ndev);
2914         ret = cpsw_update_channels(priv, chs);
2915         if (ret)
2916                 goto err;
2917
2918         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2919                 if (!(slave->ndev && netif_running(slave->ndev)))
2920                         continue;
2921
2922                 /* Inform stack about new count of queues */
2923                 ret = netif_set_real_num_tx_queues(slave->ndev,
2924                                                    cpsw->tx_ch_num);
2925                 if (ret) {
2926                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2927                         goto err;
2928                 }
2929
2930                 ret = netif_set_real_num_rx_queues(slave->ndev,
2931                                                    cpsw->rx_ch_num);
2932                 if (ret) {
2933                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2934                         goto err;
2935                 }
2936         }
2937
2938         if (cpsw->usage_count)
2939                 cpsw_split_res(ndev);
2940
2941         ret = cpsw_resume_data_pass(ndev);
2942         if (!ret)
2943                 return 0;
2944 err:
2945         dev_err(priv->dev, "cannot update channels number, closing device\n");
2946         dev_close(ndev);
2947         return ret;
2948 }
2949
2950 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2951 {
2952         struct cpsw_priv *priv = netdev_priv(ndev);
2953         struct cpsw_common *cpsw = priv->cpsw;
2954         int slave_no = cpsw_slave_index(cpsw, priv);
2955
2956         if (cpsw->slaves[slave_no].phy)
2957                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2958         else
2959                 return -EOPNOTSUPP;
2960 }
2961
2962 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2963 {
2964         struct cpsw_priv *priv = netdev_priv(ndev);
2965         struct cpsw_common *cpsw = priv->cpsw;
2966         int slave_no = cpsw_slave_index(cpsw, priv);
2967
2968         if (cpsw->slaves[slave_no].phy)
2969                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2970         else
2971                 return -EOPNOTSUPP;
2972 }
2973
2974 static int cpsw_nway_reset(struct net_device *ndev)
2975 {
2976         struct cpsw_priv *priv = netdev_priv(ndev);
2977         struct cpsw_common *cpsw = priv->cpsw;
2978         int slave_no = cpsw_slave_index(cpsw, priv);
2979
2980         if (cpsw->slaves[slave_no].phy)
2981                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2982         else
2983                 return -EOPNOTSUPP;
2984 }
2985
2986 static void cpsw_get_ringparam(struct net_device *ndev,
2987                                struct ethtool_ringparam *ering)
2988 {
2989         struct cpsw_priv *priv = netdev_priv(ndev);
2990         struct cpsw_common *cpsw = priv->cpsw;
2991
2992         /* not supported */
2993         ering->tx_max_pending = 0;
2994         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2995         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2996         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2997 }
2998
2999 static int cpsw_set_ringparam(struct net_device *ndev,
3000                               struct ethtool_ringparam *ering)
3001 {
3002         struct cpsw_priv *priv = netdev_priv(ndev);
3003         struct cpsw_common *cpsw = priv->cpsw;
3004         int ret;
3005
3006         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
3007
3008         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
3009             ering->rx_pending < CPSW_MAX_QUEUES ||
3010             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
3011                 return -EINVAL;
3012
3013         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
3014                 return 0;
3015
3016         cpsw_suspend_data_pass(ndev);
3017
3018         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
3019
3020         if (cpsw->usage_count)
3021                 cpdma_chan_split_pool(cpsw->dma);
3022
3023         ret = cpsw_resume_data_pass(ndev);
3024         if (!ret)
3025                 return 0;
3026
3027         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
3028         dev_close(ndev);
3029         return ret;
3030 }
3031
3032 static const struct ethtool_ops cpsw_ethtool_ops = {
3033         .get_drvinfo    = cpsw_get_drvinfo,
3034         .get_msglevel   = cpsw_get_msglevel,
3035         .set_msglevel   = cpsw_set_msglevel,
3036         .get_link       = ethtool_op_get_link,
3037         .get_ts_info    = cpsw_get_ts_info,
3038         .get_coalesce   = cpsw_get_coalesce,
3039         .set_coalesce   = cpsw_set_coalesce,
3040         .get_sset_count         = cpsw_get_sset_count,
3041         .get_strings            = cpsw_get_strings,
3042         .get_ethtool_stats      = cpsw_get_ethtool_stats,
3043         .get_pauseparam         = cpsw_get_pauseparam,
3044         .set_pauseparam         = cpsw_set_pauseparam,
3045         .get_wol        = cpsw_get_wol,
3046         .set_wol        = cpsw_set_wol,
3047         .get_regs_len   = cpsw_get_regs_len,
3048         .get_regs       = cpsw_get_regs,
3049         .begin          = cpsw_ethtool_op_begin,
3050         .complete       = cpsw_ethtool_op_complete,
3051         .get_channels   = cpsw_get_channels,
3052         .set_channels   = cpsw_set_channels,
3053         .get_link_ksettings     = cpsw_get_link_ksettings,
3054         .set_link_ksettings     = cpsw_set_link_ksettings,
3055         .get_eee        = cpsw_get_eee,
3056         .set_eee        = cpsw_set_eee,
3057         .nway_reset     = cpsw_nway_reset,
3058         .get_ringparam = cpsw_get_ringparam,
3059         .set_ringparam = cpsw_set_ringparam,
3060 };
3061
3062 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
3063                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
3064 {
3065         void __iomem            *regs = cpsw->regs;
3066         int                     slave_num = slave->slave_num;
3067         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
3068
3069         slave->data     = data;
3070         slave->regs     = regs + slave_reg_ofs;
3071         slave->sliver   = regs + sliver_reg_ofs;
3072         slave->port_vlan = data->dual_emac_res_vlan;
3073 }
3074
3075 static int cpsw_probe_dt(struct cpsw_platform_data *data,
3076                          struct platform_device *pdev)
3077 {
3078         struct device_node *node = pdev->dev.of_node;
3079         struct device_node *slave_node;
3080         int i = 0, ret;
3081         u32 prop;
3082
3083         if (!node)
3084                 return -EINVAL;
3085
3086         if (of_property_read_u32(node, "slaves", &prop)) {
3087                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
3088                 return -EINVAL;
3089         }
3090         data->slaves = prop;
3091
3092         if (of_property_read_u32(node, "active_slave", &prop)) {
3093                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
3094                 return -EINVAL;
3095         }
3096         data->active_slave = prop;
3097
3098         data->slave_data = devm_kcalloc(&pdev->dev,
3099                                         data->slaves,
3100                                         sizeof(struct cpsw_slave_data),
3101                                         GFP_KERNEL);
3102         if (!data->slave_data)
3103                 return -ENOMEM;
3104
3105         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
3106                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
3107                 return -EINVAL;
3108         }
3109         data->channels = prop;
3110
3111         if (of_property_read_u32(node, "ale_entries", &prop)) {
3112                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
3113                 return -EINVAL;
3114         }
3115         data->ale_entries = prop;
3116
3117         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
3118                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
3119                 return -EINVAL;
3120         }
3121         data->bd_ram_size = prop;
3122
3123         if (of_property_read_u32(node, "mac_control", &prop)) {
3124                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
3125                 return -EINVAL;
3126         }
3127         data->mac_control = prop;
3128
3129         if (of_property_read_bool(node, "dual_emac"))
3130                 data->dual_emac = 1;
3131
3132         /*
3133          * Populate all the child nodes here...
3134          */
3135         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
3136         /* We do not want to force this, as in some cases may not have child */
3137         if (ret)
3138                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
3139
3140         for_each_available_child_of_node(node, slave_node) {
3141                 struct cpsw_slave_data *slave_data = data->slave_data + i;
3142                 const void *mac_addr = NULL;
3143                 int lenp;
3144                 const __be32 *parp;
3145
3146                 /* This is no slave child node, continue */
3147                 if (strcmp(slave_node->name, "slave"))
3148                         continue;
3149
3150                 slave_data->phy_node = of_parse_phandle(slave_node,
3151                                                         "phy-handle", 0);
3152                 parp = of_get_property(slave_node, "phy_id", &lenp);
3153                 if (slave_data->phy_node) {
3154                         dev_dbg(&pdev->dev,
3155                                 "slave[%d] using phy-handle=\"%pOF\"\n",
3156                                 i, slave_data->phy_node);
3157                 } else if (of_phy_is_fixed_link(slave_node)) {
3158                         /* In the case of a fixed PHY, the DT node associated
3159                          * to the PHY is the Ethernet MAC DT node.
3160                          */
3161                         ret = of_phy_register_fixed_link(slave_node);
3162                         if (ret) {
3163                                 if (ret != -EPROBE_DEFER)
3164                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
3165                                 return ret;
3166                         }
3167                         slave_data->phy_node = of_node_get(slave_node);
3168                 } else if (parp) {
3169                         u32 phyid;
3170                         struct device_node *mdio_node;
3171                         struct platform_device *mdio;
3172
3173                         if (lenp != (sizeof(__be32) * 2)) {
3174                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
3175                                 goto no_phy_slave;
3176                         }
3177                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
3178                         phyid = be32_to_cpup(parp+1);
3179                         mdio = of_find_device_by_node(mdio_node);
3180                         of_node_put(mdio_node);
3181                         if (!mdio) {
3182                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
3183                                 return -EINVAL;
3184                         }
3185                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
3186                                  PHY_ID_FMT, mdio->name, phyid);
3187                         put_device(&mdio->dev);
3188                 } else {
3189                         dev_err(&pdev->dev,
3190                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
3191                                 i);
3192                         goto no_phy_slave;
3193                 }
3194                 slave_data->phy_if = of_get_phy_mode(slave_node);
3195                 if (slave_data->phy_if < 0) {
3196                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
3197                                 i);
3198                         return slave_data->phy_if;
3199                 }
3200
3201 no_phy_slave:
3202                 mac_addr = of_get_mac_address(slave_node);
3203                 if (mac_addr) {
3204                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
3205                 } else {
3206                         ret = ti_cm_get_macid(&pdev->dev, i,
3207                                               slave_data->mac_addr);
3208                         if (ret)
3209                                 return ret;
3210                 }
3211                 if (data->dual_emac) {
3212                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
3213                                                  &prop)) {
3214                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
3215                                 slave_data->dual_emac_res_vlan = i+1;
3216                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
3217                                         slave_data->dual_emac_res_vlan, i);
3218                         } else {
3219                                 slave_data->dual_emac_res_vlan = prop;
3220                         }
3221                 }
3222
3223                 i++;
3224                 if (i == data->slaves)
3225                         break;
3226         }
3227
3228         return 0;
3229 }
3230
3231 static void cpsw_remove_dt(struct platform_device *pdev)
3232 {
3233         struct net_device *ndev = platform_get_drvdata(pdev);
3234         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3235         struct cpsw_platform_data *data = &cpsw->data;
3236         struct device_node *node = pdev->dev.of_node;
3237         struct device_node *slave_node;
3238         int i = 0;
3239
3240         for_each_available_child_of_node(node, slave_node) {
3241                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
3242
3243                 if (strcmp(slave_node->name, "slave"))
3244                         continue;
3245
3246                 if (of_phy_is_fixed_link(slave_node))
3247                         of_phy_deregister_fixed_link(slave_node);
3248
3249                 of_node_put(slave_data->phy_node);
3250
3251                 i++;
3252                 if (i == data->slaves)
3253                         break;
3254         }
3255
3256         of_platform_depopulate(&pdev->dev);
3257 }
3258
3259 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
3260 {
3261         struct cpsw_common              *cpsw = priv->cpsw;
3262         struct cpsw_platform_data       *data = &cpsw->data;
3263         struct net_device               *ndev;
3264         struct cpsw_priv                *priv_sl2;
3265         int ret = 0;
3266
3267         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
3268         if (!ndev) {
3269                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
3270                 return -ENOMEM;
3271         }
3272
3273         priv_sl2 = netdev_priv(ndev);
3274         priv_sl2->cpsw = cpsw;
3275         priv_sl2->ndev = ndev;
3276         priv_sl2->dev  = &ndev->dev;
3277         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3278
3279         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
3280                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
3281                         ETH_ALEN);
3282                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
3283                          priv_sl2->mac_addr);
3284         } else {
3285                 eth_random_addr(priv_sl2->mac_addr);
3286                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
3287                          priv_sl2->mac_addr);
3288         }
3289         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
3290
3291         priv_sl2->emac_port = 1;
3292         cpsw->slaves[1].ndev = ndev;
3293         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3294
3295         ndev->netdev_ops = &cpsw_netdev_ops;
3296         ndev->ethtool_ops = &cpsw_ethtool_ops;
3297
3298         /* register the network device */
3299         SET_NETDEV_DEV(ndev, cpsw->dev);
3300         ret = register_netdev(ndev);
3301         if (ret) {
3302                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
3303                 free_netdev(ndev);
3304                 ret = -ENODEV;
3305         }