6cf4d4cb152ef8ae52d895dc89aab86547872210
[muen/linux.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2  * Texas Instruments Ethernet Switch Driver
3  *
4  * Copyright (C) 2012 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38 #include <linux/kmemleak.h>
39 #include <linux/sys_soc.h>
40
41 #include <linux/pinctrl/consumer.h>
42 #include <net/pkt_cls.h>
43
44 #include "cpsw.h"
45 #include "cpsw_ale.h"
46 #include "cpts.h"
47 #include "davinci_cpdma.h"
48
49 #include <net/pkt_sched.h>
50
51 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
52                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
53                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
54                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
55                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
56                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
57                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
58                          NETIF_MSG_RX_STATUS)
59
60 #define cpsw_info(priv, type, format, ...)              \
61 do {                                                            \
62         if (netif_msg_##type(priv) && net_ratelimit())          \
63                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
64 } while (0)
65
66 #define cpsw_err(priv, type, format, ...)               \
67 do {                                                            \
68         if (netif_msg_##type(priv) && net_ratelimit())          \
69                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
70 } while (0)
71
72 #define cpsw_dbg(priv, type, format, ...)               \
73 do {                                                            \
74         if (netif_msg_##type(priv) && net_ratelimit())          \
75                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
76 } while (0)
77
78 #define cpsw_notice(priv, type, format, ...)            \
79 do {                                                            \
80         if (netif_msg_##type(priv) && net_ratelimit())          \
81                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
82 } while (0)
83
84 #define ALE_ALL_PORTS           0x7
85
86 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
87 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
88 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
89
90 #define CPSW_VERSION_1          0x19010a
91 #define CPSW_VERSION_2          0x19010c
92 #define CPSW_VERSION_3          0x19010f
93 #define CPSW_VERSION_4          0x190112
94
95 #define HOST_PORT_NUM           0
96 #define CPSW_ALE_PORTS_NUM      3
97 #define SLIVER_SIZE             0x40
98
99 #define CPSW1_HOST_PORT_OFFSET  0x028
100 #define CPSW1_SLAVE_OFFSET      0x050
101 #define CPSW1_SLAVE_SIZE        0x040
102 #define CPSW1_CPDMA_OFFSET      0x100
103 #define CPSW1_STATERAM_OFFSET   0x200
104 #define CPSW1_HW_STATS          0x400
105 #define CPSW1_CPTS_OFFSET       0x500
106 #define CPSW1_ALE_OFFSET        0x600
107 #define CPSW1_SLIVER_OFFSET     0x700
108
109 #define CPSW2_HOST_PORT_OFFSET  0x108
110 #define CPSW2_SLAVE_OFFSET      0x200
111 #define CPSW2_SLAVE_SIZE        0x100
112 #define CPSW2_CPDMA_OFFSET      0x800
113 #define CPSW2_HW_STATS          0x900
114 #define CPSW2_STATERAM_OFFSET   0xa00
115 #define CPSW2_CPTS_OFFSET       0xc00
116 #define CPSW2_ALE_OFFSET        0xd00
117 #define CPSW2_SLIVER_OFFSET     0xd80
118 #define CPSW2_BD_OFFSET         0x2000
119
120 #define CPDMA_RXTHRESH          0x0c0
121 #define CPDMA_RXFREE            0x0e0
122 #define CPDMA_TXHDP             0x00
123 #define CPDMA_RXHDP             0x20
124 #define CPDMA_TXCP              0x40
125 #define CPDMA_RXCP              0x60
126
127 #define CPSW_POLL_WEIGHT        64
128 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE             4
129 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
130 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN +\
131                                  ETH_FCS_LEN +\
132                                  CPSW_RX_VLAN_ENCAP_HDR_SIZE)
133
134 #define RX_PRIORITY_MAPPING     0x76543210
135 #define TX_PRIORITY_MAPPING     0x33221100
136 #define CPDMA_TX_PRIORITY_MAP   0x76543210
137
138 #define CPSW_VLAN_AWARE         BIT(1)
139 #define CPSW_RX_VLAN_ENCAP      BIT(2)
140 #define CPSW_ALE_VLAN_AWARE     1
141
142 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
143 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
144 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
145
146 #define CPSW_INTPACEEN          (0x3f << 16)
147 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
148 #define CPSW_CMINTMAX_CNT       63
149 #define CPSW_CMINTMIN_CNT       2
150 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
151 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
152
153 #define cpsw_slave_index(cpsw, priv)                            \
154                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
155                 cpsw->data.active_slave)
156 #define IRQ_NUM                 2
157 #define CPSW_MAX_QUEUES         8
158 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
159 #define CPSW_FIFO_QUEUE_TYPE_SHIFT      16
160 #define CPSW_FIFO_SHAPE_EN_SHIFT        16
161 #define CPSW_FIFO_RATE_EN_SHIFT         20
162 #define CPSW_TC_NUM                     4
163 #define CPSW_FIFO_SHAPERS_NUM           (CPSW_TC_NUM - 1)
164 #define CPSW_PCT_MASK                   0x7f
165
166 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT       29
167 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK         GENMASK(2, 0)
168 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT        16
169 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT   8
170 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK     GENMASK(1, 0)
171 enum {
172         CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
173         CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
174         CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
175         CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
176 };
177
178 static int debug_level;
179 module_param(debug_level, int, 0);
180 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
181
182 static int ale_ageout = 10;
183 module_param(ale_ageout, int, 0);
184 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
185
186 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
187 module_param(rx_packet_max, int, 0);
188 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
189
190 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
191 module_param(descs_pool_size, int, 0444);
192 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
193
194 struct cpsw_wr_regs {
195         u32     id_ver;
196         u32     soft_reset;
197         u32     control;
198         u32     int_control;
199         u32     rx_thresh_en;
200         u32     rx_en;
201         u32     tx_en;
202         u32     misc_en;
203         u32     mem_allign1[8];
204         u32     rx_thresh_stat;
205         u32     rx_stat;
206         u32     tx_stat;
207         u32     misc_stat;
208         u32     mem_allign2[8];
209         u32     rx_imax;
210         u32     tx_imax;
211
212 };
213
214 struct cpsw_ss_regs {
215         u32     id_ver;
216         u32     control;
217         u32     soft_reset;
218         u32     stat_port_en;
219         u32     ptype;
220         u32     soft_idle;
221         u32     thru_rate;
222         u32     gap_thresh;
223         u32     tx_start_wds;
224         u32     flow_control;
225         u32     vlan_ltype;
226         u32     ts_ltype;
227         u32     dlr_ltype;
228 };
229
230 /* CPSW_PORT_V1 */
231 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
232 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
233 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
234 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
235 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
236 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
237 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
238 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
239
240 /* CPSW_PORT_V2 */
241 #define CPSW2_CONTROL       0x00 /* Control Register */
242 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
243 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
244 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
245 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
246 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
247 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
248
249 /* CPSW_PORT_V1 and V2 */
250 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
251 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
252 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
253
254 /* CPSW_PORT_V2 only */
255 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
256 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
257 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
258 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
259 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
260 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
261 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
262 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
263
264 /* Bit definitions for the CPSW2_CONTROL register */
265 #define PASS_PRI_TAGGED     BIT(24) /* Pass Priority Tagged */
266 #define VLAN_LTYPE2_EN      BIT(21) /* VLAN LTYPE 2 enable */
267 #define VLAN_LTYPE1_EN      BIT(20) /* VLAN LTYPE 1 enable */
268 #define DSCP_PRI_EN         BIT(16) /* DSCP Priority Enable */
269 #define TS_107              BIT(15) /* Tyme Sync Dest IP Address 107 */
270 #define TS_320              BIT(14) /* Time Sync Dest Port 320 enable */
271 #define TS_319              BIT(13) /* Time Sync Dest Port 319 enable */
272 #define TS_132              BIT(12) /* Time Sync Dest IP Addr 132 enable */
273 #define TS_131              BIT(11) /* Time Sync Dest IP Addr 131 enable */
274 #define TS_130              BIT(10) /* Time Sync Dest IP Addr 130 enable */
275 #define TS_129              BIT(9)  /* Time Sync Dest IP Addr 129 enable */
276 #define TS_TTL_NONZERO      BIT(8)  /* Time Sync Time To Live Non-zero enable */
277 #define TS_ANNEX_F_EN       BIT(6)  /* Time Sync Annex F enable */
278 #define TS_ANNEX_D_EN       BIT(4)  /* Time Sync Annex D enable */
279 #define TS_LTYPE2_EN        BIT(3)  /* Time Sync LTYPE 2 enable */
280 #define TS_LTYPE1_EN        BIT(2)  /* Time Sync LTYPE 1 enable */
281 #define TS_TX_EN            BIT(1)  /* Time Sync Transmit Enable */
282 #define TS_RX_EN            BIT(0)  /* Time Sync Receive Enable */
283
284 #define CTRL_V2_TS_BITS \
285         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
286          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
287
288 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
289 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
290 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
291
292
293 #define CTRL_V3_TS_BITS \
294         (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
295          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
296          TS_LTYPE1_EN)
297
298 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
299 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
300 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
301
302 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
303 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
304 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
305 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
306 #define TS_MSG_TYPE_EN_MASK      (0xffff)
307
308 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
309 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
310
311 /* Bit definitions for the CPSW1_TS_CTL register */
312 #define CPSW_V1_TS_RX_EN                BIT(0)
313 #define CPSW_V1_TS_TX_EN                BIT(4)
314 #define CPSW_V1_MSG_TYPE_OFS            16
315
316 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
317 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
318
319 #define CPSW_MAX_BLKS_TX                15
320 #define CPSW_MAX_BLKS_TX_SHIFT          4
321 #define CPSW_MAX_BLKS_RX                5
322
323 struct cpsw_host_regs {
324         u32     max_blks;
325         u32     blk_cnt;
326         u32     tx_in_ctl;
327         u32     port_vlan;
328         u32     tx_pri_map;
329         u32     cpdma_tx_pri_map;
330         u32     cpdma_rx_chan_map;
331 };
332
333 struct cpsw_sliver_regs {
334         u32     id_ver;
335         u32     mac_control;
336         u32     mac_status;
337         u32     soft_reset;
338         u32     rx_maxlen;
339         u32     __reserved_0;
340         u32     rx_pause;
341         u32     tx_pause;
342         u32     __reserved_1;
343         u32     rx_pri_map;
344 };
345
346 struct cpsw_hw_stats {
347         u32     rxgoodframes;
348         u32     rxbroadcastframes;
349         u32     rxmulticastframes;
350         u32     rxpauseframes;
351         u32     rxcrcerrors;
352         u32     rxaligncodeerrors;
353         u32     rxoversizedframes;
354         u32     rxjabberframes;
355         u32     rxundersizedframes;
356         u32     rxfragments;
357         u32     __pad_0[2];
358         u32     rxoctets;
359         u32     txgoodframes;
360         u32     txbroadcastframes;
361         u32     txmulticastframes;
362         u32     txpauseframes;
363         u32     txdeferredframes;
364         u32     txcollisionframes;
365         u32     txsinglecollframes;
366         u32     txmultcollframes;
367         u32     txexcessivecollisions;
368         u32     txlatecollisions;
369         u32     txunderrun;
370         u32     txcarriersenseerrors;
371         u32     txoctets;
372         u32     octetframes64;
373         u32     octetframes65t127;
374         u32     octetframes128t255;
375         u32     octetframes256t511;
376         u32     octetframes512t1023;
377         u32     octetframes1024tup;
378         u32     netoctets;
379         u32     rxsofoverruns;
380         u32     rxmofoverruns;
381         u32     rxdmaoverruns;
382 };
383
384 struct cpsw_slave_data {
385         struct device_node *phy_node;
386         char            phy_id[MII_BUS_ID_SIZE];
387         int             phy_if;
388         u8              mac_addr[ETH_ALEN];
389         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
390 };
391
392 struct cpsw_platform_data {
393         struct cpsw_slave_data  *slave_data;
394         u32     ss_reg_ofs;     /* Subsystem control register offset */
395         u32     channels;       /* number of cpdma channels (symmetric) */
396         u32     slaves;         /* number of slave cpgmac ports */
397         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
398         u32     ale_entries;    /* ale table size */
399         u32     bd_ram_size;  /*buffer descriptor ram size */
400         u32     mac_control;    /* Mac control register */
401         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
402         bool    dual_emac;      /* Enable Dual EMAC mode */
403 };
404
405 struct cpsw_slave {
406         void __iomem                    *regs;
407         struct cpsw_sliver_regs __iomem *sliver;
408         int                             slave_num;
409         u32                             mac_control;
410         struct cpsw_slave_data          *data;
411         struct phy_device               *phy;
412         struct net_device               *ndev;
413         u32                             port_vlan;
414 };
415
416 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
417 {
418         return readl_relaxed(slave->regs + offset);
419 }
420
421 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
422 {
423         writel_relaxed(val, slave->regs + offset);
424 }
425
426 struct cpsw_vector {
427         struct cpdma_chan *ch;
428         int budget;
429 };
430
431 struct cpsw_common {
432         struct device                   *dev;
433         struct cpsw_platform_data       data;
434         struct napi_struct              napi_rx;
435         struct napi_struct              napi_tx;
436         struct cpsw_ss_regs __iomem     *regs;
437         struct cpsw_wr_regs __iomem     *wr_regs;
438         u8 __iomem                      *hw_stats;
439         struct cpsw_host_regs __iomem   *host_port_regs;
440         u32                             version;
441         u32                             coal_intvl;
442         u32                             bus_freq_mhz;
443         int                             rx_packet_max;
444         struct cpsw_slave               *slaves;
445         struct cpdma_ctlr               *dma;
446         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
447         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
448         struct cpsw_ale                 *ale;
449         bool                            quirk_irq;
450         bool                            rx_irq_disabled;
451         bool                            tx_irq_disabled;
452         u32 irqs_table[IRQ_NUM];
453         struct cpts                     *cpts;
454         int                             rx_ch_num, tx_ch_num;
455         int                             speed;
456         int                             usage_count;
457 };
458
459 struct cpsw_priv {
460         struct net_device               *ndev;
461         struct device                   *dev;
462         u32                             msg_enable;
463         u8                              mac_addr[ETH_ALEN];
464         bool                            rx_pause;
465         bool                            tx_pause;
466         bool                            mqprio_hw;
467         int                             fifo_bw[CPSW_TC_NUM];
468         int                             shp_cfg_speed;
469         u32 emac_port;
470         struct cpsw_common *cpsw;
471 };
472
473 struct cpsw_stats {
474         char stat_string[ETH_GSTRING_LEN];
475         int type;
476         int sizeof_stat;
477         int stat_offset;
478 };
479
480 enum {
481         CPSW_STATS,
482         CPDMA_RX_STATS,
483         CPDMA_TX_STATS,
484 };
485
486 #define CPSW_STAT(m)            CPSW_STATS,                             \
487                                 FIELD_SIZEOF(struct cpsw_hw_stats, m), \
488                                 offsetof(struct cpsw_hw_stats, m)
489 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
490                                 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
491                                 offsetof(struct cpdma_chan_stats, m)
492 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
493                                 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
494                                 offsetof(struct cpdma_chan_stats, m)
495
496 static const struct cpsw_stats cpsw_gstrings_stats[] = {
497         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
498         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
499         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
500         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
501         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
502         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
503         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
504         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
505         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
506         { "Rx Fragments", CPSW_STAT(rxfragments) },
507         { "Rx Octets", CPSW_STAT(rxoctets) },
508         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
509         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
510         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
511         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
512         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
513         { "Collisions", CPSW_STAT(txcollisionframes) },
514         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
515         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
516         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
517         { "Late Collisions", CPSW_STAT(txlatecollisions) },
518         { "Tx Underrun", CPSW_STAT(txunderrun) },
519         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
520         { "Tx Octets", CPSW_STAT(txoctets) },
521         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
522         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
523         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
524         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
525         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
526         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
527         { "Net Octets", CPSW_STAT(netoctets) },
528         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
529         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
530         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
531 };
532
533 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
534         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
535         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
536         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
537         { "misqueued", CPDMA_RX_STAT(misqueued) },
538         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
539         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
540         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
541         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
542         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
543         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
544         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
545         { "requeue", CPDMA_RX_STAT(requeue) },
546         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
547 };
548
549 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
550 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
551
552 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
553 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
554 #define for_each_slave(priv, func, arg...)                              \
555         do {                                                            \
556                 struct cpsw_slave *slave;                               \
557                 struct cpsw_common *cpsw = (priv)->cpsw;                \
558                 int n;                                                  \
559                 if (cpsw->data.dual_emac)                               \
560                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
561                 else                                                    \
562                         for (n = cpsw->data.slaves,                     \
563                                         slave = cpsw->slaves;           \
564                                         n; n--)                         \
565                                 (func)(slave++, ##arg);                 \
566         } while (0)
567
568 static inline int cpsw_get_slave_port(u32 slave_num)
569 {
570         return slave_num + 1;
571 }
572
573 static void cpsw_add_mcast(struct cpsw_priv *priv, const u8 *addr)
574 {
575         struct cpsw_common *cpsw = priv->cpsw;
576
577         if (cpsw->data.dual_emac) {
578                 struct cpsw_slave *slave = cpsw->slaves + priv->emac_port;
579
580                 cpsw_ale_add_mcast(cpsw->ale, addr, ALE_PORT_HOST,
581                                    ALE_VLAN, slave->port_vlan, 0);
582                 return;
583         }
584
585         cpsw_ale_add_mcast(cpsw->ale, addr, ALE_ALL_PORTS, 0, 0, 0);
586 }
587
588 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
589 {
590         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
591         struct cpsw_ale *ale = cpsw->ale;
592         int i;
593
594         if (cpsw->data.dual_emac) {
595                 bool flag = false;
596
597                 /* Enabling promiscuous mode for one interface will be
598                  * common for both the interface as the interface shares
599                  * the same hardware resource.
600                  */
601                 for (i = 0; i < cpsw->data.slaves; i++)
602                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
603                                 flag = true;
604
605                 if (!enable && flag) {
606                         enable = true;
607                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
608                 }
609
610                 if (enable) {
611                         /* Enable Bypass */
612                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
613
614                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
615                 } else {
616                         /* Disable Bypass */
617                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
618                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
619                 }
620         } else {
621                 if (enable) {
622                         unsigned long timeout = jiffies + HZ;
623
624                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
625                         for (i = 0; i <= cpsw->data.slaves; i++) {
626                                 cpsw_ale_control_set(ale, i,
627                                                      ALE_PORT_NOLEARN, 1);
628                                 cpsw_ale_control_set(ale, i,
629                                                      ALE_PORT_NO_SA_UPDATE, 1);
630                         }
631
632                         /* Clear All Untouched entries */
633                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
634                         do {
635                                 cpu_relax();
636                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
637                                         break;
638                         } while (time_after(timeout, jiffies));
639                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
640
641                         /* Clear all mcast from ALE */
642                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
643
644                         /* Flood All Unicast Packets to Host port */
645                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
646                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
647                 } else {
648                         /* Don't Flood All Unicast Packets to Host port */
649                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
650
651                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
652                         for (i = 0; i <= cpsw->data.slaves; i++) {
653                                 cpsw_ale_control_set(ale, i,
654                                                      ALE_PORT_NOLEARN, 0);
655                                 cpsw_ale_control_set(ale, i,
656                                                      ALE_PORT_NO_SA_UPDATE, 0);
657                         }
658                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
659                 }
660         }
661 }
662
663 static int cpsw_add_mc_addr(struct net_device *ndev, const u8 *addr)
664 {
665         struct cpsw_priv *priv = netdev_priv(ndev);
666
667         cpsw_add_mcast(priv, addr);
668         return 0;
669 }
670
671 static int cpsw_del_mc_addr(struct net_device *ndev, const u8 *addr)
672 {
673         struct cpsw_priv *priv = netdev_priv(ndev);
674         struct cpsw_common *cpsw = priv->cpsw;
675         int vid, flags;
676
677         if (cpsw->data.dual_emac) {
678                 vid = cpsw->slaves[priv->emac_port].port_vlan;
679                 flags = ALE_VLAN;
680         } else {
681                 vid = 0;
682                 flags = 0;
683         }
684
685         cpsw_ale_del_mcast(cpsw->ale, addr, 0, flags, vid);
686         return 0;
687 }
688
689 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
690 {
691         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
692
693         if (ndev->flags & IFF_PROMISC) {
694                 /* Enable promiscuous mode */
695                 cpsw_set_promiscious(ndev, true);
696                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
697                 return;
698         } else {
699                 /* Disable promiscuous mode */
700                 cpsw_set_promiscious(ndev, false);
701         }
702
703         /* Restore allmulti on vlans if necessary */
704         cpsw_ale_set_allmulti(cpsw->ale, ndev->flags & IFF_ALLMULTI);
705
706         __dev_mc_sync(ndev, cpsw_add_mc_addr, cpsw_del_mc_addr);
707 }
708
709 static void cpsw_intr_enable(struct cpsw_common *cpsw)
710 {
711         writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
712         writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
713
714         cpdma_ctlr_int_ctrl(cpsw->dma, true);
715         return;
716 }
717
718 static void cpsw_intr_disable(struct cpsw_common *cpsw)
719 {
720         writel_relaxed(0, &cpsw->wr_regs->tx_en);
721         writel_relaxed(0, &cpsw->wr_regs->rx_en);
722
723         cpdma_ctlr_int_ctrl(cpsw->dma, false);
724         return;
725 }
726
727 static void cpsw_tx_handler(void *token, int len, int status)
728 {
729         struct netdev_queue     *txq;
730         struct sk_buff          *skb = token;
731         struct net_device       *ndev = skb->dev;
732         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
733
734         /* Check whether the queue is stopped due to stalled tx dma, if the
735          * queue is stopped then start the queue as we have free desc for tx
736          */
737         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
738         if (unlikely(netif_tx_queue_stopped(txq)))
739                 netif_tx_wake_queue(txq);
740
741         cpts_tx_timestamp(cpsw->cpts, skb);
742         ndev->stats.tx_packets++;
743         ndev->stats.tx_bytes += len;
744         dev_kfree_skb_any(skb);
745 }
746
747 static void cpsw_rx_vlan_encap(struct sk_buff *skb)
748 {
749         struct cpsw_priv *priv = netdev_priv(skb->dev);
750         struct cpsw_common *cpsw = priv->cpsw;
751         u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
752         u16 vtag, vid, prio, pkt_type;
753
754         /* Remove VLAN header encapsulation word */
755         skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
756
757         pkt_type = (rx_vlan_encap_hdr >>
758                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
759                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
760         /* Ignore unknown & Priority-tagged packets*/
761         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
762             pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
763                 return;
764
765         vid = (rx_vlan_encap_hdr >>
766                CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
767                VLAN_VID_MASK;
768         /* Ignore vid 0 and pass packet as is */
769         if (!vid)
770                 return;
771         /* Ignore default vlans in dual mac mode */
772         if (cpsw->data.dual_emac &&
773             vid == cpsw->slaves[priv->emac_port].port_vlan)
774                 return;
775
776         prio = (rx_vlan_encap_hdr >>
777                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
778                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
779
780         vtag = (prio << VLAN_PRIO_SHIFT) | vid;
781         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
782
783         /* strip vlan tag for VLAN-tagged packet */
784         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
785                 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
786                 skb_pull(skb, VLAN_HLEN);
787         }
788 }
789
790 static void cpsw_rx_handler(void *token, int len, int status)
791 {
792         struct cpdma_chan       *ch;
793         struct sk_buff          *skb = token;
794         struct sk_buff          *new_skb;
795         struct net_device       *ndev = skb->dev;
796         int                     ret = 0, port;
797         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
798
799         if (cpsw->data.dual_emac) {
800                 port = CPDMA_RX_SOURCE_PORT(status);
801                 if (port) {
802                         ndev = cpsw->slaves[--port].ndev;
803                         skb->dev = ndev;
804                 }
805         }
806
807         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
808                 /* In dual emac mode check for all interfaces */
809                 if (cpsw->data.dual_emac && cpsw->usage_count &&
810                     (status >= 0)) {
811                         /* The packet received is for the interface which
812                          * is already down and the other interface is up
813                          * and running, instead of freeing which results
814                          * in reducing of the number of rx descriptor in
815                          * DMA engine, requeue skb back to cpdma.
816                          */
817                         new_skb = skb;
818                         goto requeue;
819                 }
820
821                 /* the interface is going down, skbs are purged */
822                 dev_kfree_skb_any(skb);
823                 return;
824         }
825
826         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
827         if (new_skb) {
828                 skb_copy_queue_mapping(new_skb, skb);
829                 skb_put(skb, len);
830                 if (status & CPDMA_RX_VLAN_ENCAP)
831                         cpsw_rx_vlan_encap(skb);
832                 cpts_rx_timestamp(cpsw->cpts, skb);
833                 skb->protocol = eth_type_trans(skb, ndev);
834                 netif_receive_skb(skb);
835                 ndev->stats.rx_bytes += len;
836                 ndev->stats.rx_packets++;
837                 kmemleak_not_leak(new_skb);
838         } else {
839                 ndev->stats.rx_dropped++;
840                 new_skb = skb;
841         }
842
843 requeue:
844         if (netif_dormant(ndev)) {
845                 dev_kfree_skb_any(new_skb);
846                 return;
847         }
848
849         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
850         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
851                                 skb_tailroom(new_skb), 0);
852         if (WARN_ON(ret < 0))
853                 dev_kfree_skb_any(new_skb);
854 }
855
856 static void cpsw_split_res(struct net_device *ndev)
857 {
858         struct cpsw_priv *priv = netdev_priv(ndev);
859         u32 consumed_rate = 0, bigest_rate = 0;
860         struct cpsw_common *cpsw = priv->cpsw;
861         struct cpsw_vector *txv = cpsw->txv;
862         int i, ch_weight, rlim_ch_num = 0;
863         int budget, bigest_rate_ch = 0;
864         u32 ch_rate, max_rate;
865         int ch_budget = 0;
866
867         for (i = 0; i < cpsw->tx_ch_num; i++) {
868                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
869                 if (!ch_rate)
870                         continue;
871
872                 rlim_ch_num++;
873                 consumed_rate += ch_rate;
874         }
875
876         if (cpsw->tx_ch_num == rlim_ch_num) {
877                 max_rate = consumed_rate;
878         } else if (!rlim_ch_num) {
879                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
880                 bigest_rate = 0;
881                 max_rate = consumed_rate;
882         } else {
883                 max_rate = cpsw->speed * 1000;
884
885                 /* if max_rate is less then expected due to reduced link speed,
886                  * split proportionally according next potential max speed
887                  */
888                 if (max_rate < consumed_rate)
889                         max_rate *= 10;
890
891                 if (max_rate < consumed_rate)
892                         max_rate *= 10;
893
894                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
895                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
896                             (cpsw->tx_ch_num - rlim_ch_num);
897                 bigest_rate = (max_rate - consumed_rate) /
898                               (cpsw->tx_ch_num - rlim_ch_num);
899         }
900
901         /* split tx weight/budget */
902         budget = CPSW_POLL_WEIGHT;
903         for (i = 0; i < cpsw->tx_ch_num; i++) {
904                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
905                 if (ch_rate) {
906                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
907                         if (!txv[i].budget)
908                                 txv[i].budget++;
909                         if (ch_rate > bigest_rate) {
910                                 bigest_rate_ch = i;
911                                 bigest_rate = ch_rate;
912                         }
913
914                         ch_weight = (ch_rate * 100) / max_rate;
915                         if (!ch_weight)
916                                 ch_weight++;
917                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
918                 } else {
919                         txv[i].budget = ch_budget;
920                         if (!bigest_rate_ch)
921                                 bigest_rate_ch = i;
922                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
923                 }
924
925                 budget -= txv[i].budget;
926         }
927
928         if (budget)
929                 txv[bigest_rate_ch].budget += budget;
930
931         /* split rx budget */
932         budget = CPSW_POLL_WEIGHT;
933         ch_budget = budget / cpsw->rx_ch_num;
934         for (i = 0; i < cpsw->rx_ch_num; i++) {
935                 cpsw->rxv[i].budget = ch_budget;
936                 budget -= ch_budget;
937         }
938
939         if (budget)
940                 cpsw->rxv[0].budget += budget;
941 }
942
943 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
944 {
945         struct cpsw_common *cpsw = dev_id;
946
947         writel(0, &cpsw->wr_regs->tx_en);
948         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
949
950         if (cpsw->quirk_irq) {
951                 disable_irq_nosync(cpsw->irqs_table[1]);
952                 cpsw->tx_irq_disabled = true;
953         }
954
955         napi_schedule(&cpsw->napi_tx);
956         return IRQ_HANDLED;
957 }
958
959 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
960 {
961         struct cpsw_common *cpsw = dev_id;
962
963         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
964         writel(0, &cpsw->wr_regs->rx_en);
965
966         if (cpsw->quirk_irq) {
967                 disable_irq_nosync(cpsw->irqs_table[0]);
968                 cpsw->rx_irq_disabled = true;
969         }
970
971         napi_schedule(&cpsw->napi_rx);
972         return IRQ_HANDLED;
973 }
974
975 static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
976 {
977         u32                     ch_map;
978         int                     num_tx, cur_budget, ch;
979         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
980         struct cpsw_vector      *txv;
981
982         /* process every unprocessed channel */
983         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
984         for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) {
985                 if (!(ch_map & 0x80))
986                         continue;
987
988                 txv = &cpsw->txv[ch];
989                 if (unlikely(txv->budget > budget - num_tx))
990                         cur_budget = budget - num_tx;
991                 else
992                         cur_budget = txv->budget;
993
994                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
995                 if (num_tx >= budget)
996                         break;
997         }
998
999         if (num_tx < budget) {
1000                 napi_complete(napi_tx);
1001                 writel(0xff, &cpsw->wr_regs->tx_en);
1002         }
1003
1004         return num_tx;
1005 }
1006
1007 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
1008 {
1009         struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
1010         int num_tx;
1011
1012         num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
1013         if (num_tx < budget) {
1014                 napi_complete(napi_tx);
1015                 writel(0xff, &cpsw->wr_regs->tx_en);
1016                 if (cpsw->tx_irq_disabled) {
1017                         cpsw->tx_irq_disabled = false;
1018                         enable_irq(cpsw->irqs_table[1]);
1019                 }
1020         }
1021
1022         return num_tx;
1023 }
1024
1025 static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
1026 {
1027         u32                     ch_map;
1028         int                     num_rx, cur_budget, ch;
1029         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
1030         struct cpsw_vector      *rxv;
1031
1032         /* process every unprocessed channel */
1033         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
1034         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
1035                 if (!(ch_map & 0x01))
1036                         continue;
1037
1038                 rxv = &cpsw->rxv[ch];
1039                 if (unlikely(rxv->budget > budget - num_rx))
1040                         cur_budget = budget - num_rx;
1041                 else
1042                         cur_budget = rxv->budget;
1043
1044                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
1045                 if (num_rx >= budget)
1046                         break;
1047         }
1048
1049         if (num_rx < budget) {
1050                 napi_complete_done(napi_rx, num_rx);
1051                 writel(0xff, &cpsw->wr_regs->rx_en);
1052         }
1053
1054         return num_rx;
1055 }
1056
1057 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
1058 {
1059         struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1060         int num_rx;
1061
1062         num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
1063         if (num_rx < budget) {
1064                 napi_complete_done(napi_rx, num_rx);
1065                 writel(0xff, &cpsw->wr_regs->rx_en);
1066                 if (cpsw->rx_irq_disabled) {
1067                         cpsw->rx_irq_disabled = false;
1068                         enable_irq(cpsw->irqs_table[0]);
1069                 }
1070         }
1071
1072         return num_rx;
1073 }
1074
1075 static inline void soft_reset(const char *module, void __iomem *reg)
1076 {
1077         unsigned long timeout = jiffies + HZ;
1078
1079         writel_relaxed(1, reg);
1080         do {
1081                 cpu_relax();
1082         } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
1083
1084         WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
1085 }
1086
1087 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
1088                                struct cpsw_priv *priv)
1089 {
1090         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
1091         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
1092 }
1093
1094 static bool cpsw_shp_is_off(struct cpsw_priv *priv)
1095 {
1096         struct cpsw_common *cpsw = priv->cpsw;
1097         struct cpsw_slave *slave;
1098         u32 shift, mask, val;
1099
1100         val = readl_relaxed(&cpsw->regs->ptype);
1101
1102         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1103         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1104         mask = 7 << shift;
1105         val = val & mask;
1106
1107         return !val;
1108 }
1109
1110 static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on)
1111 {
1112         struct cpsw_common *cpsw = priv->cpsw;
1113         struct cpsw_slave *slave;
1114         u32 shift, mask, val;
1115
1116         val = readl_relaxed(&cpsw->regs->ptype);
1117
1118         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1119         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1120         mask = (1 << --fifo) << shift;
1121         val = on ? val | mask : val & ~mask;
1122
1123         writel_relaxed(val, &cpsw->regs->ptype);
1124 }
1125
1126 static void _cpsw_adjust_link(struct cpsw_slave *slave,
1127                               struct cpsw_priv *priv, bool *link)
1128 {
1129         struct phy_device       *phy = slave->phy;
1130         u32                     mac_control = 0;
1131         u32                     slave_port;
1132         struct cpsw_common *cpsw = priv->cpsw;
1133
1134         if (!phy)
1135                 return;
1136
1137         slave_port = cpsw_get_slave_port(slave->slave_num);
1138
1139         if (phy->link) {
1140                 mac_control = cpsw->data.mac_control;
1141
1142                 /* enable forwarding */
1143                 cpsw_ale_control_set(cpsw->ale, slave_port,
1144                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1145
1146                 if (phy->speed == 1000)
1147                         mac_control |= BIT(7);  /* GIGABITEN    */
1148                 if (phy->duplex)
1149                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
1150
1151                 /* set speed_in input in case RMII mode is used in 100Mbps */
1152                 if (phy->speed == 100)
1153                         mac_control |= BIT(15);
1154                 /* in band mode only works in 10Mbps RGMII mode */
1155                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1156                         mac_control |= BIT(18); /* In Band mode */
1157
1158                 if (priv->rx_pause)
1159                         mac_control |= BIT(3);
1160
1161                 if (priv->tx_pause)
1162                         mac_control |= BIT(4);
1163
1164                 *link = true;
1165
1166                 if (priv->shp_cfg_speed &&
1167                     priv->shp_cfg_speed != slave->phy->speed &&
1168                     !cpsw_shp_is_off(priv))
1169                         dev_warn(priv->dev,
1170                                  "Speed was changed, CBS shaper speeds are changed!");
1171         } else {
1172                 mac_control = 0;
1173                 /* disable forwarding */
1174                 cpsw_ale_control_set(cpsw->ale, slave_port,
1175                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1176         }
1177
1178         if (mac_control != slave->mac_control) {
1179                 phy_print_status(phy);
1180                 writel_relaxed(mac_control, &slave->sliver->mac_control);
1181         }
1182
1183         slave->mac_control = mac_control;
1184 }
1185
1186 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1187 {
1188         int i, speed;
1189
1190         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1191                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1192                         speed += cpsw->slaves[i].phy->speed;
1193
1194         return speed;
1195 }
1196
1197 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1198 {
1199         int i, rlim_ch_num;
1200         int speed, ch_rate;
1201
1202         /* re-split resources only in case speed was changed */
1203         speed = cpsw_get_common_speed(cpsw);
1204         if (speed == cpsw->speed || !speed)
1205                 return 0;
1206
1207         cpsw->speed = speed;
1208
1209         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1210                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1211                 if (!ch_rate)
1212                         break;
1213
1214                 rlim_ch_num++;
1215         }
1216
1217         /* cases not dependent on speed */
1218         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1219                 return 0;
1220
1221         return 1;
1222 }
1223
1224 static void cpsw_adjust_link(struct net_device *ndev)
1225 {
1226         struct cpsw_priv        *priv = netdev_priv(ndev);
1227         struct cpsw_common      *cpsw = priv->cpsw;
1228         bool                    link = false;
1229
1230         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1231
1232         if (link) {
1233                 if (cpsw_need_resplit(cpsw))
1234                         cpsw_split_res(ndev);
1235
1236                 netif_carrier_on(ndev);
1237                 if (netif_running(ndev))
1238                         netif_tx_wake_all_queues(ndev);
1239         } else {
1240                 netif_carrier_off(ndev);
1241                 netif_tx_stop_all_queues(ndev);
1242         }
1243 }
1244
1245 static int cpsw_get_coalesce(struct net_device *ndev,
1246                                 struct ethtool_coalesce *coal)
1247 {
1248         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1249
1250         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1251         return 0;
1252 }
1253
1254 static int cpsw_set_coalesce(struct net_device *ndev,
1255                                 struct ethtool_coalesce *coal)
1256 {
1257         struct cpsw_priv *priv = netdev_priv(ndev);
1258         u32 int_ctrl;
1259         u32 num_interrupts = 0;
1260         u32 prescale = 0;
1261         u32 addnl_dvdr = 1;
1262         u32 coal_intvl = 0;
1263         struct cpsw_common *cpsw = priv->cpsw;
1264
1265         coal_intvl = coal->rx_coalesce_usecs;
1266
1267         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1268         prescale = cpsw->bus_freq_mhz * 4;
1269
1270         if (!coal->rx_coalesce_usecs) {
1271                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1272                 goto update_return;
1273         }
1274
1275         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1276                 coal_intvl = CPSW_CMINTMIN_INTVL;
1277
1278         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1279                 /* Interrupt pacer works with 4us Pulse, we can
1280                  * throttle further by dilating the 4us pulse.
1281                  */
1282                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1283
1284                 if (addnl_dvdr > 1) {
1285                         prescale *= addnl_dvdr;
1286                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1287                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1288                                                 * addnl_dvdr);
1289                 } else {
1290                         addnl_dvdr = 1;
1291                         coal_intvl = CPSW_CMINTMAX_INTVL;
1292                 }
1293         }
1294
1295         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1296         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1297         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1298
1299         int_ctrl |= CPSW_INTPACEEN;
1300         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1301         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1302
1303 update_return:
1304         writel(int_ctrl, &cpsw->wr_regs->int_control);
1305
1306         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1307         cpsw->coal_intvl = coal_intvl;
1308
1309         return 0;
1310 }
1311
1312 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1313 {
1314         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1315
1316         switch (sset) {
1317         case ETH_SS_STATS:
1318                 return (CPSW_STATS_COMMON_LEN +
1319                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1320                        CPSW_STATS_CH_LEN);
1321         default:
1322                 return -EOPNOTSUPP;
1323         }
1324 }
1325
1326 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1327 {
1328         int ch_stats_len;
1329         int line;
1330         int i;
1331
1332         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1333         for (i = 0; i < ch_stats_len; i++) {
1334                 line = i % CPSW_STATS_CH_LEN;
1335                 snprintf(*p, ETH_GSTRING_LEN,
1336                          "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1337                          (long)(i / CPSW_STATS_CH_LEN),
1338                          cpsw_gstrings_ch_stats[line].stat_string);
1339                 *p += ETH_GSTRING_LEN;
1340         }
1341 }
1342
1343 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1344 {
1345         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1346         u8 *p = data;
1347         int i;
1348
1349         switch (stringset) {
1350         case ETH_SS_STATS:
1351                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1352                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1353                                ETH_GSTRING_LEN);
1354                         p += ETH_GSTRING_LEN;
1355                 }
1356
1357                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1358                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1359                 break;
1360         }
1361 }
1362
1363 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1364                                     struct ethtool_stats *stats, u64 *data)
1365 {
1366         u8 *p;
1367         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1368         struct cpdma_chan_stats ch_stats;
1369         int i, l, ch;
1370
1371         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1372         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1373                 data[l] = readl(cpsw->hw_stats +
1374                                 cpsw_gstrings_stats[l].stat_offset);
1375
1376         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1377                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1378                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1379                         p = (u8 *)&ch_stats +
1380                                 cpsw_gstrings_ch_stats[i].stat_offset;
1381                         data[l] = *(u32 *)p;
1382                 }
1383         }
1384
1385         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1386                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1387                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1388                         p = (u8 *)&ch_stats +
1389                                 cpsw_gstrings_ch_stats[i].stat_offset;
1390                         data[l] = *(u32 *)p;
1391                 }
1392         }
1393 }
1394
1395 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1396                                         struct sk_buff *skb,
1397                                         struct cpdma_chan *txch)
1398 {
1399         struct cpsw_common *cpsw = priv->cpsw;
1400
1401         skb_tx_timestamp(skb);
1402         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1403                                  priv->emac_port + cpsw->data.dual_emac);
1404 }
1405
1406 static inline void cpsw_add_dual_emac_def_ale_entries(
1407                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1408                 u32 slave_port)
1409 {
1410         struct cpsw_common *cpsw = priv->cpsw;
1411         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1412
1413         if (cpsw->version == CPSW_VERSION_1)
1414                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1415         else
1416                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1417         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1418                           port_mask, port_mask, 0);
1419         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1420                            ALE_PORT_HOST, ALE_VLAN, slave->port_vlan, 0);
1421         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1422                            HOST_PORT_NUM, ALE_VLAN |
1423                            ALE_SECURE, slave->port_vlan);
1424         cpsw_ale_control_set(cpsw->ale, slave_port,
1425                              ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1426 }
1427
1428 static void soft_reset_slave(struct cpsw_slave *slave)
1429 {
1430         char name[32];
1431
1432         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1433         soft_reset(name, &slave->sliver->soft_reset);
1434 }
1435
1436 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1437 {
1438         u32 slave_port;
1439         struct phy_device *phy;
1440         struct cpsw_common *cpsw = priv->cpsw;
1441
1442         soft_reset_slave(slave);
1443
1444         /* setup priority mapping */
1445         writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1446
1447         switch (cpsw->version) {
1448         case CPSW_VERSION_1:
1449                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1450                 /* Increase RX FIFO size to 5 for supporting fullduplex
1451                  * flow control mode
1452                  */
1453                 slave_write(slave,
1454                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1455                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1456                 break;
1457         case CPSW_VERSION_2:
1458         case CPSW_VERSION_3:
1459         case CPSW_VERSION_4:
1460                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1461                 /* Increase RX FIFO size to 5 for supporting fullduplex
1462                  * flow control mode
1463                  */
1464                 slave_write(slave,
1465                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1466                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1467                 break;
1468         }
1469
1470         /* setup max packet size, and mac address */
1471         writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1472         cpsw_set_slave_mac(slave, priv);
1473
1474         slave->mac_control = 0; /* no link yet */
1475
1476         slave_port = cpsw_get_slave_port(slave->slave_num);
1477
1478         if (cpsw->data.dual_emac)
1479                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1480         else
1481                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1482                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1483
1484         if (slave->data->phy_node) {
1485                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1486                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1487                 if (!phy) {
1488                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1489                                 slave->data->phy_node,
1490                                 slave->slave_num);
1491                         return;
1492                 }
1493         } else {
1494                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1495                                  &cpsw_adjust_link, slave->data->phy_if);
1496                 if (IS_ERR(phy)) {
1497                         dev_err(priv->dev,
1498                                 "phy \"%s\" not found on slave %d, err %ld\n",
1499                                 slave->data->phy_id, slave->slave_num,
1500                                 PTR_ERR(phy));
1501                         return;
1502                 }
1503         }
1504
1505         slave->phy = phy;
1506
1507         phy_attached_info(slave->phy);
1508
1509         phy_start(slave->phy);
1510
1511         /* Configure GMII_SEL register */
1512         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1513 }
1514
1515 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1516 {
1517         struct cpsw_common *cpsw = priv->cpsw;
1518         const int vlan = cpsw->data.default_vlan;
1519         u32 reg;
1520         int i;
1521         int unreg_mcast_mask;
1522
1523         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1524                CPSW2_PORT_VLAN;
1525
1526         writel(vlan, &cpsw->host_port_regs->port_vlan);
1527
1528         for (i = 0; i < cpsw->data.slaves; i++)
1529                 slave_write(cpsw->slaves + i, vlan, reg);
1530
1531         if (priv->ndev->flags & IFF_ALLMULTI)
1532                 unreg_mcast_mask = ALE_ALL_PORTS;
1533         else
1534                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1535
1536         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1537                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1538                           unreg_mcast_mask);
1539 }
1540
1541 static void cpsw_init_host_port(struct cpsw_priv *priv)
1542 {
1543         u32 fifo_mode;
1544         u32 control_reg;
1545         struct cpsw_common *cpsw = priv->cpsw;
1546
1547         /* soft reset the controller and initialize ale */
1548         soft_reset("cpsw", &cpsw->regs->soft_reset);
1549         cpsw_ale_start(cpsw->ale);
1550
1551         /* switch to vlan unaware mode */
1552         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1553                              CPSW_ALE_VLAN_AWARE);
1554         control_reg = readl(&cpsw->regs->control);
1555         control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
1556         writel(control_reg, &cpsw->regs->control);
1557         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1558                      CPSW_FIFO_NORMAL_MODE;
1559         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1560
1561         /* setup host port priority mapping */
1562         writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1563                        &cpsw->host_port_regs->cpdma_tx_pri_map);
1564         writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1565
1566         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1567                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1568
1569         if (!cpsw->data.dual_emac) {
1570                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1571                                    0, 0);
1572                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1573                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1574         }
1575 }
1576
1577 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1578 {
1579         struct cpsw_common *cpsw = priv->cpsw;
1580         struct sk_buff *skb;
1581         int ch_buf_num;
1582         int ch, i, ret;
1583
1584         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1585                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1586                 for (i = 0; i < ch_buf_num; i++) {
1587                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1588                                                           cpsw->rx_packet_max,
1589                                                           GFP_KERNEL);
1590                         if (!skb) {
1591                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1592                                 return -ENOMEM;
1593                         }
1594
1595                         skb_set_queue_mapping(skb, ch);
1596                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1597                                                 skb->data, skb_tailroom(skb),
1598                                                 0);
1599                         if (ret < 0) {
1600                                 cpsw_err(priv, ifup,
1601                                          "cannot submit skb to channel %d rx, error %d\n",
1602                                          ch, ret);
1603                                 kfree_skb(skb);
1604                                 return ret;
1605                         }
1606                         kmemleak_not_leak(skb);
1607                 }
1608
1609                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1610                           ch, ch_buf_num);
1611         }
1612
1613         return 0;
1614 }
1615
1616 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1617 {
1618         u32 slave_port;
1619
1620         slave_port = cpsw_get_slave_port(slave->slave_num);
1621
1622         if (!slave->phy)
1623                 return;
1624         phy_stop(slave->phy);
1625         phy_disconnect(slave->phy);
1626         slave->phy = NULL;
1627         cpsw_ale_control_set(cpsw->ale, slave_port,
1628                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1629         soft_reset_slave(slave);
1630 }
1631
1632 static int cpsw_tc_to_fifo(int tc, int num_tc)
1633 {
1634         if (tc == num_tc - 1)
1635                 return 0;
1636
1637         return CPSW_FIFO_SHAPERS_NUM - tc;
1638 }
1639
1640 static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw)
1641 {
1642         struct cpsw_common *cpsw = priv->cpsw;
1643         u32 val = 0, send_pct, shift;
1644         struct cpsw_slave *slave;
1645         int pct = 0, i;
1646
1647         if (bw > priv->shp_cfg_speed * 1000)
1648                 goto err;
1649
1650         /* shaping has to stay enabled for highest fifos linearly
1651          * and fifo bw no more then interface can allow
1652          */
1653         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1654         send_pct = slave_read(slave, SEND_PERCENT);
1655         for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) {
1656                 if (!bw) {
1657                         if (i >= fifo || !priv->fifo_bw[i])
1658                                 continue;
1659
1660                         dev_warn(priv->dev, "Prev FIFO%d is shaped", i);
1661                         continue;
1662                 }
1663
1664                 if (!priv->fifo_bw[i] && i > fifo) {
1665                         dev_err(priv->dev, "Upper FIFO%d is not shaped", i);
1666                         return -EINVAL;
1667                 }
1668
1669                 shift = (i - 1) * 8;
1670                 if (i == fifo) {
1671                         send_pct &= ~(CPSW_PCT_MASK << shift);
1672                         val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10);
1673                         if (!val)
1674                                 val = 1;
1675
1676                         send_pct |= val << shift;
1677                         pct += val;
1678                         continue;
1679                 }
1680
1681                 if (priv->fifo_bw[i])
1682                         pct += (send_pct >> shift) & CPSW_PCT_MASK;
1683         }
1684
1685         if (pct >= 100)
1686                 goto err;
1687
1688         slave_write(slave, send_pct, SEND_PERCENT);
1689         priv->fifo_bw[fifo] = bw;
1690
1691         dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo,
1692                  DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100));
1693
1694         return 0;
1695 err:
1696         dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration");
1697         return -EINVAL;
1698 }
1699
1700 static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw)
1701 {
1702         struct cpsw_common *cpsw = priv->cpsw;
1703         struct cpsw_slave *slave;
1704         u32 tx_in_ctl_rg, val;
1705         int ret;
1706
1707         ret = cpsw_set_fifo_bw(priv, fifo, bw);
1708         if (ret)
1709                 return ret;
1710
1711         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1712         tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
1713                        CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL;
1714
1715         if (!bw)
1716                 cpsw_fifo_shp_on(priv, fifo, bw);
1717
1718         val = slave_read(slave, tx_in_ctl_rg);
1719         if (cpsw_shp_is_off(priv)) {
1720                 /* disable FIFOs rate limited queues */
1721                 val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT);
1722
1723                 /* set type of FIFO queues to normal priority mode */
1724                 val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT);
1725
1726                 /* set type of FIFO queues to be rate limited */
1727                 if (bw)
1728                         val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT;
1729                 else
1730                         priv->shp_cfg_speed = 0;
1731         }
1732
1733         /* toggle a FIFO rate limited queue */
1734         if (bw)
1735                 val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1736         else
1737                 val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1738         slave_write(slave, val, tx_in_ctl_rg);
1739
1740         /* FIFO transmit shape enable */
1741         cpsw_fifo_shp_on(priv, fifo, bw);
1742         return 0;
1743 }
1744
1745 /* Defaults:
1746  * class A - prio 3
1747  * class B - prio 2
1748  * shaping for class A should be set first
1749  */
1750 static int cpsw_set_cbs(struct net_device *ndev,
1751                         struct tc_cbs_qopt_offload *qopt)
1752 {
1753         struct cpsw_priv *priv = netdev_priv(ndev);
1754         struct cpsw_common *cpsw = priv->cpsw;
1755         struct cpsw_slave *slave;
1756         int prev_speed = 0;
1757         int tc, ret, fifo;
1758         u32 bw = 0;
1759
1760         tc = netdev_txq_to_tc(priv->ndev, qopt->queue);
1761
1762         /* enable channels in backward order, as highest FIFOs must be rate
1763          * limited first and for compliance with CPDMA rate limited channels
1764          * that also used in bacward order. FIFO0 cannot be rate limited.
1765          */
1766         fifo = cpsw_tc_to_fifo(tc, ndev->num_tc);
1767         if (!fifo) {
1768                 dev_err(priv->dev, "Last tc%d can't be rate limited", tc);
1769                 return -EINVAL;
1770         }
1771
1772         /* do nothing, it's disabled anyway */
1773         if (!qopt->enable && !priv->fifo_bw[fifo])
1774                 return 0;
1775
1776         /* shapers can be set if link speed is known */
1777         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1778         if (slave->phy && slave->phy->link) {
1779                 if (priv->shp_cfg_speed &&
1780                     priv->shp_cfg_speed != slave->phy->speed)
1781                         prev_speed = priv->shp_cfg_speed;
1782
1783                 priv->shp_cfg_speed = slave->phy->speed;
1784         }
1785
1786         if (!priv->shp_cfg_speed) {
1787                 dev_err(priv->dev, "Link speed is not known");
1788                 return -1;
1789         }
1790
1791         ret = pm_runtime_get_sync(cpsw->dev);
1792         if (ret < 0) {
1793                 pm_runtime_put_noidle(cpsw->dev);
1794                 return ret;
1795         }
1796
1797         bw = qopt->enable ? qopt->idleslope : 0;
1798         ret = cpsw_set_fifo_rlimit(priv, fifo, bw);
1799         if (ret) {
1800                 priv->shp_cfg_speed = prev_speed;
1801                 prev_speed = 0;
1802         }
1803
1804         if (bw && prev_speed)
1805                 dev_warn(priv->dev,
1806                          "Speed was changed, CBS shaper speeds are changed!");
1807
1808         pm_runtime_put_sync(cpsw->dev);
1809         return ret;
1810 }
1811
1812 static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1813 {
1814         int fifo, bw;
1815
1816         for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) {
1817                 bw = priv->fifo_bw[fifo];
1818                 if (!bw)
1819                         continue;
1820
1821                 cpsw_set_fifo_rlimit(priv, fifo, bw);
1822         }
1823 }
1824
1825 static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1826 {
1827         struct cpsw_common *cpsw = priv->cpsw;
1828         u32 tx_prio_map = 0;
1829         int i, tc, fifo;
1830         u32 tx_prio_rg;
1831
1832         if (!priv->mqprio_hw)
1833                 return;
1834
1835         for (i = 0; i < 8; i++) {
1836                 tc = netdev_get_prio_tc_map(priv->ndev, i);
1837                 fifo = CPSW_FIFO_SHAPERS_NUM - tc;
1838                 tx_prio_map |= fifo << (4 * i);
1839         }
1840
1841         tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
1842                      CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
1843
1844         slave_write(slave, tx_prio_map, tx_prio_rg);
1845 }
1846
1847 /* restore resources after port reset */
1848 static void cpsw_restore(struct cpsw_priv *priv)
1849 {
1850         /* restore MQPRIO offload */
1851         for_each_slave(priv, cpsw_mqprio_resume, priv);
1852
1853         /* restore CBS offload */
1854         for_each_slave(priv, cpsw_cbs_resume, priv);
1855 }
1856
1857 static int cpsw_ndo_open(struct net_device *ndev)
1858 {
1859         struct cpsw_priv *priv = netdev_priv(ndev);
1860         struct cpsw_common *cpsw = priv->cpsw;
1861         int ret;
1862         u32 reg;
1863
1864         ret = pm_runtime_get_sync(cpsw->dev);
1865         if (ret < 0) {
1866                 pm_runtime_put_noidle(cpsw->dev);
1867                 return ret;
1868         }
1869
1870         netif_carrier_off(ndev);
1871
1872         /* Notify the stack of the actual queue counts. */
1873         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1874         if (ret) {
1875                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1876                 goto err_cleanup;
1877         }
1878
1879         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1880         if (ret) {
1881                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1882                 goto err_cleanup;
1883         }
1884
1885         reg = cpsw->version;
1886
1887         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1888                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1889                  CPSW_RTL_VERSION(reg));
1890
1891         /* Initialize host and slave ports */
1892         if (!cpsw->usage_count)
1893                 cpsw_init_host_port(priv);
1894         for_each_slave(priv, cpsw_slave_open, priv);
1895
1896         /* Add default VLAN */
1897         if (!cpsw->data.dual_emac)
1898                 cpsw_add_default_vlan(priv);
1899         else
1900                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1901                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1902
1903         /* initialize shared resources for every ndev */
1904         if (!cpsw->usage_count) {
1905                 /* disable priority elevation */
1906                 writel_relaxed(0, &cpsw->regs->ptype);
1907
1908                 /* enable statistics collection only on all ports */
1909                 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1910
1911                 /* Enable internal fifo flow control */
1912                 writel(0x7, &cpsw->regs->flow_control);
1913
1914                 napi_enable(&cpsw->napi_rx);
1915                 napi_enable(&cpsw->napi_tx);
1916
1917                 if (cpsw->tx_irq_disabled) {
1918                         cpsw->tx_irq_disabled = false;
1919                         enable_irq(cpsw->irqs_table[1]);
1920                 }
1921
1922                 if (cpsw->rx_irq_disabled) {
1923                         cpsw->rx_irq_disabled = false;
1924                         enable_irq(cpsw->irqs_table[0]);
1925                 }
1926
1927                 ret = cpsw_fill_rx_channels(priv);
1928                 if (ret < 0)
1929                         goto err_cleanup;
1930
1931                 if (cpts_register(cpsw->cpts))
1932                         dev_err(priv->dev, "error registering cpts device\n");
1933
1934         }
1935
1936         cpsw_restore(priv);
1937
1938         /* Enable Interrupt pacing if configured */
1939         if (cpsw->coal_intvl != 0) {
1940                 struct ethtool_coalesce coal;
1941
1942                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1943                 cpsw_set_coalesce(ndev, &coal);
1944         }
1945
1946         cpdma_ctlr_start(cpsw->dma);
1947         cpsw_intr_enable(cpsw);
1948         cpsw->usage_count++;
1949
1950         return 0;
1951
1952 err_cleanup:
1953         cpdma_ctlr_stop(cpsw->dma);
1954         for_each_slave(priv, cpsw_slave_stop, cpsw);
1955         pm_runtime_put_sync(cpsw->dev);
1956         netif_carrier_off(priv->ndev);
1957         return ret;
1958 }
1959
1960 static int cpsw_ndo_stop(struct net_device *ndev)
1961 {
1962         struct cpsw_priv *priv = netdev_priv(ndev);
1963         struct cpsw_common *cpsw = priv->cpsw;
1964
1965         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1966         __dev_mc_unsync(priv->ndev, cpsw_del_mc_addr);
1967         netif_tx_stop_all_queues(priv->ndev);
1968         netif_carrier_off(priv->ndev);
1969
1970         if (cpsw->usage_count <= 1) {
1971                 napi_disable(&cpsw->napi_rx);
1972                 napi_disable(&cpsw->napi_tx);
1973                 cpts_unregister(cpsw->cpts);
1974                 cpsw_intr_disable(cpsw);
1975                 cpdma_ctlr_stop(cpsw->dma);
1976                 cpsw_ale_stop(cpsw->ale);
1977         }
1978         for_each_slave(priv, cpsw_slave_stop, cpsw);
1979
1980         if (cpsw_need_resplit(cpsw))
1981                 cpsw_split_res(ndev);
1982
1983         cpsw->usage_count--;
1984         pm_runtime_put_sync(cpsw->dev);
1985         return 0;
1986 }
1987
1988 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1989                                        struct net_device *ndev)
1990 {
1991         struct cpsw_priv *priv = netdev_priv(ndev);
1992         struct cpsw_common *cpsw = priv->cpsw;
1993         struct cpts *cpts = cpsw->cpts;
1994         struct netdev_queue *txq;
1995         struct cpdma_chan *txch;
1996         int ret, q_idx;
1997
1998         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1999                 cpsw_err(priv, tx_err, "packet pad failed\n");
2000                 ndev->stats.tx_dropped++;
2001                 return NET_XMIT_DROP;
2002         }
2003
2004         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2005             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
2006                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2007
2008         q_idx = skb_get_queue_mapping(skb);
2009         if (q_idx >= cpsw->tx_ch_num)
2010                 q_idx = q_idx % cpsw->tx_ch_num;
2011
2012         txch = cpsw->txv[q_idx].ch;
2013         txq = netdev_get_tx_queue(ndev, q_idx);
2014         ret = cpsw_tx_packet_submit(priv, skb, txch);
2015         if (unlikely(ret != 0)) {
2016                 cpsw_err(priv, tx_err, "desc submit failed\n");
2017                 goto fail;
2018         }
2019
2020         /* If there is no more tx desc left free then we need to
2021          * tell the kernel to stop sending us tx frames.
2022          */
2023         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
2024                 netif_tx_stop_queue(txq);
2025
2026                 /* Barrier, so that stop_queue visible to other cpus */
2027                 smp_mb__after_atomic();
2028
2029                 if (cpdma_check_free_tx_desc(txch))
2030                         netif_tx_wake_queue(txq);
2031         }
2032
2033         return NETDEV_TX_OK;
2034 fail:
2035         ndev->stats.tx_dropped++;
2036         netif_tx_stop_queue(txq);
2037
2038         /* Barrier, so that stop_queue visible to other cpus */
2039         smp_mb__after_atomic();
2040
2041         if (cpdma_check_free_tx_desc(txch))
2042                 netif_tx_wake_queue(txq);
2043
2044         return NETDEV_TX_BUSY;
2045 }
2046
2047 #if IS_ENABLED(CONFIG_TI_CPTS)
2048
2049 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
2050 {
2051         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2052         u32 ts_en, seq_id;
2053
2054         if (!cpts_is_tx_enabled(cpsw->cpts) &&
2055             !cpts_is_rx_enabled(cpsw->cpts)) {
2056                 slave_write(slave, 0, CPSW1_TS_CTL);
2057                 return;
2058         }
2059
2060         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2061         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
2062
2063         if (cpts_is_tx_enabled(cpsw->cpts))
2064                 ts_en |= CPSW_V1_TS_TX_EN;
2065
2066         if (cpts_is_rx_enabled(cpsw->cpts))
2067                 ts_en |= CPSW_V1_TS_RX_EN;
2068
2069         slave_write(slave, ts_en, CPSW1_TS_CTL);
2070         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
2071 }
2072
2073 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
2074 {
2075         struct cpsw_slave *slave;
2076         struct cpsw_common *cpsw = priv->cpsw;
2077         u32 ctrl, mtype;
2078
2079         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2080
2081         ctrl = slave_read(slave, CPSW2_CONTROL);
2082         switch (cpsw->version) {
2083         case CPSW_VERSION_2:
2084                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2085
2086                 if (cpts_is_tx_enabled(cpsw->cpts))
2087                         ctrl |= CTRL_V2_TX_TS_BITS;
2088
2089                 if (cpts_is_rx_enabled(cpsw->cpts))
2090                         ctrl |= CTRL_V2_RX_TS_BITS;
2091                 break;
2092         case CPSW_VERSION_3:
2093         default:
2094                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
2095
2096                 if (cpts_is_tx_enabled(cpsw->cpts))
2097                         ctrl |= CTRL_V3_TX_TS_BITS;
2098
2099                 if (cpts_is_rx_enabled(cpsw->cpts))
2100                         ctrl |= CTRL_V3_RX_TS_BITS;
2101                 break;
2102         }
2103
2104         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
2105
2106         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
2107         slave_write(slave, ctrl, CPSW2_CONTROL);
2108         writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
2109 }
2110
2111 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2112 {
2113         struct cpsw_priv *priv = netdev_priv(dev);
2114         struct hwtstamp_config cfg;
2115         struct cpsw_common *cpsw = priv->cpsw;
2116         struct cpts *cpts = cpsw->cpts;
2117
2118         if (cpsw->version != CPSW_VERSION_1 &&
2119             cpsw->version != CPSW_VERSION_2 &&
2120             cpsw->version != CPSW_VERSION_3)
2121                 return -EOPNOTSUPP;
2122
2123         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2124                 return -EFAULT;
2125
2126         /* reserved for future extensions */
2127         if (cfg.flags)
2128                 return -EINVAL;
2129
2130         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2131                 return -ERANGE;
2132
2133         switch (cfg.rx_filter) {
2134         case HWTSTAMP_FILTER_NONE:
2135                 cpts_rx_enable(cpts, 0);
2136                 break;
2137         case HWTSTAMP_FILTER_ALL:
2138         case HWTSTAMP_FILTER_NTP_ALL:
2139                 return -ERANGE;
2140         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2141         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2142         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2143                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
2144                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2145                 break;
2146         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2147         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2148         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2149         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2150         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2151         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2152         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2153         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2154         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2155                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
2156                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2157                 break;
2158         default:
2159                 return -ERANGE;
2160         }
2161
2162         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
2163
2164         switch (cpsw->version) {
2165         case CPSW_VERSION_1:
2166                 cpsw_hwtstamp_v1(cpsw);
2167                 break;
2168         case CPSW_VERSION_2:
2169         case CPSW_VERSION_3:
2170                 cpsw_hwtstamp_v2(priv);
2171                 break;
2172         default:
2173                 WARN_ON(1);
2174         }
2175
2176         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2177 }
2178
2179 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2180 {
2181         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
2182         struct cpts *cpts = cpsw->cpts;
2183         struct hwtstamp_config cfg;
2184
2185         if (cpsw->version != CPSW_VERSION_1 &&
2186             cpsw->version != CPSW_VERSION_2 &&
2187             cpsw->version != CPSW_VERSION_3)
2188                 return -EOPNOTSUPP;
2189
2190         cfg.flags = 0;
2191         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
2192                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2193         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
2194                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
2195
2196         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2197 }
2198 #else
2199 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2200 {
2201         return -EOPNOTSUPP;
2202 }
2203
2204 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2205 {
2206         return -EOPNOTSUPP;
2207 }
2208 #endif /*CONFIG_TI_CPTS*/
2209
2210 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2211 {
2212         struct cpsw_priv *priv = netdev_priv(dev);
2213         struct cpsw_common *cpsw = priv->cpsw;
2214         int slave_no = cpsw_slave_index(cpsw, priv);
2215
2216         if (!netif_running(dev))
2217                 return -EINVAL;
2218
2219         switch (cmd) {
2220         case SIOCSHWTSTAMP:
2221                 return cpsw_hwtstamp_set(dev, req);
2222         case SIOCGHWTSTAMP:
2223                 return cpsw_hwtstamp_get(dev, req);
2224         }
2225
2226         if (!cpsw->slaves[slave_no].phy)
2227                 return -EOPNOTSUPP;
2228         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2229 }
2230
2231 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
2232 {
2233         struct cpsw_priv *priv = netdev_priv(ndev);
2234         struct cpsw_common *cpsw = priv->cpsw;
2235         int ch;
2236
2237         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
2238         ndev->stats.tx_errors++;
2239         cpsw_intr_disable(cpsw);
2240         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
2241                 cpdma_chan_stop(cpsw->txv[ch].ch);
2242                 cpdma_chan_start(cpsw->txv[ch].ch);
2243         }
2244
2245         cpsw_intr_enable(cpsw);
2246         netif_trans_update(ndev);
2247         netif_tx_wake_all_queues(ndev);
2248 }
2249
2250 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
2251 {
2252         struct cpsw_priv *priv = netdev_priv(ndev);
2253         struct sockaddr *addr = (struct sockaddr *)p;
2254         struct cpsw_common *cpsw = priv->cpsw;
2255         int flags = 0;
2256         u16 vid = 0;
2257         int ret;
2258
2259         if (!is_valid_ether_addr(addr->sa_data))
2260                 return -EADDRNOTAVAIL;
2261
2262         ret = pm_runtime_get_sync(cpsw->dev);
2263         if (ret < 0) {
2264                 pm_runtime_put_noidle(cpsw->dev);
2265                 return ret;
2266         }
2267
2268         if (cpsw->data.dual_emac) {
2269                 vid = cpsw->slaves[priv->emac_port].port_vlan;
2270                 flags = ALE_VLAN;
2271         }
2272
2273         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
2274                            flags, vid);
2275         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
2276                            flags, vid);
2277
2278         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
2279         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2280         for_each_slave(priv, cpsw_set_slave_mac, priv);
2281
2282         pm_runtime_put(cpsw->dev);
2283
2284         return 0;
2285 }
2286
2287 #ifdef CONFIG_NET_POLL_CONTROLLER
2288 static void cpsw_ndo_poll_controller(struct net_device *ndev)
2289 {
2290         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2291
2292         cpsw_intr_disable(cpsw);
2293         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2294         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2295         cpsw_intr_enable(cpsw);
2296 }
2297 #endif
2298
2299 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2300                                 unsigned short vid)
2301 {
2302         int ret;
2303         int unreg_mcast_mask = 0;
2304         int mcast_mask;
2305         u32 port_mask;
2306         struct cpsw_common *cpsw = priv->cpsw;
2307
2308         if (cpsw->data.dual_emac) {
2309                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
2310
2311                 mcast_mask = ALE_PORT_HOST;
2312                 if (priv->ndev->flags & IFF_ALLMULTI)
2313                         unreg_mcast_mask = mcast_mask;
2314         } else {
2315                 port_mask = ALE_ALL_PORTS;
2316                 mcast_mask = port_mask;
2317
2318                 if (priv->ndev->flags & IFF_ALLMULTI)
2319                         unreg_mcast_mask = ALE_ALL_PORTS;
2320                 else
2321                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
2322         }
2323
2324         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
2325                                 unreg_mcast_mask);
2326         if (ret != 0)
2327                 return ret;
2328
2329         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
2330                                  HOST_PORT_NUM, ALE_VLAN, vid);
2331         if (ret != 0)
2332                 goto clean_vid;
2333
2334         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
2335                                  mcast_mask, ALE_VLAN, vid, 0);
2336         if (ret != 0)
2337                 goto clean_vlan_ucast;
2338         return 0;
2339
2340 clean_vlan_ucast:
2341         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2342                            HOST_PORT_NUM, ALE_VLAN, vid);
2343 clean_vid:
2344         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2345         return ret;
2346 }
2347
2348 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
2349                                     __be16 proto, u16 vid)
2350 {
2351         struct cpsw_priv *priv = netdev_priv(ndev);
2352         struct cpsw_common *cpsw = priv->cpsw;
2353         int ret;
2354
2355         if (vid == cpsw->data.default_vlan)
2356                 return 0;
2357
2358         ret = pm_runtime_get_sync(cpsw->dev);
2359         if (ret < 0) {
2360                 pm_runtime_put_noidle(cpsw->dev);
2361                 return ret;
2362         }
2363
2364         if (cpsw->data.dual_emac) {
2365                 /* In dual EMAC, reserved VLAN id should not be used for
2366                  * creating VLAN interfaces as this can break the dual
2367                  * EMAC port separation
2368                  */
2369                 int i;
2370
2371                 for (i = 0; i < cpsw->data.slaves; i++) {
2372                         if (vid == cpsw->slaves[i].port_vlan) {
2373                                 ret = -EINVAL;
2374                                 goto err;
2375                         }
2376                 }
2377         }
2378
2379         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2380         ret = cpsw_add_vlan_ale_entry(priv, vid);
2381 err:
2382         pm_runtime_put(cpsw->dev);
2383         return ret;
2384 }
2385
2386 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2387                                      __be16 proto, u16 vid)
2388 {
2389         struct cpsw_priv *priv = netdev_priv(ndev);
2390         struct cpsw_common *cpsw = priv->cpsw;
2391         int ret;
2392
2393         if (vid == cpsw->data.default_vlan)
2394                 return 0;
2395
2396         ret = pm_runtime_get_sync(cpsw->dev);
2397         if (ret < 0) {
2398                 pm_runtime_put_noidle(cpsw->dev);
2399                 return ret;
2400         }
2401
2402         if (cpsw->data.dual_emac) {
2403                 int i;
2404
2405                 for (i = 0; i < cpsw->data.slaves; i++) {
2406                         if (vid == cpsw->slaves[i].port_vlan)
2407                                 goto err;
2408                 }
2409         }
2410
2411         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2412         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2413         ret |= cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2414                                   HOST_PORT_NUM, ALE_VLAN, vid);
2415         ret |= cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2416                                   0, ALE_VLAN, vid);
2417 err:
2418         pm_runtime_put(cpsw->dev);
2419         return ret;
2420 }
2421
2422 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2423 {
2424         struct cpsw_priv *priv = netdev_priv(ndev);
2425         struct cpsw_common *cpsw = priv->cpsw;
2426         struct cpsw_slave *slave;
2427         u32 min_rate;
2428         u32 ch_rate;
2429         int i, ret;
2430
2431         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2432         if (ch_rate == rate)
2433                 return 0;
2434
2435         ch_rate = rate * 1000;
2436         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2437         if ((ch_rate < min_rate && ch_rate)) {
2438                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2439                         min_rate);
2440                 return -EINVAL;
2441         }
2442
2443         if (rate > cpsw->speed) {
2444                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2445                 return -EINVAL;
2446         }
2447
2448         ret = pm_runtime_get_sync(cpsw->dev);
2449         if (ret < 0) {
2450                 pm_runtime_put_noidle(cpsw->dev);
2451                 return ret;
2452         }
2453
2454         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2455         pm_runtime_put(cpsw->dev);
2456
2457         if (ret)
2458                 return ret;
2459
2460         /* update rates for slaves tx queues */
2461         for (i = 0; i < cpsw->data.slaves; i++) {
2462                 slave = &cpsw->slaves[i];
2463                 if (!slave->ndev)
2464                         continue;
2465
2466                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2467         }
2468
2469         cpsw_split_res(ndev);
2470         return ret;
2471 }
2472
2473 static int cpsw_set_mqprio(struct net_device *ndev, void *type_data)
2474 {
2475         struct tc_mqprio_qopt_offload *mqprio = type_data;
2476         struct cpsw_priv *priv = netdev_priv(ndev);
2477         struct cpsw_common *cpsw = priv->cpsw;
2478         int fifo, num_tc, count, offset;
2479         struct cpsw_slave *slave;
2480         u32 tx_prio_map = 0;
2481         int i, tc, ret;
2482
2483         num_tc = mqprio->qopt.num_tc;
2484         if (num_tc > CPSW_TC_NUM)
2485                 return -EINVAL;
2486
2487         if (mqprio->mode != TC_MQPRIO_MODE_DCB)
2488                 return -EINVAL;
2489
2490         ret = pm_runtime_get_sync(cpsw->dev);
2491         if (ret < 0) {
2492                 pm_runtime_put_noidle(cpsw->dev);
2493                 return ret;
2494         }
2495
2496         if (num_tc) {
2497                 for (i = 0; i < 8; i++) {
2498                         tc = mqprio->qopt.prio_tc_map[i];
2499                         fifo = cpsw_tc_to_fifo(tc, num_tc);
2500                         tx_prio_map |= fifo << (4 * i);
2501                 }
2502
2503                 netdev_set_num_tc(ndev, num_tc);
2504                 for (i = 0; i < num_tc; i++) {
2505                         count = mqprio->qopt.count[i];
2506                         offset = mqprio->qopt.offset[i];
2507                         netdev_set_tc_queue(ndev, i, count, offset);
2508                 }
2509         }
2510
2511         if (!mqprio->qopt.hw) {
2512                 /* restore default configuration */
2513                 netdev_reset_tc(ndev);
2514                 tx_prio_map = TX_PRIORITY_MAPPING;
2515         }
2516
2517         priv->mqprio_hw = mqprio->qopt.hw;
2518
2519         offset = cpsw->version == CPSW_VERSION_1 ?
2520                  CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
2521
2522         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2523         slave_write(slave, tx_prio_map, offset);
2524
2525         pm_runtime_put_sync(cpsw->dev);
2526
2527         return 0;
2528 }
2529
2530 static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
2531                              void *type_data)
2532 {
2533         switch (type) {
2534         case TC_SETUP_QDISC_CBS:
2535                 return cpsw_set_cbs(ndev, type_data);
2536
2537         case TC_SETUP_QDISC_MQPRIO:
2538                 return cpsw_set_mqprio(ndev, type_data);
2539
2540         default:
2541                 return -EOPNOTSUPP;
2542         }
2543 }
2544
2545 static const struct net_device_ops cpsw_netdev_ops = {
2546         .ndo_open               = cpsw_ndo_open,
2547         .ndo_stop               = cpsw_ndo_stop,
2548         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2549         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2550         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2551         .ndo_validate_addr      = eth_validate_addr,
2552         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2553         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2554         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2555 #ifdef CONFIG_NET_POLL_CONTROLLER
2556         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2557 #endif
2558         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2559         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2560         .ndo_setup_tc           = cpsw_ndo_setup_tc,
2561 };
2562
2563 static int cpsw_get_regs_len(struct net_device *ndev)
2564 {
2565         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2566
2567         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2568 }
2569
2570 static void cpsw_get_regs(struct net_device *ndev,
2571                           struct ethtool_regs *regs, void *p)
2572 {
2573         u32 *reg = p;
2574         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2575
2576         /* update CPSW IP version */
2577         regs->version = cpsw->version;
2578
2579         cpsw_ale_dump(cpsw->ale, reg);
2580 }
2581
2582 static void cpsw_get_drvinfo(struct net_device *ndev,
2583                              struct ethtool_drvinfo *info)
2584 {
2585         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2586         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2587
2588         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2589         strlcpy(info->version, "1.0", sizeof(info->version));
2590         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2591 }
2592
2593 static u32 cpsw_get_msglevel(struct net_device *ndev)
2594 {
2595         struct cpsw_priv *priv = netdev_priv(ndev);
2596         return priv->msg_enable;
2597 }
2598
2599 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2600 {
2601         struct cpsw_priv *priv = netdev_priv(ndev);
2602         priv->msg_enable = value;
2603 }
2604
2605 #if IS_ENABLED(CONFIG_TI_CPTS)
2606 static int cpsw_get_ts_info(struct net_device *ndev,
2607                             struct ethtool_ts_info *info)
2608 {
2609         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2610
2611         info->so_timestamping =
2612                 SOF_TIMESTAMPING_TX_HARDWARE |
2613                 SOF_TIMESTAMPING_TX_SOFTWARE |
2614                 SOF_TIMESTAMPING_RX_HARDWARE |
2615                 SOF_TIMESTAMPING_RX_SOFTWARE |
2616                 SOF_TIMESTAMPING_SOFTWARE |
2617                 SOF_TIMESTAMPING_RAW_HARDWARE;
2618         info->phc_index = cpsw->cpts->phc_index;
2619         info->tx_types =
2620                 (1 << HWTSTAMP_TX_OFF) |
2621                 (1 << HWTSTAMP_TX_ON);
2622         info->rx_filters =
2623                 (1 << HWTSTAMP_FILTER_NONE) |
2624                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2625                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2626         return 0;
2627 }
2628 #else
2629 static int cpsw_get_ts_info(struct net_device *ndev,
2630                             struct ethtool_ts_info *info)
2631 {
2632         info->so_timestamping =
2633                 SOF_TIMESTAMPING_TX_SOFTWARE |
2634                 SOF_TIMESTAMPING_RX_SOFTWARE |
2635                 SOF_TIMESTAMPING_SOFTWARE;
2636         info->phc_index = -1;
2637         info->tx_types = 0;
2638         info->rx_filters = 0;
2639         return 0;
2640 }
2641 #endif
2642
2643 static int cpsw_get_link_ksettings(struct net_device *ndev,
2644                                    struct ethtool_link_ksettings *ecmd)
2645 {
2646         struct cpsw_priv *priv = netdev_priv(ndev);
2647         struct cpsw_common *cpsw = priv->cpsw;
2648         int slave_no = cpsw_slave_index(cpsw, priv);
2649
2650         if (!cpsw->slaves[slave_no].phy)
2651                 return -EOPNOTSUPP;
2652
2653         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2654         return 0;
2655 }
2656
2657 static int cpsw_set_link_ksettings(struct net_device *ndev,
2658                                    const struct ethtool_link_ksettings *ecmd)
2659 {
2660         struct cpsw_priv *priv = netdev_priv(ndev);
2661         struct cpsw_common *cpsw = priv->cpsw;
2662         int slave_no = cpsw_slave_index(cpsw, priv);
2663
2664         if (cpsw->slaves[slave_no].phy)
2665                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2666                                                  ecmd);
2667         else
2668                 return -EOPNOTSUPP;
2669 }
2670
2671 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2672 {
2673         struct cpsw_priv *priv = netdev_priv(ndev);
2674         struct cpsw_common *cpsw = priv->cpsw;
2675         int slave_no = cpsw_slave_index(cpsw, priv);
2676
2677         wol->supported = 0;
2678         wol->wolopts = 0;
2679
2680         if (cpsw->slaves[slave_no].phy)
2681                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2682 }
2683
2684 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2685 {
2686         struct cpsw_priv *priv = netdev_priv(ndev);
2687         struct cpsw_common *cpsw = priv->cpsw;
2688         int slave_no = cpsw_slave_index(cpsw, priv);
2689
2690         if (cpsw->slaves[slave_no].phy)
2691                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2692         else
2693                 return -EOPNOTSUPP;
2694 }
2695
2696 static void cpsw_get_pauseparam(struct net_device *ndev,
2697                                 struct ethtool_pauseparam *pause)
2698 {
2699         struct cpsw_priv *priv = netdev_priv(ndev);
2700
2701         pause->autoneg = AUTONEG_DISABLE;
2702         pause->rx_pause = priv->rx_pause ? true : false;
2703         pause->tx_pause = priv->tx_pause ? true : false;
2704 }
2705
2706 static int cpsw_set_pauseparam(struct net_device *ndev,
2707                                struct ethtool_pauseparam *pause)
2708 {
2709         struct cpsw_priv *priv = netdev_priv(ndev);
2710         bool link;
2711
2712         priv->rx_pause = pause->rx_pause ? true : false;
2713         priv->tx_pause = pause->tx_pause ? true : false;
2714
2715         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2716         return 0;
2717 }
2718
2719 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2720 {
2721         struct cpsw_priv *priv = netdev_priv(ndev);
2722         struct cpsw_common *cpsw = priv->cpsw;
2723         int ret;
2724
2725         ret = pm_runtime_get_sync(cpsw->dev);
2726         if (ret < 0) {
2727                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2728                 pm_runtime_put_noidle(cpsw->dev);
2729         }
2730
2731         return ret;
2732 }
2733
2734 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2735 {
2736         struct cpsw_priv *priv = netdev_priv(ndev);
2737         int ret;
2738
2739         ret = pm_runtime_put(priv->cpsw->dev);
2740         if (ret < 0)
2741                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2742 }
2743
2744 static void cpsw_get_channels(struct net_device *ndev,
2745                               struct ethtool_channels *ch)
2746 {
2747         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2748
2749         ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2750         ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2751         ch->max_combined = 0;
2752         ch->max_other = 0;
2753         ch->other_count = 0;
2754         ch->rx_count = cpsw->rx_ch_num;
2755         ch->tx_count = cpsw->tx_ch_num;
2756         ch->combined_count = 0;
2757 }
2758
2759 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2760                                   struct ethtool_channels *ch)
2761 {
2762         if (cpsw->quirk_irq) {
2763                 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2764                 return -EOPNOTSUPP;
2765         }
2766
2767         if (ch->combined_count)
2768                 return -EINVAL;
2769
2770         /* verify we have at least one channel in each direction */
2771         if (!ch->rx_count || !ch->tx_count)
2772                 return -EINVAL;
2773
2774         if (ch->rx_count > cpsw->data.channels ||
2775             ch->tx_count > cpsw->data.channels)
2776                 return -EINVAL;
2777
2778         return 0;
2779 }
2780
2781 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2782 {
2783         struct cpsw_common *cpsw = priv->cpsw;
2784         void (*handler)(void *, int, int);
2785         struct netdev_queue *queue;
2786         struct cpsw_vector *vec;
2787         int ret, *ch, vch;
2788
2789         if (rx) {
2790                 ch = &cpsw->rx_ch_num;
2791                 vec = cpsw->rxv;
2792                 handler = cpsw_rx_handler;
2793         } else {
2794                 ch = &cpsw->tx_ch_num;
2795                 vec = cpsw->txv;
2796                 handler = cpsw_tx_handler;
2797         }
2798
2799         while (*ch < ch_num) {
2800                 vch = rx ? *ch : 7 - *ch;
2801                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
2802                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2803                 queue->tx_maxrate = 0;
2804
2805                 if (IS_ERR(vec[*ch].ch))
2806                         return PTR_ERR(vec[*ch].ch);
2807
2808                 if (!vec[*ch].ch)
2809                         return -EINVAL;
2810
2811                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2812                           (rx ? "rx" : "tx"));
2813                 (*ch)++;
2814         }
2815
2816         while (*ch > ch_num) {
2817                 (*ch)--;
2818
2819                 ret = cpdma_chan_destroy(vec[*ch].ch);
2820                 if (ret)
2821                         return ret;
2822
2823                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2824                           (rx ? "rx" : "tx"));
2825         }
2826
2827         return 0;
2828 }
2829
2830 static int cpsw_update_channels(struct cpsw_priv *priv,
2831                                 struct ethtool_channels *ch)
2832 {
2833         int ret;
2834
2835         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2836         if (ret)
2837                 return ret;
2838
2839         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2840         if (ret)
2841                 return ret;
2842
2843         return 0;
2844 }
2845
2846 static void cpsw_suspend_data_pass(struct net_device *ndev)
2847 {
2848         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2849         struct cpsw_slave *slave;
2850         int i;
2851
2852         /* Disable NAPI scheduling */
2853         cpsw_intr_disable(cpsw);
2854
2855         /* Stop all transmit queues for every network device.
2856          * Disable re-using rx descriptors with dormant_on.
2857          */
2858         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2859                 if (!(slave->ndev && netif_running(slave->ndev)))
2860                         continue;
2861
2862                 netif_tx_stop_all_queues(slave->ndev);
2863                 netif_dormant_on(slave->ndev);
2864         }
2865
2866         /* Handle rest of tx packets and stop cpdma channels */
2867         cpdma_ctlr_stop(cpsw->dma);
2868 }
2869
2870 static int cpsw_resume_data_pass(struct net_device *ndev)
2871 {
2872         struct cpsw_priv *priv = netdev_priv(ndev);
2873         struct cpsw_common *cpsw = priv->cpsw;
2874         struct cpsw_slave *slave;
2875         int i, ret;
2876
2877         /* Allow rx packets handling */
2878         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2879                 if (slave->ndev && netif_running(slave->ndev))
2880                         netif_dormant_off(slave->ndev);
2881
2882         /* After this receive is started */
2883         if (cpsw->usage_count) {
2884                 ret = cpsw_fill_rx_channels(priv);
2885                 if (ret)
2886                         return ret;
2887
2888                 cpdma_ctlr_start(cpsw->dma);
2889                 cpsw_intr_enable(cpsw);
2890         }
2891
2892         /* Resume transmit for every affected interface */
2893         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2894                 if (slave->ndev && netif_running(slave->ndev))
2895                         netif_tx_start_all_queues(slave->ndev);
2896
2897         return 0;
2898 }
2899
2900 static int cpsw_set_channels(struct net_device *ndev,
2901                              struct ethtool_channels *chs)
2902 {
2903         struct cpsw_priv *priv = netdev_priv(ndev);
2904         struct cpsw_common *cpsw = priv->cpsw;
2905         struct cpsw_slave *slave;
2906         int i, ret;
2907
2908         ret = cpsw_check_ch_settings(cpsw, chs);
2909         if (ret < 0)
2910                 return ret;
2911
2912         cpsw_suspend_data_pass(ndev);
2913         ret = cpsw_update_channels(priv, chs);
2914         if (ret)
2915                 goto err;
2916
2917         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2918                 if (!(slave->ndev && netif_running(slave->ndev)))
2919                         continue;
2920
2921                 /* Inform stack about new count of queues */
2922                 ret = netif_set_real_num_tx_queues(slave->ndev,
2923                                                    cpsw->tx_ch_num);
2924                 if (ret) {
2925                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2926                         goto err;
2927                 }
2928
2929                 ret = netif_set_real_num_rx_queues(slave->ndev,
2930                                                    cpsw->rx_ch_num);
2931                 if (ret) {
2932                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2933                         goto err;
2934                 }
2935         }
2936
2937         if (cpsw->usage_count)
2938                 cpsw_split_res(ndev);
2939
2940         ret = cpsw_resume_data_pass(ndev);
2941         if (!ret)
2942                 return 0;
2943 err:
2944         dev_err(priv->dev, "cannot update channels number, closing device\n");
2945         dev_close(ndev);
2946         return ret;
2947 }
2948
2949 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2950 {
2951         struct cpsw_priv *priv = netdev_priv(ndev);
2952         struct cpsw_common *cpsw = priv->cpsw;
2953         int slave_no = cpsw_slave_index(cpsw, priv);
2954
2955         if (cpsw->slaves[slave_no].phy)
2956                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2957         else
2958                 return -EOPNOTSUPP;
2959 }
2960
2961 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2962 {
2963         struct cpsw_priv *priv = netdev_priv(ndev);
2964         struct cpsw_common *cpsw = priv->cpsw;
2965         int slave_no = cpsw_slave_index(cpsw, priv);
2966
2967         if (cpsw->slaves[slave_no].phy)
2968                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2969         else
2970                 return -EOPNOTSUPP;
2971 }
2972
2973 static int cpsw_nway_reset(struct net_device *ndev)
2974 {
2975         struct cpsw_priv *priv = netdev_priv(ndev);
2976         struct cpsw_common *cpsw = priv->cpsw;
2977         int slave_no = cpsw_slave_index(cpsw, priv);
2978
2979         if (cpsw->slaves[slave_no].phy)
2980                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2981         else
2982                 return -EOPNOTSUPP;
2983 }
2984
2985 static void cpsw_get_ringparam(struct net_device *ndev,
2986                                struct ethtool_ringparam *ering)
2987 {
2988         struct cpsw_priv *priv = netdev_priv(ndev);
2989         struct cpsw_common *cpsw = priv->cpsw;
2990
2991         /* not supported */
2992         ering->tx_max_pending = 0;
2993         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2994         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2995         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2996 }
2997
2998 static int cpsw_set_ringparam(struct net_device *ndev,
2999                               struct ethtool_ringparam *ering)
3000 {
3001         struct cpsw_priv *priv = netdev_priv(ndev);
3002         struct cpsw_common *cpsw = priv->cpsw;
3003         int ret;
3004
3005         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
3006
3007         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
3008             ering->rx_pending < CPSW_MAX_QUEUES ||
3009             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
3010                 return -EINVAL;
3011
3012         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
3013                 return 0;
3014
3015         cpsw_suspend_data_pass(ndev);
3016
3017         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
3018
3019         if (cpsw->usage_count)
3020                 cpdma_chan_split_pool(cpsw->dma);
3021
3022         ret = cpsw_resume_data_pass(ndev);
3023         if (!ret)
3024                 return 0;
3025
3026         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
3027         dev_close(ndev);
3028         return ret;
3029 }
3030
3031 static const struct ethtool_ops cpsw_ethtool_ops = {
3032         .get_drvinfo    = cpsw_get_drvinfo,
3033         .get_msglevel   = cpsw_get_msglevel,
3034         .set_msglevel   = cpsw_set_msglevel,
3035         .get_link       = ethtool_op_get_link,
3036         .get_ts_info    = cpsw_get_ts_info,
3037         .get_coalesce   = cpsw_get_coalesce,
3038         .set_coalesce   = cpsw_set_coalesce,
3039         .get_sset_count         = cpsw_get_sset_count,
3040         .get_strings            = cpsw_get_strings,
3041         .get_ethtool_stats      = cpsw_get_ethtool_stats,
3042         .get_pauseparam         = cpsw_get_pauseparam,
3043         .set_pauseparam         = cpsw_set_pauseparam,
3044         .get_wol        = cpsw_get_wol,
3045         .set_wol        = cpsw_set_wol,
3046         .get_regs_len   = cpsw_get_regs_len,
3047         .get_regs       = cpsw_get_regs,
3048         .begin          = cpsw_ethtool_op_begin,
3049         .complete       = cpsw_ethtool_op_complete,
3050         .get_channels   = cpsw_get_channels,
3051         .set_channels   = cpsw_set_channels,
3052         .get_link_ksettings     = cpsw_get_link_ksettings,
3053         .set_link_ksettings     = cpsw_set_link_ksettings,
3054         .get_eee        = cpsw_get_eee,
3055         .set_eee        = cpsw_set_eee,
3056         .nway_reset     = cpsw_nway_reset,
3057         .get_ringparam = cpsw_get_ringparam,
3058         .set_ringparam = cpsw_set_ringparam,
3059 };
3060
3061 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
3062                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
3063 {
3064         void __iomem            *regs = cpsw->regs;
3065         int                     slave_num = slave->slave_num;
3066         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
3067
3068         slave->data     = data;
3069         slave->regs     = regs + slave_reg_ofs;
3070         slave->sliver   = regs + sliver_reg_ofs;
3071         slave->port_vlan = data->dual_emac_res_vlan;
3072 }
3073
3074 static int cpsw_probe_dt(struct cpsw_platform_data *data,
3075                          struct platform_device *pdev)
3076 {
3077         struct device_node *node = pdev->dev.of_node;
3078         struct device_node *slave_node;
3079         int i = 0, ret;
3080         u32 prop;
3081
3082         if (!node)
3083                 return -EINVAL;
3084
3085         if (of_property_read_u32(node, "slaves", &prop)) {
3086                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
3087                 return -EINVAL;
3088         }
3089         data->slaves = prop;
3090
3091         if (of_property_read_u32(node, "active_slave", &prop)) {
3092                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
3093                 return -EINVAL;
3094         }
3095         data->active_slave = prop;
3096
3097         data->slave_data = devm_kcalloc(&pdev->dev,
3098                                         data->slaves,
3099                                         sizeof(struct cpsw_slave_data),
3100                                         GFP_KERNEL);
3101         if (!data->slave_data)
3102                 return -ENOMEM;
3103
3104         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
3105                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
3106                 return -EINVAL;
3107         }
3108         data->channels = prop;
3109
3110         if (of_property_read_u32(node, "ale_entries", &prop)) {
3111                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
3112                 return -EINVAL;
3113         }
3114         data->ale_entries = prop;
3115
3116         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
3117                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
3118                 return -EINVAL;
3119         }
3120         data->bd_ram_size = prop;
3121
3122         if (of_property_read_u32(node, "mac_control", &prop)) {
3123                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
3124                 return -EINVAL;
3125         }
3126         data->mac_control = prop;
3127
3128         if (of_property_read_bool(node, "dual_emac"))
3129                 data->dual_emac = 1;
3130
3131         /*
3132          * Populate all the child nodes here...
3133          */
3134         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
3135         /* We do not want to force this, as in some cases may not have child */
3136         if (ret)
3137                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
3138
3139         for_each_available_child_of_node(node, slave_node) {
3140                 struct cpsw_slave_data *slave_data = data->slave_data + i;
3141                 const void *mac_addr = NULL;
3142                 int lenp;
3143                 const __be32 *parp;
3144
3145                 /* This is no slave child node, continue */
3146                 if (strcmp(slave_node->name, "slave"))
3147                         continue;
3148
3149                 slave_data->phy_node = of_parse_phandle(slave_node,
3150                                                         "phy-handle", 0);
3151                 parp = of_get_property(slave_node, "phy_id", &lenp);
3152                 if (slave_data->phy_node) {
3153                         dev_dbg(&pdev->dev,
3154                                 "slave[%d] using phy-handle=\"%pOF\"\n",
3155                                 i, slave_data->phy_node);
3156                 } else if (of_phy_is_fixed_link(slave_node)) {
3157                         /* In the case of a fixed PHY, the DT node associated
3158                          * to the PHY is the Ethernet MAC DT node.
3159                          */
3160                         ret = of_phy_register_fixed_link(slave_node);
3161                         if (ret) {
3162                                 if (ret != -EPROBE_DEFER)
3163                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
3164                                 return ret;
3165                         }
3166                         slave_data->phy_node = of_node_get(slave_node);
3167                 } else if (parp) {
3168                         u32 phyid;
3169                         struct device_node *mdio_node;
3170                         struct platform_device *mdio;
3171
3172                         if (lenp != (sizeof(__be32) * 2)) {
3173                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
3174                                 goto no_phy_slave;
3175                         }
3176                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
3177                         phyid = be32_to_cpup(parp+1);
3178                         mdio = of_find_device_by_node(mdio_node);
3179                         of_node_put(mdio_node);
3180                         if (!mdio) {
3181                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
3182                                 return -EINVAL;
3183                         }
3184                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
3185                                  PHY_ID_FMT, mdio->name, phyid);
3186                         put_device(&mdio->dev);
3187                 } else {
3188                         dev_err(&pdev->dev,
3189                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
3190                                 i);
3191                         goto no_phy_slave;
3192                 }
3193                 slave_data->phy_if = of_get_phy_mode(slave_node);
3194                 if (slave_data->phy_if < 0) {
3195                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
3196                                 i);
3197                         return slave_data->phy_if;
3198                 }
3199
3200 no_phy_slave:
3201                 mac_addr = of_get_mac_address(slave_node);
3202                 if (mac_addr) {
3203                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
3204                 } else {
3205                         ret = ti_cm_get_macid(&pdev->dev, i,
3206                                               slave_data->mac_addr);
3207                         if (ret)
3208                                 return ret;
3209                 }
3210                 if (data->dual_emac) {
3211                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
3212                                                  &prop)) {
3213                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
3214                                 slave_data->dual_emac_res_vlan = i+1;
3215                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
3216                                         slave_data->dual_emac_res_vlan, i);
3217                         } else {
3218                                 slave_data->dual_emac_res_vlan = prop;
3219                         }
3220                 }
3221
3222                 i++;
3223                 if (i == data->slaves)
3224                         break;
3225         }
3226
3227         return 0;
3228 }
3229
3230 static void cpsw_remove_dt(struct platform_device *pdev)
3231 {
3232         struct net_device *ndev = platform_get_drvdata(pdev);
3233         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3234         struct cpsw_platform_data *data = &cpsw->data;
3235         struct device_node *node = pdev->dev.of_node;
3236         struct device_node *slave_node;
3237         int i = 0;
3238
3239         for_each_available_child_of_node(node, slave_node) {
3240                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
3241
3242                 if (strcmp(slave_node->name, "slave"))
3243                         continue;
3244
3245                 if (of_phy_is_fixed_link(slave_node))
3246                         of_phy_deregister_fixed_link(slave_node);
3247
3248                 of_node_put(slave_data->phy_node);
3249
3250                 i++;
3251                 if (i == data->slaves)
3252                         break;
3253         }
3254
3255         of_platform_depopulate(&pdev->dev);
3256 }
3257
3258 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
3259 {
3260         struct cpsw_common              *cpsw = priv->cpsw;
3261         struct cpsw_platform_data       *data = &cpsw->data;
3262         struct net_device               *ndev;
3263         struct cpsw_priv                *priv_sl2;
3264         int ret = 0;
3265
3266         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
3267         if (!ndev) {
3268                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
3269                 return -ENOMEM;
3270         }
3271
3272         priv_sl2 = netdev_priv(ndev);
3273         priv_sl2->cpsw = cpsw;
3274         priv_sl2->ndev = ndev;
3275         priv_sl2->dev  = &ndev->dev;
3276         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3277
3278         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
3279                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
3280                         ETH_ALEN);
3281                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
3282                          priv_sl2->mac_addr);
3283         } else {
3284                 eth_random_addr(priv_sl2->mac_addr);
3285                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
3286                          priv_sl2->mac_addr);
3287         }
3288         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
3289
3290         priv_sl2->emac_port = 1;
3291         cpsw->slaves[1].ndev = ndev;
3292         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3293
3294         ndev->netdev_ops = &cpsw_netdev_ops;
3295         ndev->ethtool_ops = &cpsw_ethtool_ops;
3296
3297         /* register the network device */
3298         SET_NETDEV_DEV(ndev, cpsw->dev);
3299         ret = register_netdev(ndev);
3300         if (ret) {
3301                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
3302                 free_netdev(ndev);
3303                 ret = -ENODEV;
3304         }
3305
3306         return ret;
3307 }
3308
3309 static const struct of_device_id cpsw_of_mtable[] = {
3310         { .compatible = "ti,cpsw"},
3311         { .compatible = "ti,am335x-cpsw"},
3312         { .compatible = "ti,am4372-cpsw"},
3313         { .compatible = "ti,dra7-cpsw"},
3314         { /* sentinel */ },
3315 };
3316 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
3317
3318 static const struct soc_device_attribute cpsw_soc_devices[] = {
3319         { .family = "AM33xx", .revision = "ES1.0"},
3320         { /* sentinel */ }
3321 };
3322
3323 static int cpsw_probe(struct platform_device *pdev)
3324 {
3325         struct clk                      *clk;
3326         struct cpsw_platform_data       *data;
3327         struct net_device               *ndev;
3328         struct cpsw_priv                *priv;
3329         struct cpdma_params             dma_params;
3330         struct cpsw_ale_params          ale_params;
3331         void __iomem                    *ss_regs;
3332         void __iomem                    *cpts_regs;
3333         struct resource                 *res, *ss_res;
3334         struct gpio_descs               *mode;
3335         u32 slave_offset, sliver_offset, slave_size;
3336         const struct soc_device_attribute *soc;
3337         struct cpsw_common              *cpsw;
3338         int ret = 0, i, ch;
3339         int irq;
3340
3341         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
3342         if (!cpsw)
3343                 return -ENOMEM;
3344
3345         cpsw->dev = &pdev->dev;
3346
3347         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
3348         if (!ndev) {
3349                 dev_err(&pdev->dev, "error allocating net_device\n");
3350                 return -ENOMEM;
3351         }
3352
3353         platform_set_drvdata(pdev, ndev);
3354         priv = netdev_priv(ndev);
3355         priv->cpsw = cpsw;
3356         priv->ndev = ndev;
3357         priv->dev  = &ndev->dev;
3358         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3359         cpsw->rx_packet_max = max(rx_packet_max, 128);
3360
3361         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
3362         if (IS_ERR(mode)) {
3363                 ret = PTR_ERR(mode);
3364                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
3365                 goto clean_ndev_ret;
3366         }
3367
3368         /*
3369          * This may be required here for child devices.
3370          */
3371         pm_runtime_enable(&pdev->dev);
3372
3373         /* Select default pin state */
3374         pinctrl_pm_select_default_state(&pdev->dev);
3375
3376         /* Need to enable clocks with runtime PM api to access module
3377          * registers
3378          */
3379         ret = pm_runtime_get_sync(&pdev->dev);
3380         if (ret < 0) {
3381                 pm_runtime_put_noidle(&pdev->dev);
3382                 goto clean_runtime_disable_ret;
3383         }
3384
3385         ret = cpsw_probe_dt(&cpsw->data, pdev);
3386         if (ret)
3387                 goto clean_dt_ret;
3388
3389         data = &cpsw->data;
3390         cpsw->rx_ch_num = 1;
3391         cpsw->tx_ch_num = 1;
3392
3393         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
3394                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
3395                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
3396         } else {
3397                 eth_random_addr(priv->mac_addr);
3398                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
3399         }
3400
3401         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
3402
3403         cpsw->slaves = devm_kcalloc(&pdev->dev,
3404                                     data->slaves, sizeof(struct cpsw_slave),
3405                                     GFP_KERNEL);
3406         if (!cpsw->slaves) {
3407                 ret = -ENOMEM;
3408                 goto clean_dt_ret;
3409         }
3410         for (i = 0; i < data->slaves; i++)
3411                 cpsw->slaves[i].slave_num = i;
3412
3413         cpsw->slaves[0].ndev = ndev;
3414         priv->emac_port = 0;
3415
3416         clk = devm_clk_get(&pdev->dev, "fck");
3417         if (IS_ERR(clk)) {
3418                 dev_err(priv->dev, "fck is not found\n");
3419                 ret = -ENODEV;
3420                 goto clean_dt_ret;
3421         }
3422         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
3423
3424         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3425         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
3426         if (IS_ERR(ss_regs)) {
3427                 ret = PTR_ERR(ss_regs);
3428                 goto clean_dt_ret;
3429         }
3430         cpsw->regs = ss_regs;
3431
3432         cpsw->version = readl(&cpsw->regs->id_ver);
3433
3434         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3435         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
3436         if (IS_ERR(cpsw->wr_regs)) {
3437                 ret = PTR_ERR(cpsw->wr_regs);
3438                 goto clean_dt_ret;
3439         }
3440
3441         memset(&dma_params, 0, sizeof(dma_params));
3442         memset(&ale_params, 0, sizeof(ale_params));
3443
3444         switch (cpsw->version) {
3445         case CPSW_VERSION_1:
3446                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3447                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
3448                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
3449                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
3450                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
3451                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
3452                 slave_offset         = CPSW1_SLAVE_OFFSET;
3453                 slave_size           = CPSW1_SLAVE_SIZE;
3454                 sliver_offset        = CPSW1_SLIVER_OFFSET;
3455                 dma_params.desc_mem_phys = 0;
3456                 break;
3457         case CPSW_VERSION_2:
3458         case CPSW_VERSION_3:
3459         case CPSW_VERSION_4:
3460                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3461                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3462                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3463                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3464                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3465                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3466                 slave_offset         = CPSW2_SLAVE_OFFSET;
3467                 slave_size           = CPSW2_SLAVE_SIZE;
3468                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3469                 dma_params.desc_mem_phys =
3470                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3471                 break;
3472         default:
3473                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3474                 ret = -ENODEV;
3475                 goto clean_dt_ret;
3476         }
3477         for (i = 0; i < cpsw->data.slaves; i++) {
3478                 struct cpsw_slave *slave = &cpsw->slaves[i];
3479
3480                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3481                 slave_offset  += slave_size;
3482                 sliver_offset += SLIVER_SIZE;
3483         }
3484
3485         dma_params.dev          = &pdev->dev;
3486         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3487         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3488         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3489         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3490         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3491
3492         dma_params.num_chan             = data->channels;
3493         dma_params.has_soft_reset       = true;
3494         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3495         dma_params.desc_mem_size        = data->bd_ram_size;
3496         dma_params.desc_align           = 16;
3497         dma_params.has_ext_regs         = true;
3498         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3499         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3500         dma_params.descs_pool_size      = descs_pool_size;
3501
3502         cpsw->dma = cpdma_ctlr_create(&dma_params);
3503         if (!cpsw->dma) {
3504                 dev_err(priv->dev, "error initializing dma\n");
3505                 ret = -ENOMEM;
3506                 goto clean_dt_ret;
3507         }
3508
3509         soc = soc_device_match(cpsw_soc_devices);
3510         if (soc)
3511                 cpsw->quirk_irq = 1;
3512
3513         ch = cpsw->quirk_irq ? 0 : 7;
3514         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0);
3515         if (IS_ERR(cpsw->txv[0].ch)) {
3516                 dev_err(priv->dev, "error initializing tx dma channel\n");
3517                 ret = PTR_ERR(cpsw->txv[0].ch);
3518                 goto clean_dma_ret;
3519         }
3520
3521         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3522         if (IS_ERR(cpsw->rxv[0].ch)) {
3523                 dev_err(priv->dev, "error initializing rx dma channel\n");
3524                 ret = PTR_ERR(cpsw->rxv[0].ch);
3525                 goto clean_dma_ret;
3526         }
3527
3528         ale_params.dev                  = &pdev->dev;
3529         ale_params.ale_ageout           = ale_ageout;
3530         ale_params.ale_entries          = data->ale_entries;
3531         ale_params.ale_ports            = CPSW_ALE_PORTS_NUM;
3532
3533         cpsw->ale = cpsw_ale_create(&ale_params);
3534         if (!cpsw->ale) {
3535                 dev_err(priv->dev, "error initializing ale engine\n");
3536                 ret = -ENODEV;
3537                 goto clean_dma_ret;
3538         }
3539
3540         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3541         if (IS_ERR(cpsw->cpts)) {
3542                 ret = PTR_ERR(cpsw->cpts);
3543                 goto clean_dma_ret;
3544         }
3545
3546         ndev->irq = platform_get_irq(pdev, 1);
3547         if (ndev->irq < 0) {
3548                 dev_err(priv->dev, "error getting irq resource\n");
3549                 ret = ndev->irq;
3550                 goto clean_dma_ret;
3551         }
3552
3553         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3554
3555         ndev->netdev_ops = &cpsw_netdev_ops;
3556         ndev->ethtool_ops = &cpsw_ethtool_ops;
3557         netif_napi_add(ndev, &cpsw->napi_rx,
3558                        cpsw->quirk_irq ? cpsw_rx_poll : cpsw_rx_mq_poll,
3559                        CPSW_POLL_WEIGHT);
3560         netif_tx_napi_add(ndev, &cpsw->napi_tx,
3561                           cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll,
3562                           CPSW_POLL_WEIGHT);
3563         cpsw_split_res(ndev);
3564
3565         /* register the network device */
3566         SET_NETDEV_DEV(ndev, &pdev->dev);
3567         ret = register_netdev(ndev);
3568         if (ret) {
3569                 dev_err(priv->dev, "error registering net device\n");
3570                 ret = -ENODEV;
3571                 goto clean_dma_ret;
3572         }
3573
3574         if (cpsw->data.dual_emac) {
3575                 ret = cpsw_probe_dual_emac(priv);
3576                 if (ret) {
3577                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3578                         goto clean_unregister_netdev_ret;
3579                 }
3580         }
3581
3582         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3583          * MISC IRQs which are always kept disabled with this driver so
3584          * we will not request them.
3585          *
3586          * If anyone wants to implement support for those, make sure to
3587          * first request and append them to irqs_table array.
3588          */
3589
3590         /* RX IRQ */
3591         irq = platform_get_irq(pdev, 1);
3592         if (irq < 0) {
3593                 ret = irq;
3594                 goto clean_dma_ret;
3595         }
3596
3597         cpsw->irqs_table[0] = irq;
3598         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3599                                0, dev_name(&pdev->dev), cpsw);
3600         if (ret < 0) {
3601                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3602                 goto clean_dma_ret;
3603         }
3604
3605         /* TX IRQ */
3606         irq = platform_get_irq(pdev, 2);
3607         if (irq < 0) {
3608                 ret = irq;
3609                 goto clean_dma_ret;
3610         }
3611
3612         cpsw->irqs_table[1] = irq;
3613         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3614                                0, dev_name(&pdev->dev), cpsw);
3615         if (ret < 0) {
3616                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3617                 goto clean_dma_ret;
3618         }
3619
3620         cpsw_notice(priv, probe,
3621                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3622                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3623
3624         pm_runtime_put(&pdev->dev);
3625
3626         return 0;
3627
3628 clean_unregister_netdev_ret:
3629         unregister_netdev(ndev);
3630 clean_dma_ret:
3631         cpdma_ctlr_destroy(cpsw->dma);
3632 clean_dt_ret:
3633         cpsw_remove_dt(pdev);
3634         pm_runtime_put_sync(&pdev->dev);
3635 clean_runtime_disable_ret:
3636         pm_runtime_disable(&pdev->dev);
3637 clean_ndev_ret:
3638         free_netdev(priv->ndev);
3639         return ret;
3640 }
3641
3642 static int cpsw_remove(struct platform_device *pdev)
3643 {
3644         struct net_device *ndev = platform_get_drvdata(pdev);
3645         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3646         int ret;
3647
3648         ret = pm_runtime_get_sync(&pdev->dev);
3649         if (ret < 0) {
3650                 pm_runtime_put_noidle(&pdev->dev);
3651                 return ret;
3652         }
3653
3654         if (cpsw->data.dual_emac)
3655                 unregister_netdev(cpsw->slaves[1].ndev);
3656         unregister_netdev(ndev);
3657
3658         cpts_release(cpsw->cpts);
3659         cpdma_ctlr_destroy(cpsw->dma);
3660         cpsw_remove_dt(pdev);
3661         pm_runtime_put_sync(&pdev->dev);
3662         pm_runtime_disable(&pdev->dev);
3663         if (cpsw->data.dual_emac)
3664                 free_netdev(cpsw->slaves[1].ndev);
3665         free_netdev(ndev);
3666         return 0;
3667 }
3668
3669 #ifdef CONFIG_PM_SLEEP
3670 static int cpsw_suspend(struct device *dev)
3671 {
3672         struct net_device       *ndev = dev_get_drvdata(dev);
3673         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3674
3675         if (cpsw->data.dual_emac) {
3676                 int i;
3677
3678                 for (i = 0; i < cpsw->data.slaves; i++) {
3679                         if (netif_running(cpsw->slaves[i].ndev))
3680                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3681                 }
3682         } else {
3683                 if (netif_running(ndev))
3684                         cpsw_ndo_stop(ndev);
3685         }
3686
3687         /* Select sleep pin state */
3688         pinctrl_pm_select_sleep_state(dev);
3689
3690         return 0;
3691 }
3692
3693 static int cpsw_resume(struct device *dev)
3694 {
3695         struct net_device       *ndev = dev_get_drvdata(dev);
3696         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3697
3698         /* Select default pin state */
3699         pinctrl_pm_select_default_state(dev);
3700
3701         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3702         rtnl_lock();
3703         if (cpsw->data.dual_emac) {
3704                 int i;
3705
3706                 for (i = 0; i < cpsw->data.slaves; i++) {
3707                         if (netif_running(cpsw->slaves[i].ndev))
3708                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3709                 }
3710         } else {
3711                 if (netif_running(ndev))
3712                         cpsw_ndo_open(ndev);
3713         }
3714         rtnl_unlock();
3715
3716         return 0;
3717 }
3718 #endif
3719
3720 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3721
3722 static struct platform_driver cpsw_driver = {
3723         .driver = {
3724                 .name    = "cpsw",
3725                 .pm      = &cpsw_pm_ops,
3726                 .of_match_table = cpsw_of_mtable,
3727         },
3728         .probe = cpsw_probe,
3729         .remove = cpsw_remove,
3730 };
3731
3732 module_platform_driver(cpsw_driver);
3733
3734 MODULE_LICENSE("GPL");
3735 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3736 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3737 MODULE_DESCRIPTION("TI CPSW Ethernet driver");