treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 206
[muen/linux.git] / drivers / net / ethernet / xscale / ixp4xx_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Intel IXP4xx Ethernet driver for Linux
4  *
5  * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
6  *
7  * Ethernet port config (0x00 is not present on IXP42X):
8  *
9  * logical port         0x00            0x10            0x20
10  * NPE                  0 (NPE-A)       1 (NPE-B)       2 (NPE-C)
11  * physical PortId      2               0               1
12  * TX queue             23              24              25
13  * RX-free queue        26              27              28
14  * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
15  *
16  * Queue entries:
17  * bits 0 -> 1  - NPE ID (RX and TX-done)
18  * bits 0 -> 2  - priority (TX, per 802.1D)
19  * bits 3 -> 4  - port ID (user-set?)
20  * bits 5 -> 31 - physical descriptor address
21  */
22
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmapool.h>
26 #include <linux/etherdevice.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/net_tstamp.h>
30 #include <linux/of.h>
31 #include <linux/phy.h>
32 #include <linux/platform_device.h>
33 #include <linux/ptp_classify.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <mach/ixp46x_ts.h>
37 #include <linux/soc/ixp4xx/npe.h>
38 #include <linux/soc/ixp4xx/qmgr.h>
39
40 #define DEBUG_DESC              0
41 #define DEBUG_RX                0
42 #define DEBUG_TX                0
43 #define DEBUG_PKT_BYTES         0
44 #define DEBUG_MDIO              0
45 #define DEBUG_CLOSE             0
46
47 #define DRV_NAME                "ixp4xx_eth"
48
49 #define MAX_NPES                3
50
51 #define RX_DESCS                64 /* also length of all RX queues */
52 #define TX_DESCS                16 /* also length of all TX queues */
53 #define TXDONE_QUEUE_LEN        64 /* dwords */
54
55 #define POOL_ALLOC_SIZE         (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
56 #define REGS_SIZE               0x1000
57 #define MAX_MRU                 1536 /* 0x600 */
58 #define RX_BUFF_SIZE            ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
59
60 #define NAPI_WEIGHT             16
61 #define MDIO_INTERVAL           (3 * HZ)
62 #define MAX_MDIO_RETRIES        100 /* microseconds, typically 30 cycles */
63 #define MAX_CLOSE_WAIT          1000 /* microseconds, typically 2-3 cycles */
64
65 #define NPE_ID(port_id)         ((port_id) >> 4)
66 #define PHYSICAL_ID(port_id)    ((NPE_ID(port_id) + 2) % 3)
67 #define TX_QUEUE(port_id)       (NPE_ID(port_id) + 23)
68 #define RXFREE_QUEUE(port_id)   (NPE_ID(port_id) + 26)
69 #define TXDONE_QUEUE            31
70
71 #define PTP_SLAVE_MODE          1
72 #define PTP_MASTER_MODE         2
73 #define PORT2CHANNEL(p)         NPE_ID(p->id)
74
75 /* TX Control Registers */
76 #define TX_CNTRL0_TX_EN         0x01
77 #define TX_CNTRL0_HALFDUPLEX    0x02
78 #define TX_CNTRL0_RETRY         0x04
79 #define TX_CNTRL0_PAD_EN        0x08
80 #define TX_CNTRL0_APPEND_FCS    0x10
81 #define TX_CNTRL0_2DEFER        0x20
82 #define TX_CNTRL0_RMII          0x40 /* reduced MII */
83 #define TX_CNTRL1_RETRIES       0x0F /* 4 bits */
84
85 /* RX Control Registers */
86 #define RX_CNTRL0_RX_EN         0x01
87 #define RX_CNTRL0_PADSTRIP_EN   0x02
88 #define RX_CNTRL0_SEND_FCS      0x04
89 #define RX_CNTRL0_PAUSE_EN      0x08
90 #define RX_CNTRL0_LOOP_EN       0x10
91 #define RX_CNTRL0_ADDR_FLTR_EN  0x20
92 #define RX_CNTRL0_RX_RUNT_EN    0x40
93 #define RX_CNTRL0_BCAST_DIS     0x80
94 #define RX_CNTRL1_DEFER_EN      0x01
95
96 /* Core Control Register */
97 #define CORE_RESET              0x01
98 #define CORE_RX_FIFO_FLUSH      0x02
99 #define CORE_TX_FIFO_FLUSH      0x04
100 #define CORE_SEND_JAM           0x08
101 #define CORE_MDC_EN             0x10 /* MDIO using NPE-B ETH-0 only */
102
103 #define DEFAULT_TX_CNTRL0       (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY |    \
104                                  TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
105                                  TX_CNTRL0_2DEFER)
106 #define DEFAULT_RX_CNTRL0       RX_CNTRL0_RX_EN
107 #define DEFAULT_CORE_CNTRL      CORE_MDC_EN
108
109
110 /* NPE message codes */
111 #define NPE_GETSTATUS                   0x00
112 #define NPE_EDB_SETPORTADDRESS          0x01
113 #define NPE_EDB_GETMACADDRESSDATABASE   0x02
114 #define NPE_EDB_SETMACADDRESSSDATABASE  0x03
115 #define NPE_GETSTATS                    0x04
116 #define NPE_RESETSTATS                  0x05
117 #define NPE_SETMAXFRAMELENGTHS          0x06
118 #define NPE_VLAN_SETRXTAGMODE           0x07
119 #define NPE_VLAN_SETDEFAULTRXVID        0x08
120 #define NPE_VLAN_SETPORTVLANTABLEENTRY  0x09
121 #define NPE_VLAN_SETPORTVLANTABLERANGE  0x0A
122 #define NPE_VLAN_SETRXQOSENTRY          0x0B
123 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
124 #define NPE_STP_SETBLOCKINGSTATE        0x0D
125 #define NPE_FW_SETFIREWALLMODE          0x0E
126 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
127 #define NPE_PC_SETAPMACTABLE            0x11
128 #define NPE_SETLOOPBACK_MODE            0x12
129 #define NPE_PC_SETBSSIDTABLE            0x13
130 #define NPE_ADDRESS_FILTER_CONFIG       0x14
131 #define NPE_APPENDFCSCONFIG             0x15
132 #define NPE_NOTIFY_MAC_RECOVERY_DONE    0x16
133 #define NPE_MAC_RECOVERY_START          0x17
134
135
136 #ifdef __ARMEB__
137 typedef struct sk_buff buffer_t;
138 #define free_buffer dev_kfree_skb
139 #define free_buffer_irq dev_consume_skb_irq
140 #else
141 typedef void buffer_t;
142 #define free_buffer kfree
143 #define free_buffer_irq kfree
144 #endif
145
146 struct eth_regs {
147         u32 tx_control[2], __res1[2];           /* 000 */
148         u32 rx_control[2], __res2[2];           /* 010 */
149         u32 random_seed, __res3[3];             /* 020 */
150         u32 partial_empty_threshold, __res4;    /* 030 */
151         u32 partial_full_threshold, __res5;     /* 038 */
152         u32 tx_start_bytes, __res6[3];          /* 040 */
153         u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
154         u32 tx_2part_deferral[2], __res8[2];    /* 060 */
155         u32 slot_time, __res9[3];               /* 070 */
156         u32 mdio_command[4];                    /* 080 */
157         u32 mdio_status[4];                     /* 090 */
158         u32 mcast_mask[6], __res10[2];          /* 0A0 */
159         u32 mcast_addr[6], __res11[2];          /* 0C0 */
160         u32 int_clock_threshold, __res12[3];    /* 0E0 */
161         u32 hw_addr[6], __res13[61];            /* 0F0 */
162         u32 core_control;                       /* 1FC */
163 };
164
165 struct port {
166         struct resource *mem_res;
167         struct eth_regs __iomem *regs;
168         struct npe *npe;
169         struct net_device *netdev;
170         struct napi_struct napi;
171         struct eth_plat_info *plat;
172         buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
173         struct desc *desc_tab;  /* coherent */
174         u32 desc_tab_phys;
175         int id;                 /* logical port ID */
176         int speed, duplex;
177         u8 firmware[4];
178         int hwts_tx_en;
179         int hwts_rx_en;
180 };
181
182 /* NPE message structure */
183 struct msg {
184 #ifdef __ARMEB__
185         u8 cmd, eth_id, byte2, byte3;
186         u8 byte4, byte5, byte6, byte7;
187 #else
188         u8 byte3, byte2, eth_id, cmd;
189         u8 byte7, byte6, byte5, byte4;
190 #endif
191 };
192
193 /* Ethernet packet descriptor */
194 struct desc {
195         u32 next;               /* pointer to next buffer, unused */
196
197 #ifdef __ARMEB__
198         u16 buf_len;            /* buffer length */
199         u16 pkt_len;            /* packet length */
200         u32 data;               /* pointer to data buffer in RAM */
201         u8 dest_id;
202         u8 src_id;
203         u16 flags;
204         u8 qos;
205         u8 padlen;
206         u16 vlan_tci;
207 #else
208         u16 pkt_len;            /* packet length */
209         u16 buf_len;            /* buffer length */
210         u32 data;               /* pointer to data buffer in RAM */
211         u16 flags;
212         u8 src_id;
213         u8 dest_id;
214         u16 vlan_tci;
215         u8 padlen;
216         u8 qos;
217 #endif
218
219 #ifdef __ARMEB__
220         u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
221         u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
222         u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
223 #else
224         u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
225         u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
226         u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
227 #endif
228 };
229
230
231 #define rx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
232                                  (n) * sizeof(struct desc))
233 #define rx_desc_ptr(port, n)    (&(port)->desc_tab[n])
234
235 #define tx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
236                                  ((n) + RX_DESCS) * sizeof(struct desc))
237 #define tx_desc_ptr(port, n)    (&(port)->desc_tab[(n) + RX_DESCS])
238
239 #ifndef __ARMEB__
240 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
241 {
242         int i;
243         for (i = 0; i < cnt; i++)
244                 dest[i] = swab32(src[i]);
245 }
246 #endif
247
248 static spinlock_t mdio_lock;
249 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
250 static struct mii_bus *mdio_bus;
251 static int ports_open;
252 static struct port *npe_port_tab[MAX_NPES];
253 static struct dma_pool *dma_pool;
254
255 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
256 {
257         u8 *data = skb->data;
258         unsigned int offset;
259         u16 *hi, *id;
260         u32 lo;
261
262         if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4)
263                 return 0;
264
265         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
266
267         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
268                 return 0;
269
270         hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
271         id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
272
273         memcpy(&lo, &hi[1], sizeof(lo));
274
275         return (uid_hi == ntohs(*hi) &&
276                 uid_lo == ntohl(lo) &&
277                 seqid  == ntohs(*id));
278 }
279
280 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
281 {
282         struct skb_shared_hwtstamps *shhwtstamps;
283         struct ixp46x_ts_regs *regs;
284         u64 ns;
285         u32 ch, hi, lo, val;
286         u16 uid, seq;
287
288         if (!port->hwts_rx_en)
289                 return;
290
291         ch = PORT2CHANNEL(port);
292
293         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
294
295         val = __raw_readl(&regs->channel[ch].ch_event);
296
297         if (!(val & RX_SNAPSHOT_LOCKED))
298                 return;
299
300         lo = __raw_readl(&regs->channel[ch].src_uuid_lo);
301         hi = __raw_readl(&regs->channel[ch].src_uuid_hi);
302
303         uid = hi & 0xffff;
304         seq = (hi >> 16) & 0xffff;
305
306         if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
307                 goto out;
308
309         lo = __raw_readl(&regs->channel[ch].rx_snap_lo);
310         hi = __raw_readl(&regs->channel[ch].rx_snap_hi);
311         ns = ((u64) hi) << 32;
312         ns |= lo;
313         ns <<= TICKS_NS_SHIFT;
314
315         shhwtstamps = skb_hwtstamps(skb);
316         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
317         shhwtstamps->hwtstamp = ns_to_ktime(ns);
318 out:
319         __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
320 }
321
322 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
323 {
324         struct skb_shared_hwtstamps shhwtstamps;
325         struct ixp46x_ts_regs *regs;
326         struct skb_shared_info *shtx;
327         u64 ns;
328         u32 ch, cnt, hi, lo, val;
329
330         shtx = skb_shinfo(skb);
331         if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
332                 shtx->tx_flags |= SKBTX_IN_PROGRESS;
333         else
334                 return;
335
336         ch = PORT2CHANNEL(port);
337
338         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
339
340         /*
341          * This really stinks, but we have to poll for the Tx time stamp.
342          * Usually, the time stamp is ready after 4 to 6 microseconds.
343          */
344         for (cnt = 0; cnt < 100; cnt++) {
345                 val = __raw_readl(&regs->channel[ch].ch_event);
346                 if (val & TX_SNAPSHOT_LOCKED)
347                         break;
348                 udelay(1);
349         }
350         if (!(val & TX_SNAPSHOT_LOCKED)) {
351                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
352                 return;
353         }
354
355         lo = __raw_readl(&regs->channel[ch].tx_snap_lo);
356         hi = __raw_readl(&regs->channel[ch].tx_snap_hi);
357         ns = ((u64) hi) << 32;
358         ns |= lo;
359         ns <<= TICKS_NS_SHIFT;
360
361         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
362         shhwtstamps.hwtstamp = ns_to_ktime(ns);
363         skb_tstamp_tx(skb, &shhwtstamps);
364
365         __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
366 }
367
368 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
369 {
370         struct hwtstamp_config cfg;
371         struct ixp46x_ts_regs *regs;
372         struct port *port = netdev_priv(netdev);
373         int ch;
374
375         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
376                 return -EFAULT;
377
378         if (cfg.flags) /* reserved for future extensions */
379                 return -EINVAL;
380
381         ch = PORT2CHANNEL(port);
382         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
383
384         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
385                 return -ERANGE;
386
387         switch (cfg.rx_filter) {
388         case HWTSTAMP_FILTER_NONE:
389                 port->hwts_rx_en = 0;
390                 break;
391         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
392                 port->hwts_rx_en = PTP_SLAVE_MODE;
393                 __raw_writel(0, &regs->channel[ch].ch_control);
394                 break;
395         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
396                 port->hwts_rx_en = PTP_MASTER_MODE;
397                 __raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);
398                 break;
399         default:
400                 return -ERANGE;
401         }
402
403         port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
404
405         /* Clear out any old time stamps. */
406         __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
407                      &regs->channel[ch].ch_event);
408
409         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
410 }
411
412 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
413 {
414         struct hwtstamp_config cfg;
415         struct port *port = netdev_priv(netdev);
416
417         cfg.flags = 0;
418         cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
419
420         switch (port->hwts_rx_en) {
421         case 0:
422                 cfg.rx_filter = HWTSTAMP_FILTER_NONE;
423                 break;
424         case PTP_SLAVE_MODE:
425                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
426                 break;
427         case PTP_MASTER_MODE:
428                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
429                 break;
430         default:
431                 WARN_ON_ONCE(1);
432                 return -ERANGE;
433         }
434
435         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
436 }
437
438 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
439                            int write, u16 cmd)
440 {
441         int cycles = 0;
442
443         if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
444                 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
445                 return -1;
446         }
447
448         if (write) {
449                 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
450                 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
451         }
452         __raw_writel(((phy_id << 5) | location) & 0xFF,
453                      &mdio_regs->mdio_command[2]);
454         __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
455                      &mdio_regs->mdio_command[3]);
456
457         while ((cycles < MAX_MDIO_RETRIES) &&
458                (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
459                 udelay(1);
460                 cycles++;
461         }
462
463         if (cycles == MAX_MDIO_RETRIES) {
464                 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
465                        phy_id);
466                 return -1;
467         }
468
469 #if DEBUG_MDIO
470         printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
471                phy_id, write ? "write" : "read", cycles);
472 #endif
473
474         if (write)
475                 return 0;
476
477         if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
478 #if DEBUG_MDIO
479                 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
480                        phy_id);
481 #endif
482                 return 0xFFFF; /* don't return error */
483         }
484
485         return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
486                 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
487 }
488
489 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
490 {
491         unsigned long flags;
492         int ret;
493
494         spin_lock_irqsave(&mdio_lock, flags);
495         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
496         spin_unlock_irqrestore(&mdio_lock, flags);
497 #if DEBUG_MDIO
498         printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
499                phy_id, location, ret);
500 #endif
501         return ret;
502 }
503
504 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
505                              u16 val)
506 {
507         unsigned long flags;
508         int ret;
509
510         spin_lock_irqsave(&mdio_lock, flags);
511         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
512         spin_unlock_irqrestore(&mdio_lock, flags);
513 #if DEBUG_MDIO
514         printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
515                bus->name, phy_id, location, val, ret);
516 #endif
517         return ret;
518 }
519
520 static int ixp4xx_mdio_register(void)
521 {
522         int err;
523
524         if (!(mdio_bus = mdiobus_alloc()))
525                 return -ENOMEM;
526
527         if (cpu_is_ixp43x()) {
528                 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
529                 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
530                         return -ENODEV;
531                 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
532         } else {
533                 /* All MII PHY accesses use NPE-B Ethernet registers */
534                 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
535                         return -ENODEV;
536                 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
537         }
538
539         __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
540         spin_lock_init(&mdio_lock);
541         mdio_bus->name = "IXP4xx MII Bus";
542         mdio_bus->read = &ixp4xx_mdio_read;
543         mdio_bus->write = &ixp4xx_mdio_write;
544         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
545
546         if ((err = mdiobus_register(mdio_bus)))
547                 mdiobus_free(mdio_bus);
548         return err;
549 }
550
551 static void ixp4xx_mdio_remove(void)
552 {
553         mdiobus_unregister(mdio_bus);
554         mdiobus_free(mdio_bus);
555 }
556
557
558 static void ixp4xx_adjust_link(struct net_device *dev)
559 {
560         struct port *port = netdev_priv(dev);
561         struct phy_device *phydev = dev->phydev;
562
563         if (!phydev->link) {
564                 if (port->speed) {
565                         port->speed = 0;
566                         printk(KERN_INFO "%s: link down\n", dev->name);
567                 }
568                 return;
569         }
570
571         if (port->speed == phydev->speed && port->duplex == phydev->duplex)
572                 return;
573
574         port->speed = phydev->speed;
575         port->duplex = phydev->duplex;
576
577         if (port->duplex)
578                 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
579                              &port->regs->tx_control[0]);
580         else
581                 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
582                              &port->regs->tx_control[0]);
583
584         printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
585                dev->name, port->speed, port->duplex ? "full" : "half");
586 }
587
588
589 static inline void debug_pkt(struct net_device *dev, const char *func,
590                              u8 *data, int len)
591 {
592 #if DEBUG_PKT_BYTES
593         int i;
594
595         printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
596         for (i = 0; i < len; i++) {
597                 if (i >= DEBUG_PKT_BYTES)
598                         break;
599                 printk("%s%02X",
600                        ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
601                        data[i]);
602         }
603         printk("\n");
604 #endif
605 }
606
607
608 static inline void debug_desc(u32 phys, struct desc *desc)
609 {
610 #if DEBUG_DESC
611         printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
612                " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
613                phys, desc->next, desc->buf_len, desc->pkt_len,
614                desc->data, desc->dest_id, desc->src_id, desc->flags,
615                desc->qos, desc->padlen, desc->vlan_tci,
616                desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
617                desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
618                desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
619                desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
620 #endif
621 }
622
623 static inline int queue_get_desc(unsigned int queue, struct port *port,
624                                  int is_tx)
625 {
626         u32 phys, tab_phys, n_desc;
627         struct desc *tab;
628
629         if (!(phys = qmgr_get_entry(queue)))
630                 return -1;
631
632         phys &= ~0x1F; /* mask out non-address bits */
633         tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
634         tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
635         n_desc = (phys - tab_phys) / sizeof(struct desc);
636         BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
637         debug_desc(phys, &tab[n_desc]);
638         BUG_ON(tab[n_desc].next);
639         return n_desc;
640 }
641
642 static inline void queue_put_desc(unsigned int queue, u32 phys,
643                                   struct desc *desc)
644 {
645         debug_desc(phys, desc);
646         BUG_ON(phys & 0x1F);
647         qmgr_put_entry(queue, phys);
648         /* Don't check for queue overflow here, we've allocated sufficient
649            length and queues >= 32 don't support this check anyway. */
650 }
651
652
653 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
654 {
655 #ifdef __ARMEB__
656         dma_unmap_single(&port->netdev->dev, desc->data,
657                          desc->buf_len, DMA_TO_DEVICE);
658 #else
659         dma_unmap_single(&port->netdev->dev, desc->data & ~3,
660                          ALIGN((desc->data & 3) + desc->buf_len, 4),
661                          DMA_TO_DEVICE);
662 #endif
663 }
664
665
666 static void eth_rx_irq(void *pdev)
667 {
668         struct net_device *dev = pdev;
669         struct port *port = netdev_priv(dev);
670
671 #if DEBUG_RX
672         printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
673 #endif
674         qmgr_disable_irq(port->plat->rxq);
675         napi_schedule(&port->napi);
676 }
677
678 static int eth_poll(struct napi_struct *napi, int budget)
679 {
680         struct port *port = container_of(napi, struct port, napi);
681         struct net_device *dev = port->netdev;
682         unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
683         int received = 0;
684
685 #if DEBUG_RX
686         printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
687 #endif
688
689         while (received < budget) {
690                 struct sk_buff *skb;
691                 struct desc *desc;
692                 int n;
693 #ifdef __ARMEB__
694                 struct sk_buff *temp;
695                 u32 phys;
696 #endif
697
698                 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
699 #if DEBUG_RX
700                         printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
701                                dev->name);
702 #endif
703                         napi_complete(napi);
704                         qmgr_enable_irq(rxq);
705                         if (!qmgr_stat_below_low_watermark(rxq) &&
706                             napi_reschedule(napi)) { /* not empty again */
707 #if DEBUG_RX
708                                 printk(KERN_DEBUG "%s: eth_poll napi_reschedule succeeded\n",
709                                        dev->name);
710 #endif
711                                 qmgr_disable_irq(rxq);
712                                 continue;
713                         }
714 #if DEBUG_RX
715                         printk(KERN_DEBUG "%s: eth_poll all done\n",
716                                dev->name);
717 #endif
718                         return received; /* all work done */
719                 }
720
721                 desc = rx_desc_ptr(port, n);
722
723 #ifdef __ARMEB__
724                 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
725                         phys = dma_map_single(&dev->dev, skb->data,
726                                               RX_BUFF_SIZE, DMA_FROM_DEVICE);
727                         if (dma_mapping_error(&dev->dev, phys)) {
728                                 dev_kfree_skb(skb);
729                                 skb = NULL;
730                         }
731                 }
732 #else
733                 skb = netdev_alloc_skb(dev,
734                                        ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
735 #endif
736
737                 if (!skb) {
738                         dev->stats.rx_dropped++;
739                         /* put the desc back on RX-ready queue */
740                         desc->buf_len = MAX_MRU;
741                         desc->pkt_len = 0;
742                         queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
743                         continue;
744                 }
745
746                 /* process received frame */
747 #ifdef __ARMEB__
748                 temp = skb;
749                 skb = port->rx_buff_tab[n];
750                 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
751                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
752 #else
753                 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
754                                         RX_BUFF_SIZE, DMA_FROM_DEVICE);
755                 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
756                               ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
757 #endif
758                 skb_reserve(skb, NET_IP_ALIGN);
759                 skb_put(skb, desc->pkt_len);
760
761                 debug_pkt(dev, "eth_poll", skb->data, skb->len);
762
763                 ixp_rx_timestamp(port, skb);
764                 skb->protocol = eth_type_trans(skb, dev);
765                 dev->stats.rx_packets++;
766                 dev->stats.rx_bytes += skb->len;
767                 netif_receive_skb(skb);
768
769                 /* put the new buffer on RX-free queue */
770 #ifdef __ARMEB__
771                 port->rx_buff_tab[n] = temp;
772                 desc->data = phys + NET_IP_ALIGN;
773 #endif
774                 desc->buf_len = MAX_MRU;
775                 desc->pkt_len = 0;
776                 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
777                 received++;
778         }
779
780 #if DEBUG_RX
781         printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
782 #endif
783         return received;                /* not all work done */
784 }
785
786
787 static void eth_txdone_irq(void *unused)
788 {
789         u32 phys;
790
791 #if DEBUG_TX
792         printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
793 #endif
794         while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
795                 u32 npe_id, n_desc;
796                 struct port *port;
797                 struct desc *desc;
798                 int start;
799
800                 npe_id = phys & 3;
801                 BUG_ON(npe_id >= MAX_NPES);
802                 port = npe_port_tab[npe_id];
803                 BUG_ON(!port);
804                 phys &= ~0x1F; /* mask out non-address bits */
805                 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
806                 BUG_ON(n_desc >= TX_DESCS);
807                 desc = tx_desc_ptr(port, n_desc);
808                 debug_desc(phys, desc);
809
810                 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
811                         port->netdev->stats.tx_packets++;
812                         port->netdev->stats.tx_bytes += desc->pkt_len;
813
814                         dma_unmap_tx(port, desc);
815 #if DEBUG_TX
816                         printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
817                                port->netdev->name, port->tx_buff_tab[n_desc]);
818 #endif
819                         free_buffer_irq(port->tx_buff_tab[n_desc]);
820                         port->tx_buff_tab[n_desc] = NULL;
821                 }
822
823                 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
824                 queue_put_desc(port->plat->txreadyq, phys, desc);
825                 if (start) { /* TX-ready queue was empty */
826 #if DEBUG_TX
827                         printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
828                                port->netdev->name);
829 #endif
830                         netif_wake_queue(port->netdev);
831                 }
832         }
833 }
834
835 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
836 {
837         struct port *port = netdev_priv(dev);
838         unsigned int txreadyq = port->plat->txreadyq;
839         int len, offset, bytes, n;
840         void *mem;
841         u32 phys;
842         struct desc *desc;
843
844 #if DEBUG_TX
845         printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
846 #endif
847
848         if (unlikely(skb->len > MAX_MRU)) {
849                 dev_kfree_skb(skb);
850                 dev->stats.tx_errors++;
851                 return NETDEV_TX_OK;
852         }
853
854         debug_pkt(dev, "eth_xmit", skb->data, skb->len);
855
856         len = skb->len;
857 #ifdef __ARMEB__
858         offset = 0; /* no need to keep alignment */
859         bytes = len;
860         mem = skb->data;
861 #else
862         offset = (int)skb->data & 3; /* keep 32-bit alignment */
863         bytes = ALIGN(offset + len, 4);
864         if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
865                 dev_kfree_skb(skb);
866                 dev->stats.tx_dropped++;
867                 return NETDEV_TX_OK;
868         }
869         memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
870 #endif
871
872         phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
873         if (dma_mapping_error(&dev->dev, phys)) {
874                 dev_kfree_skb(skb);
875 #ifndef __ARMEB__
876                 kfree(mem);
877 #endif
878                 dev->stats.tx_dropped++;
879                 return NETDEV_TX_OK;
880         }
881
882         n = queue_get_desc(txreadyq, port, 1);
883         BUG_ON(n < 0);
884         desc = tx_desc_ptr(port, n);
885
886 #ifdef __ARMEB__
887         port->tx_buff_tab[n] = skb;
888 #else
889         port->tx_buff_tab[n] = mem;
890 #endif
891         desc->data = phys + offset;
892         desc->buf_len = desc->pkt_len = len;
893
894         /* NPE firmware pads short frames with zeros internally */
895         wmb();
896         queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
897
898         if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
899 #if DEBUG_TX
900                 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
901 #endif
902                 netif_stop_queue(dev);
903                 /* we could miss TX ready interrupt */
904                 /* really empty in fact */
905                 if (!qmgr_stat_below_low_watermark(txreadyq)) {
906 #if DEBUG_TX
907                         printk(KERN_DEBUG "%s: eth_xmit ready again\n",
908                                dev->name);
909 #endif
910                         netif_wake_queue(dev);
911                 }
912         }
913
914 #if DEBUG_TX
915         printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
916 #endif
917
918         ixp_tx_timestamp(port, skb);
919         skb_tx_timestamp(skb);
920
921 #ifndef __ARMEB__
922         dev_kfree_skb(skb);
923 #endif
924         return NETDEV_TX_OK;
925 }
926
927
928 static void eth_set_mcast_list(struct net_device *dev)
929 {
930         struct port *port = netdev_priv(dev);
931         struct netdev_hw_addr *ha;
932         u8 diffs[ETH_ALEN], *addr;
933         int i;
934         static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
935
936         if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) {
937                 for (i = 0; i < ETH_ALEN; i++) {
938                         __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
939                         __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
940                 }
941                 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
942                         &port->regs->rx_control[0]);
943                 return;
944         }
945
946         if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
947                 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
948                              &port->regs->rx_control[0]);
949                 return;
950         }
951
952         eth_zero_addr(diffs);
953
954         addr = NULL;
955         netdev_for_each_mc_addr(ha, dev) {
956                 if (!addr)
957                         addr = ha->addr; /* first MAC address */
958                 for (i = 0; i < ETH_ALEN; i++)
959                         diffs[i] |= addr[i] ^ ha->addr[i];
960         }
961
962         for (i = 0; i < ETH_ALEN; i++) {
963                 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
964                 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
965         }
966
967         __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
968                      &port->regs->rx_control[0]);
969 }
970
971
972 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
973 {
974         if (!netif_running(dev))
975                 return -EINVAL;
976
977         if (cpu_is_ixp46x()) {
978                 if (cmd == SIOCSHWTSTAMP)
979                         return hwtstamp_set(dev, req);
980                 if (cmd == SIOCGHWTSTAMP)
981                         return hwtstamp_get(dev, req);
982         }
983
984         return phy_mii_ioctl(dev->phydev, req, cmd);
985 }
986
987 /* ethtool support */
988
989 static void ixp4xx_get_drvinfo(struct net_device *dev,
990                                struct ethtool_drvinfo *info)
991 {
992         struct port *port = netdev_priv(dev);
993
994         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
995         snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
996                  port->firmware[0], port->firmware[1],
997                  port->firmware[2], port->firmware[3]);
998         strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
999 }
1000
1001 int ixp46x_phc_index = -1;
1002 EXPORT_SYMBOL_GPL(ixp46x_phc_index);
1003
1004 static int ixp4xx_get_ts_info(struct net_device *dev,
1005                               struct ethtool_ts_info *info)
1006 {
1007         if (!cpu_is_ixp46x()) {
1008                 info->so_timestamping =
1009                         SOF_TIMESTAMPING_TX_SOFTWARE |
1010                         SOF_TIMESTAMPING_RX_SOFTWARE |
1011                         SOF_TIMESTAMPING_SOFTWARE;
1012                 info->phc_index = -1;
1013                 return 0;
1014         }
1015         info->so_timestamping =
1016                 SOF_TIMESTAMPING_TX_HARDWARE |
1017                 SOF_TIMESTAMPING_RX_HARDWARE |
1018                 SOF_TIMESTAMPING_RAW_HARDWARE;
1019         info->phc_index = ixp46x_phc_index;
1020         info->tx_types =
1021                 (1 << HWTSTAMP_TX_OFF) |
1022                 (1 << HWTSTAMP_TX_ON);
1023         info->rx_filters =
1024                 (1 << HWTSTAMP_FILTER_NONE) |
1025                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1026                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1027         return 0;
1028 }
1029
1030 static const struct ethtool_ops ixp4xx_ethtool_ops = {
1031         .get_drvinfo = ixp4xx_get_drvinfo,
1032         .nway_reset = phy_ethtool_nway_reset,
1033         .get_link = ethtool_op_get_link,
1034         .get_ts_info = ixp4xx_get_ts_info,
1035         .get_link_ksettings = phy_ethtool_get_link_ksettings,
1036         .set_link_ksettings = phy_ethtool_set_link_ksettings,
1037 };
1038
1039
1040 static int request_queues(struct port *port)
1041 {
1042         int err;
1043
1044         err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1045                                  "%s:RX-free", port->netdev->name);
1046         if (err)
1047                 return err;
1048
1049         err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1050                                  "%s:RX", port->netdev->name);
1051         if (err)
1052                 goto rel_rxfree;
1053
1054         err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1055                                  "%s:TX", port->netdev->name);
1056         if (err)
1057                 goto rel_rx;
1058
1059         err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1060                                  "%s:TX-ready", port->netdev->name);
1061         if (err)
1062                 goto rel_tx;
1063
1064         /* TX-done queue handles skbs sent out by the NPEs */
1065         if (!ports_open) {
1066                 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1067                                          "%s:TX-done", DRV_NAME);
1068                 if (err)
1069                         goto rel_txready;
1070         }
1071         return 0;
1072
1073 rel_txready:
1074         qmgr_release_queue(port->plat->txreadyq);
1075 rel_tx:
1076         qmgr_release_queue(TX_QUEUE(port->id));
1077 rel_rx:
1078         qmgr_release_queue(port->plat->rxq);
1079 rel_rxfree:
1080         qmgr_release_queue(RXFREE_QUEUE(port->id));
1081         printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1082                port->netdev->name);
1083         return err;
1084 }
1085
1086 static void release_queues(struct port *port)
1087 {
1088         qmgr_release_queue(RXFREE_QUEUE(port->id));
1089         qmgr_release_queue(port->plat->rxq);
1090         qmgr_release_queue(TX_QUEUE(port->id));
1091         qmgr_release_queue(port->plat->txreadyq);
1092
1093         if (!ports_open)
1094                 qmgr_release_queue(TXDONE_QUEUE);
1095 }
1096
1097 static int init_queues(struct port *port)
1098 {
1099         int i;
1100
1101         if (!ports_open) {
1102                 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1103                                            POOL_ALLOC_SIZE, 32, 0);
1104                 if (!dma_pool)
1105                         return -ENOMEM;
1106         }
1107
1108         if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1109                                               &port->desc_tab_phys)))
1110                 return -ENOMEM;
1111         memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1112         memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1113         memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1114
1115         /* Setup RX buffers */
1116         for (i = 0; i < RX_DESCS; i++) {
1117                 struct desc *desc = rx_desc_ptr(port, i);
1118                 buffer_t *buff; /* skb or kmalloc()ated memory */
1119                 void *data;
1120 #ifdef __ARMEB__
1121                 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1122                         return -ENOMEM;
1123                 data = buff->data;
1124 #else
1125                 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1126                         return -ENOMEM;
1127                 data = buff;
1128 #endif
1129                 desc->buf_len = MAX_MRU;
1130                 desc->data = dma_map_single(&port->netdev->dev, data,
1131                                             RX_BUFF_SIZE, DMA_FROM_DEVICE);
1132                 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1133                         free_buffer(buff);
1134                         return -EIO;
1135                 }
1136                 desc->data += NET_IP_ALIGN;
1137                 port->rx_buff_tab[i] = buff;
1138         }
1139
1140         return 0;
1141 }
1142
1143 static void destroy_queues(struct port *port)
1144 {
1145         int i;
1146
1147         if (port->desc_tab) {
1148                 for (i = 0; i < RX_DESCS; i++) {
1149                         struct desc *desc = rx_desc_ptr(port, i);
1150                         buffer_t *buff = port->rx_buff_tab[i];
1151                         if (buff) {
1152                                 dma_unmap_single(&port->netdev->dev,
1153                                                  desc->data - NET_IP_ALIGN,
1154                                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
1155                                 free_buffer(buff);
1156                         }
1157                 }
1158                 for (i = 0; i < TX_DESCS; i++) {
1159                         struct desc *desc = tx_desc_ptr(port, i);
1160                         buffer_t *buff = port->tx_buff_tab[i];
1161                         if (buff) {
1162                                 dma_unmap_tx(port, desc);
1163                                 free_buffer(buff);
1164                         }
1165                 }
1166                 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1167                 port->desc_tab = NULL;
1168         }
1169
1170         if (!ports_open && dma_pool) {
1171                 dma_pool_destroy(dma_pool);
1172                 dma_pool = NULL;
1173         }
1174 }
1175
1176 static int eth_open(struct net_device *dev)
1177 {
1178         struct port *port = netdev_priv(dev);
1179         struct npe *npe = port->npe;
1180         struct msg msg;
1181         int i, err;
1182
1183         if (!npe_running(npe)) {
1184                 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1185                 if (err)
1186                         return err;
1187
1188                 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1189                         printk(KERN_ERR "%s: %s not responding\n", dev->name,
1190                                npe_name(npe));
1191                         return -EIO;
1192                 }
1193                 port->firmware[0] = msg.byte4;
1194                 port->firmware[1] = msg.byte5;
1195                 port->firmware[2] = msg.byte6;
1196                 port->firmware[3] = msg.byte7;
1197         }
1198
1199         memset(&msg, 0, sizeof(msg));
1200         msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1201         msg.eth_id = port->id;
1202         msg.byte5 = port->plat->rxq | 0x80;
1203         msg.byte7 = port->plat->rxq << 4;
1204         for (i = 0; i < 8; i++) {
1205                 msg.byte3 = i;
1206                 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1207                         return -EIO;
1208         }
1209
1210         msg.cmd = NPE_EDB_SETPORTADDRESS;
1211         msg.eth_id = PHYSICAL_ID(port->id);
1212         msg.byte2 = dev->dev_addr[0];
1213         msg.byte3 = dev->dev_addr[1];
1214         msg.byte4 = dev->dev_addr[2];
1215         msg.byte5 = dev->dev_addr[3];
1216         msg.byte6 = dev->dev_addr[4];
1217         msg.byte7 = dev->dev_addr[5];
1218         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1219                 return -EIO;
1220
1221         memset(&msg, 0, sizeof(msg));
1222         msg.cmd = NPE_FW_SETFIREWALLMODE;
1223         msg.eth_id = port->id;
1224         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1225                 return -EIO;
1226
1227         if ((err = request_queues(port)) != 0)
1228                 return err;
1229
1230         if ((err = init_queues(port)) != 0) {
1231                 destroy_queues(port);
1232                 release_queues(port);
1233                 return err;
1234         }
1235
1236         port->speed = 0;        /* force "link up" message */
1237         phy_start(dev->phydev);
1238
1239         for (i = 0; i < ETH_ALEN; i++)
1240                 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1241         __raw_writel(0x08, &port->regs->random_seed);
1242         __raw_writel(0x12, &port->regs->partial_empty_threshold);
1243         __raw_writel(0x30, &port->regs->partial_full_threshold);
1244         __raw_writel(0x08, &port->regs->tx_start_bytes);
1245         __raw_writel(0x15, &port->regs->tx_deferral);
1246         __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1247         __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1248         __raw_writel(0x80, &port->regs->slot_time);
1249         __raw_writel(0x01, &port->regs->int_clock_threshold);
1250
1251         /* Populate queues with buffers, no failure after this point */
1252         for (i = 0; i < TX_DESCS; i++)
1253                 queue_put_desc(port->plat->txreadyq,
1254                                tx_desc_phys(port, i), tx_desc_ptr(port, i));
1255
1256         for (i = 0; i < RX_DESCS; i++)
1257                 queue_put_desc(RXFREE_QUEUE(port->id),
1258                                rx_desc_phys(port, i), rx_desc_ptr(port, i));
1259
1260         __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1261         __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1262         __raw_writel(0, &port->regs->rx_control[1]);
1263         __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1264
1265         napi_enable(&port->napi);
1266         eth_set_mcast_list(dev);
1267         netif_start_queue(dev);
1268
1269         qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1270                      eth_rx_irq, dev);
1271         if (!ports_open) {
1272                 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1273                              eth_txdone_irq, NULL);
1274                 qmgr_enable_irq(TXDONE_QUEUE);
1275         }
1276         ports_open++;
1277         /* we may already have RX data, enables IRQ */
1278         napi_schedule(&port->napi);
1279         return 0;
1280 }
1281
1282 static int eth_close(struct net_device *dev)
1283 {
1284         struct port *port = netdev_priv(dev);
1285         struct msg msg;
1286         int buffs = RX_DESCS; /* allocated RX buffers */
1287         int i;
1288
1289         ports_open--;
1290         qmgr_disable_irq(port->plat->rxq);
1291         napi_disable(&port->napi);
1292         netif_stop_queue(dev);
1293
1294         while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1295                 buffs--;
1296
1297         memset(&msg, 0, sizeof(msg));
1298         msg.cmd = NPE_SETLOOPBACK_MODE;
1299         msg.eth_id = port->id;
1300         msg.byte3 = 1;
1301         if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1302                 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1303
1304         i = 0;
1305         do {                    /* drain RX buffers */
1306                 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1307                         buffs--;
1308                 if (!buffs)
1309                         break;
1310                 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1311                         /* we have to inject some packet */
1312                         struct desc *desc;
1313                         u32 phys;
1314                         int n = queue_get_desc(port->plat->txreadyq, port, 1);
1315                         BUG_ON(n < 0);
1316                         desc = tx_desc_ptr(port, n);
1317                         phys = tx_desc_phys(port, n);
1318                         desc->buf_len = desc->pkt_len = 1;
1319                         wmb();
1320                         queue_put_desc(TX_QUEUE(port->id), phys, desc);
1321                 }
1322                 udelay(1);
1323         } while (++i < MAX_CLOSE_WAIT);
1324
1325         if (buffs)
1326                 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1327                        " left in NPE\n", dev->name, buffs);
1328 #if DEBUG_CLOSE
1329         if (!buffs)
1330                 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1331 #endif
1332
1333         buffs = TX_DESCS;
1334         while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1335                 buffs--; /* cancel TX */
1336
1337         i = 0;
1338         do {
1339                 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1340                         buffs--;
1341                 if (!buffs)
1342                         break;
1343         } while (++i < MAX_CLOSE_WAIT);
1344
1345         if (buffs)
1346                 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1347                        "left in NPE\n", dev->name, buffs);
1348 #if DEBUG_CLOSE
1349         if (!buffs)
1350                 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1351 #endif
1352
1353         msg.byte3 = 0;
1354         if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1355                 printk(KERN_CRIT "%s: unable to disable loopback\n",
1356                        dev->name);
1357
1358         phy_stop(dev->phydev);
1359
1360         if (!ports_open)
1361                 qmgr_disable_irq(TXDONE_QUEUE);
1362         destroy_queues(port);
1363         release_queues(port);
1364         return 0;
1365 }
1366
1367 static const struct net_device_ops ixp4xx_netdev_ops = {
1368         .ndo_open = eth_open,
1369         .ndo_stop = eth_close,
1370         .ndo_start_xmit = eth_xmit,
1371         .ndo_set_rx_mode = eth_set_mcast_list,
1372         .ndo_do_ioctl = eth_ioctl,
1373         .ndo_set_mac_address = eth_mac_addr,
1374         .ndo_validate_addr = eth_validate_addr,
1375 };
1376
1377 static int eth_init_one(struct platform_device *pdev)
1378 {
1379         struct port *port;
1380         struct net_device *dev;
1381         struct eth_plat_info *plat = dev_get_platdata(&pdev->dev);
1382         struct phy_device *phydev = NULL;
1383         u32 regs_phys;
1384         char phy_id[MII_BUS_ID_SIZE + 3];
1385         int err;
1386
1387         if (!(dev = alloc_etherdev(sizeof(struct port))))
1388                 return -ENOMEM;
1389
1390         SET_NETDEV_DEV(dev, &pdev->dev);
1391         port = netdev_priv(dev);
1392         port->netdev = dev;
1393         port->id = pdev->id;
1394
1395         switch (port->id) {
1396         case IXP4XX_ETH_NPEA:
1397                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1398                 regs_phys  = IXP4XX_EthA_BASE_PHYS;
1399                 break;
1400         case IXP4XX_ETH_NPEB:
1401                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1402                 regs_phys  = IXP4XX_EthB_BASE_PHYS;
1403                 break;
1404         case IXP4XX_ETH_NPEC:
1405                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1406                 regs_phys  = IXP4XX_EthC_BASE_PHYS;
1407                 break;
1408         default:
1409                 err = -ENODEV;
1410                 goto err_free;
1411         }
1412
1413         dev->netdev_ops = &ixp4xx_netdev_ops;
1414         dev->ethtool_ops = &ixp4xx_ethtool_ops;
1415         dev->tx_queue_len = 100;
1416
1417         netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1418
1419         if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1420                 err = -EIO;
1421                 goto err_free;
1422         }
1423
1424         port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1425         if (!port->mem_res) {
1426                 err = -EBUSY;
1427                 goto err_npe_rel;
1428         }
1429
1430         port->plat = plat;
1431         npe_port_tab[NPE_ID(port->id)] = port;
1432         memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1433
1434         platform_set_drvdata(pdev, dev);
1435
1436         __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1437                      &port->regs->core_control);
1438         udelay(50);
1439         __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1440         udelay(50);
1441
1442         snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
1443                 mdio_bus->id, plat->phy);
1444         phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link,
1445                              PHY_INTERFACE_MODE_MII);
1446         if (IS_ERR(phydev)) {
1447                 err = PTR_ERR(phydev);
1448                 goto err_free_mem;
1449         }
1450
1451         phydev->irq = PHY_POLL;
1452
1453         if ((err = register_netdev(dev)))
1454                 goto err_phy_dis;
1455
1456         printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1457                npe_name(port->npe));
1458
1459         return 0;
1460
1461 err_phy_dis:
1462         phy_disconnect(phydev);
1463 err_free_mem:
1464         npe_port_tab[NPE_ID(port->id)] = NULL;
1465         release_resource(port->mem_res);
1466 err_npe_rel:
1467         npe_release(port->npe);
1468 err_free:
1469         free_netdev(dev);
1470         return err;
1471 }
1472
1473 static int eth_remove_one(struct platform_device *pdev)
1474 {
1475         struct net_device *dev = platform_get_drvdata(pdev);
1476         struct phy_device *phydev = dev->phydev;
1477         struct port *port = netdev_priv(dev);
1478
1479         unregister_netdev(dev);
1480         phy_disconnect(phydev);
1481         npe_port_tab[NPE_ID(port->id)] = NULL;
1482         npe_release(port->npe);
1483         release_resource(port->mem_res);
1484         free_netdev(dev);
1485         return 0;
1486 }
1487
1488 static struct platform_driver ixp4xx_eth_driver = {
1489         .driver.name    = DRV_NAME,
1490         .probe          = eth_init_one,
1491         .remove         = eth_remove_one,
1492 };
1493
1494 static int __init eth_init_module(void)
1495 {
1496         int err;
1497
1498         /*
1499          * FIXME: we bail out on device tree boot but this really needs
1500          * to be fixed in a nicer way: this registers the MDIO bus before
1501          * even matching the driver infrastructure, we should only probe
1502          * detected hardware.
1503          */
1504         if (of_have_populated_dt())
1505                 return -ENODEV;
1506         if ((err = ixp4xx_mdio_register()))
1507                 return err;
1508         return platform_driver_register(&ixp4xx_eth_driver);
1509 }
1510
1511 static void __exit eth_cleanup_module(void)
1512 {
1513         platform_driver_unregister(&ixp4xx_eth_driver);
1514         ixp4xx_mdio_remove();
1515 }
1516
1517 MODULE_AUTHOR("Krzysztof Halasa");
1518 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1519 MODULE_LICENSE("GPL v2");
1520 MODULE_ALIAS("platform:ixp4xx_eth");
1521 module_init(eth_init_module);
1522 module_exit(eth_cleanup_module);