d91a8e8349e6a82693b56509c5911c309b19da27
[muen/linux.git] / drivers / net / wireless / intel / iwlwifi / iwl-nvm-parse.c
1 /******************************************************************************
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
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5  *
6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11  * Copyright(c) 2018 - 2019 Intel Corporation
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14  * it under the terms of version 2 of the GNU General Public License as
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31  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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62  *****************************************************************************/
63 #include <linux/types.h>
64 #include <linux/slab.h>
65 #include <linux/export.h>
66 #include <linux/etherdevice.h>
67 #include <linux/pci.h>
68 #include <linux/firmware.h>
69
70 #include "iwl-drv.h"
71 #include "iwl-modparams.h"
72 #include "iwl-nvm-parse.h"
73 #include "iwl-prph.h"
74 #include "iwl-io.h"
75 #include "iwl-csr.h"
76 #include "fw/acpi.h"
77 #include "fw/api/nvm-reg.h"
78 #include "fw/api/commands.h"
79 #include "fw/api/cmdhdr.h"
80 #include "fw/img.h"
81
82 /* NVM offsets (in words) definitions */
83 enum nvm_offsets {
84         /* NVM HW-Section offset (in words) definitions */
85         SUBSYSTEM_ID = 0x0A,
86         HW_ADDR = 0x15,
87
88         /* NVM SW-Section offset (in words) definitions */
89         NVM_SW_SECTION = 0x1C0,
90         NVM_VERSION = 0,
91         RADIO_CFG = 1,
92         SKU = 2,
93         N_HW_ADDRS = 3,
94         NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
95
96         /* NVM calibration section offset (in words) definitions */
97         NVM_CALIB_SECTION = 0x2B8,
98         XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
99
100         /* NVM REGULATORY -Section offset (in words) definitions */
101         NVM_CHANNELS_SDP = 0,
102 };
103
104 enum ext_nvm_offsets {
105         /* NVM HW-Section offset (in words) definitions */
106         MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
107
108         /* NVM SW-Section offset (in words) definitions */
109         NVM_VERSION_EXT_NVM = 0,
110         RADIO_CFG_FAMILY_EXT_NVM = 0,
111         SKU_FAMILY_8000 = 2,
112         N_HW_ADDRS_FAMILY_8000 = 3,
113
114         /* NVM REGULATORY -Section offset (in words) definitions */
115         NVM_CHANNELS_EXTENDED = 0,
116         NVM_LAR_OFFSET_OLD = 0x4C7,
117         NVM_LAR_OFFSET = 0x507,
118         NVM_LAR_ENABLED = 0x7,
119 };
120
121 /* SKU Capabilities (actual values from NVM definition) */
122 enum nvm_sku_bits {
123         NVM_SKU_CAP_BAND_24GHZ          = BIT(0),
124         NVM_SKU_CAP_BAND_52GHZ          = BIT(1),
125         NVM_SKU_CAP_11N_ENABLE          = BIT(2),
126         NVM_SKU_CAP_11AC_ENABLE         = BIT(3),
127         NVM_SKU_CAP_MIMO_DISABLE        = BIT(5),
128 };
129
130 /*
131  * These are the channel numbers in the order that they are stored in the NVM
132  */
133 static const u16 iwl_nvm_channels[] = {
134         /* 2.4 GHz */
135         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
136         /* 5 GHz */
137         36, 40, 44 , 48, 52, 56, 60, 64,
138         100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
139         149, 153, 157, 161, 165
140 };
141
142 static const u16 iwl_ext_nvm_channels[] = {
143         /* 2.4 GHz */
144         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
145         /* 5 GHz */
146         36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
147         96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
148         149, 153, 157, 161, 165, 169, 173, 177, 181
149 };
150
151 static const u16 iwl_uhb_nvm_channels[] = {
152         /* 2.4 GHz */
153         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
154         /* 5 GHz */
155         36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
156         96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
157         149, 153, 157, 161, 165, 169, 173, 177, 181,
158         /* 6-7 GHz */
159         1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
160         73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
161         133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
162         189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
163 };
164
165 #define IWL_NVM_NUM_CHANNELS            ARRAY_SIZE(iwl_nvm_channels)
166 #define IWL_NVM_NUM_CHANNELS_EXT        ARRAY_SIZE(iwl_ext_nvm_channels)
167 #define IWL_NVM_NUM_CHANNELS_UHB        ARRAY_SIZE(iwl_uhb_nvm_channels)
168 #define NUM_2GHZ_CHANNELS               14
169 #define FIRST_2GHZ_HT_MINUS             5
170 #define LAST_2GHZ_HT_PLUS               9
171 #define N_HW_ADDR_MASK                  0xF
172
173 /* rate data (static) */
174 static struct ieee80211_rate iwl_cfg80211_rates[] = {
175         { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
176         { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
177           .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
178         { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
179           .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
180         { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
181           .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
182         { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
183         { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
184         { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
185         { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
186         { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
187         { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
188         { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
189         { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
190 };
191 #define RATES_24_OFFS   0
192 #define N_RATES_24      ARRAY_SIZE(iwl_cfg80211_rates)
193 #define RATES_52_OFFS   4
194 #define N_RATES_52      (N_RATES_24 - RATES_52_OFFS)
195
196 /**
197  * enum iwl_nvm_channel_flags - channel flags in NVM
198  * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
199  * @NVM_CHANNEL_IBSS: usable as an IBSS channel
200  * @NVM_CHANNEL_ACTIVE: active scanning allowed
201  * @NVM_CHANNEL_RADAR: radar detection required
202  * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
203  * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
204  *      on same channel on 2.4 or same UNII band on 5.2
205  * @NVM_CHANNEL_UNIFORM: uniform spreading required
206  * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
207  * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
208  * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
209  * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
210  * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
211  */
212 enum iwl_nvm_channel_flags {
213         NVM_CHANNEL_VALID               = BIT(0),
214         NVM_CHANNEL_IBSS                = BIT(1),
215         NVM_CHANNEL_ACTIVE              = BIT(3),
216         NVM_CHANNEL_RADAR               = BIT(4),
217         NVM_CHANNEL_INDOOR_ONLY         = BIT(5),
218         NVM_CHANNEL_GO_CONCURRENT       = BIT(6),
219         NVM_CHANNEL_UNIFORM             = BIT(7),
220         NVM_CHANNEL_20MHZ               = BIT(8),
221         NVM_CHANNEL_40MHZ               = BIT(9),
222         NVM_CHANNEL_80MHZ               = BIT(10),
223         NVM_CHANNEL_160MHZ              = BIT(11),
224         NVM_CHANNEL_DC_HIGH             = BIT(12),
225 };
226
227 /**
228  * enum iwl_reg_capa_flags - global flags applied for the whole regulatory
229  * domain.
230  * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
231  *      2.4Ghz band is allowed.
232  * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
233  *      5Ghz band is allowed.
234  * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
235  *      for this regulatory domain (valid only in 5Ghz).
236  * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
237  *      for this regulatory domain (valid only in 5Ghz).
238  * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
239  * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
240  * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
241  *      for this regulatory domain (valid only in 5Ghz).
242  * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed.
243  */
244 enum iwl_reg_capa_flags {
245         REG_CAPA_BF_CCD_LOW_BAND        = BIT(0),
246         REG_CAPA_BF_CCD_HIGH_BAND       = BIT(1),
247         REG_CAPA_160MHZ_ALLOWED         = BIT(2),
248         REG_CAPA_80MHZ_ALLOWED          = BIT(3),
249         REG_CAPA_MCS_8_ALLOWED          = BIT(4),
250         REG_CAPA_MCS_9_ALLOWED          = BIT(5),
251         REG_CAPA_40MHZ_FORBIDDEN        = BIT(7),
252         REG_CAPA_DC_HIGH_ENABLED        = BIT(9),
253 };
254
255 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
256                                                int chan, u32 flags)
257 {
258 #define CHECK_AND_PRINT_I(x)    \
259         ((flags & NVM_CHANNEL_##x) ? " " #x : "")
260
261         if (!(flags & NVM_CHANNEL_VALID)) {
262                 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
263                               chan, flags);
264                 return;
265         }
266
267         /* Note: already can print up to 101 characters, 110 is the limit! */
268         IWL_DEBUG_DEV(dev, level,
269                       "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
270                       chan, flags,
271                       CHECK_AND_PRINT_I(VALID),
272                       CHECK_AND_PRINT_I(IBSS),
273                       CHECK_AND_PRINT_I(ACTIVE),
274                       CHECK_AND_PRINT_I(RADAR),
275                       CHECK_AND_PRINT_I(INDOOR_ONLY),
276                       CHECK_AND_PRINT_I(GO_CONCURRENT),
277                       CHECK_AND_PRINT_I(UNIFORM),
278                       CHECK_AND_PRINT_I(20MHZ),
279                       CHECK_AND_PRINT_I(40MHZ),
280                       CHECK_AND_PRINT_I(80MHZ),
281                       CHECK_AND_PRINT_I(160MHZ),
282                       CHECK_AND_PRINT_I(DC_HIGH));
283 #undef CHECK_AND_PRINT_I
284 }
285
286 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
287                                  u32 nvm_flags, const struct iwl_cfg *cfg)
288 {
289         u32 flags = IEEE80211_CHAN_NO_HT40;
290
291         if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
292                 if (ch_num <= LAST_2GHZ_HT_PLUS)
293                         flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
294                 if (ch_num >= FIRST_2GHZ_HT_MINUS)
295                         flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
296         } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
297                 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
298                         flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
299                 else
300                         flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
301         }
302         if (!(nvm_flags & NVM_CHANNEL_80MHZ))
303                 flags |= IEEE80211_CHAN_NO_80MHZ;
304         if (!(nvm_flags & NVM_CHANNEL_160MHZ))
305                 flags |= IEEE80211_CHAN_NO_160MHZ;
306
307         if (!(nvm_flags & NVM_CHANNEL_IBSS))
308                 flags |= IEEE80211_CHAN_NO_IR;
309
310         if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
311                 flags |= IEEE80211_CHAN_NO_IR;
312
313         if (nvm_flags & NVM_CHANNEL_RADAR)
314                 flags |= IEEE80211_CHAN_RADAR;
315
316         if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
317                 flags |= IEEE80211_CHAN_INDOOR_ONLY;
318
319         /* Set the GO concurrent flag only in case that NO_IR is set.
320          * Otherwise it is meaningless
321          */
322         if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
323             (flags & IEEE80211_CHAN_NO_IR))
324                 flags |= IEEE80211_CHAN_IR_CONCURRENT;
325
326         return flags;
327 }
328
329 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
330 {
331         if (ch_idx >= NUM_2GHZ_CHANNELS)
332                 return NL80211_BAND_5GHZ;
333         return NL80211_BAND_2GHZ;
334 }
335
336 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
337                                 struct iwl_nvm_data *data,
338                                 const void * const nvm_ch_flags,
339                                 u32 sbands_flags, bool v4)
340 {
341         int ch_idx;
342         int n_channels = 0;
343         struct ieee80211_channel *channel;
344         u32 ch_flags;
345         int num_of_ch;
346         const u16 *nvm_chan;
347
348         if (cfg->uhb_supported) {
349                 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
350                 nvm_chan = iwl_uhb_nvm_channels;
351         } else if (cfg->nvm_type == IWL_NVM_EXT) {
352                 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
353                 nvm_chan = iwl_ext_nvm_channels;
354         } else {
355                 num_of_ch = IWL_NVM_NUM_CHANNELS;
356                 nvm_chan = iwl_nvm_channels;
357         }
358
359         for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
360                 enum nl80211_band band =
361                         iwl_nl80211_band_from_channel_idx(ch_idx);
362
363                 if (v4)
364                         ch_flags =
365                                 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx);
366                 else
367                         ch_flags =
368                                 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx);
369
370                 if (band == NL80211_BAND_5GHZ &&
371                     !data->sku_cap_band_52ghz_enable)
372                         continue;
373
374                 /* workaround to disable wide channels in 5GHz */
375                 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
376                     band == NL80211_BAND_5GHZ) {
377                         ch_flags &= ~(NVM_CHANNEL_40MHZ |
378                                      NVM_CHANNEL_80MHZ |
379                                      NVM_CHANNEL_160MHZ);
380                 }
381
382                 if (ch_flags & NVM_CHANNEL_160MHZ)
383                         data->vht160_supported = true;
384
385                 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
386                     !(ch_flags & NVM_CHANNEL_VALID)) {
387                         /*
388                          * Channels might become valid later if lar is
389                          * supported, hence we still want to add them to
390                          * the list of supported channels to cfg80211.
391                          */
392                         iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
393                                                     nvm_chan[ch_idx], ch_flags);
394                         continue;
395                 }
396
397                 channel = &data->channels[n_channels];
398                 n_channels++;
399
400                 channel->hw_value = nvm_chan[ch_idx];
401                 channel->band = band;
402                 channel->center_freq =
403                         ieee80211_channel_to_frequency(
404                                 channel->hw_value, channel->band);
405
406                 /* Initialize regulatory-based run-time data */
407
408                 /*
409                  * Default value - highest tx power value.  max_power
410                  * is not used in mvm, and is used for backwards compatibility
411                  */
412                 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
413
414                 /* don't put limitations in case we're using LAR */
415                 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
416                         channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
417                                                                ch_idx, band,
418                                                                ch_flags, cfg);
419                 else
420                         channel->flags = 0;
421
422                 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
423                                             channel->hw_value, ch_flags);
424                 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
425                                  channel->hw_value, channel->max_power);
426         }
427
428         return n_channels;
429 }
430
431 static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
432                                   struct iwl_nvm_data *data,
433                                   struct ieee80211_sta_vht_cap *vht_cap,
434                                   u8 tx_chains, u8 rx_chains)
435 {
436         const struct iwl_cfg *cfg = trans->cfg;
437         int num_rx_ants = num_of_ant(rx_chains);
438         int num_tx_ants = num_of_ant(tx_chains);
439         unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
440                                            IEEE80211_VHT_MAX_AMPDU_1024K);
441
442         vht_cap->vht_supported = true;
443
444         vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
445                        IEEE80211_VHT_CAP_RXSTBC_1 |
446                        IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
447                        3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
448                        max_ampdu_exponent <<
449                        IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
450
451         if (data->vht160_supported)
452                 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
453                                 IEEE80211_VHT_CAP_SHORT_GI_160;
454
455         if (cfg->vht_mu_mimo_supported)
456                 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
457
458         if (cfg->ht_params->ldpc)
459                 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
460
461         if (data->sku_cap_mimo_disabled) {
462                 num_rx_ants = 1;
463                 num_tx_ants = 1;
464         }
465
466         if (num_tx_ants > 1)
467                 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
468         else
469                 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
470
471         switch (iwlwifi_mod_params.amsdu_size) {
472         case IWL_AMSDU_DEF:
473                 if (trans->trans_cfg->mq_rx_supported)
474                         vht_cap->cap |=
475                                 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
476                 else
477                         vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
478                 break;
479         case IWL_AMSDU_2K:
480                 if (trans->trans_cfg->mq_rx_supported)
481                         vht_cap->cap |=
482                                 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
483                 else
484                         WARN(1, "RB size of 2K is not supported by this device\n");
485                 break;
486         case IWL_AMSDU_4K:
487                 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
488                 break;
489         case IWL_AMSDU_8K:
490                 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
491                 break;
492         case IWL_AMSDU_12K:
493                 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
494                 break;
495         default:
496                 break;
497         }
498
499         vht_cap->vht_mcs.rx_mcs_map =
500                 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
501                             IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
502                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
503                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
504                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
505                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
506                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
507                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
508
509         if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
510                 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
511                 /* this works because NOT_SUPPORTED == 3 */
512                 vht_cap->vht_mcs.rx_mcs_map |=
513                         cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
514         }
515
516         vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
517
518         vht_cap->vht_mcs.tx_highest |=
519                 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
520 }
521
522 static struct ieee80211_sband_iftype_data iwl_he_capa[] = {
523         {
524                 .types_mask = BIT(NL80211_IFTYPE_STATION),
525                 .he_cap = {
526                         .has_he = true,
527                         .he_cap_elem = {
528                                 .mac_cap_info[0] =
529                                         IEEE80211_HE_MAC_CAP0_HTC_HE |
530                                         IEEE80211_HE_MAC_CAP0_TWT_REQ,
531                                 .mac_cap_info[1] =
532                                         IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
533                                         IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
534                                 .mac_cap_info[2] =
535                                         IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
536                                 .mac_cap_info[3] =
537                                         IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
538                                         IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
539                                 .mac_cap_info[4] =
540                                         IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU |
541                                         IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
542                                 .mac_cap_info[5] =
543                                         IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
544                                         IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
545                                         IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
546                                         IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
547                                         IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
548                                 .phy_cap_info[0] =
549                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
550                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
551                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
552                                 .phy_cap_info[1] =
553                                         IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
554                                         IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
555                                         IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
556                                 .phy_cap_info[2] =
557                                         IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
558                                 .phy_cap_info[3] =
559                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
560                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
561                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
562                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
563                                 .phy_cap_info[4] =
564                                         IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
565                                         IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
566                                         IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
567                                 .phy_cap_info[5] =
568                                         IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
569                                         IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
570                                 .phy_cap_info[6] =
571                                         IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
572                                 .phy_cap_info[7] =
573                                         IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR |
574                                         IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
575                                         IEEE80211_HE_PHY_CAP7_MAX_NC_1,
576                                 .phy_cap_info[8] =
577                                         IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
578                                         IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
579                                         IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
580                                         IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
581                                         IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
582                                 .phy_cap_info[9] =
583                                         IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
584                                         IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
585                                         IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
586                                         IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
587                         },
588                         /*
589                          * Set default Tx/Rx HE MCS NSS Support field.
590                          * Indicate support for up to 2 spatial streams and all
591                          * MCS, without any special cases
592                          */
593                         .he_mcs_nss_supp = {
594                                 .rx_mcs_80 = cpu_to_le16(0xfffa),
595                                 .tx_mcs_80 = cpu_to_le16(0xfffa),
596                                 .rx_mcs_160 = cpu_to_le16(0xfffa),
597                                 .tx_mcs_160 = cpu_to_le16(0xfffa),
598                                 .rx_mcs_80p80 = cpu_to_le16(0xffff),
599                                 .tx_mcs_80p80 = cpu_to_le16(0xffff),
600                         },
601                         /*
602                          * Set default PPE thresholds, with PPET16 set to 0,
603                          * PPET8 set to 7
604                          */
605                         .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
606                 },
607         },
608         {
609                 .types_mask = BIT(NL80211_IFTYPE_AP),
610                 .he_cap = {
611                         .has_he = true,
612                         .he_cap_elem = {
613                                 .mac_cap_info[0] =
614                                         IEEE80211_HE_MAC_CAP0_HTC_HE,
615                                 .mac_cap_info[1] =
616                                         IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
617                                         IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
618                                 .mac_cap_info[2] =
619                                         IEEE80211_HE_MAC_CAP2_BSR,
620                                 .mac_cap_info[3] =
621                                         IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
622                                         IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
623                                 .mac_cap_info[4] =
624                                         IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU,
625                                 .mac_cap_info[5] =
626                                         IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU,
627                                 .phy_cap_info[0] =
628                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
629                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
630                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
631                                 .phy_cap_info[1] =
632                                         IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
633                                 .phy_cap_info[2] =
634                                         IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
635                                 .phy_cap_info[3] =
636                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
637                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
638                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
639                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
640                                 .phy_cap_info[4] =
641                                         IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
642                                         IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
643                                         IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
644                                 .phy_cap_info[5] =
645                                         IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
646                                         IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
647                                 .phy_cap_info[6] =
648                                         IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
649                                 .phy_cap_info[7] =
650                                         IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
651                                         IEEE80211_HE_PHY_CAP7_MAX_NC_1,
652                                 .phy_cap_info[8] =
653                                         IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
654                                         IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
655                                         IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
656                                         IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
657                                         IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
658                                 .phy_cap_info[9] =
659                                         IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
660                                         IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
661                                         IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
662                         },
663                         /*
664                          * Set default Tx/Rx HE MCS NSS Support field.
665                          * Indicate support for up to 2 spatial streams and all
666                          * MCS, without any special cases
667                          */
668                         .he_mcs_nss_supp = {
669                                 .rx_mcs_80 = cpu_to_le16(0xfffa),
670                                 .tx_mcs_80 = cpu_to_le16(0xfffa),
671                                 .rx_mcs_160 = cpu_to_le16(0xfffa),
672                                 .tx_mcs_160 = cpu_to_le16(0xfffa),
673                                 .rx_mcs_80p80 = cpu_to_le16(0xffff),
674                                 .tx_mcs_80p80 = cpu_to_le16(0xffff),
675                         },
676                         /*
677                          * Set default PPE thresholds, with PPET16 set to 0,
678                          * PPET8 set to 7
679                          */
680                         .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
681                 },
682         },
683 };
684
685 static void iwl_init_he_hw_capab(struct iwl_trans *trans,
686                                  struct iwl_nvm_data *data,
687                                  struct ieee80211_supported_band *sband,
688                                  u8 tx_chains, u8 rx_chains)
689 {
690         sband->iftype_data = iwl_he_capa;
691         sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
692
693         /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */
694         if ((tx_chains & rx_chains) != ANT_AB) {
695                 int i;
696
697                 for (i = 0; i < sband->n_iftype_data; i++) {
698                         iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &=
699                                 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
700                         iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &=
701                                 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
702                         iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &=
703                                 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
704                 }
705         }
706 }
707
708 static void iwl_init_sbands(struct iwl_trans *trans,
709                             struct iwl_nvm_data *data,
710                             const void *nvm_ch_flags, u8 tx_chains,
711                             u8 rx_chains, u32 sbands_flags, bool v4)
712 {
713         struct device *dev = trans->dev;
714         const struct iwl_cfg *cfg = trans->cfg;
715         int n_channels;
716         int n_used = 0;
717         struct ieee80211_supported_band *sband;
718
719         n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
720                                           sbands_flags, v4);
721         sband = &data->bands[NL80211_BAND_2GHZ];
722         sband->band = NL80211_BAND_2GHZ;
723         sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
724         sband->n_bitrates = N_RATES_24;
725         n_used += iwl_init_sband_channels(data, sband, n_channels,
726                                           NL80211_BAND_2GHZ);
727         iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
728                              tx_chains, rx_chains);
729
730         if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
731                 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
732
733         sband = &data->bands[NL80211_BAND_5GHZ];
734         sband->band = NL80211_BAND_5GHZ;
735         sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
736         sband->n_bitrates = N_RATES_52;
737         n_used += iwl_init_sband_channels(data, sband, n_channels,
738                                           NL80211_BAND_5GHZ);
739         iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
740                              tx_chains, rx_chains);
741         if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
742                 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
743                                       tx_chains, rx_chains);
744
745         if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
746                 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
747
748         if (n_channels != n_used)
749                 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
750                             n_used, n_channels);
751 }
752
753 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
754                        const __le16 *phy_sku)
755 {
756         if (cfg->nvm_type != IWL_NVM_EXT)
757                 return le16_to_cpup(nvm_sw + SKU);
758
759         return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
760 }
761
762 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
763 {
764         if (cfg->nvm_type != IWL_NVM_EXT)
765                 return le16_to_cpup(nvm_sw + NVM_VERSION);
766         else
767                 return le32_to_cpup((__le32 *)(nvm_sw +
768                                                NVM_VERSION_EXT_NVM));
769 }
770
771 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
772                              const __le16 *phy_sku)
773 {
774         if (cfg->nvm_type != IWL_NVM_EXT)
775                 return le16_to_cpup(nvm_sw + RADIO_CFG);
776
777         return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
778
779 }
780
781 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
782 {
783         int n_hw_addr;
784
785         if (cfg->nvm_type != IWL_NVM_EXT)
786                 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
787
788         n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
789
790         return n_hw_addr & N_HW_ADDR_MASK;
791 }
792
793 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
794                               struct iwl_nvm_data *data,
795                               u32 radio_cfg)
796 {
797         if (cfg->nvm_type != IWL_NVM_EXT) {
798                 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
799                 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
800                 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
801                 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
802                 return;
803         }
804
805         /* set the radio configuration for family 8000 */
806         data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
807         data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
808         data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
809         data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
810         data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
811         data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
812 }
813
814 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
815 {
816         const u8 *hw_addr;
817
818         hw_addr = (const u8 *)&mac_addr0;
819         dest[0] = hw_addr[3];
820         dest[1] = hw_addr[2];
821         dest[2] = hw_addr[1];
822         dest[3] = hw_addr[0];
823
824         hw_addr = (const u8 *)&mac_addr1;
825         dest[4] = hw_addr[1];
826         dest[5] = hw_addr[0];
827 }
828
829 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
830                                         struct iwl_nvm_data *data)
831 {
832         __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
833         __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
834
835         iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
836         /*
837          * If the OEM fused a valid address, use it instead of the one in the
838          * OTP
839          */
840         if (is_valid_ether_addr(data->hw_addr))
841                 return;
842
843         mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
844         mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
845
846         iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
847 }
848
849 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
850                                            const struct iwl_cfg *cfg,
851                                            struct iwl_nvm_data *data,
852                                            const __le16 *mac_override,
853                                            const __be16 *nvm_hw)
854 {
855         const u8 *hw_addr;
856
857         if (mac_override) {
858                 static const u8 reserved_mac[] = {
859                         0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
860                 };
861
862                 hw_addr = (const u8 *)(mac_override +
863                                  MAC_ADDRESS_OVERRIDE_EXT_NVM);
864
865                 /*
866                  * Store the MAC address from MAO section.
867                  * No byte swapping is required in MAO section
868                  */
869                 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
870
871                 /*
872                  * Force the use of the OTP MAC address in case of reserved MAC
873                  * address in the NVM, or if address is given but invalid.
874                  */
875                 if (is_valid_ether_addr(data->hw_addr) &&
876                     memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
877                         return;
878
879                 IWL_ERR(trans,
880                         "mac address from nvm override section is not valid\n");
881         }
882
883         if (nvm_hw) {
884                 /* read the mac address from WFMP registers */
885                 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
886                                                 WFMP_MAC_ADDR_0));
887                 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
888                                                 WFMP_MAC_ADDR_1));
889
890                 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
891
892                 return;
893         }
894
895         IWL_ERR(trans, "mac address is not found\n");
896 }
897
898 static int iwl_set_hw_address(struct iwl_trans *trans,
899                               const struct iwl_cfg *cfg,
900                               struct iwl_nvm_data *data, const __be16 *nvm_hw,
901                               const __le16 *mac_override)
902 {
903         if (cfg->mac_addr_from_csr) {
904                 iwl_set_hw_address_from_csr(trans, data);
905         } else if (cfg->nvm_type != IWL_NVM_EXT) {
906                 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
907
908                 /* The byte order is little endian 16 bit, meaning 214365 */
909                 data->hw_addr[0] = hw_addr[1];
910                 data->hw_addr[1] = hw_addr[0];
911                 data->hw_addr[2] = hw_addr[3];
912                 data->hw_addr[3] = hw_addr[2];
913                 data->hw_addr[4] = hw_addr[5];
914                 data->hw_addr[5] = hw_addr[4];
915         } else {
916                 iwl_set_hw_address_family_8000(trans, cfg, data,
917                                                mac_override, nvm_hw);
918         }
919
920         if (!is_valid_ether_addr(data->hw_addr)) {
921                 IWL_ERR(trans, "no valid mac address was found\n");
922                 return -EINVAL;
923         }
924
925         IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
926
927         return 0;
928 }
929
930 static bool
931 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
932                         const __be16 *nvm_hw)
933 {
934         /*
935          * Workaround a bug in Indonesia SKUs where the regulatory in
936          * some 7000-family OTPs erroneously allow wide channels in
937          * 5GHz.  To check for Indonesia, we take the SKU value from
938          * bits 1-4 in the subsystem ID and check if it is either 5 or
939          * 9.  In those cases, we need to force-disable wide channels
940          * in 5GHz otherwise the FW will throw a sysassert when we try
941          * to use them.
942          */
943         if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
944                 /*
945                  * Unlike the other sections in the NVM, the hw
946                  * section uses big-endian.
947                  */
948                 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
949                 u8 sku = (subsystem_id & 0x1e) >> 1;
950
951                 if (sku == 5 || sku == 9) {
952                         IWL_DEBUG_EEPROM(trans->dev,
953                                          "disabling wide channels in 5GHz (0x%0x %d)\n",
954                                          subsystem_id, sku);
955                         return true;
956                 }
957         }
958
959         return false;
960 }
961
962 struct iwl_nvm_data *
963 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
964                    const struct iwl_fw *fw,
965                    const __be16 *nvm_hw, const __le16 *nvm_sw,
966                    const __le16 *nvm_calib, const __le16 *regulatory,
967                    const __le16 *mac_override, const __le16 *phy_sku,
968                    u8 tx_chains, u8 rx_chains)
969 {
970         struct iwl_nvm_data *data;
971         bool lar_enabled;
972         u32 sku, radio_cfg;
973         u32 sbands_flags = 0;
974         u16 lar_config;
975         const __le16 *ch_section;
976
977         if (cfg->uhb_supported)
978                 data = kzalloc(struct_size(data, channels,
979                                            IWL_NVM_NUM_CHANNELS_UHB),
980                                            GFP_KERNEL);
981         else if (cfg->nvm_type != IWL_NVM_EXT)
982                 data = kzalloc(struct_size(data, channels,
983                                            IWL_NVM_NUM_CHANNELS),
984                                            GFP_KERNEL);
985         else
986                 data = kzalloc(struct_size(data, channels,
987                                            IWL_NVM_NUM_CHANNELS_EXT),
988                                            GFP_KERNEL);
989         if (!data)
990                 return NULL;
991
992         data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
993
994         radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
995         iwl_set_radio_cfg(cfg, data, radio_cfg);
996         if (data->valid_tx_ant)
997                 tx_chains &= data->valid_tx_ant;
998         if (data->valid_rx_ant)
999                 rx_chains &= data->valid_rx_ant;
1000
1001         sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1002         data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1003         data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1004         data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1005         if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1006                 data->sku_cap_11n_enable = false;
1007         data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1008                                     (sku & NVM_SKU_CAP_11AC_ENABLE);
1009         data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1010
1011         data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1012
1013         if (cfg->nvm_type != IWL_NVM_EXT) {
1014                 /* Checking for required sections */
1015                 if (!nvm_calib) {
1016                         IWL_ERR(trans,
1017                                 "Can't parse empty Calib NVM sections\n");
1018                         kfree(data);
1019                         return NULL;
1020                 }
1021
1022                 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1023                              &regulatory[NVM_CHANNELS_SDP] :
1024                              &nvm_sw[NVM_CHANNELS];
1025
1026                 /* in family 8000 Xtal calibration values moved to OTP */
1027                 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1028                 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1029                 lar_enabled = true;
1030         } else {
1031                 u16 lar_offset = data->nvm_version < 0xE39 ?
1032                                  NVM_LAR_OFFSET_OLD :
1033                                  NVM_LAR_OFFSET;
1034
1035                 lar_config = le16_to_cpup(regulatory + lar_offset);
1036                 data->lar_enabled = !!(lar_config &
1037                                        NVM_LAR_ENABLED);
1038                 lar_enabled = data->lar_enabled;
1039                 ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
1040         }
1041
1042         /* If no valid mac address was found - bail out */
1043         if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1044                 kfree(data);
1045                 return NULL;
1046         }
1047
1048         if (lar_enabled &&
1049             fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1050                 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1051
1052         if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1053                 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1054
1055         iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1056                         sbands_flags, false);
1057         data->calib_version = 255;
1058
1059         return data;
1060 }
1061 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1062
1063 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1064                                        int ch_idx, u16 nvm_flags,
1065                                        u16 cap_flags,
1066                                        const struct iwl_cfg *cfg)
1067 {
1068         u32 flags = NL80211_RRF_NO_HT40;
1069
1070         if (ch_idx < NUM_2GHZ_CHANNELS &&
1071             (nvm_flags & NVM_CHANNEL_40MHZ)) {
1072                 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1073                         flags &= ~NL80211_RRF_NO_HT40PLUS;
1074                 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1075                         flags &= ~NL80211_RRF_NO_HT40MINUS;
1076         } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1077                 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1078                         flags &= ~NL80211_RRF_NO_HT40PLUS;
1079                 else
1080                         flags &= ~NL80211_RRF_NO_HT40MINUS;
1081         }
1082
1083         if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1084                 flags |= NL80211_RRF_NO_80MHZ;
1085         if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1086                 flags |= NL80211_RRF_NO_160MHZ;
1087
1088         if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1089                 flags |= NL80211_RRF_NO_IR;
1090
1091         if (nvm_flags & NVM_CHANNEL_RADAR)
1092                 flags |= NL80211_RRF_DFS;
1093
1094         if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1095                 flags |= NL80211_RRF_NO_OUTDOOR;
1096
1097         /* Set the GO concurrent flag only in case that NO_IR is set.
1098          * Otherwise it is meaningless
1099          */
1100         if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1101             (flags & NL80211_RRF_NO_IR))
1102                 flags |= NL80211_RRF_GO_CONCURRENT;
1103
1104         /*
1105          * cap_flags is per regulatory domain so apply it for every channel
1106          */
1107         if (ch_idx >= NUM_2GHZ_CHANNELS) {
1108                 if (cap_flags & REG_CAPA_40MHZ_FORBIDDEN)
1109                         flags |= NL80211_RRF_NO_HT40;
1110
1111                 if (!(cap_flags & REG_CAPA_80MHZ_ALLOWED))
1112                         flags |= NL80211_RRF_NO_80MHZ;
1113
1114                 if (!(cap_flags & REG_CAPA_160MHZ_ALLOWED))
1115                         flags |= NL80211_RRF_NO_160MHZ;
1116         }
1117
1118         return flags;
1119 }
1120
1121 struct ieee80211_regdomain *
1122 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1123                        int num_of_ch, __le32 *channels, u16 fw_mcc,
1124                        u16 geo_info, u16 cap)
1125 {
1126         int ch_idx;
1127         u16 ch_flags;
1128         u32 reg_rule_flags, prev_reg_rule_flags = 0;
1129         const u16 *nvm_chan;
1130         struct ieee80211_regdomain *regd, *copy_rd;
1131         struct ieee80211_reg_rule *rule;
1132         enum nl80211_band band;
1133         int center_freq, prev_center_freq = 0;
1134         int valid_rules = 0;
1135         bool new_rule;
1136         int max_num_ch;
1137
1138         if (cfg->uhb_supported) {
1139                 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1140                 nvm_chan = iwl_uhb_nvm_channels;
1141         } else if (cfg->nvm_type == IWL_NVM_EXT) {
1142                 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1143                 nvm_chan = iwl_ext_nvm_channels;
1144         } else {
1145                 max_num_ch = IWL_NVM_NUM_CHANNELS;
1146                 nvm_chan = iwl_nvm_channels;
1147         }
1148
1149         if (WARN_ON(num_of_ch > max_num_ch))
1150                 num_of_ch = max_num_ch;
1151
1152         if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1153                 return ERR_PTR(-EINVAL);
1154
1155         IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1156                       num_of_ch);
1157
1158         /* build a regdomain rule for every valid channel */
1159         regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1160         if (!regd)
1161                 return ERR_PTR(-ENOMEM);
1162
1163         /* set alpha2 from FW. */
1164         regd->alpha2[0] = fw_mcc >> 8;
1165         regd->alpha2[1] = fw_mcc & 0xff;
1166
1167         for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1168                 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1169                 band = iwl_nl80211_band_from_channel_idx(ch_idx);
1170                 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1171                                                              band);
1172                 new_rule = false;
1173
1174                 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1175                         iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1176                                                     nvm_chan[ch_idx], ch_flags);
1177                         continue;
1178                 }
1179
1180                 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1181                                                              ch_flags, cap,
1182                                                              cfg);
1183
1184                 /* we can't continue the same rule */
1185                 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1186                     center_freq - prev_center_freq > 20) {
1187                         valid_rules++;
1188                         new_rule = true;
1189                 }
1190
1191                 rule = &regd->reg_rules[valid_rules - 1];
1192
1193                 if (new_rule)
1194                         rule->freq_range.start_freq_khz =
1195                                                 MHZ_TO_KHZ(center_freq - 10);
1196
1197                 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1198
1199                 /* this doesn't matter - not used by FW */
1200                 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1201                 rule->power_rule.max_eirp =
1202                         DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1203
1204                 rule->flags = reg_rule_flags;
1205
1206                 /* rely on auto-calculation to merge BW of contiguous chans */
1207                 rule->flags |= NL80211_RRF_AUTO_BW;
1208                 rule->freq_range.max_bandwidth_khz = 0;
1209
1210                 prev_center_freq = center_freq;
1211                 prev_reg_rule_flags = reg_rule_flags;
1212
1213                 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1214                                             nvm_chan[ch_idx], ch_flags);
1215
1216                 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1217                     band == NL80211_BAND_2GHZ)
1218                         continue;
1219
1220                 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1221         }
1222
1223         regd->n_reg_rules = valid_rules;
1224
1225         /*
1226          * Narrow down regdom for unused regulatory rules to prevent hole
1227          * between reg rules to wmm rules.
1228          */
1229         copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1230                           GFP_KERNEL);
1231         if (!copy_rd)
1232                 copy_rd = ERR_PTR(-ENOMEM);
1233
1234         kfree(regd);
1235         return copy_rd;
1236 }
1237 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1238
1239 #define IWL_MAX_NVM_SECTION_SIZE        0x1b58
1240 #define IWL_MAX_EXT_NVM_SECTION_SIZE    0x1ffc
1241 #define MAX_NVM_FILE_LEN        16384
1242
1243 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1244                     unsigned int len)
1245 {
1246 #define IWL_4165_DEVICE_ID      0x5501
1247 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1248
1249         if (section == NVM_SECTION_TYPE_PHY_SKU &&
1250             hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1251             (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1252                 /* OTP 0x52 bug work around: it's a 1x1 device */
1253                 data[3] = ANT_B | (ANT_B << 4);
1254 }
1255 IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1256
1257 /*
1258  * Reads external NVM from a file into mvm->nvm_sections
1259  *
1260  * HOW TO CREATE THE NVM FILE FORMAT:
1261  * ------------------------------
1262  * 1. create hex file, format:
1263  *      3800 -> header
1264  *      0000 -> header
1265  *      5a40 -> data
1266  *
1267  *   rev - 6 bit (word1)
1268  *   len - 10 bit (word1)
1269  *   id - 4 bit (word2)
1270  *   rsv - 12 bit (word2)
1271  *
1272  * 2. flip 8bits with 8 bits per line to get the right NVM file format
1273  *
1274  * 3. create binary file from the hex file
1275  *
1276  * 4. save as "iNVM_xxx.bin" under /lib/firmware
1277  */
1278 int iwl_read_external_nvm(struct iwl_trans *trans,
1279                           const char *nvm_file_name,
1280                           struct iwl_nvm_section *nvm_sections)
1281 {
1282         int ret, section_size;
1283         u16 section_id;
1284         const struct firmware *fw_entry;
1285         const struct {
1286                 __le16 word1;
1287                 __le16 word2;
1288                 u8 data[];
1289         } *file_sec;
1290         const u8 *eof;
1291         u8 *temp;
1292         int max_section_size;
1293         const __le32 *dword_buff;
1294
1295 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1296 #define NVM_WORD2_ID(x) (x >> 12)
1297 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1298 #define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1299 #define NVM_HEADER_0    (0x2A504C54)
1300 #define NVM_HEADER_1    (0x4E564D2A)
1301 #define NVM_HEADER_SIZE (4 * sizeof(u32))
1302
1303         IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1304
1305         /* Maximal size depends on NVM version */
1306         if (trans->cfg->nvm_type != IWL_NVM_EXT)
1307                 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1308         else
1309                 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1310
1311         /*
1312          * Obtain NVM image via request_firmware. Since we already used
1313          * request_firmware_nowait() for the firmware binary load and only
1314          * get here after that we assume the NVM request can be satisfied
1315          * synchronously.
1316          */
1317         ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1318         if (ret) {
1319                 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1320                         nvm_file_name, ret);
1321                 return ret;
1322         }
1323
1324         IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1325                  nvm_file_name, fw_entry->size);
1326
1327         if (fw_entry->size > MAX_NVM_FILE_LEN) {
1328                 IWL_ERR(trans, "NVM file too large\n");
1329                 ret = -EINVAL;
1330                 goto out;
1331         }
1332
1333         eof = fw_entry->data + fw_entry->size;
1334         dword_buff = (__le32 *)fw_entry->data;
1335
1336         /* some NVM file will contain a header.
1337          * The header is identified by 2 dwords header as follow:
1338          * dword[0] = 0x2A504C54
1339          * dword[1] = 0x4E564D2A
1340          *
1341          * This header must be skipped when providing the NVM data to the FW.
1342          */
1343         if (fw_entry->size > NVM_HEADER_SIZE &&
1344             dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1345             dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1346                 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1347                 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1348                 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1349                          le32_to_cpu(dword_buff[3]));
1350
1351                 /* nvm file validation, dword_buff[2] holds the file version */
1352                 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1353                     CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1354                     le32_to_cpu(dword_buff[2]) < 0xE4A) {
1355                         ret = -EFAULT;
1356                         goto out;
1357                 }
1358         } else {
1359                 file_sec = (void *)fw_entry->data;
1360         }
1361
1362         while (true) {
1363                 if (file_sec->data > eof) {
1364                         IWL_ERR(trans,
1365                                 "ERROR - NVM file too short for section header\n");
1366                         ret = -EINVAL;
1367                         break;
1368                 }
1369
1370                 /* check for EOF marker */
1371                 if (!file_sec->word1 && !file_sec->word2) {
1372                         ret = 0;
1373                         break;
1374                 }
1375
1376                 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1377                         section_size =
1378                                 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1379                         section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1380                 } else {
1381                         section_size = 2 * EXT_NVM_WORD2_LEN(
1382                                                 le16_to_cpu(file_sec->word2));
1383                         section_id = EXT_NVM_WORD1_ID(
1384                                                 le16_to_cpu(file_sec->word1));
1385                 }
1386
1387                 if (section_size > max_section_size) {
1388                         IWL_ERR(trans, "ERROR - section too large (%d)\n",
1389                                 section_size);
1390                         ret = -EINVAL;
1391                         break;
1392                 }
1393
1394                 if (!section_size) {
1395                         IWL_ERR(trans, "ERROR - section empty\n");
1396                         ret = -EINVAL;
1397                         break;
1398                 }
1399
1400                 if (file_sec->data + section_size > eof) {
1401                         IWL_ERR(trans,
1402                                 "ERROR - NVM file too short for section (%d bytes)\n",
1403                                 section_size);
1404                         ret = -EINVAL;
1405                         break;
1406                 }
1407
1408                 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1409                          "Invalid NVM section ID %d\n", section_id)) {
1410                         ret = -EINVAL;
1411                         break;
1412                 }
1413
1414                 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1415                 if (!temp) {
1416                         ret = -ENOMEM;
1417                         break;
1418                 }
1419
1420                 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1421
1422                 kfree(nvm_sections[section_id].data);
1423                 nvm_sections[section_id].data = temp;
1424                 nvm_sections[section_id].length = section_size;
1425
1426                 /* advance to the next section */
1427                 file_sec = (void *)(file_sec->data + section_size);
1428         }
1429 out:
1430         release_firmware(fw_entry);
1431         return ret;
1432 }
1433 IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1434
1435 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1436                                  const struct iwl_fw *fw)
1437 {
1438         struct iwl_nvm_get_info cmd = {};
1439         struct iwl_nvm_data *nvm;
1440         struct iwl_host_cmd hcmd = {
1441                 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1442                 .data = { &cmd, },
1443                 .len = { sizeof(cmd) },
1444                 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1445         };
1446         int  ret;
1447         bool empty_otp;
1448         u32 mac_flags;
1449         u32 sbands_flags = 0;
1450         /*
1451          * All the values in iwl_nvm_get_info_rsp v4 are the same as
1452          * in v3, except for the channel profile part of the
1453          * regulatory.  So we can just access the new struct, with the
1454          * exception of the latter.
1455          */
1456         struct iwl_nvm_get_info_rsp *rsp;
1457         struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
1458         bool v4 = fw_has_api(&fw->ucode_capa,
1459                              IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
1460         size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
1461         void *channel_profile;
1462
1463         ret = iwl_trans_send_cmd(trans, &hcmd);
1464         if (ret)
1465                 return ERR_PTR(ret);
1466
1467         if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
1468                  "Invalid payload len in NVM response from FW %d",
1469                  iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1470                 ret = -EINVAL;
1471                 goto out;
1472         }
1473
1474         rsp = (void *)hcmd.resp_pkt->data;
1475         empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1476                        NVM_GENERAL_FLAGS_EMPTY_OTP);
1477         if (empty_otp)
1478                 IWL_INFO(trans, "OTP is empty\n");
1479
1480         nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1481         if (!nvm) {
1482                 ret = -ENOMEM;
1483                 goto out;
1484         }
1485
1486         iwl_set_hw_address_from_csr(trans, nvm);
1487         /* TODO: if platform NVM has MAC address - override it here */
1488
1489         if (!is_valid_ether_addr(nvm->hw_addr)) {
1490                 IWL_ERR(trans, "no valid mac address was found\n");
1491                 ret = -EINVAL;
1492                 goto err_free;
1493         }
1494
1495         IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1496
1497         /* Initialize general data */
1498         nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1499         nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1500         if (nvm->n_hw_addrs == 0)
1501                 IWL_WARN(trans,
1502                          "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1503                          empty_otp);
1504
1505         /* Initialize MAC sku data */
1506         mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1507         nvm->sku_cap_11ac_enable =
1508                 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1509         nvm->sku_cap_11n_enable =
1510                 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1511         nvm->sku_cap_11ax_enable =
1512                 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1513         nvm->sku_cap_band_24ghz_enable =
1514                 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1515         nvm->sku_cap_band_52ghz_enable =
1516                 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1517         nvm->sku_cap_mimo_disabled =
1518                 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1519
1520         /* Initialize PHY sku data */
1521         nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1522         nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1523
1524         if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
1525             fw_has_capa(&fw->ucode_capa,
1526                         IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
1527                 nvm->lar_enabled = true;
1528                 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1529         }
1530
1531         rsp_v3 = (void *)rsp;
1532         channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
1533                           (void *)rsp_v3->regulatory.channel_profile;
1534
1535         iwl_init_sbands(trans, nvm,
1536                         channel_profile,
1537                         nvm->valid_tx_ant & fw->valid_tx_ant,
1538                         nvm->valid_rx_ant & fw->valid_rx_ant,
1539                         sbands_flags, v4);
1540
1541         iwl_free_resp(&hcmd);
1542         return nvm;
1543
1544 err_free:
1545         kfree(nvm);
1546 out:
1547         iwl_free_resp(&hcmd);
1548         return ERR_PTR(ret);
1549 }
1550 IWL_EXPORT_SYMBOL(iwl_get_nvm);