3bcbc2967c886b76dd9f7b38cb58fb63fc47f51d
[muen/linux.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
1 /******************************************************************************
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
10  * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of version 2 of the GNU General Public License as
14  * published by the Free Software Foundation.
15  *
16  * This program is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19  * General Public License for more details.
20  *
21  * The full GNU General Public License is included in this distribution
22  * in the file called COPYING.
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25  *  Intel Linux Wireless <linuxwifi@intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  * BSD LICENSE
29  *
30  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
32  * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
33  * All rights reserved.
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36  * modification, are permitted provided that the following conditions
37  * are met:
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40  *    notice, this list of conditions and the following disclaimer.
41  *  * Redistributions in binary form must reproduce the above copyright
42  *    notice, this list of conditions and the following disclaimer in
43  *    the documentation and/or other materials provided with the
44  *    distribution.
45  *  * Neither the name Intel Corporation nor the names of its
46  *    contributors may be used to endorse or promote products derived
47  *    from this software without specific prior written permission.
48  *
49  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60  *
61  *****************************************************************************/
62 #include <linux/pci.h>
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/sched.h>
66 #include <linux/bitops.h>
67 #include <linux/gfp.h>
68 #include <linux/vmalloc.h>
69 #include <linux/module.h>
70 #include <linux/wait.h>
71 #include <linux/seq_file.h>
72
73 #include "iwl-drv.h"
74 #include "iwl-trans.h"
75 #include "iwl-csr.h"
76 #include "iwl-prph.h"
77 #include "iwl-scd.h"
78 #include "iwl-agn-hw.h"
79 #include "fw/error-dump.h"
80 #include "fw/dbg.h"
81 #include "fw/api/tx.h"
82 #include "internal.h"
83 #include "iwl-fh.h"
84
85 /* extended range in FW SRAM */
86 #define IWL_FW_MEM_EXTENDED_START       0x40000
87 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
88
89 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
90 {
91 #define PCI_DUMP_SIZE           352
92 #define PCI_MEM_DUMP_SIZE       64
93 #define PCI_PARENT_DUMP_SIZE    524
94 #define PREFIX_LEN              32
95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
96         struct pci_dev *pdev = trans_pcie->pci_dev;
97         u32 i, pos, alloc_size, *ptr, *buf;
98         char *prefix;
99
100         if (trans_pcie->pcie_dbg_dumped_once)
101                 return;
102
103         /* Should be a multiple of 4 */
104         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
105         BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
106         BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
107
108         /* Alloc a max size buffer */
109         alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
110         alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
111         alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
112         alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
113
114         buf = kmalloc(alloc_size, GFP_ATOMIC);
115         if (!buf)
116                 return;
117         prefix = (char *)buf + alloc_size - PREFIX_LEN;
118
119         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
120
121         /* Print wifi device registers */
122         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
123         IWL_ERR(trans, "iwlwifi device config registers:\n");
124         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
125                 if (pci_read_config_dword(pdev, i, ptr))
126                         goto err_read;
127         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
128
129         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
130         for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
131                 *ptr = iwl_read32(trans, i);
132         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
133
134         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
135         if (pos) {
136                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
137                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
138                         if (pci_read_config_dword(pdev, pos + i, ptr))
139                                 goto err_read;
140                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
141                                32, 4, buf, i, 0);
142         }
143
144         /* Print parent device registers next */
145         if (!pdev->bus->self)
146                 goto out;
147
148         pdev = pdev->bus->self;
149         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
150
151         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
152                 pci_name(pdev));
153         for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
154                 if (pci_read_config_dword(pdev, i, ptr))
155                         goto err_read;
156         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
157
158         /* Print root port AER registers */
159         pos = 0;
160         pdev = pcie_find_root_port(pdev);
161         if (pdev)
162                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
163         if (pos) {
164                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
165                         pci_name(pdev));
166                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
167                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
168                         if (pci_read_config_dword(pdev, pos + i, ptr))
169                                 goto err_read;
170                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
171                                4, buf, i, 0);
172         }
173         goto out;
174
175 err_read:
176         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
177         IWL_ERR(trans, "Read failed at 0x%X\n", i);
178 out:
179         trans_pcie->pcie_dbg_dumped_once = 1;
180         kfree(buf);
181 }
182
183 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
184 {
185         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
186         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
187         usleep_range(5000, 6000);
188 }
189
190 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
191 {
192         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
193
194         if (!fw_mon->size)
195                 return;
196
197         dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
198                           fw_mon->physical);
199
200         fw_mon->block = NULL;
201         fw_mon->physical = 0;
202         fw_mon->size = 0;
203 }
204
205 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
206                                             u8 max_power, u8 min_power)
207 {
208         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
209         void *block = NULL;
210         dma_addr_t physical = 0;
211         u32 size = 0;
212         u8 power;
213
214         if (fw_mon->size)
215                 return;
216
217         for (power = max_power; power >= min_power; power--) {
218                 size = BIT(power);
219                 block = dma_alloc_coherent(trans->dev, size, &physical,
220                                            GFP_KERNEL | __GFP_NOWARN);
221                 if (!block)
222                         continue;
223
224                 IWL_INFO(trans,
225                          "Allocated 0x%08x bytes for firmware monitor.\n",
226                          size);
227                 break;
228         }
229
230         if (WARN_ON_ONCE(!block))
231                 return;
232
233         if (power != max_power)
234                 IWL_ERR(trans,
235                         "Sorry - debug buffer is only %luK while you requested %luK\n",
236                         (unsigned long)BIT(power - 10),
237                         (unsigned long)BIT(max_power - 10));
238
239         fw_mon->block = block;
240         fw_mon->physical = physical;
241         fw_mon->size = size;
242 }
243
244 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
245 {
246         if (!max_power) {
247                 /* default max_power is maximum */
248                 max_power = 26;
249         } else {
250                 max_power += 11;
251         }
252
253         if (WARN(max_power > 26,
254                  "External buffer size for monitor is too big %d, check the FW TLV\n",
255                  max_power))
256                 return;
257
258         if (trans->dbg.fw_mon.size)
259                 return;
260
261         iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
262 }
263
264 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
265 {
266         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
267                     ((reg & 0x0000ffff) | (2 << 28)));
268         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
269 }
270
271 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
272 {
273         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
274         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
275                     ((reg & 0x0000ffff) | (3 << 28)));
276 }
277
278 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
279 {
280         if (trans->cfg->apmg_not_supported)
281                 return;
282
283         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
284                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
285                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
286                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
287         else
288                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
289                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
290                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
291 }
292
293 /* PCI registers */
294 #define PCI_CFG_RETRY_TIMEOUT   0x041
295
296 void iwl_pcie_apm_config(struct iwl_trans *trans)
297 {
298         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
299         u16 lctl;
300         u16 cap;
301
302         /*
303          * L0S states have been found to be unstable with our devices
304          * and in newer hardware they are not officially supported at
305          * all, so we must always set the L0S_DISABLED bit.
306          */
307         iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
308
309         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
310         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
311
312         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
313         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
314         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
315                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
316                         trans->ltr_enabled ? "En" : "Dis");
317 }
318
319 /*
320  * Start up NIC's basic functionality after it has been reset
321  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
322  * NOTE:  This does not load uCode nor start the embedded processor
323  */
324 static int iwl_pcie_apm_init(struct iwl_trans *trans)
325 {
326         int ret;
327
328         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
329
330         /*
331          * Use "set_bit" below rather than "write", to preserve any hardware
332          * bits already set by default after reset.
333          */
334
335         /* Disable L0S exit timer (platform NMI Work/Around) */
336         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
337                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
338                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
339
340         /*
341          * Disable L0s without affecting L1;
342          *  don't wait for ICH L0s (ICH bug W/A)
343          */
344         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
345                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
346
347         /* Set FH wait threshold to maximum (HW error during stress W/A) */
348         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
349
350         /*
351          * Enable HAP INTA (interrupt from management bus) to
352          * wake device's PCI Express link L1a -> L0s
353          */
354         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
355                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
356
357         iwl_pcie_apm_config(trans);
358
359         /* Configure analog phase-lock-loop before activating to D0A */
360         if (trans->trans_cfg->base_params->pll_cfg)
361                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
362
363         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
364         if (ret)
365                 return ret;
366
367         if (trans->cfg->host_interrupt_operation_mode) {
368                 /*
369                  * This is a bit of an abuse - This is needed for 7260 / 3160
370                  * only check host_interrupt_operation_mode even if this is
371                  * not related to host_interrupt_operation_mode.
372                  *
373                  * Enable the oscillator to count wake up time for L1 exit. This
374                  * consumes slightly more power (100uA) - but allows to be sure
375                  * that we wake up from L1 on time.
376                  *
377                  * This looks weird: read twice the same register, discard the
378                  * value, set a bit, and yet again, read that same register
379                  * just to discard the value. But that's the way the hardware
380                  * seems to like it.
381                  */
382                 iwl_read_prph(trans, OSC_CLK);
383                 iwl_read_prph(trans, OSC_CLK);
384                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
385                 iwl_read_prph(trans, OSC_CLK);
386                 iwl_read_prph(trans, OSC_CLK);
387         }
388
389         /*
390          * Enable DMA clock and wait for it to stabilize.
391          *
392          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
393          * bits do not disable clocks.  This preserves any hardware
394          * bits already set by default in "CLK_CTRL_REG" after reset.
395          */
396         if (!trans->cfg->apmg_not_supported) {
397                 iwl_write_prph(trans, APMG_CLK_EN_REG,
398                                APMG_CLK_VAL_DMA_CLK_RQT);
399                 udelay(20);
400
401                 /* Disable L1-Active */
402                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
403                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
404
405                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
406                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
407                                APMG_RTC_INT_STT_RFKILL);
408         }
409
410         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
411
412         return 0;
413 }
414
415 /*
416  * Enable LP XTAL to avoid HW bug where device may consume much power if
417  * FW is not loaded after device reset. LP XTAL is disabled by default
418  * after device HW reset. Do it only if XTAL is fed by internal source.
419  * Configure device's "persistence" mode to avoid resetting XTAL again when
420  * SHRD_HW_RST occurs in S3.
421  */
422 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
423 {
424         int ret;
425         u32 apmg_gp1_reg;
426         u32 apmg_xtal_cfg_reg;
427         u32 dl_cfg_reg;
428
429         /* Force XTAL ON */
430         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
431                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
432
433         iwl_trans_pcie_sw_reset(trans);
434
435         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
436         if (WARN_ON(ret)) {
437                 /* Release XTAL ON request */
438                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
439                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
440                 return;
441         }
442
443         /*
444          * Clear "disable persistence" to avoid LP XTAL resetting when
445          * SHRD_HW_RST is applied in S3.
446          */
447         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
448                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
449
450         /*
451          * Force APMG XTAL to be active to prevent its disabling by HW
452          * caused by APMG idle state.
453          */
454         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
455                                                     SHR_APMG_XTAL_CFG_REG);
456         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
457                                  apmg_xtal_cfg_reg |
458                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
459
460         iwl_trans_pcie_sw_reset(trans);
461
462         /* Enable LP XTAL by indirect access through CSR */
463         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
464         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
465                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
466                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
467
468         /* Clear delay line clock power up */
469         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
470         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
471                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
472
473         /*
474          * Enable persistence mode to avoid LP XTAL resetting when
475          * SHRD_HW_RST is applied in S3.
476          */
477         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
478                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
479
480         /*
481          * Clear "initialization complete" bit to move adapter from
482          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
483          */
484         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
485
486         /* Activates XTAL resources monitor */
487         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
488                                  CSR_MONITOR_XTAL_RESOURCES);
489
490         /* Release XTAL ON request */
491         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
492                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
493         udelay(10);
494
495         /* Release APMG XTAL */
496         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
497                                  apmg_xtal_cfg_reg &
498                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
499 }
500
501 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
502 {
503         int ret;
504
505         /* stop device's busmaster DMA activity */
506         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
507
508         ret = iwl_poll_bit(trans, CSR_RESET,
509                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
510                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
511         if (ret < 0)
512                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
513
514         IWL_DEBUG_INFO(trans, "stop master\n");
515 }
516
517 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
518 {
519         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
520
521         if (op_mode_leave) {
522                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
523                         iwl_pcie_apm_init(trans);
524
525                 /* inform ME that we are leaving */
526                 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
527                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
528                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
529                 else if (trans->trans_cfg->device_family >=
530                          IWL_DEVICE_FAMILY_8000) {
531                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
532                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
533                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
534                                     CSR_HW_IF_CONFIG_REG_PREPARE |
535                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
536                         mdelay(1);
537                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
538                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
539                 }
540                 mdelay(5);
541         }
542
543         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
544
545         /* Stop device's DMA activity */
546         iwl_pcie_apm_stop_master(trans);
547
548         if (trans->cfg->lp_xtal_workaround) {
549                 iwl_pcie_apm_lp_xtal_enable(trans);
550                 return;
551         }
552
553         iwl_trans_pcie_sw_reset(trans);
554
555         /*
556          * Clear "initialization complete" bit to move adapter from
557          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
558          */
559         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
560 }
561
562 static int iwl_pcie_nic_init(struct iwl_trans *trans)
563 {
564         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
565         int ret;
566
567         /* nic_init */
568         spin_lock(&trans_pcie->irq_lock);
569         ret = iwl_pcie_apm_init(trans);
570         spin_unlock(&trans_pcie->irq_lock);
571
572         if (ret)
573                 return ret;
574
575         iwl_pcie_set_pwr(trans, false);
576
577         iwl_op_mode_nic_config(trans->op_mode);
578
579         /* Allocate the RX queue, or reset if it is already allocated */
580         iwl_pcie_rx_init(trans);
581
582         /* Allocate or reset and init all Tx and Command queues */
583         if (iwl_pcie_tx_init(trans))
584                 return -ENOMEM;
585
586         if (trans->trans_cfg->base_params->shadow_reg_enable) {
587                 /* enable shadow regs in HW */
588                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
589                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
590         }
591
592         return 0;
593 }
594
595 #define HW_READY_TIMEOUT (50)
596
597 /* Note: returns poll_bit return value, which is >= 0 if success */
598 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
599 {
600         int ret;
601
602         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
603                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
604
605         /* See if we got it */
606         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
607                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
608                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
609                            HW_READY_TIMEOUT);
610
611         if (ret >= 0)
612                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
613
614         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
615         return ret;
616 }
617
618 /* Note: returns standard 0/-ERROR code */
619 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
620 {
621         int ret;
622         int t = 0;
623         int iter;
624
625         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
626
627         ret = iwl_pcie_set_hw_ready(trans);
628         /* If the card is ready, exit 0 */
629         if (ret >= 0)
630                 return 0;
631
632         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
633                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
634         usleep_range(1000, 2000);
635
636         for (iter = 0; iter < 10; iter++) {
637                 /* If HW is not ready, prepare the conditions to check again */
638                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
639                             CSR_HW_IF_CONFIG_REG_PREPARE);
640
641                 do {
642                         ret = iwl_pcie_set_hw_ready(trans);
643                         if (ret >= 0)
644                                 return 0;
645
646                         usleep_range(200, 1000);
647                         t += 200;
648                 } while (t < 150000);
649                 msleep(25);
650         }
651
652         IWL_ERR(trans, "Couldn't prepare the card\n");
653
654         return ret;
655 }
656
657 /*
658  * ucode
659  */
660 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
661                                             u32 dst_addr, dma_addr_t phy_addr,
662                                             u32 byte_cnt)
663 {
664         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
665                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
666
667         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
668                     dst_addr);
669
670         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
671                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
672
673         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
674                     (iwl_get_dma_hi_addr(phy_addr)
675                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
676
677         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
678                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
679                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
680                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
681
682         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
683                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
684                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
685                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
686 }
687
688 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
689                                         u32 dst_addr, dma_addr_t phy_addr,
690                                         u32 byte_cnt)
691 {
692         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
693         unsigned long flags;
694         int ret;
695
696         trans_pcie->ucode_write_complete = false;
697
698         if (!iwl_trans_grab_nic_access(trans, &flags))
699                 return -EIO;
700
701         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
702                                         byte_cnt);
703         iwl_trans_release_nic_access(trans, &flags);
704
705         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
706                                  trans_pcie->ucode_write_complete, 5 * HZ);
707         if (!ret) {
708                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
709                 iwl_trans_pcie_dump_regs(trans);
710                 return -ETIMEDOUT;
711         }
712
713         return 0;
714 }
715
716 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
717                             const struct fw_desc *section)
718 {
719         u8 *v_addr;
720         dma_addr_t p_addr;
721         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
722         int ret = 0;
723
724         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
725                      section_num);
726
727         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
728                                     GFP_KERNEL | __GFP_NOWARN);
729         if (!v_addr) {
730                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
731                 chunk_sz = PAGE_SIZE;
732                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
733                                             &p_addr, GFP_KERNEL);
734                 if (!v_addr)
735                         return -ENOMEM;
736         }
737
738         for (offset = 0; offset < section->len; offset += chunk_sz) {
739                 u32 copy_size, dst_addr;
740                 bool extended_addr = false;
741
742                 copy_size = min_t(u32, chunk_sz, section->len - offset);
743                 dst_addr = section->offset + offset;
744
745                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
746                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
747                         extended_addr = true;
748
749                 if (extended_addr)
750                         iwl_set_bits_prph(trans, LMPM_CHICK,
751                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
752
753                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
754                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
755                                                    copy_size);
756
757                 if (extended_addr)
758                         iwl_clear_bits_prph(trans, LMPM_CHICK,
759                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
760
761                 if (ret) {
762                         IWL_ERR(trans,
763                                 "Could not load the [%d] uCode section\n",
764                                 section_num);
765                         break;
766                 }
767         }
768
769         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
770         return ret;
771 }
772
773 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
774                                            const struct fw_img *image,
775                                            int cpu,
776                                            int *first_ucode_section)
777 {
778         int shift_param;
779         int i, ret = 0, sec_num = 0x1;
780         u32 val, last_read_idx = 0;
781
782         if (cpu == 1) {
783                 shift_param = 0;
784                 *first_ucode_section = 0;
785         } else {
786                 shift_param = 16;
787                 (*first_ucode_section)++;
788         }
789
790         for (i = *first_ucode_section; i < image->num_sec; i++) {
791                 last_read_idx = i;
792
793                 /*
794                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
795                  * CPU1 to CPU2.
796                  * PAGING_SEPARATOR_SECTION delimiter - separate between
797                  * CPU2 non paged to CPU2 paging sec.
798                  */
799                 if (!image->sec[i].data ||
800                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
801                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
802                         IWL_DEBUG_FW(trans,
803                                      "Break since Data not valid or Empty section, sec = %d\n",
804                                      i);
805                         break;
806                 }
807
808                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
809                 if (ret)
810                         return ret;
811
812                 /* Notify ucode of loaded section number and status */
813                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
814                 val = val | (sec_num << shift_param);
815                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
816
817                 sec_num = (sec_num << 1) | 0x1;
818         }
819
820         *first_ucode_section = last_read_idx;
821
822         iwl_enable_interrupts(trans);
823
824         if (trans->trans_cfg->use_tfh) {
825                 if (cpu == 1)
826                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
827                                        0xFFFF);
828                 else
829                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
830                                        0xFFFFFFFF);
831         } else {
832                 if (cpu == 1)
833                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
834                                            0xFFFF);
835                 else
836                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
837                                            0xFFFFFFFF);
838         }
839
840         return 0;
841 }
842
843 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
844                                       const struct fw_img *image,
845                                       int cpu,
846                                       int *first_ucode_section)
847 {
848         int i, ret = 0;
849         u32 last_read_idx = 0;
850
851         if (cpu == 1)
852                 *first_ucode_section = 0;
853         else
854                 (*first_ucode_section)++;
855
856         for (i = *first_ucode_section; i < image->num_sec; i++) {
857                 last_read_idx = i;
858
859                 /*
860                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
861                  * CPU1 to CPU2.
862                  * PAGING_SEPARATOR_SECTION delimiter - separate between
863                  * CPU2 non paged to CPU2 paging sec.
864                  */
865                 if (!image->sec[i].data ||
866                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
867                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
868                         IWL_DEBUG_FW(trans,
869                                      "Break since Data not valid or Empty section, sec = %d\n",
870                                      i);
871                         break;
872                 }
873
874                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
875                 if (ret)
876                         return ret;
877         }
878
879         *first_ucode_section = last_read_idx;
880
881         return 0;
882 }
883
884 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
885 {
886         enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
887         struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
888                 &trans->dbg.fw_mon_cfg[alloc_id];
889         struct iwl_dram_data *frag;
890
891         if (!iwl_trans_dbg_ini_valid(trans))
892                 return;
893
894         if (le32_to_cpu(fw_mon_cfg->buf_location) ==
895             IWL_FW_INI_LOCATION_SRAM_PATH) {
896                 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
897                 /* set sram monitor by enabling bit 7 */
898                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
899                             CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
900
901                 return;
902         }
903
904         if (le32_to_cpu(fw_mon_cfg->buf_location) !=
905             IWL_FW_INI_LOCATION_DRAM_PATH ||
906             !trans->dbg.fw_mon_ini[alloc_id].num_frags)
907                 return;
908
909         frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
910
911         IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
912                      alloc_id);
913
914         iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
915                             frag->physical >> MON_BUFF_SHIFT_VER2);
916         iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
917                             (frag->physical + frag->size - 256) >>
918                             MON_BUFF_SHIFT_VER2);
919 }
920
921 void iwl_pcie_apply_destination(struct iwl_trans *trans)
922 {
923         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
924         const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
925         int i;
926
927         if (iwl_trans_dbg_ini_valid(trans)) {
928                 iwl_pcie_apply_destination_ini(trans);
929                 return;
930         }
931
932         IWL_INFO(trans, "Applying debug destination %s\n",
933                  get_fw_dbg_mode_string(dest->monitor_mode));
934
935         if (dest->monitor_mode == EXTERNAL_MODE)
936                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
937         else
938                 IWL_WARN(trans, "PCI should have external buffer debug\n");
939
940         for (i = 0; i < trans->dbg.n_dest_reg; i++) {
941                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
942                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
943
944                 switch (dest->reg_ops[i].op) {
945                 case CSR_ASSIGN:
946                         iwl_write32(trans, addr, val);
947                         break;
948                 case CSR_SETBIT:
949                         iwl_set_bit(trans, addr, BIT(val));
950                         break;
951                 case CSR_CLEARBIT:
952                         iwl_clear_bit(trans, addr, BIT(val));
953                         break;
954                 case PRPH_ASSIGN:
955                         iwl_write_prph(trans, addr, val);
956                         break;
957                 case PRPH_SETBIT:
958                         iwl_set_bits_prph(trans, addr, BIT(val));
959                         break;
960                 case PRPH_CLEARBIT:
961                         iwl_clear_bits_prph(trans, addr, BIT(val));
962                         break;
963                 case PRPH_BLOCKBIT:
964                         if (iwl_read_prph(trans, addr) & BIT(val)) {
965                                 IWL_ERR(trans,
966                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
967                                         val, addr);
968                                 goto monitor;
969                         }
970                         break;
971                 default:
972                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
973                                 dest->reg_ops[i].op);
974                         break;
975                 }
976         }
977
978 monitor:
979         if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
980                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
981                                fw_mon->physical >> dest->base_shift);
982                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
983                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
984                                        (fw_mon->physical + fw_mon->size -
985                                         256) >> dest->end_shift);
986                 else
987                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
988                                        (fw_mon->physical + fw_mon->size) >>
989                                        dest->end_shift);
990         }
991 }
992
993 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
994                                 const struct fw_img *image)
995 {
996         int ret = 0;
997         int first_ucode_section;
998
999         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1000                      image->is_dual_cpus ? "Dual" : "Single");
1001
1002         /* load to FW the binary non secured sections of CPU1 */
1003         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1004         if (ret)
1005                 return ret;
1006
1007         if (image->is_dual_cpus) {
1008                 /* set CPU2 header address */
1009                 iwl_write_prph(trans,
1010                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1011                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1012
1013                 /* load to FW the binary sections of CPU2 */
1014                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1015                                                  &first_ucode_section);
1016                 if (ret)
1017                         return ret;
1018         }
1019
1020         if (iwl_pcie_dbg_on(trans))
1021                 iwl_pcie_apply_destination(trans);
1022
1023         iwl_enable_interrupts(trans);
1024
1025         /* release CPU reset */
1026         iwl_write32(trans, CSR_RESET, 0);
1027
1028         return 0;
1029 }
1030
1031 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1032                                           const struct fw_img *image)
1033 {
1034         int ret = 0;
1035         int first_ucode_section;
1036
1037         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1038                      image->is_dual_cpus ? "Dual" : "Single");
1039
1040         if (iwl_pcie_dbg_on(trans))
1041                 iwl_pcie_apply_destination(trans);
1042
1043         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1044                         iwl_read_prph(trans, WFPM_GP2));
1045
1046         /*
1047          * Set default value. On resume reading the values that were
1048          * zeored can provide debug data on the resume flow.
1049          * This is for debugging only and has no functional impact.
1050          */
1051         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1052
1053         /* configure the ucode to be ready to get the secured image */
1054         /* release CPU reset */
1055         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1056
1057         /* load to FW the binary Secured sections of CPU1 */
1058         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1059                                               &first_ucode_section);
1060         if (ret)
1061                 return ret;
1062
1063         /* load to FW the binary sections of CPU2 */
1064         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1065                                                &first_ucode_section);
1066 }
1067
1068 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1069 {
1070         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1071         bool hw_rfkill = iwl_is_rfkill_set(trans);
1072         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1073         bool report;
1074
1075         if (hw_rfkill) {
1076                 set_bit(STATUS_RFKILL_HW, &trans->status);
1077                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1078         } else {
1079                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1080                 if (trans_pcie->opmode_down)
1081                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1082         }
1083
1084         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1085
1086         if (prev != report)
1087                 iwl_trans_pcie_rf_kill(trans, report);
1088
1089         return hw_rfkill;
1090 }
1091
1092 struct iwl_causes_list {
1093         u32 cause_num;
1094         u32 mask_reg;
1095         u8 addr;
1096 };
1097
1098 static struct iwl_causes_list causes_list[] = {
1099         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1100         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1101         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1102         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1103         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1104         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1105         {MSIX_HW_INT_CAUSES_REG_IML,            CSR_MSIX_HW_INT_MASK_AD, 0x12},
1106         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1107         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1108         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1109         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1110         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1111         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1112         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1113         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1114 };
1115
1116 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1117 {
1118         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1119         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1120         int i, arr_size = ARRAY_SIZE(causes_list);
1121         struct iwl_causes_list *causes = causes_list;
1122
1123         /*
1124          * Access all non RX causes and map them to the default irq.
1125          * In case we are missing at least one interrupt vector,
1126          * the first interrupt vector will serve non-RX and FBQ causes.
1127          */
1128         for (i = 0; i < arr_size; i++) {
1129                 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1130                 iwl_clear_bit(trans, causes[i].mask_reg,
1131                               causes[i].cause_num);
1132         }
1133 }
1134
1135 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1136 {
1137         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1138         u32 offset =
1139                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1140         u32 val, idx;
1141
1142         /*
1143          * The first RX queue - fallback queue, which is designated for
1144          * management frame, command responses etc, is always mapped to the
1145          * first interrupt vector. The other RX queues are mapped to
1146          * the other (N - 2) interrupt vectors.
1147          */
1148         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1149         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1150                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1151                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1152                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1153         }
1154         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1155
1156         val = MSIX_FH_INT_CAUSES_Q(0);
1157         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1158                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1159         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1160
1161         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1162                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1163 }
1164
1165 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1166 {
1167         struct iwl_trans *trans = trans_pcie->trans;
1168
1169         if (!trans_pcie->msix_enabled) {
1170                 if (trans->trans_cfg->mq_rx_supported &&
1171                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1172                         iwl_write_umac_prph(trans, UREG_CHICK,
1173                                             UREG_CHICK_MSI_ENABLE);
1174                 return;
1175         }
1176         /*
1177          * The IVAR table needs to be configured again after reset,
1178          * but if the device is disabled, we can't write to
1179          * prph.
1180          */
1181         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1182                 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1183
1184         /*
1185          * Each cause from the causes list above and the RX causes is
1186          * represented as a byte in the IVAR table. The first nibble
1187          * represents the bound interrupt vector of the cause, the second
1188          * represents no auto clear for this cause. This will be set if its
1189          * interrupt vector is bound to serve other causes.
1190          */
1191         iwl_pcie_map_rx_causes(trans);
1192
1193         iwl_pcie_map_non_rx_causes(trans);
1194 }
1195
1196 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1197 {
1198         struct iwl_trans *trans = trans_pcie->trans;
1199
1200         iwl_pcie_conf_msix_hw(trans_pcie);
1201
1202         if (!trans_pcie->msix_enabled)
1203                 return;
1204
1205         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1206         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1207         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1208         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1209 }
1210
1211 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1212 {
1213         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1214
1215         lockdep_assert_held(&trans_pcie->mutex);
1216
1217         if (trans_pcie->is_down)
1218                 return;
1219
1220         trans_pcie->is_down = true;
1221
1222         /* tell the device to stop sending interrupts */
1223         iwl_disable_interrupts(trans);
1224
1225         /* device going down, Stop using ICT table */
1226         iwl_pcie_disable_ict(trans);
1227
1228         /*
1229          * If a HW restart happens during firmware loading,
1230          * then the firmware loading might call this function
1231          * and later it might be called again due to the
1232          * restart. So don't process again if the device is
1233          * already dead.
1234          */
1235         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1236                 IWL_DEBUG_INFO(trans,
1237                                "DEVICE_ENABLED bit was set and is now cleared\n");
1238                 iwl_pcie_tx_stop(trans);
1239                 iwl_pcie_rx_stop(trans);
1240
1241                 /* Power-down device's busmaster DMA clocks */
1242                 if (!trans->cfg->apmg_not_supported) {
1243                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1244                                        APMG_CLK_VAL_DMA_CLK_RQT);
1245                         udelay(5);
1246                 }
1247         }
1248
1249         /* Make sure (redundant) we've released our request to stay awake */
1250         iwl_clear_bit(trans, CSR_GP_CNTRL,
1251                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1252
1253         /* Stop the device, and put it in low power state */
1254         iwl_pcie_apm_stop(trans, false);
1255
1256         iwl_trans_pcie_sw_reset(trans);
1257
1258         /*
1259          * Upon stop, the IVAR table gets erased, so msi-x won't
1260          * work. This causes a bug in RF-KILL flows, since the interrupt
1261          * that enables radio won't fire on the correct irq, and the
1262          * driver won't be able to handle the interrupt.
1263          * Configure the IVAR table again after reset.
1264          */
1265         iwl_pcie_conf_msix_hw(trans_pcie);
1266
1267         /*
1268          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1269          * This is a bug in certain verions of the hardware.
1270          * Certain devices also keep sending HW RF kill interrupt all
1271          * the time, unless the interrupt is ACKed even if the interrupt
1272          * should be masked. Re-ACK all the interrupts here.
1273          */
1274         iwl_disable_interrupts(trans);
1275
1276         /* clear all status bits */
1277         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1278         clear_bit(STATUS_INT_ENABLED, &trans->status);
1279         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1280
1281         /*
1282          * Even if we stop the HW, we still want the RF kill
1283          * interrupt
1284          */
1285         iwl_enable_rfkill_int(trans);
1286
1287         /* re-take ownership to prevent other users from stealing the device */
1288         iwl_pcie_prepare_card_hw(trans);
1289 }
1290
1291 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1292 {
1293         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1294
1295         if (trans_pcie->msix_enabled) {
1296                 int i;
1297
1298                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1299                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1300         } else {
1301                 synchronize_irq(trans_pcie->pci_dev->irq);
1302         }
1303 }
1304
1305 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1306                                    const struct fw_img *fw, bool run_in_rfkill)
1307 {
1308         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1309         bool hw_rfkill;
1310         int ret;
1311
1312         /* This may fail if AMT took ownership of the device */
1313         if (iwl_pcie_prepare_card_hw(trans)) {
1314                 IWL_WARN(trans, "Exit HW not ready\n");
1315                 ret = -EIO;
1316                 goto out;
1317         }
1318
1319         iwl_enable_rfkill_int(trans);
1320
1321         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1322
1323         /*
1324          * We enabled the RF-Kill interrupt and the handler may very
1325          * well be running. Disable the interrupts to make sure no other
1326          * interrupt can be fired.
1327          */
1328         iwl_disable_interrupts(trans);
1329
1330         /* Make sure it finished running */
1331         iwl_pcie_synchronize_irqs(trans);
1332
1333         mutex_lock(&trans_pcie->mutex);
1334
1335         /* If platform's RF_KILL switch is NOT set to KILL */
1336         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1337         if (hw_rfkill && !run_in_rfkill) {
1338                 ret = -ERFKILL;
1339                 goto out;
1340         }
1341
1342         /* Someone called stop_device, don't try to start_fw */
1343         if (trans_pcie->is_down) {
1344                 IWL_WARN(trans,
1345                          "Can't start_fw since the HW hasn't been started\n");
1346                 ret = -EIO;
1347                 goto out;
1348         }
1349
1350         /* make sure rfkill handshake bits are cleared */
1351         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1352         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1353                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1354
1355         /* clear (again), then enable host interrupts */
1356         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1357
1358         ret = iwl_pcie_nic_init(trans);
1359         if (ret) {
1360                 IWL_ERR(trans, "Unable to init nic\n");
1361                 goto out;
1362         }
1363
1364         /*
1365          * Now, we load the firmware and don't want to be interrupted, even
1366          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1367          * FH_TX interrupt which is needed to load the firmware). If the
1368          * RF-Kill switch is toggled, we will find out after having loaded
1369          * the firmware and return the proper value to the caller.
1370          */
1371         iwl_enable_fw_load_int(trans);
1372
1373         /* really make sure rfkill handshake bits are cleared */
1374         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1375         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1376
1377         /* Load the given image to the HW */
1378         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1379                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1380         else
1381                 ret = iwl_pcie_load_given_ucode(trans, fw);
1382
1383         /* re-check RF-Kill state since we may have missed the interrupt */
1384         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1385         if (hw_rfkill && !run_in_rfkill)
1386                 ret = -ERFKILL;
1387
1388 out:
1389         mutex_unlock(&trans_pcie->mutex);
1390         return ret;
1391 }
1392
1393 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1394 {
1395         iwl_pcie_reset_ict(trans);
1396         iwl_pcie_tx_start(trans, scd_addr);
1397 }
1398
1399 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1400                                        bool was_in_rfkill)
1401 {
1402         bool hw_rfkill;
1403
1404         /*
1405          * Check again since the RF kill state may have changed while
1406          * all the interrupts were disabled, in this case we couldn't
1407          * receive the RF kill interrupt and update the state in the
1408          * op_mode.
1409          * Don't call the op_mode if the rkfill state hasn't changed.
1410          * This allows the op_mode to call stop_device from the rfkill
1411          * notification without endless recursion. Under very rare
1412          * circumstances, we might have a small recursion if the rfkill
1413          * state changed exactly now while we were called from stop_device.
1414          * This is very unlikely but can happen and is supported.
1415          */
1416         hw_rfkill = iwl_is_rfkill_set(trans);
1417         if (hw_rfkill) {
1418                 set_bit(STATUS_RFKILL_HW, &trans->status);
1419                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1420         } else {
1421                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1422                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1423         }
1424         if (hw_rfkill != was_in_rfkill)
1425                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1426 }
1427
1428 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1429 {
1430         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1431         bool was_in_rfkill;
1432
1433         mutex_lock(&trans_pcie->mutex);
1434         trans_pcie->opmode_down = true;
1435         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1436         _iwl_trans_pcie_stop_device(trans);
1437         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1438         mutex_unlock(&trans_pcie->mutex);
1439 }
1440
1441 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1442 {
1443         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1444                 IWL_TRANS_GET_PCIE_TRANS(trans);
1445
1446         lockdep_assert_held(&trans_pcie->mutex);
1447
1448         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1449                  state ? "disabled" : "enabled");
1450         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1451                 if (trans->trans_cfg->gen2)
1452                         _iwl_trans_pcie_gen2_stop_device(trans);
1453                 else
1454                         _iwl_trans_pcie_stop_device(trans);
1455         }
1456 }
1457
1458 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1459                                   bool test, bool reset)
1460 {
1461         iwl_disable_interrupts(trans);
1462
1463         /*
1464          * in testing mode, the host stays awake and the
1465          * hardware won't be reset (not even partially)
1466          */
1467         if (test)
1468                 return;
1469
1470         iwl_pcie_disable_ict(trans);
1471
1472         iwl_pcie_synchronize_irqs(trans);
1473
1474         iwl_clear_bit(trans, CSR_GP_CNTRL,
1475                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1476         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1477
1478         if (reset) {
1479                 /*
1480                  * reset TX queues -- some of their registers reset during S3
1481                  * so if we don't reset everything here the D3 image would try
1482                  * to execute some invalid memory upon resume
1483                  */
1484                 iwl_trans_pcie_tx_reset(trans);
1485         }
1486
1487         iwl_pcie_set_pwr(trans, true);
1488 }
1489
1490 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1491                                      bool reset)
1492 {
1493         int ret;
1494         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1495
1496         if (!reset)
1497                 /* Enable persistence mode to avoid reset */
1498                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1499                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1500
1501         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1502                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1503                                     UREG_DOORBELL_TO_ISR6_SUSPEND);
1504
1505                 ret = wait_event_timeout(trans_pcie->sx_waitq,
1506                                          trans_pcie->sx_complete, 2 * HZ);
1507                 /*
1508                  * Invalidate it toward resume.
1509                  */
1510                 trans_pcie->sx_complete = false;
1511
1512                 if (!ret) {
1513                         IWL_ERR(trans, "Timeout entering D3\n");
1514                         return -ETIMEDOUT;
1515                 }
1516         }
1517         iwl_pcie_d3_complete_suspend(trans, test, reset);
1518
1519         return 0;
1520 }
1521
1522 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1523                                     enum iwl_d3_status *status,
1524                                     bool test,  bool reset)
1525 {
1526         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1527         u32 val;
1528         int ret;
1529
1530         if (test) {
1531                 iwl_enable_interrupts(trans);
1532                 *status = IWL_D3_STATUS_ALIVE;
1533                 goto out;
1534         }
1535
1536         iwl_set_bit(trans, CSR_GP_CNTRL,
1537                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1538
1539         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1540         if (ret)
1541                 return ret;
1542
1543         /*
1544          * Reconfigure IVAR table in case of MSIX or reset ict table in
1545          * MSI mode since HW reset erased it.
1546          * Also enables interrupts - none will happen as
1547          * the device doesn't know we're waking it up, only when
1548          * the opmode actually tells it after this call.
1549          */
1550         iwl_pcie_conf_msix_hw(trans_pcie);
1551         if (!trans_pcie->msix_enabled)
1552                 iwl_pcie_reset_ict(trans);
1553         iwl_enable_interrupts(trans);
1554
1555         iwl_pcie_set_pwr(trans, false);
1556
1557         if (!reset) {
1558                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1559                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1560         } else {
1561                 iwl_trans_pcie_tx_reset(trans);
1562
1563                 ret = iwl_pcie_rx_init(trans);
1564                 if (ret) {
1565                         IWL_ERR(trans,
1566                                 "Failed to resume the device (RX reset)\n");
1567                         return ret;
1568                 }
1569         }
1570
1571         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1572                         iwl_read_umac_prph(trans, WFPM_GP2));
1573
1574         val = iwl_read32(trans, CSR_RESET);
1575         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1576                 *status = IWL_D3_STATUS_RESET;
1577         else
1578                 *status = IWL_D3_STATUS_ALIVE;
1579
1580 out:
1581         if (*status == IWL_D3_STATUS_ALIVE &&
1582             trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1583                 trans_pcie->sx_complete = false;
1584                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1585                                     UREG_DOORBELL_TO_ISR6_RESUME);
1586
1587                 ret = wait_event_timeout(trans_pcie->sx_waitq,
1588                                          trans_pcie->sx_complete, 2 * HZ);
1589                 /*
1590                  * Invalidate it toward next suspend.
1591                  */
1592                 trans_pcie->sx_complete = false;
1593
1594                 if (!ret) {
1595                         IWL_ERR(trans, "Timeout exiting D3\n");
1596                         return -ETIMEDOUT;
1597                 }
1598         }
1599         return 0;
1600 }
1601
1602 static void
1603 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1604                             struct iwl_trans *trans,
1605                             const struct iwl_cfg_trans_params *cfg_trans)
1606 {
1607         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1608         int max_irqs, num_irqs, i, ret;
1609         u16 pci_cmd;
1610
1611         if (!cfg_trans->mq_rx_supported)
1612                 goto enable_msi;
1613
1614         max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
1615         for (i = 0; i < max_irqs; i++)
1616                 trans_pcie->msix_entries[i].entry = i;
1617
1618         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1619                                          MSIX_MIN_INTERRUPT_VECTORS,
1620                                          max_irqs);
1621         if (num_irqs < 0) {
1622                 IWL_DEBUG_INFO(trans,
1623                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1624                                num_irqs);
1625                 goto enable_msi;
1626         }
1627         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1628
1629         IWL_DEBUG_INFO(trans,
1630                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1631                        num_irqs);
1632
1633         /*
1634          * In case the OS provides fewer interrupts than requested, different
1635          * causes will share the same interrupt vector as follows:
1636          * One interrupt less: non rx causes shared with FBQ.
1637          * Two interrupts less: non rx causes shared with FBQ and RSS.
1638          * More than two interrupts: we will use fewer RSS queues.
1639          */
1640         if (num_irqs <= max_irqs - 2) {
1641                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1642                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1643                         IWL_SHARED_IRQ_FIRST_RSS;
1644         } else if (num_irqs == max_irqs - 1) {
1645                 trans_pcie->trans->num_rx_queues = num_irqs;
1646                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1647         } else {
1648                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1649         }
1650         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1651
1652         trans_pcie->alloc_vecs = num_irqs;
1653         trans_pcie->msix_enabled = true;
1654         return;
1655
1656 enable_msi:
1657         ret = pci_enable_msi(pdev);
1658         if (ret) {
1659                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1660                 /* enable rfkill interrupt: hw bug w/a */
1661                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1662                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1663                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1664                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1665                 }
1666         }
1667 }
1668
1669 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1670 {
1671         int iter_rx_q, i, ret, cpu, offset;
1672         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1673
1674         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1675         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1676         offset = 1 + i;
1677         for (; i < iter_rx_q ; i++) {
1678                 /*
1679                  * Get the cpu prior to the place to search
1680                  * (i.e. return will be > i - 1).
1681                  */
1682                 cpu = cpumask_next(i - offset, cpu_online_mask);
1683                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1684                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1685                                             &trans_pcie->affinity_mask[i]);
1686                 if (ret)
1687                         IWL_ERR(trans_pcie->trans,
1688                                 "Failed to set affinity mask for IRQ %d\n",
1689                                 i);
1690         }
1691 }
1692
1693 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1694                                       struct iwl_trans_pcie *trans_pcie)
1695 {
1696         int i;
1697
1698         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1699                 int ret;
1700                 struct msix_entry *msix_entry;
1701                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1702
1703                 if (!qname)
1704                         return -ENOMEM;
1705
1706                 msix_entry = &trans_pcie->msix_entries[i];
1707                 ret = devm_request_threaded_irq(&pdev->dev,
1708                                                 msix_entry->vector,
1709                                                 iwl_pcie_msix_isr,
1710                                                 (i == trans_pcie->def_irq) ?
1711                                                 iwl_pcie_irq_msix_handler :
1712                                                 iwl_pcie_irq_rx_msix_handler,
1713                                                 IRQF_SHARED,
1714                                                 qname,
1715                                                 msix_entry);
1716                 if (ret) {
1717                         IWL_ERR(trans_pcie->trans,
1718                                 "Error allocating IRQ %d\n", i);
1719
1720                         return ret;
1721                 }
1722         }
1723         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1724
1725         return 0;
1726 }
1727
1728 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1729 {
1730         u32 hpm, wprot;
1731
1732         switch (trans->trans_cfg->device_family) {
1733         case IWL_DEVICE_FAMILY_9000:
1734                 wprot = PREG_PRPH_WPROT_9000;
1735                 break;
1736         case IWL_DEVICE_FAMILY_22000:
1737                 wprot = PREG_PRPH_WPROT_22000;
1738                 break;
1739         default:
1740                 return 0;
1741         }
1742
1743         hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1744         if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1745                 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1746
1747                 if (wprot_val & PREG_WFPM_ACCESS) {
1748                         IWL_ERR(trans,
1749                                 "Error, can not clear persistence bit\n");
1750                         return -EPERM;
1751                 }
1752                 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1753                                             hpm & ~PERSISTENCE_BIT);
1754         }
1755
1756         return 0;
1757 }
1758
1759 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1760 {
1761         int ret;
1762
1763         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1764         if (ret < 0)
1765                 return ret;
1766
1767         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1768                           HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1769         udelay(20);
1770         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1771                           HPM_HIPM_GEN_CFG_CR_PG_EN |
1772                           HPM_HIPM_GEN_CFG_CR_SLP_EN);
1773         udelay(20);
1774         iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1775                             HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1776
1777         iwl_trans_pcie_sw_reset(trans);
1778
1779         return 0;
1780 }
1781
1782 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1783 {
1784         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1785         int err;
1786
1787         lockdep_assert_held(&trans_pcie->mutex);
1788
1789         err = iwl_pcie_prepare_card_hw(trans);
1790         if (err) {
1791                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1792                 return err;
1793         }
1794
1795         err = iwl_trans_pcie_clear_persistence_bit(trans);
1796         if (err)
1797                 return err;
1798
1799         iwl_trans_pcie_sw_reset(trans);
1800
1801         if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1802             trans->trans_cfg->integrated) {
1803                 err = iwl_pcie_gen2_force_power_gating(trans);
1804                 if (err)
1805                         return err;
1806         }
1807
1808         err = iwl_pcie_apm_init(trans);
1809         if (err)
1810                 return err;
1811
1812         iwl_pcie_init_msix(trans_pcie);
1813
1814         /* From now on, the op_mode will be kept updated about RF kill state */
1815         iwl_enable_rfkill_int(trans);
1816
1817         trans_pcie->opmode_down = false;
1818
1819         /* Set is_down to false here so that...*/
1820         trans_pcie->is_down = false;
1821
1822         /* ...rfkill can call stop_device and set it false if needed */
1823         iwl_pcie_check_hw_rf_kill(trans);
1824
1825         return 0;
1826 }
1827
1828 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1829 {
1830         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1831         int ret;
1832
1833         mutex_lock(&trans_pcie->mutex);
1834         ret = _iwl_trans_pcie_start_hw(trans);
1835         mutex_unlock(&trans_pcie->mutex);
1836
1837         return ret;
1838 }
1839
1840 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1841 {
1842         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1843
1844         mutex_lock(&trans_pcie->mutex);
1845
1846         /* disable interrupts - don't enable HW RF kill interrupt */
1847         iwl_disable_interrupts(trans);
1848
1849         iwl_pcie_apm_stop(trans, true);
1850
1851         iwl_disable_interrupts(trans);
1852
1853         iwl_pcie_disable_ict(trans);
1854
1855         mutex_unlock(&trans_pcie->mutex);
1856
1857         iwl_pcie_synchronize_irqs(trans);
1858 }
1859
1860 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1861 {
1862         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1863 }
1864
1865 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1866 {
1867         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1868 }
1869
1870 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1871 {
1872         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1873 }
1874
1875 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1876 {
1877         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1878                 return 0x00FFFFFF;
1879         else
1880                 return 0x000FFFFF;
1881 }
1882
1883 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1884 {
1885         u32 mask = iwl_trans_pcie_prph_msk(trans);
1886
1887         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1888                                ((reg & mask) | (3 << 24)));
1889         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1890 }
1891
1892 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1893                                       u32 val)
1894 {
1895         u32 mask = iwl_trans_pcie_prph_msk(trans);
1896
1897         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1898                                ((addr & mask) | (3 << 24)));
1899         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1900 }
1901
1902 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1903                                      const struct iwl_trans_config *trans_cfg)
1904 {
1905         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1906
1907         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1908         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1909         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1910         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1911                 trans_pcie->n_no_reclaim_cmds = 0;
1912         else
1913                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1914         if (trans_pcie->n_no_reclaim_cmds)
1915                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1916                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1917
1918         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1919         trans_pcie->rx_page_order =
1920                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1921         trans_pcie->rx_buf_bytes =
1922                 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
1923         trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1924         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1925                 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
1926
1927         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1928         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1929         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1930
1931         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1932         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1933
1934         trans->command_groups = trans_cfg->command_groups;
1935         trans->command_groups_size = trans_cfg->command_groups_size;
1936
1937         /* Initialize NAPI here - it should be before registering to mac80211
1938          * in the opmode but after the HW struct is allocated.
1939          * As this function may be called again in some corner cases don't
1940          * do anything if NAPI was already initialized.
1941          */
1942         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1943                 init_dummy_netdev(&trans_pcie->napi_dev);
1944 }
1945
1946 void iwl_trans_pcie_free(struct iwl_trans *trans)
1947 {
1948         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1949         int i;
1950
1951         iwl_pcie_synchronize_irqs(trans);
1952
1953         if (trans->trans_cfg->gen2)
1954                 iwl_pcie_gen2_tx_free(trans);
1955         else
1956                 iwl_pcie_tx_free(trans);
1957         iwl_pcie_rx_free(trans);
1958
1959         if (trans_pcie->rba.alloc_wq) {
1960                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1961                 trans_pcie->rba.alloc_wq = NULL;
1962         }
1963
1964         if (trans_pcie->msix_enabled) {
1965                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1966                         irq_set_affinity_hint(
1967                                 trans_pcie->msix_entries[i].vector,
1968                                 NULL);
1969                 }
1970
1971                 trans_pcie->msix_enabled = false;
1972         } else {
1973                 iwl_pcie_free_ict(trans);
1974         }
1975
1976         iwl_pcie_free_fw_monitor(trans);
1977
1978         for_each_possible_cpu(i) {
1979                 struct iwl_tso_hdr_page *p =
1980                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1981
1982                 if (p->page)
1983                         __free_page(p->page);
1984         }
1985
1986         free_percpu(trans_pcie->tso_hdr_page);
1987         mutex_destroy(&trans_pcie->mutex);
1988         iwl_trans_free(trans);
1989 }
1990
1991 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1992 {
1993         if (state)
1994                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1995         else
1996                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1997 }
1998
1999 struct iwl_trans_pcie_removal {
2000         struct pci_dev *pdev;
2001         struct work_struct work;
2002 };
2003
2004 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2005 {
2006         struct iwl_trans_pcie_removal *removal =
2007                 container_of(wk, struct iwl_trans_pcie_removal, work);
2008         struct pci_dev *pdev = removal->pdev;
2009         static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2010
2011         dev_err(&pdev->dev, "Device gone - attempting removal\n");
2012         kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2013         pci_lock_rescan_remove();
2014         pci_dev_put(pdev);
2015         pci_stop_and_remove_bus_device(pdev);
2016         pci_unlock_rescan_remove();
2017
2018         kfree(removal);
2019         module_put(THIS_MODULE);
2020 }
2021
2022 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
2023                                            unsigned long *flags)
2024 {
2025         int ret;
2026         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2027
2028         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
2029
2030         if (trans_pcie->cmd_hold_nic_awake)
2031                 goto out;
2032
2033         /* this bit wakes up the NIC */
2034         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
2035                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2036         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2037                 udelay(2);
2038
2039         /*
2040          * These bits say the device is running, and should keep running for
2041          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2042          * but they do not indicate that embedded SRAM is restored yet;
2043          * HW with volatile SRAM must save/restore contents to/from
2044          * host DRAM when sleeping/waking for power-saving.
2045          * Each direction takes approximately 1/4 millisecond; with this
2046          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2047          * series of register accesses are expected (e.g. reading Event Log),
2048          * to keep device from sleeping.
2049          *
2050          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2051          * SRAM is okay/restored.  We don't check that here because this call
2052          * is just for hardware register access; but GP1 MAC_SLEEP
2053          * check is a good idea before accessing the SRAM of HW with
2054          * volatile SRAM (e.g. reading Event Log).
2055          *
2056          * 5000 series and later (including 1000 series) have non-volatile SRAM,
2057          * and do not save/restore SRAM when power cycling.
2058          */
2059         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2060                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2061                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2062                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2063         if (unlikely(ret < 0)) {
2064                 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2065
2066                 WARN_ONCE(1,
2067                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2068                           cntrl);
2069
2070                 iwl_trans_pcie_dump_regs(trans);
2071
2072                 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2073                         struct iwl_trans_pcie_removal *removal;
2074
2075                         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2076                                 goto err;
2077
2078                         IWL_ERR(trans, "Device gone - scheduling removal!\n");
2079
2080                         /*
2081                          * get a module reference to avoid doing this
2082                          * while unloading anyway and to avoid
2083                          * scheduling a work with code that's being
2084                          * removed.
2085                          */
2086                         if (!try_module_get(THIS_MODULE)) {
2087                                 IWL_ERR(trans,
2088                                         "Module is being unloaded - abort\n");
2089                                 goto err;
2090                         }
2091
2092                         removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2093                         if (!removal) {
2094                                 module_put(THIS_MODULE);
2095                                 goto err;
2096                         }
2097                         /*
2098                          * we don't need to clear this flag, because
2099                          * the trans will be freed and reallocated.
2100                         */
2101                         set_bit(STATUS_TRANS_DEAD, &trans->status);
2102
2103                         removal->pdev = to_pci_dev(trans->dev);
2104                         INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2105                         pci_dev_get(removal->pdev);
2106                         schedule_work(&removal->work);
2107                 } else {
2108                         iwl_write32(trans, CSR_RESET,
2109                                     CSR_RESET_REG_FLAG_FORCE_NMI);
2110                 }
2111
2112 err:
2113                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2114                 return false;
2115         }
2116
2117 out:
2118         /*
2119          * Fool sparse by faking we release the lock - sparse will
2120          * track nic_access anyway.
2121          */
2122         __release(&trans_pcie->reg_lock);
2123         return true;
2124 }
2125
2126 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2127                                               unsigned long *flags)
2128 {
2129         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2130
2131         lockdep_assert_held(&trans_pcie->reg_lock);
2132
2133         /*
2134          * Fool sparse by faking we acquiring the lock - sparse will
2135          * track nic_access anyway.
2136          */
2137         __acquire(&trans_pcie->reg_lock);
2138
2139         if (trans_pcie->cmd_hold_nic_awake)
2140                 goto out;
2141
2142         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2143                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2144         /*
2145          * Above we read the CSR_GP_CNTRL register, which will flush
2146          * any previous writes, but we need the write that clears the
2147          * MAC_ACCESS_REQ bit to be performed before any other writes
2148          * scheduled on different CPUs (after we drop reg_lock).
2149          */
2150 out:
2151         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2152 }
2153
2154 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2155                                    void *buf, int dwords)
2156 {
2157         unsigned long flags;
2158         int offs, ret = 0;
2159         u32 *vals = buf;
2160
2161         if (iwl_trans_grab_nic_access(trans, &flags)) {
2162                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2163                 for (offs = 0; offs < dwords; offs++)
2164                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
2165                 iwl_trans_release_nic_access(trans, &flags);
2166         } else {
2167                 ret = -EBUSY;
2168         }
2169         return ret;
2170 }
2171
2172 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2173                                     const void *buf, int dwords)
2174 {
2175         unsigned long flags;
2176         int offs, ret = 0;
2177         const u32 *vals = buf;
2178
2179         if (iwl_trans_grab_nic_access(trans, &flags)) {
2180                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2181                 for (offs = 0; offs < dwords; offs++)
2182                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2183                                     vals ? vals[offs] : 0);
2184                 iwl_trans_release_nic_access(trans, &flags);
2185         } else {
2186                 ret = -EBUSY;
2187         }
2188         return ret;
2189 }
2190
2191 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2192                                         u32 *val)
2193 {
2194         return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2195                                      ofs, val);
2196 }
2197
2198 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2199                                             unsigned long txqs,
2200                                             bool freeze)
2201 {
2202         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2203         int queue;
2204
2205         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2206                 struct iwl_txq *txq = trans_pcie->txq[queue];
2207                 unsigned long now;
2208
2209                 spin_lock_bh(&txq->lock);
2210
2211                 now = jiffies;
2212
2213                 if (txq->frozen == freeze)
2214                         goto next_queue;
2215
2216                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2217                                     freeze ? "Freezing" : "Waking", queue);
2218
2219                 txq->frozen = freeze;
2220
2221                 if (txq->read_ptr == txq->write_ptr)
2222                         goto next_queue;
2223
2224                 if (freeze) {
2225                         if (unlikely(time_after(now,
2226                                                 txq->stuck_timer.expires))) {
2227                                 /*
2228                                  * The timer should have fired, maybe it is
2229                                  * spinning right now on the lock.
2230                                  */
2231                                 goto next_queue;
2232                         }
2233                         /* remember how long until the timer fires */
2234                         txq->frozen_expiry_remainder =
2235                                 txq->stuck_timer.expires - now;
2236                         del_timer(&txq->stuck_timer);
2237                         goto next_queue;
2238                 }
2239
2240                 /*
2241                  * Wake a non-empty queue -> arm timer with the
2242                  * remainder before it froze
2243                  */
2244                 mod_timer(&txq->stuck_timer,
2245                           now + txq->frozen_expiry_remainder);
2246
2247 next_queue:
2248                 spin_unlock_bh(&txq->lock);
2249         }
2250 }
2251
2252 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2253 {
2254         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2255         int i;
2256
2257         for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
2258                 struct iwl_txq *txq = trans_pcie->txq[i];
2259
2260                 if (i == trans_pcie->cmd_queue)
2261                         continue;
2262
2263                 spin_lock_bh(&txq->lock);
2264
2265                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2266                         txq->block--;
2267                         if (!txq->block) {
2268                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2269                                             txq->write_ptr | (i << 8));
2270                         }
2271                 } else if (block) {
2272                         txq->block++;
2273                 }
2274
2275                 spin_unlock_bh(&txq->lock);
2276         }
2277 }
2278
2279 #define IWL_FLUSH_WAIT_MS       2000
2280
2281 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2282 {
2283         u32 txq_id = txq->id;
2284         u32 status;
2285         bool active;
2286         u8 fifo;
2287
2288         if (trans->trans_cfg->use_tfh) {
2289                 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2290                         txq->read_ptr, txq->write_ptr);
2291                 /* TODO: access new SCD registers and dump them */
2292                 return;
2293         }
2294
2295         status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2296         fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2297         active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2298
2299         IWL_ERR(trans,
2300                 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2301                 txq_id, active ? "" : "in", fifo,
2302                 jiffies_to_msecs(txq->wd_timeout),
2303                 txq->read_ptr, txq->write_ptr,
2304                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2305                         (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2306                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2307                         (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2308                         iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2309 }
2310
2311 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2312                                        struct iwl_trans_rxq_dma_data *data)
2313 {
2314         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2315
2316         if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2317                 return -EINVAL;
2318
2319         data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2320         data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2321         data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2322         data->fr_bd_wid = 0;
2323
2324         return 0;
2325 }
2326
2327 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2328 {
2329         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2330         struct iwl_txq *txq;
2331         unsigned long now = jiffies;
2332         bool overflow_tx;
2333         u8 wr_ptr;
2334
2335         /* Make sure the NIC is still alive in the bus */
2336         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2337                 return -ENODEV;
2338
2339         if (!test_bit(txq_idx, trans_pcie->queue_used))
2340                 return -EINVAL;
2341
2342         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2343         txq = trans_pcie->txq[txq_idx];
2344
2345         spin_lock_bh(&txq->lock);
2346         overflow_tx = txq->overflow_tx ||
2347                       !skb_queue_empty(&txq->overflow_q);
2348         spin_unlock_bh(&txq->lock);
2349
2350         wr_ptr = READ_ONCE(txq->write_ptr);
2351
2352         while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2353                 overflow_tx) &&
2354                !time_after(jiffies,
2355                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2356                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2357
2358                 /*
2359                  * If write pointer moved during the wait, warn only
2360                  * if the TX came from op mode. In case TX came from
2361                  * trans layer (overflow TX) don't warn.
2362                  */
2363                 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2364                               "WR pointer moved while flushing %d -> %d\n",
2365                               wr_ptr, write_ptr))
2366                         return -ETIMEDOUT;
2367                 wr_ptr = write_ptr;
2368
2369                 usleep_range(1000, 2000);
2370
2371                 spin_lock_bh(&txq->lock);
2372                 overflow_tx = txq->overflow_tx ||
2373                               !skb_queue_empty(&txq->overflow_q);
2374                 spin_unlock_bh(&txq->lock);
2375         }
2376
2377         if (txq->read_ptr != txq->write_ptr) {
2378                 IWL_ERR(trans,
2379                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2380                 iwl_trans_pcie_log_scd_error(trans, txq);
2381                 return -ETIMEDOUT;
2382         }
2383
2384         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2385
2386         return 0;
2387 }
2388
2389 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2390 {
2391         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2392         int cnt;
2393         int ret = 0;
2394
2395         /* waiting for all the tx frames complete might take a while */
2396         for (cnt = 0;
2397              cnt < trans->trans_cfg->base_params->num_of_queues;
2398              cnt++) {
2399
2400                 if (cnt == trans_pcie->cmd_queue)
2401                         continue;
2402                 if (!test_bit(cnt, trans_pcie->queue_used))
2403                         continue;
2404                 if (!(BIT(cnt) & txq_bm))
2405                         continue;
2406
2407                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2408                 if (ret)
2409                         break;
2410         }
2411
2412         return ret;
2413 }
2414
2415 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2416                                          u32 mask, u32 value)
2417 {
2418         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2419         unsigned long flags;
2420
2421         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2422         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2423         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2424 }
2425
2426 static const char *get_csr_string(int cmd)
2427 {
2428 #define IWL_CMD(x) case x: return #x
2429         switch (cmd) {
2430         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2431         IWL_CMD(CSR_INT_COALESCING);
2432         IWL_CMD(CSR_INT);
2433         IWL_CMD(CSR_INT_MASK);
2434         IWL_CMD(CSR_FH_INT_STATUS);
2435         IWL_CMD(CSR_GPIO_IN);
2436         IWL_CMD(CSR_RESET);
2437         IWL_CMD(CSR_GP_CNTRL);
2438         IWL_CMD(CSR_HW_REV);
2439         IWL_CMD(CSR_EEPROM_REG);
2440         IWL_CMD(CSR_EEPROM_GP);
2441         IWL_CMD(CSR_OTP_GP_REG);
2442         IWL_CMD(CSR_GIO_REG);
2443         IWL_CMD(CSR_GP_UCODE_REG);
2444         IWL_CMD(CSR_GP_DRIVER_REG);
2445         IWL_CMD(CSR_UCODE_DRV_GP1);
2446         IWL_CMD(CSR_UCODE_DRV_GP2);
2447         IWL_CMD(CSR_LED_REG);
2448         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2449         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2450         IWL_CMD(CSR_ANA_PLL_CFG);
2451         IWL_CMD(CSR_HW_REV_WA_REG);
2452         IWL_CMD(CSR_MONITOR_STATUS_REG);
2453         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2454         default:
2455                 return "UNKNOWN";
2456         }
2457 #undef IWL_CMD
2458 }
2459
2460 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2461 {
2462         int i;
2463         static const u32 csr_tbl[] = {
2464                 CSR_HW_IF_CONFIG_REG,
2465                 CSR_INT_COALESCING,
2466                 CSR_INT,
2467                 CSR_INT_MASK,
2468                 CSR_FH_INT_STATUS,
2469                 CSR_GPIO_IN,
2470                 CSR_RESET,
2471                 CSR_GP_CNTRL,
2472                 CSR_HW_REV,
2473                 CSR_EEPROM_REG,
2474                 CSR_EEPROM_GP,
2475                 CSR_OTP_GP_REG,
2476                 CSR_GIO_REG,
2477                 CSR_GP_UCODE_REG,
2478                 CSR_GP_DRIVER_REG,
2479                 CSR_UCODE_DRV_GP1,
2480                 CSR_UCODE_DRV_GP2,
2481                 CSR_LED_REG,
2482                 CSR_DRAM_INT_TBL_REG,
2483                 CSR_GIO_CHICKEN_BITS,
2484                 CSR_ANA_PLL_CFG,
2485                 CSR_MONITOR_STATUS_REG,
2486                 CSR_HW_REV_WA_REG,
2487                 CSR_DBG_HPET_MEM_REG
2488         };
2489         IWL_ERR(trans, "CSR values:\n");
2490         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2491                 "CSR_INT_PERIODIC_REG)\n");
2492         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2493                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2494                         get_csr_string(csr_tbl[i]),
2495                         iwl_read32(trans, csr_tbl[i]));
2496         }
2497 }
2498
2499 #ifdef CONFIG_IWLWIFI_DEBUGFS
2500 /* create and remove of files */
2501 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2502         debugfs_create_file(#name, mode, parent, trans,                 \
2503                             &iwl_dbgfs_##name##_ops);                   \
2504 } while (0)
2505
2506 /* file operation */
2507 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2508 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2509         .read = iwl_dbgfs_##name##_read,                                \
2510         .open = simple_open,                                            \
2511         .llseek = generic_file_llseek,                                  \
2512 };
2513
2514 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2515 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2516         .write = iwl_dbgfs_##name##_write,                              \
2517         .open = simple_open,                                            \
2518         .llseek = generic_file_llseek,                                  \
2519 };
2520
2521 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2522 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2523         .write = iwl_dbgfs_##name##_write,                              \
2524         .read = iwl_dbgfs_##name##_read,                                \
2525         .open = simple_open,                                            \
2526         .llseek = generic_file_llseek,                                  \
2527 };
2528
2529 struct iwl_dbgfs_tx_queue_priv {
2530         struct iwl_trans *trans;
2531 };
2532
2533 struct iwl_dbgfs_tx_queue_state {
2534         loff_t pos;
2535 };
2536
2537 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
2538 {
2539         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2540         struct iwl_dbgfs_tx_queue_state *state;
2541
2542         if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2543                 return NULL;
2544
2545         state = kmalloc(sizeof(*state), GFP_KERNEL);
2546         if (!state)
2547                 return NULL;
2548         state->pos = *pos;
2549         return state;
2550 }
2551
2552 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2553                                          void *v, loff_t *pos)
2554 {
2555         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2556         struct iwl_dbgfs_tx_queue_state *state = v;
2557
2558         *pos = ++state->pos;
2559
2560         if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2561                 return NULL;
2562
2563         return state;
2564 }
2565
2566 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2567 {
2568         kfree(v);
2569 }
2570
2571 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2572 {
2573         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2574         struct iwl_dbgfs_tx_queue_state *state = v;
2575         struct iwl_trans *trans = priv->trans;
2576         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2577         struct iwl_txq *txq = trans_pcie->txq[state->pos];
2578
2579         seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2580                    (unsigned int)state->pos,
2581                    !!test_bit(state->pos, trans_pcie->queue_used),
2582                    !!test_bit(state->pos, trans_pcie->queue_stopped));
2583         if (txq)
2584                 seq_printf(seq,
2585                            "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2586                            txq->read_ptr, txq->write_ptr,
2587                            txq->need_update, txq->frozen,
2588                            txq->n_window, txq->ampdu);
2589         else
2590                 seq_puts(seq, "(unallocated)");
2591
2592         if (state->pos == trans_pcie->cmd_queue)
2593                 seq_puts(seq, " (HCMD)");
2594         seq_puts(seq, "\n");
2595
2596         return 0;
2597 }
2598
2599 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2600         .start = iwl_dbgfs_tx_queue_seq_start,
2601         .next = iwl_dbgfs_tx_queue_seq_next,
2602         .stop = iwl_dbgfs_tx_queue_seq_stop,
2603         .show = iwl_dbgfs_tx_queue_seq_show,
2604 };
2605
2606 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2607 {
2608         struct iwl_dbgfs_tx_queue_priv *priv;
2609
2610         priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2611                                   sizeof(*priv));
2612
2613         if (!priv)
2614                 return -ENOMEM;
2615
2616         priv->trans = inode->i_private;
2617         return 0;
2618 }
2619
2620 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2621                                        char __user *user_buf,
2622                                        size_t count, loff_t *ppos)
2623 {
2624         struct iwl_trans *trans = file->private_data;
2625         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2626         char *buf;
2627         int pos = 0, i, ret;
2628         size_t bufsz;
2629
2630         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2631
2632         if (!trans_pcie->rxq)
2633                 return -EAGAIN;
2634
2635         buf = kzalloc(bufsz, GFP_KERNEL);
2636         if (!buf)
2637                 return -ENOMEM;
2638
2639         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2640                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2641
2642                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2643                                  i);
2644                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2645                                  rxq->read);
2646                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2647                                  rxq->write);
2648                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2649                                  rxq->write_actual);
2650                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2651                                  rxq->need_update);
2652                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2653                                  rxq->free_count);
2654                 if (rxq->rb_stts) {
2655                         u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2656                                                                      rxq));
2657                         pos += scnprintf(buf + pos, bufsz - pos,
2658                                          "\tclosed_rb_num: %u\n",
2659                                          r & 0x0FFF);
2660                 } else {
2661                         pos += scnprintf(buf + pos, bufsz - pos,
2662                                          "\tclosed_rb_num: Not Allocated\n");
2663                 }
2664         }
2665         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2666         kfree(buf);
2667
2668         return ret;
2669 }
2670
2671 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2672                                         char __user *user_buf,
2673                                         size_t count, loff_t *ppos)
2674 {
2675         struct iwl_trans *trans = file->private_data;
2676         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2677         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2678
2679         int pos = 0;
2680         char *buf;
2681         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2682         ssize_t ret;
2683
2684         buf = kzalloc(bufsz, GFP_KERNEL);
2685         if (!buf)
2686                 return -ENOMEM;
2687
2688         pos += scnprintf(buf + pos, bufsz - pos,
2689                         "Interrupt Statistics Report:\n");
2690
2691         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2692                 isr_stats->hw);
2693         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2694                 isr_stats->sw);
2695         if (isr_stats->sw || isr_stats->hw) {
2696                 pos += scnprintf(buf + pos, bufsz - pos,
2697                         "\tLast Restarting Code:  0x%X\n",
2698                         isr_stats->err_code);
2699         }
2700 #ifdef CONFIG_IWLWIFI_DEBUG
2701         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2702                 isr_stats->sch);
2703         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2704                 isr_stats->alive);
2705 #endif
2706         pos += scnprintf(buf + pos, bufsz - pos,
2707                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2708
2709         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2710                 isr_stats->ctkill);
2711
2712         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2713                 isr_stats->wakeup);
2714
2715         pos += scnprintf(buf + pos, bufsz - pos,
2716                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2717
2718         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2719                 isr_stats->tx);
2720
2721         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2722                 isr_stats->unhandled);
2723
2724         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2725         kfree(buf);
2726         return ret;
2727 }
2728
2729 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2730                                          const char __user *user_buf,
2731                                          size_t count, loff_t *ppos)
2732 {
2733         struct iwl_trans *trans = file->private_data;
2734         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2735         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2736         u32 reset_flag;
2737         int ret;
2738
2739         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2740         if (ret)
2741                 return ret;
2742         if (reset_flag == 0)
2743                 memset(isr_stats, 0, sizeof(*isr_stats));
2744
2745         return count;
2746 }
2747
2748 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2749                                    const char __user *user_buf,
2750                                    size_t count, loff_t *ppos)
2751 {
2752         struct iwl_trans *trans = file->private_data;
2753
2754         iwl_pcie_dump_csr(trans);
2755
2756         return count;
2757 }
2758
2759 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2760                                      char __user *user_buf,
2761                                      size_t count, loff_t *ppos)
2762 {
2763         struct iwl_trans *trans = file->private_data;
2764         char *buf = NULL;
2765         ssize_t ret;
2766
2767         ret = iwl_dump_fh(trans, &buf);
2768         if (ret < 0)
2769                 return ret;
2770         if (!buf)
2771                 return -EINVAL;
2772         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2773         kfree(buf);
2774         return ret;
2775 }
2776
2777 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2778                                      char __user *user_buf,
2779                                      size_t count, loff_t *ppos)
2780 {
2781         struct iwl_trans *trans = file->private_data;
2782         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2783         char buf[100];
2784         int pos;
2785
2786         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2787                         trans_pcie->debug_rfkill,
2788                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2789                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2790
2791         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2792 }
2793
2794 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2795                                       const char __user *user_buf,
2796                                       size_t count, loff_t *ppos)
2797 {
2798         struct iwl_trans *trans = file->private_data;
2799         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2800         bool new_value;
2801         int ret;
2802
2803         ret = kstrtobool_from_user(user_buf, count, &new_value);
2804         if (ret)
2805                 return ret;
2806         if (new_value == trans_pcie->debug_rfkill)
2807                 return count;
2808         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2809                  trans_pcie->debug_rfkill, new_value);
2810         trans_pcie->debug_rfkill = new_value;
2811         iwl_pcie_handle_rfkill_irq(trans);
2812
2813         return count;
2814 }
2815
2816 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2817                                        struct file *file)
2818 {
2819         struct iwl_trans *trans = inode->i_private;
2820         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2821
2822         if (!trans->dbg.dest_tlv ||
2823             trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2824                 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2825                 return -ENOENT;
2826         }
2827
2828         if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2829                 return -EBUSY;
2830
2831         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2832         return simple_open(inode, file);
2833 }
2834
2835 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2836                                           struct file *file)
2837 {
2838         struct iwl_trans_pcie *trans_pcie =
2839                 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2840
2841         if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2842                 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2843         return 0;
2844 }
2845
2846 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2847                                   void *buf, ssize_t *size,
2848                                   ssize_t *bytes_copied)
2849 {
2850         int buf_size_left = count - *bytes_copied;
2851
2852         buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2853         if (*size > buf_size_left)
2854                 *size = buf_size_left;
2855
2856         *size -= copy_to_user(user_buf, buf, *size);
2857         *bytes_copied += *size;
2858
2859         if (buf_size_left == *size)
2860                 return true;
2861         return false;
2862 }
2863
2864 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2865                                            char __user *user_buf,
2866                                            size_t count, loff_t *ppos)
2867 {
2868         struct iwl_trans *trans = file->private_data;
2869         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2870         void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
2871         struct cont_rec *data = &trans_pcie->fw_mon_data;
2872         u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2873         ssize_t size, bytes_copied = 0;
2874         bool b_full;
2875
2876         if (trans->dbg.dest_tlv) {
2877                 write_ptr_addr =
2878                         le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2879                 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2880         } else {
2881                 write_ptr_addr = MON_BUFF_WRPTR;
2882                 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2883         }
2884
2885         if (unlikely(!trans->dbg.rec_on))
2886                 return 0;
2887
2888         mutex_lock(&data->mutex);
2889         if (data->state ==
2890             IWL_FW_MON_DBGFS_STATE_DISABLED) {
2891                 mutex_unlock(&data->mutex);
2892                 return 0;
2893         }
2894
2895         /* write_ptr position in bytes rather then DW */
2896         write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2897         wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2898
2899         if (data->prev_wrap_cnt == wrap_cnt) {
2900                 size = write_ptr - data->prev_wr_ptr;
2901                 curr_buf = cpu_addr + data->prev_wr_ptr;
2902                 b_full = iwl_write_to_user_buf(user_buf, count,
2903                                                curr_buf, &size,
2904                                                &bytes_copied);
2905                 data->prev_wr_ptr += size;
2906
2907         } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2908                    write_ptr < data->prev_wr_ptr) {
2909                 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
2910                 curr_buf = cpu_addr + data->prev_wr_ptr;
2911                 b_full = iwl_write_to_user_buf(user_buf, count,
2912                                                curr_buf, &size,
2913                                                &bytes_copied);
2914                 data->prev_wr_ptr += size;
2915
2916                 if (!b_full) {
2917                         size = write_ptr;
2918                         b_full = iwl_write_to_user_buf(user_buf, count,
2919                                                        cpu_addr, &size,
2920                                                        &bytes_copied);
2921                         data->prev_wr_ptr = size;
2922                         data->prev_wrap_cnt++;
2923                 }
2924         } else {
2925                 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2926                     write_ptr > data->prev_wr_ptr)
2927                         IWL_WARN(trans,
2928                                  "write pointer passed previous write pointer, start copying from the beginning\n");
2929                 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2930                                    data->prev_wr_ptr == 0))
2931                         IWL_WARN(trans,
2932                                  "monitor data is out of sync, start copying from the beginning\n");
2933
2934                 size = write_ptr;
2935                 b_full = iwl_write_to_user_buf(user_buf, count,
2936                                                cpu_addr, &size,
2937                                                &bytes_copied);
2938                 data->prev_wr_ptr = size;
2939                 data->prev_wrap_cnt = wrap_cnt;
2940         }
2941
2942         mutex_unlock(&data->mutex);
2943
2944         return bytes_copied;
2945 }
2946
2947 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2948 DEBUGFS_READ_FILE_OPS(fh_reg);
2949 DEBUGFS_READ_FILE_OPS(rx_queue);
2950 DEBUGFS_WRITE_FILE_OPS(csr);
2951 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2952 static const struct file_operations iwl_dbgfs_tx_queue_ops = {
2953         .owner = THIS_MODULE,
2954         .open = iwl_dbgfs_tx_queue_open,
2955         .read = seq_read,
2956         .llseek = seq_lseek,
2957         .release = seq_release_private,
2958 };
2959
2960 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2961         .read = iwl_dbgfs_monitor_data_read,
2962         .open = iwl_dbgfs_monitor_data_open,
2963         .release = iwl_dbgfs_monitor_data_release,
2964 };
2965
2966 /* Create the debugfs files and directories */
2967 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2968 {
2969         struct dentry *dir = trans->dbgfs_dir;
2970
2971         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2972         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2973         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2974         DEBUGFS_ADD_FILE(csr, dir, 0200);
2975         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2976         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2977         DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
2978 }
2979
2980 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2981 {
2982         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2983         struct cont_rec *data = &trans_pcie->fw_mon_data;
2984
2985         mutex_lock(&data->mutex);
2986         data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2987         mutex_unlock(&data->mutex);
2988 }
2989 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2990
2991 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2992 {
2993         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2994         u32 cmdlen = 0;
2995         int i;
2996
2997         for (i = 0; i < trans_pcie->max_tbs; i++)
2998                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2999
3000         return cmdlen;
3001 }
3002
3003 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
3004                                    struct iwl_fw_error_dump_data **data,
3005                                    int allocated_rb_nums)
3006 {
3007         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3008         int max_len = trans_pcie->rx_buf_bytes;
3009         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3010         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3011         u32 i, r, j, rb_len = 0;
3012
3013         spin_lock(&rxq->lock);
3014
3015         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
3016
3017         for (i = rxq->read, j = 0;
3018              i != r && j < allocated_rb_nums;
3019              i = (i + 1) & RX_QUEUE_MASK, j++) {
3020                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3021                 struct iwl_fw_error_dump_rb *rb;
3022
3023                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
3024                                DMA_FROM_DEVICE);
3025
3026                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3027
3028                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3029                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3030                 rb = (void *)(*data)->data;
3031                 rb->index = cpu_to_le32(i);
3032                 memcpy(rb->data, page_address(rxb->page), max_len);
3033                 /* remap the page for the free benefit */
3034                 rxb->page_dma = dma_map_page(trans->dev, rxb->page,
3035                                              rxb->offset, max_len,
3036                                              DMA_FROM_DEVICE);
3037
3038                 *data = iwl_fw_error_next_data(*data);
3039         }
3040
3041         spin_unlock(&rxq->lock);
3042
3043         return rb_len;
3044 }
3045 #define IWL_CSR_TO_DUMP (0x250)
3046
3047 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3048                                    struct iwl_fw_error_dump_data **data)
3049 {
3050         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3051         __le32 *val;
3052         int i;
3053
3054         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3055         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3056         val = (void *)(*data)->data;
3057
3058         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3059                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3060
3061         *data = iwl_fw_error_next_data(*data);
3062
3063         return csr_len;
3064 }
3065
3066 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3067                                        struct iwl_fw_error_dump_data **data)
3068 {
3069         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3070         unsigned long flags;
3071         __le32 *val;
3072         int i;
3073
3074         if (!iwl_trans_grab_nic_access(trans, &flags))
3075                 return 0;
3076
3077         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3078         (*data)->len = cpu_to_le32(fh_regs_len);
3079         val = (void *)(*data)->data;
3080
3081         if (!trans->trans_cfg->gen2)
3082                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3083                      i += sizeof(u32))
3084                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3085         else
3086                 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3087                      i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3088                      i += sizeof(u32))
3089                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3090                                                                       i));
3091
3092         iwl_trans_release_nic_access(trans, &flags);
3093
3094         *data = iwl_fw_error_next_data(*data);
3095
3096         return sizeof(**data) + fh_regs_len;
3097 }
3098
3099 static u32
3100 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3101                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3102                                  u32 monitor_len)
3103 {
3104         u32 buf_size_in_dwords = (monitor_len >> 2);
3105         u32 *buffer = (u32 *)fw_mon_data->data;
3106         unsigned long flags;
3107         u32 i;
3108
3109         if (!iwl_trans_grab_nic_access(trans, &flags))
3110                 return 0;
3111
3112         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3113         for (i = 0; i < buf_size_in_dwords; i++)
3114                 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3115                                                        MON_DMARB_RD_DATA_ADDR);
3116         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3117
3118         iwl_trans_release_nic_access(trans, &flags);
3119
3120         return monitor_len;
3121 }
3122
3123 static void
3124 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3125                              struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3126 {
3127         u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3128
3129         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3130                 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3131                 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3132                 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3133                 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3134         } else if (trans->dbg.dest_tlv) {
3135                 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3136                 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3137                 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3138         } else {
3139                 base = MON_BUFF_BASE_ADDR;
3140                 write_ptr = MON_BUFF_WRPTR;
3141                 wrap_cnt = MON_BUFF_CYCLE_CNT;
3142         }
3143
3144         write_ptr_val = iwl_read_prph(trans, write_ptr);
3145         fw_mon_data->fw_mon_cycle_cnt =
3146                 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3147         fw_mon_data->fw_mon_base_ptr =
3148                 cpu_to_le32(iwl_read_prph(trans, base));
3149         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3150                 fw_mon_data->fw_mon_base_high_ptr =
3151                         cpu_to_le32(iwl_read_prph(trans, base_high));
3152                 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3153         }
3154         fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3155 }
3156
3157 static u32
3158 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3159                             struct iwl_fw_error_dump_data **data,
3160                             u32 monitor_len)
3161 {
3162         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3163         u32 len = 0;
3164
3165         if (trans->dbg.dest_tlv ||
3166             (fw_mon->size &&
3167              (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3168               trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3169                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3170
3171                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3172                 fw_mon_data = (void *)(*data)->data;
3173
3174                 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3175
3176                 len += sizeof(**data) + sizeof(*fw_mon_data);
3177                 if (fw_mon->size) {
3178                         memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3179                         monitor_len = fw_mon->size;
3180                 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3181                         u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3182                         /*
3183                          * Update pointers to reflect actual values after
3184                          * shifting
3185                          */
3186                         if (trans->dbg.dest_tlv->version) {
3187                                 base = (iwl_read_prph(trans, base) &
3188                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
3189                                        trans->dbg.dest_tlv->base_shift;
3190                                 base *= IWL_M2S_UNIT_SIZE;
3191                                 base += trans->cfg->smem_offset;
3192                         } else {
3193                                 base = iwl_read_prph(trans, base) <<
3194                                        trans->dbg.dest_tlv->base_shift;
3195                         }
3196
3197                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
3198                                            monitor_len / sizeof(u32));
3199                 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3200                         monitor_len =
3201                                 iwl_trans_pci_dump_marbh_monitor(trans,
3202                                                                  fw_mon_data,
3203                                                                  monitor_len);
3204                 } else {
3205                         /* Didn't match anything - output no monitor data */
3206                         monitor_len = 0;
3207                 }
3208
3209                 len += monitor_len;
3210                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3211         }
3212
3213         return len;
3214 }
3215
3216 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3217 {
3218         if (trans->dbg.fw_mon.size) {
3219                 *len += sizeof(struct iwl_fw_error_dump_data) +
3220                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3221                         trans->dbg.fw_mon.size;
3222                 return trans->dbg.fw_mon.size;
3223         } else if (trans->dbg.dest_tlv) {
3224                 u32 base, end, cfg_reg, monitor_len;
3225
3226                 if (trans->dbg.dest_tlv->version == 1) {
3227                         cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3228                         cfg_reg = iwl_read_prph(trans, cfg_reg);
3229                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3230                                 trans->dbg.dest_tlv->base_shift;
3231                         base *= IWL_M2S_UNIT_SIZE;
3232                         base += trans->cfg->smem_offset;
3233
3234                         monitor_len =
3235                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3236                                 trans->dbg.dest_tlv->end_shift;
3237                         monitor_len *= IWL_M2S_UNIT_SIZE;
3238                 } else {
3239                         base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3240                         end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3241
3242                         base = iwl_read_prph(trans, base) <<
3243                                trans->dbg.dest_tlv->base_shift;
3244                         end = iwl_read_prph(trans, end) <<
3245                               trans->dbg.dest_tlv->end_shift;
3246
3247                         /* Make "end" point to the actual end */
3248                         if (trans->trans_cfg->device_family >=
3249                             IWL_DEVICE_FAMILY_8000 ||
3250                             trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3251                                 end += (1 << trans->dbg.dest_tlv->end_shift);
3252                         monitor_len = end - base;
3253                 }
3254                 *len += sizeof(struct iwl_fw_error_dump_data) +
3255                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3256                         monitor_len;
3257                 return monitor_len;
3258         }
3259         return 0;
3260 }
3261
3262 static struct iwl_trans_dump_data
3263 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3264                           u32 dump_mask)
3265 {
3266         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3267         struct iwl_fw_error_dump_data *data;
3268         struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
3269         struct iwl_fw_error_dump_txcmd *txcmd;
3270         struct iwl_trans_dump_data *dump_data;
3271         u32 len, num_rbs = 0, monitor_len = 0;
3272         int i, ptr;
3273         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3274                         !trans->trans_cfg->mq_rx_supported &&
3275                         dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3276
3277         if (!dump_mask)
3278                 return NULL;
3279
3280         /* transport dump header */
3281         len = sizeof(*dump_data);
3282
3283         /* host commands */
3284         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3285                 len += sizeof(*data) +
3286                         cmdq->n_window * (sizeof(*txcmd) +
3287                                           TFD_MAX_PAYLOAD_SIZE);
3288
3289         /* FW monitor */
3290         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3291                 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3292
3293         /* CSR registers */
3294         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3295                 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3296
3297         /* FH registers */
3298         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3299                 if (trans->trans_cfg->gen2)
3300                         len += sizeof(*data) +
3301                                (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3302                                 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3303                 else
3304                         len += sizeof(*data) +
3305                                (FH_MEM_UPPER_BOUND -
3306                                 FH_MEM_LOWER_BOUND);
3307         }
3308
3309         if (dump_rbs) {
3310                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3311                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3312                 /* RBs */
3313                 num_rbs =
3314                         le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3315                         & 0x0FFF;
3316                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3317                 len += num_rbs * (sizeof(*data) +
3318                                   sizeof(struct iwl_fw_error_dump_rb) +
3319                                   (PAGE_SIZE << trans_pcie->rx_page_order));
3320         }
3321
3322         /* Paged memory for gen2 HW */
3323         if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3324                 for (i = 0; i < trans->init_dram.paging_cnt; i++)
3325                         len += sizeof(*data) +
3326                                sizeof(struct iwl_fw_error_dump_paging) +
3327                                trans->init_dram.paging[i].size;
3328
3329         dump_data = vzalloc(len);
3330         if (!dump_data)
3331                 return NULL;
3332
3333         len = 0;
3334         data = (void *)dump_data->data;
3335
3336         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3337                 u16 tfd_size = trans_pcie->tfd_size;
3338
3339                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3340                 txcmd = (void *)data->data;
3341                 spin_lock_bh(&cmdq->lock);
3342                 ptr = cmdq->write_ptr;
3343                 for (i = 0; i < cmdq->n_window; i++) {
3344                         u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
3345                         u8 tfdidx;
3346                         u32 caplen, cmdlen;
3347
3348                         if (trans->trans_cfg->use_tfh)
3349                                 tfdidx = idx;
3350                         else
3351                                 tfdidx = ptr;
3352
3353                         cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3354                                                            (u8 *)cmdq->tfds +
3355                                                            tfd_size * tfdidx);
3356                         caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3357
3358                         if (cmdlen) {
3359                                 len += sizeof(*txcmd) + caplen;
3360                                 txcmd->cmdlen = cpu_to_le32(cmdlen);
3361                                 txcmd->caplen = cpu_to_le32(caplen);
3362                                 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3363                                        caplen);
3364                                 txcmd = (void *)((u8 *)txcmd->data + caplen);
3365                         }
3366
3367                         ptr = iwl_queue_dec_wrap(trans, ptr);
3368                 }
3369                 spin_unlock_bh(&cmdq->lock);
3370
3371                 data->len = cpu_to_le32(len);
3372                 len += sizeof(*data);
3373                 data = iwl_fw_error_next_data(data);
3374         }
3375
3376         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3377                 len += iwl_trans_pcie_dump_csr(trans, &data);
3378         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3379                 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3380         if (dump_rbs)
3381                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3382
3383         /* Paged memory for gen2 HW */
3384         if (trans->trans_cfg->gen2 &&
3385             dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3386                 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3387                         struct iwl_fw_error_dump_paging *paging;
3388                         u32 page_len = trans->init_dram.paging[i].size;
3389
3390                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3391                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3392                         paging = (void *)data->data;
3393                         paging->index = cpu_to_le32(i);
3394                         memcpy(paging->data,
3395                                trans->init_dram.paging[i].block, page_len);
3396                         data = iwl_fw_error_next_data(data);
3397
3398                         len += sizeof(*data) + sizeof(*paging) + page_len;
3399                 }
3400         }
3401         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3402                 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3403
3404         dump_data->len = len;
3405
3406         return dump_data;
3407 }
3408
3409 #ifdef CONFIG_PM_SLEEP
3410 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3411 {
3412         return 0;
3413 }
3414
3415 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3416 {
3417 }
3418 #endif /* CONFIG_PM_SLEEP */
3419
3420 #define IWL_TRANS_COMMON_OPS                                            \
3421         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3422         .write8 = iwl_trans_pcie_write8,                                \
3423         .write32 = iwl_trans_pcie_write32,                              \
3424         .read32 = iwl_trans_pcie_read32,                                \
3425         .read_prph = iwl_trans_pcie_read_prph,                          \
3426         .write_prph = iwl_trans_pcie_write_prph,                        \
3427         .read_mem = iwl_trans_pcie_read_mem,                            \
3428         .write_mem = iwl_trans_pcie_write_mem,                          \
3429         .read_config32 = iwl_trans_pcie_read_config32,                  \
3430         .configure = iwl_trans_pcie_configure,                          \
3431         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3432         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3433         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3434         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3435         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3436         .dump_data = iwl_trans_pcie_dump_data,                          \
3437         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3438         .d3_resume = iwl_trans_pcie_d3_resume,                          \
3439         .sync_nmi = iwl_trans_pcie_sync_nmi
3440
3441 #ifdef CONFIG_PM_SLEEP
3442 #define IWL_TRANS_PM_OPS                                                \
3443         .suspend = iwl_trans_pcie_suspend,                              \
3444         .resume = iwl_trans_pcie_resume,
3445 #else
3446 #define IWL_TRANS_PM_OPS
3447 #endif /* CONFIG_PM_SLEEP */
3448
3449 static const struct iwl_trans_ops trans_ops_pcie = {
3450         IWL_TRANS_COMMON_OPS,
3451         IWL_TRANS_PM_OPS
3452         .start_hw = iwl_trans_pcie_start_hw,
3453         .fw_alive = iwl_trans_pcie_fw_alive,
3454         .start_fw = iwl_trans_pcie_start_fw,
3455         .stop_device = iwl_trans_pcie_stop_device,
3456
3457         .send_cmd = iwl_trans_pcie_send_hcmd,
3458
3459         .tx = iwl_trans_pcie_tx,
3460         .reclaim = iwl_trans_pcie_reclaim,
3461
3462         .txq_disable = iwl_trans_pcie_txq_disable,
3463         .txq_enable = iwl_trans_pcie_txq_enable,
3464
3465         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3466
3467         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3468
3469         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3470         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3471 #ifdef CONFIG_IWLWIFI_DEBUGFS
3472         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3473 #endif
3474 };
3475
3476 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3477         IWL_TRANS_COMMON_OPS,
3478         IWL_TRANS_PM_OPS
3479         .start_hw = iwl_trans_pcie_start_hw,
3480         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3481         .start_fw = iwl_trans_pcie_gen2_start_fw,
3482         .stop_device = iwl_trans_pcie_gen2_stop_device,
3483
3484         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3485
3486         .tx = iwl_trans_pcie_gen2_tx,
3487         .reclaim = iwl_trans_pcie_reclaim,
3488
3489         .set_q_ptrs = iwl_trans_pcie_set_q_ptrs,
3490
3491         .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3492         .txq_free = iwl_trans_pcie_dyn_txq_free,
3493         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3494         .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3495 #ifdef CONFIG_IWLWIFI_DEBUGFS
3496         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3497 #endif
3498 };
3499
3500 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3501                                const struct pci_device_id *ent,
3502                                const struct iwl_cfg_trans_params *cfg_trans)
3503 {
3504         struct iwl_trans_pcie *trans_pcie;
3505         struct iwl_trans *trans;
3506         int ret, addr_size, txcmd_size, txcmd_align;
3507         const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3508
3509         if (!cfg_trans->gen2) {
3510                 ops = &trans_ops_pcie;
3511                 txcmd_size = sizeof(struct iwl_tx_cmd);
3512                 txcmd_align = sizeof(void *);
3513         } else if (cfg_trans->device_family < IWL_DEVICE_FAMILY_AX210) {
3514                 txcmd_size = sizeof(struct iwl_tx_cmd_gen2);
3515                 txcmd_align = 64;
3516         } else {
3517                 txcmd_size = sizeof(struct iwl_tx_cmd_gen3);
3518                 txcmd_align = 128;
3519         }
3520
3521         txcmd_size += sizeof(struct iwl_cmd_header);
3522         txcmd_size += 36; /* biggest possible 802.11 header */
3523
3524         /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */
3525         if (WARN_ON(cfg_trans->gen2 && txcmd_size >= txcmd_align))
3526                 return ERR_PTR(-EINVAL);
3527
3528         ret = pcim_enable_device(pdev);
3529         if (ret)
3530                 return ERR_PTR(ret);
3531
3532         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3533                                 txcmd_size, txcmd_align);
3534         if (!trans)