f30031945ee4b671033a0d80583d05c0724a096e
[muen/linux.git] / drivers / nvme / host / pci.c
1 /*
2  * NVM Express device driver
3  * Copyright (c) 2011-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/mm.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
33 #include <linux/pci-p2pdma.h>
34
35 #include "nvme.h"
36
37 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
38 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
39
40 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
41
42 /*
43  * These can be higher, but we need to ensure that any command doesn't
44  * require an sg allocation that needs more than a page of data.
45  */
46 #define NVME_MAX_KB_SZ  4096
47 #define NVME_MAX_SEGS   127
48
49 static int use_threaded_interrupts;
50 module_param(use_threaded_interrupts, int, 0);
51
52 static bool use_cmb_sqes = true;
53 module_param(use_cmb_sqes, bool, 0444);
54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55
56 static unsigned int max_host_mem_size_mb = 128;
57 module_param(max_host_mem_size_mb, uint, 0444);
58 MODULE_PARM_DESC(max_host_mem_size_mb,
59         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
60
61 static unsigned int sgl_threshold = SZ_32K;
62 module_param(sgl_threshold, uint, 0644);
63 MODULE_PARM_DESC(sgl_threshold,
64                 "Use SGLs when average request segment size is larger or equal to "
65                 "this size. Use 0 to disable SGLs.");
66
67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops io_queue_depth_ops = {
69         .set = io_queue_depth_set,
70         .get = param_get_int,
71 };
72
73 static int io_queue_depth = 1024;
74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
76
77 struct nvme_dev;
78 struct nvme_queue;
79
80 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
81
82 /*
83  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
84  */
85 struct nvme_dev {
86         struct nvme_queue *queues;
87         struct blk_mq_tag_set tagset;
88         struct blk_mq_tag_set admin_tagset;
89         u32 __iomem *dbs;
90         struct device *dev;
91         struct dma_pool *prp_page_pool;
92         struct dma_pool *prp_small_pool;
93         unsigned online_queues;
94         unsigned max_qid;
95         unsigned int num_vecs;
96         int q_depth;
97         u32 db_stride;
98         void __iomem *bar;
99         unsigned long bar_mapped_size;
100         struct work_struct remove_work;
101         struct mutex shutdown_lock;
102         bool subsystem;
103         u64 cmb_size;
104         bool cmb_use_sqes;
105         u32 cmbsz;
106         u32 cmbloc;
107         struct nvme_ctrl ctrl;
108         struct completion ioq_wait;
109
110         mempool_t *iod_mempool;
111
112         /* shadow doorbell buffer support: */
113         u32 *dbbuf_dbs;
114         dma_addr_t dbbuf_dbs_dma_addr;
115         u32 *dbbuf_eis;
116         dma_addr_t dbbuf_eis_dma_addr;
117
118         /* host memory buffer support: */
119         u64 host_mem_size;
120         u32 nr_host_mem_descs;
121         dma_addr_t host_mem_descs_dma;
122         struct nvme_host_mem_buf_desc *host_mem_descs;
123         void **host_mem_desc_bufs;
124 };
125
126 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
127 {
128         int n = 0, ret;
129
130         ret = kstrtoint(val, 10, &n);
131         if (ret != 0 || n < 2)
132                 return -EINVAL;
133
134         return param_set_int(val, kp);
135 }
136
137 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
138 {
139         return qid * 2 * stride;
140 }
141
142 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
143 {
144         return (qid * 2 + 1) * stride;
145 }
146
147 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
148 {
149         return container_of(ctrl, struct nvme_dev, ctrl);
150 }
151
152 /*
153  * An NVM Express queue.  Each device has at least two (one for admin
154  * commands and one for I/O commands).
155  */
156 struct nvme_queue {
157         struct device *q_dmadev;
158         struct nvme_dev *dev;
159         spinlock_t sq_lock;
160         struct nvme_command *sq_cmds;
161         bool sq_cmds_is_io;
162         spinlock_t cq_lock ____cacheline_aligned_in_smp;
163         volatile struct nvme_completion *cqes;
164         struct blk_mq_tags **tags;
165         dma_addr_t sq_dma_addr;
166         dma_addr_t cq_dma_addr;
167         u32 __iomem *q_db;
168         u16 q_depth;
169         s16 cq_vector;
170         u16 sq_tail;
171         u16 cq_head;
172         u16 last_cq_head;
173         u16 qid;
174         u8 cq_phase;
175         u32 *dbbuf_sq_db;
176         u32 *dbbuf_cq_db;
177         u32 *dbbuf_sq_ei;
178         u32 *dbbuf_cq_ei;
179 };
180
181 /*
182  * The nvme_iod describes the data in an I/O, including the list of PRP
183  * entries.  You can't see it in this data structure because C doesn't let
184  * me express that.  Use nvme_init_iod to ensure there's enough space
185  * allocated to store the PRP list.
186  */
187 struct nvme_iod {
188         struct nvme_request req;
189         struct nvme_queue *nvmeq;
190         bool use_sgl;
191         int aborted;
192         int npages;             /* In the PRP list. 0 means small pool in use */
193         int nents;              /* Used in scatterlist */
194         int length;             /* Of data, in bytes */
195         dma_addr_t first_dma;
196         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
197         struct scatterlist *sg;
198         struct scatterlist inline_sg[0];
199 };
200
201 /*
202  * Check we didin't inadvertently grow the command struct
203  */
204 static inline void _nvme_check_size(void)
205 {
206         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
207         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
208         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
209         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
210         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
211         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
212         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
213         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
214         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
215         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
216         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
217         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
218         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
219 }
220
221 static inline unsigned int nvme_dbbuf_size(u32 stride)
222 {
223         return ((num_possible_cpus() + 1) * 8 * stride);
224 }
225
226 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
227 {
228         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
229
230         if (dev->dbbuf_dbs)
231                 return 0;
232
233         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
234                                             &dev->dbbuf_dbs_dma_addr,
235                                             GFP_KERNEL);
236         if (!dev->dbbuf_dbs)
237                 return -ENOMEM;
238         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
239                                             &dev->dbbuf_eis_dma_addr,
240                                             GFP_KERNEL);
241         if (!dev->dbbuf_eis) {
242                 dma_free_coherent(dev->dev, mem_size,
243                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
244                 dev->dbbuf_dbs = NULL;
245                 return -ENOMEM;
246         }
247
248         return 0;
249 }
250
251 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
252 {
253         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
254
255         if (dev->dbbuf_dbs) {
256                 dma_free_coherent(dev->dev, mem_size,
257                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
258                 dev->dbbuf_dbs = NULL;
259         }
260         if (dev->dbbuf_eis) {
261                 dma_free_coherent(dev->dev, mem_size,
262                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
263                 dev->dbbuf_eis = NULL;
264         }
265 }
266
267 static void nvme_dbbuf_init(struct nvme_dev *dev,
268                             struct nvme_queue *nvmeq, int qid)
269 {
270         if (!dev->dbbuf_dbs || !qid)
271                 return;
272
273         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
274         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
275         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
276         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
277 }
278
279 static void nvme_dbbuf_set(struct nvme_dev *dev)
280 {
281         struct nvme_command c;
282
283         if (!dev->dbbuf_dbs)
284                 return;
285
286         memset(&c, 0, sizeof(c));
287         c.dbbuf.opcode = nvme_admin_dbbuf;
288         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
289         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
290
291         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
292                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
293                 /* Free memory and continue on */
294                 nvme_dbbuf_dma_free(dev);
295         }
296 }
297
298 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
299 {
300         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
301 }
302
303 /* Update dbbuf and return true if an MMIO is required */
304 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
305                                               volatile u32 *dbbuf_ei)
306 {
307         if (dbbuf_db) {
308                 u16 old_value;
309
310                 /*
311                  * Ensure that the queue is written before updating
312                  * the doorbell in memory
313                  */
314                 wmb();
315
316                 old_value = *dbbuf_db;
317                 *dbbuf_db = value;
318
319                 /*
320                  * Ensure that the doorbell is updated before reading the event
321                  * index from memory.  The controller needs to provide similar
322                  * ordering to ensure the envent index is updated before reading
323                  * the doorbell.
324                  */
325                 mb();
326
327                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
328                         return false;
329         }
330
331         return true;
332 }
333
334 /*
335  * Max size of iod being embedded in the request payload
336  */
337 #define NVME_INT_PAGES          2
338 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
339
340 /*
341  * Will slightly overestimate the number of pages needed.  This is OK
342  * as it only leads to a small amount of wasted memory for the lifetime of
343  * the I/O.
344  */
345 static int nvme_npages(unsigned size, struct nvme_dev *dev)
346 {
347         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
348                                       dev->ctrl.page_size);
349         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
350 }
351
352 /*
353  * Calculates the number of pages needed for the SGL segments. For example a 4k
354  * page can accommodate 256 SGL descriptors.
355  */
356 static int nvme_pci_npages_sgl(unsigned int num_seg)
357 {
358         return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
359 }
360
361 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
362                 unsigned int size, unsigned int nseg, bool use_sgl)
363 {
364         size_t alloc_size;
365
366         if (use_sgl)
367                 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
368         else
369                 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
370
371         return alloc_size + sizeof(struct scatterlist) * nseg;
372 }
373
374 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
375 {
376         unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
377                                     NVME_INT_BYTES(dev), NVME_INT_PAGES,
378                                     use_sgl);
379
380         return sizeof(struct nvme_iod) + alloc_size;
381 }
382
383 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
384                                 unsigned int hctx_idx)
385 {
386         struct nvme_dev *dev = data;
387         struct nvme_queue *nvmeq = &dev->queues[0];
388
389         WARN_ON(hctx_idx != 0);
390         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
391         WARN_ON(nvmeq->tags);
392
393         hctx->driver_data = nvmeq;
394         nvmeq->tags = &dev->admin_tagset.tags[0];
395         return 0;
396 }
397
398 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
399 {
400         struct nvme_queue *nvmeq = hctx->driver_data;
401
402         nvmeq->tags = NULL;
403 }
404
405 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
406                           unsigned int hctx_idx)
407 {
408         struct nvme_dev *dev = data;
409         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
410
411         if (!nvmeq->tags)
412                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
413
414         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415         hctx->driver_data = nvmeq;
416         return 0;
417 }
418
419 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
420                 unsigned int hctx_idx, unsigned int numa_node)
421 {
422         struct nvme_dev *dev = set->driver_data;
423         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
424         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
425         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
426
427         BUG_ON(!nvmeq);
428         iod->nvmeq = nvmeq;
429
430         nvme_req(req)->ctrl = &dev->ctrl;
431         return 0;
432 }
433
434 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
435 {
436         struct nvme_dev *dev = set->driver_data;
437
438         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
439                         dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
440 }
441
442 /**
443  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
444  * @nvmeq: The queue to use
445  * @cmd: The command to send
446  */
447 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
448 {
449         spin_lock(&nvmeq->sq_lock);
450
451         memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
452
453         if (++nvmeq->sq_tail == nvmeq->q_depth)
454                 nvmeq->sq_tail = 0;
455         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
456                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
457                 writel(nvmeq->sq_tail, nvmeq->q_db);
458         spin_unlock(&nvmeq->sq_lock);
459 }
460
461 static void **nvme_pci_iod_list(struct request *req)
462 {
463         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
464         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
465 }
466
467 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
468 {
469         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
470         int nseg = blk_rq_nr_phys_segments(req);
471         unsigned int avg_seg_size;
472
473         if (nseg == 0)
474                 return false;
475
476         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
477
478         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
479                 return false;
480         if (!iod->nvmeq->qid)
481                 return false;
482         if (!sgl_threshold || avg_seg_size < sgl_threshold)
483                 return false;
484         return true;
485 }
486
487 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
488 {
489         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
490         int nseg = blk_rq_nr_phys_segments(rq);
491         unsigned int size = blk_rq_payload_bytes(rq);
492
493         iod->use_sgl = nvme_pci_use_sgls(dev, rq);
494
495         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
496                 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
497                 if (!iod->sg)
498                         return BLK_STS_RESOURCE;
499         } else {
500                 iod->sg = iod->inline_sg;
501         }
502
503         iod->aborted = 0;
504         iod->npages = -1;
505         iod->nents = 0;
506         iod->length = size;
507
508         return BLK_STS_OK;
509 }
510
511 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
512 {
513         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
514         const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
515         dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
516
517         int i;
518
519         if (iod->npages == 0)
520                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
521                         dma_addr);
522
523         for (i = 0; i < iod->npages; i++) {
524                 void *addr = nvme_pci_iod_list(req)[i];
525
526                 if (iod->use_sgl) {
527                         struct nvme_sgl_desc *sg_list = addr;
528
529                         next_dma_addr =
530                             le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
531                 } else {
532                         __le64 *prp_list = addr;
533
534                         next_dma_addr = le64_to_cpu(prp_list[last_prp]);
535                 }
536
537                 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
538                 dma_addr = next_dma_addr;
539         }
540
541         if (iod->sg != iod->inline_sg)
542                 mempool_free(iod->sg, dev->iod_mempool);
543 }
544
545 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
546 {
547         int i;
548         struct scatterlist *sg;
549
550         for_each_sg(sgl, sg, nents, i) {
551                 dma_addr_t phys = sg_phys(sg);
552                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
553                         "dma_address:%pad dma_length:%d\n",
554                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
555                         sg_dma_len(sg));
556         }
557 }
558
559 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
560                 struct request *req, struct nvme_rw_command *cmnd)
561 {
562         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
563         struct dma_pool *pool;
564         int length = blk_rq_payload_bytes(req);
565         struct scatterlist *sg = iod->sg;
566         int dma_len = sg_dma_len(sg);
567         u64 dma_addr = sg_dma_address(sg);
568         u32 page_size = dev->ctrl.page_size;
569         int offset = dma_addr & (page_size - 1);
570         __le64 *prp_list;
571         void **list = nvme_pci_iod_list(req);
572         dma_addr_t prp_dma;
573         int nprps, i;
574
575         length -= (page_size - offset);
576         if (length <= 0) {
577                 iod->first_dma = 0;
578                 goto done;
579         }
580
581         dma_len -= (page_size - offset);
582         if (dma_len) {
583                 dma_addr += (page_size - offset);
584         } else {
585                 sg = sg_next(sg);
586                 dma_addr = sg_dma_address(sg);
587                 dma_len = sg_dma_len(sg);
588         }
589
590         if (length <= page_size) {
591                 iod->first_dma = dma_addr;
592                 goto done;
593         }
594
595         nprps = DIV_ROUND_UP(length, page_size);
596         if (nprps <= (256 / 8)) {
597                 pool = dev->prp_small_pool;
598                 iod->npages = 0;
599         } else {
600                 pool = dev->prp_page_pool;
601                 iod->npages = 1;
602         }
603
604         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
605         if (!prp_list) {
606                 iod->first_dma = dma_addr;
607                 iod->npages = -1;
608                 return BLK_STS_RESOURCE;
609         }
610         list[0] = prp_list;
611         iod->first_dma = prp_dma;
612         i = 0;
613         for (;;) {
614                 if (i == page_size >> 3) {
615                         __le64 *old_prp_list = prp_list;
616                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
617                         if (!prp_list)
618                                 return BLK_STS_RESOURCE;
619                         list[iod->npages++] = prp_list;
620                         prp_list[0] = old_prp_list[i - 1];
621                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
622                         i = 1;
623                 }
624                 prp_list[i++] = cpu_to_le64(dma_addr);
625                 dma_len -= page_size;
626                 dma_addr += page_size;
627                 length -= page_size;
628                 if (length <= 0)
629                         break;
630                 if (dma_len > 0)
631                         continue;
632                 if (unlikely(dma_len < 0))
633                         goto bad_sgl;
634                 sg = sg_next(sg);
635                 dma_addr = sg_dma_address(sg);
636                 dma_len = sg_dma_len(sg);
637         }
638
639 done:
640         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
641         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
642
643         return BLK_STS_OK;
644
645  bad_sgl:
646         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
647                         "Invalid SGL for payload:%d nents:%d\n",
648                         blk_rq_payload_bytes(req), iod->nents);
649         return BLK_STS_IOERR;
650 }
651
652 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
653                 struct scatterlist *sg)
654 {
655         sge->addr = cpu_to_le64(sg_dma_address(sg));
656         sge->length = cpu_to_le32(sg_dma_len(sg));
657         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
658 }
659
660 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
661                 dma_addr_t dma_addr, int entries)
662 {
663         sge->addr = cpu_to_le64(dma_addr);
664         if (entries < SGES_PER_PAGE) {
665                 sge->length = cpu_to_le32(entries * sizeof(*sge));
666                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
667         } else {
668                 sge->length = cpu_to_le32(PAGE_SIZE);
669                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
670         }
671 }
672
673 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
674                 struct request *req, struct nvme_rw_command *cmd, int entries)
675 {
676         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
677         struct dma_pool *pool;
678         struct nvme_sgl_desc *sg_list;
679         struct scatterlist *sg = iod->sg;
680         dma_addr_t sgl_dma;
681         int i = 0;
682
683         /* setting the transfer type as SGL */
684         cmd->flags = NVME_CMD_SGL_METABUF;
685
686         if (entries == 1) {
687                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
688                 return BLK_STS_OK;
689         }
690
691         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
692                 pool = dev->prp_small_pool;
693                 iod->npages = 0;
694         } else {
695                 pool = dev->prp_page_pool;
696                 iod->npages = 1;
697         }
698
699         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
700         if (!sg_list) {
701                 iod->npages = -1;
702                 return BLK_STS_RESOURCE;
703         }
704
705         nvme_pci_iod_list(req)[0] = sg_list;
706         iod->first_dma = sgl_dma;
707
708         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
709
710         do {
711                 if (i == SGES_PER_PAGE) {
712                         struct nvme_sgl_desc *old_sg_desc = sg_list;
713                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
714
715                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
716                         if (!sg_list)
717                                 return BLK_STS_RESOURCE;
718
719                         i = 0;
720                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
721                         sg_list[i++] = *link;
722                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
723                 }
724
725                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
726                 sg = sg_next(sg);
727         } while (--entries > 0);
728
729         return BLK_STS_OK;
730 }
731
732 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
733                 struct nvme_command *cmnd)
734 {
735         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
736         struct request_queue *q = req->q;
737         enum dma_data_direction dma_dir = rq_data_dir(req) ?
738                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
739         blk_status_t ret = BLK_STS_IOERR;
740         int nr_mapped;
741
742         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
743         iod->nents = blk_rq_map_sg(q, req, iod->sg);
744         if (!iod->nents)
745                 goto out;
746
747         ret = BLK_STS_RESOURCE;
748
749         if (is_pci_p2pdma_page(sg_page(iod->sg)))
750                 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
751                                           dma_dir);
752         else
753                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
754                                              dma_dir,  DMA_ATTR_NO_WARN);
755         if (!nr_mapped)
756                 goto out;
757
758         if (iod->use_sgl)
759                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
760         else
761                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
762
763         if (ret != BLK_STS_OK)
764                 goto out_unmap;
765
766         ret = BLK_STS_IOERR;
767         if (blk_integrity_rq(req)) {
768                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
769                         goto out_unmap;
770
771                 sg_init_table(&iod->meta_sg, 1);
772                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
773                         goto out_unmap;
774
775                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
776                         goto out_unmap;
777
778                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
779         }
780
781         return BLK_STS_OK;
782
783 out_unmap:
784         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
785 out:
786         return ret;
787 }
788
789 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
790 {
791         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
792         enum dma_data_direction dma_dir = rq_data_dir(req) ?
793                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
794
795         if (iod->nents) {
796                 /* P2PDMA requests do not need to be unmapped */
797                 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
798                         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
799
800                 if (blk_integrity_rq(req))
801                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
802         }
803
804         nvme_cleanup_cmd(req);
805         nvme_free_iod(dev, req);
806 }
807
808 /*
809  * NOTE: ns is NULL when called on the admin queue.
810  */
811 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
812                          const struct blk_mq_queue_data *bd)
813 {
814         struct nvme_ns *ns = hctx->queue->queuedata;
815         struct nvme_queue *nvmeq = hctx->driver_data;
816         struct nvme_dev *dev = nvmeq->dev;
817         struct request *req = bd->rq;
818         struct nvme_command cmnd;
819         blk_status_t ret;
820
821         /*
822          * We should not need to do this, but we're still using this to
823          * ensure we can drain requests on a dying queue.
824          */
825         if (unlikely(nvmeq->cq_vector < 0))
826                 return BLK_STS_IOERR;
827
828         ret = nvme_setup_cmd(ns, req, &cmnd);
829         if (ret)
830                 return ret;
831
832         ret = nvme_init_iod(req, dev);
833         if (ret)
834                 goto out_free_cmd;
835
836         if (blk_rq_nr_phys_segments(req)) {
837                 ret = nvme_map_data(dev, req, &cmnd);
838                 if (ret)
839                         goto out_cleanup_iod;
840         }
841
842         blk_mq_start_request(req);
843         nvme_submit_cmd(nvmeq, &cmnd);
844         return BLK_STS_OK;
845 out_cleanup_iod:
846         nvme_free_iod(dev, req);
847 out_free_cmd:
848         nvme_cleanup_cmd(req);
849         return ret;
850 }
851
852 static void nvme_pci_complete_rq(struct request *req)
853 {
854         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
855
856         nvme_unmap_data(iod->nvmeq->dev, req);
857         nvme_complete_rq(req);
858 }
859
860 /* We read the CQE phase first to check if the rest of the entry is valid */
861 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
862 {
863         return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
864                         nvmeq->cq_phase;
865 }
866
867 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
868 {
869         u16 head = nvmeq->cq_head;
870
871         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
872                                               nvmeq->dbbuf_cq_ei))
873                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
874 }
875
876 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
877 {
878         volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
879         struct request *req;
880
881         if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
882                 dev_warn(nvmeq->dev->ctrl.device,
883                         "invalid id %d completed on queue %d\n",
884                         cqe->command_id, le16_to_cpu(cqe->sq_id));
885                 return;
886         }
887
888         /*
889          * AEN requests are special as they don't time out and can
890          * survive any kind of queue freeze and often don't respond to
891          * aborts.  We don't even bother to allocate a struct request
892          * for them but rather special case them here.
893          */
894         if (unlikely(nvmeq->qid == 0 &&
895                         cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
896                 nvme_complete_async_event(&nvmeq->dev->ctrl,
897                                 cqe->status, &cqe->result);
898                 return;
899         }
900
901         req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
902         nvme_end_request(req, cqe->status, cqe->result);
903 }
904
905 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
906 {
907         while (start != end) {
908                 nvme_handle_cqe(nvmeq, start);
909                 if (++start == nvmeq->q_depth)
910                         start = 0;
911         }
912 }
913
914 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
915 {
916         if (++nvmeq->cq_head == nvmeq->q_depth) {
917                 nvmeq->cq_head = 0;
918                 nvmeq->cq_phase = !nvmeq->cq_phase;
919         }
920 }
921
922 static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
923                 u16 *end, int tag)
924 {
925         bool found = false;
926
927         *start = nvmeq->cq_head;
928         while (!found && nvme_cqe_pending(nvmeq)) {
929                 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
930                         found = true;
931                 nvme_update_cq_head(nvmeq);
932         }
933         *end = nvmeq->cq_head;
934
935         if (*start != *end)
936                 nvme_ring_cq_doorbell(nvmeq);
937         return found;
938 }
939
940 static irqreturn_t nvme_irq(int irq, void *data)
941 {
942         struct nvme_queue *nvmeq = data;
943         irqreturn_t ret = IRQ_NONE;
944         u16 start, end;
945
946         spin_lock(&nvmeq->cq_lock);
947         if (nvmeq->cq_head != nvmeq->last_cq_head)
948                 ret = IRQ_HANDLED;
949         nvme_process_cq(nvmeq, &start, &end, -1);
950         nvmeq->last_cq_head = nvmeq->cq_head;
951         spin_unlock(&nvmeq->cq_lock);
952
953         if (start != end) {
954                 nvme_complete_cqes(nvmeq, start, end);
955                 return IRQ_HANDLED;
956         }
957
958         return ret;
959 }
960
961 static irqreturn_t nvme_irq_check(int irq, void *data)
962 {
963         struct nvme_queue *nvmeq = data;
964         if (nvme_cqe_pending(nvmeq))
965                 return IRQ_WAKE_THREAD;
966         return IRQ_NONE;
967 }
968
969 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
970 {
971         u16 start, end;
972         bool found;
973
974         if (!nvme_cqe_pending(nvmeq))
975                 return 0;
976
977         spin_lock_irq(&nvmeq->cq_lock);
978         found = nvme_process_cq(nvmeq, &start, &end, tag);
979         spin_unlock_irq(&nvmeq->cq_lock);
980
981         nvme_complete_cqes(nvmeq, start, end);
982         return found;
983 }
984
985 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
986 {
987         struct nvme_queue *nvmeq = hctx->driver_data;
988
989         return __nvme_poll(nvmeq, tag);
990 }
991
992 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
993 {
994         struct nvme_dev *dev = to_nvme_dev(ctrl);
995         struct nvme_queue *nvmeq = &dev->queues[0];
996         struct nvme_command c;
997
998         memset(&c, 0, sizeof(c));
999         c.common.opcode = nvme_admin_async_event;
1000         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1001         nvme_submit_cmd(nvmeq, &c);
1002 }
1003
1004 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1005 {
1006         struct nvme_command c;
1007
1008         memset(&c, 0, sizeof(c));
1009         c.delete_queue.opcode = opcode;
1010         c.delete_queue.qid = cpu_to_le16(id);
1011
1012         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1013 }
1014
1015 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1016                 struct nvme_queue *nvmeq, s16 vector)
1017 {
1018         struct nvme_command c;
1019         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1020
1021         /*
1022          * Note: we (ab)use the fact that the prp fields survive if no data
1023          * is attached to the request.
1024          */
1025         memset(&c, 0, sizeof(c));
1026         c.create_cq.opcode = nvme_admin_create_cq;
1027         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1028         c.create_cq.cqid = cpu_to_le16(qid);
1029         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1030         c.create_cq.cq_flags = cpu_to_le16(flags);
1031         c.create_cq.irq_vector = cpu_to_le16(vector);
1032
1033         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1034 }
1035
1036 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1037                                                 struct nvme_queue *nvmeq)
1038 {
1039         struct nvme_ctrl *ctrl = &dev->ctrl;
1040         struct nvme_command c;
1041         int flags = NVME_QUEUE_PHYS_CONTIG;
1042
1043         /*
1044          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1045          * set. Since URGENT priority is zeroes, it makes all queues
1046          * URGENT.
1047          */
1048         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1049                 flags |= NVME_SQ_PRIO_MEDIUM;
1050
1051         /*
1052          * Note: we (ab)use the fact that the prp fields survive if no data
1053          * is attached to the request.
1054          */
1055         memset(&c, 0, sizeof(c));
1056         c.create_sq.opcode = nvme_admin_create_sq;
1057         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1058         c.create_sq.sqid = cpu_to_le16(qid);
1059         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1060         c.create_sq.sq_flags = cpu_to_le16(flags);
1061         c.create_sq.cqid = cpu_to_le16(qid);
1062
1063         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1064 }
1065
1066 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1067 {
1068         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1069 }
1070
1071 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1072 {
1073         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1074 }
1075
1076 static void abort_endio(struct request *req, blk_status_t error)
1077 {
1078         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1079         struct nvme_queue *nvmeq = iod->nvmeq;
1080
1081         dev_warn(nvmeq->dev->ctrl.device,
1082                  "Abort status: 0x%x", nvme_req(req)->status);
1083         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1084         blk_mq_free_request(req);
1085 }
1086
1087 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1088 {
1089
1090         /* If true, indicates loss of adapter communication, possibly by a
1091          * NVMe Subsystem reset.
1092          */
1093         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1094
1095         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1096         switch (dev->ctrl.state) {
1097         case NVME_CTRL_RESETTING:
1098         case NVME_CTRL_CONNECTING:
1099                 return false;
1100         default:
1101                 break;
1102         }
1103
1104         /* We shouldn't reset unless the controller is on fatal error state
1105          * _or_ if we lost the communication with it.
1106          */
1107         if (!(csts & NVME_CSTS_CFS) && !nssro)
1108                 return false;
1109
1110         return true;
1111 }
1112
1113 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1114 {
1115         /* Read a config register to help see what died. */
1116         u16 pci_status;
1117         int result;
1118
1119         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1120                                       &pci_status);
1121         if (result == PCIBIOS_SUCCESSFUL)
1122                 dev_warn(dev->ctrl.device,
1123                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1124                          csts, pci_status);
1125         else
1126                 dev_warn(dev->ctrl.device,
1127                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1128                          csts, result);
1129 }
1130
1131 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1132 {
1133         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1134         struct nvme_queue *nvmeq = iod->nvmeq;
1135         struct nvme_dev *dev = nvmeq->dev;
1136         struct request *abort_req;
1137         struct nvme_command cmd;
1138         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1139
1140         /* If PCI error recovery process is happening, we cannot reset or
1141          * the recovery mechanism will surely fail.
1142          */
1143         mb();
1144         if (pci_channel_offline(to_pci_dev(dev->dev)))
1145                 return BLK_EH_RESET_TIMER;
1146
1147         /*
1148          * Reset immediately if the controller is failed
1149          */
1150         if (nvme_should_reset(dev, csts)) {
1151                 nvme_warn_reset(dev, csts);
1152                 nvme_dev_disable(dev, false);
1153                 nvme_reset_ctrl(&dev->ctrl);
1154                 return BLK_EH_DONE;
1155         }
1156
1157         /*
1158          * Did we miss an interrupt?
1159          */
1160         if (__nvme_poll(nvmeq, req->tag)) {
1161                 dev_warn(dev->ctrl.device,
1162                          "I/O %d QID %d timeout, completion polled\n",
1163                          req->tag, nvmeq->qid);
1164                 return BLK_EH_DONE;
1165         }
1166
1167         /*
1168          * Shutdown immediately if controller times out while starting. The
1169          * reset work will see the pci device disabled when it gets the forced
1170          * cancellation error. All outstanding requests are completed on
1171          * shutdown, so we return BLK_EH_DONE.
1172          */
1173         switch (dev->ctrl.state) {
1174         case NVME_CTRL_CONNECTING:
1175         case NVME_CTRL_RESETTING:
1176                 dev_warn_ratelimited(dev->ctrl.device,
1177                          "I/O %d QID %d timeout, disable controller\n",
1178                          req->tag, nvmeq->qid);
1179                 nvme_dev_disable(dev, false);
1180                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1181                 return BLK_EH_DONE;
1182         default:
1183                 break;
1184         }
1185
1186         /*
1187          * Shutdown the controller immediately and schedule a reset if the
1188          * command was already aborted once before and still hasn't been
1189          * returned to the driver, or if this is the admin queue.
1190          */
1191         if (!nvmeq->qid || iod->aborted) {
1192                 dev_warn(dev->ctrl.device,
1193                          "I/O %d QID %d timeout, reset controller\n",
1194                          req->tag, nvmeq->qid);
1195                 nvme_dev_disable(dev, false);
1196                 nvme_reset_ctrl(&dev->ctrl);
1197
1198                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1199                 return BLK_EH_DONE;
1200         }
1201
1202         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1203                 atomic_inc(&dev->ctrl.abort_limit);
1204                 return BLK_EH_RESET_TIMER;
1205         }
1206         iod->aborted = 1;
1207
1208         memset(&cmd, 0, sizeof(cmd));
1209         cmd.abort.opcode = nvme_admin_abort_cmd;
1210         cmd.abort.cid = req->tag;
1211         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1212
1213         dev_warn(nvmeq->dev->ctrl.device,
1214                 "I/O %d QID %d timeout, aborting\n",
1215                  req->tag, nvmeq->qid);
1216
1217         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1218                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1219         if (IS_ERR(abort_req)) {
1220                 atomic_inc(&dev->ctrl.abort_limit);
1221                 return BLK_EH_RESET_TIMER;
1222         }
1223
1224         abort_req->timeout = ADMIN_TIMEOUT;
1225         abort_req->end_io_data = NULL;
1226         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1227
1228         /*
1229          * The aborted req will be completed on receiving the abort req.
1230          * We enable the timer again. If hit twice, it'll cause a device reset,
1231          * as the device then is in a faulty state.
1232          */
1233         return BLK_EH_RESET_TIMER;
1234 }
1235
1236 static void nvme_free_queue(struct nvme_queue *nvmeq)
1237 {
1238         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1239                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1240
1241         if (nvmeq->sq_cmds) {
1242                 if (nvmeq->sq_cmds_is_io)
1243                         pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1244                                         nvmeq->sq_cmds,
1245                                         SQ_SIZE(nvmeq->q_depth));
1246                 else
1247                         dma_free_coherent(nvmeq->q_dmadev,
1248                                           SQ_SIZE(nvmeq->q_depth),
1249                                           nvmeq->sq_cmds,
1250                                           nvmeq->sq_dma_addr);
1251         }
1252 }
1253
1254 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1255 {
1256         int i;
1257
1258         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1259                 dev->ctrl.queue_count--;
1260                 nvme_free_queue(&dev->queues[i]);
1261         }
1262 }
1263
1264 /**
1265  * nvme_suspend_queue - put queue into suspended state
1266  * @nvmeq: queue to suspend
1267  */
1268 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1269 {
1270         int vector;
1271
1272         spin_lock_irq(&nvmeq->cq_lock);
1273         if (nvmeq->cq_vector == -1) {
1274                 spin_unlock_irq(&nvmeq->cq_lock);
1275                 return 1;
1276         }
1277         vector = nvmeq->cq_vector;
1278         nvmeq->dev->online_queues--;
1279         nvmeq->cq_vector = -1;
1280         spin_unlock_irq(&nvmeq->cq_lock);
1281
1282         /*
1283          * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1284          * having to grab the lock.
1285          */
1286         mb();
1287
1288         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1289                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1290
1291         pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1292
1293         return 0;
1294 }
1295
1296 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1297 {
1298         struct nvme_queue *nvmeq = &dev->queues[0];
1299         u16 start, end;
1300
1301         if (shutdown)
1302                 nvme_shutdown_ctrl(&dev->ctrl);
1303         else
1304                 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1305
1306         spin_lock_irq(&nvmeq->cq_lock);
1307         nvme_process_cq(nvmeq, &start, &end, -1);
1308         spin_unlock_irq(&nvmeq->cq_lock);
1309
1310         nvme_complete_cqes(nvmeq, start, end);
1311 }
1312
1313 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1314                                 int entry_size)
1315 {
1316         int q_depth = dev->q_depth;
1317         unsigned q_size_aligned = roundup(q_depth * entry_size,
1318                                           dev->ctrl.page_size);
1319
1320         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1321                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1322                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1323                 q_depth = div_u64(mem_per_q, entry_size);
1324
1325                 /*
1326                  * Ensure the reduced q_depth is above some threshold where it
1327                  * would be better to map queues in system memory with the
1328                  * original depth
1329                  */
1330                 if (q_depth < 64)
1331                         return -ENOMEM;
1332         }
1333
1334         return q_depth;
1335 }
1336
1337 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1338                                 int qid, int depth)
1339 {
1340         struct pci_dev *pdev = to_pci_dev(dev->dev);
1341
1342         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1343                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1344                 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1345                                                 nvmeq->sq_cmds);
1346                 nvmeq->sq_cmds_is_io = true;
1347         }
1348
1349         if (!nvmeq->sq_cmds) {
1350                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1351                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1352                 nvmeq->sq_cmds_is_io = false;
1353         }
1354
1355         if (!nvmeq->sq_cmds)
1356                 return -ENOMEM;
1357         return 0;
1358 }
1359
1360 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1361 {
1362         struct nvme_queue *nvmeq = &dev->queues[qid];
1363
1364         if (dev->ctrl.queue_count > qid)
1365                 return 0;
1366
1367         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1368                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1369         if (!nvmeq->cqes)
1370                 goto free_nvmeq;
1371
1372         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1373                 goto free_cqdma;
1374
1375         nvmeq->q_dmadev = dev->dev;
1376         nvmeq->dev = dev;
1377         spin_lock_init(&nvmeq->sq_lock);
1378         spin_lock_init(&nvmeq->cq_lock);
1379         nvmeq->cq_head = 0;
1380         nvmeq->cq_phase = 1;
1381         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1382         nvmeq->q_depth = depth;
1383         nvmeq->qid = qid;
1384         nvmeq->cq_vector = -1;
1385         dev->ctrl.queue_count++;
1386
1387         return 0;
1388
1389  free_cqdma:
1390         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1391                                                         nvmeq->cq_dma_addr);
1392  free_nvmeq:
1393         return -ENOMEM;
1394 }
1395
1396 static int queue_request_irq(struct nvme_queue *nvmeq)
1397 {
1398         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1399         int nr = nvmeq->dev->ctrl.instance;
1400
1401         if (use_threaded_interrupts) {
1402                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1403                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1404         } else {
1405                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1406                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1407         }
1408 }
1409
1410 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1411 {
1412         struct nvme_dev *dev = nvmeq->dev;
1413
1414         spin_lock_irq(&nvmeq->cq_lock);
1415         nvmeq->sq_tail = 0;
1416         nvmeq->cq_head = 0;
1417         nvmeq->cq_phase = 1;
1418         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1419         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1420         nvme_dbbuf_init(dev, nvmeq, qid);
1421         dev->online_queues++;
1422         spin_unlock_irq(&nvmeq->cq_lock);
1423 }
1424
1425 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1426 {
1427         struct nvme_dev *dev = nvmeq->dev;
1428         int result;
1429         s16 vector;
1430
1431         /*
1432          * A queue's vector matches the queue identifier unless the controller
1433          * has only one vector available.
1434          */
1435         vector = dev->num_vecs == 1 ? 0 : qid;
1436         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1437         if (result)
1438                 return result;
1439
1440         result = adapter_alloc_sq(dev, qid, nvmeq);
1441         if (result < 0)
1442                 return result;
1443         else if (result)
1444                 goto release_cq;
1445
1446         /*
1447          * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1448          * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1449          * xxx' warning if the create CQ/SQ command times out.
1450          */
1451         nvmeq->cq_vector = vector;
1452         nvme_init_queue(nvmeq, qid);
1453         result = queue_request_irq(nvmeq);
1454         if (result < 0)
1455                 goto release_sq;
1456
1457         return result;
1458
1459 release_sq:
1460         nvmeq->cq_vector = -1;
1461         dev->online_queues--;
1462         adapter_delete_sq(dev, qid);
1463 release_cq:
1464         adapter_delete_cq(dev, qid);
1465         return result;
1466 }
1467
1468 static const struct blk_mq_ops nvme_mq_admin_ops = {
1469         .queue_rq       = nvme_queue_rq,
1470         .complete       = nvme_pci_complete_rq,
1471         .init_hctx      = nvme_admin_init_hctx,
1472         .exit_hctx      = nvme_admin_exit_hctx,
1473         .init_request   = nvme_init_request,
1474         .timeout        = nvme_timeout,
1475 };
1476
1477 static const struct blk_mq_ops nvme_mq_ops = {
1478         .queue_rq       = nvme_queue_rq,
1479         .complete       = nvme_pci_complete_rq,
1480         .init_hctx      = nvme_init_hctx,
1481         .init_request   = nvme_init_request,
1482         .map_queues     = nvme_pci_map_queues,
1483         .timeout        = nvme_timeout,
1484         .poll           = nvme_poll,
1485 };
1486
1487 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1488 {
1489         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1490                 /*
1491                  * If the controller was reset during removal, it's possible
1492                  * user requests may be waiting on a stopped queue. Start the
1493                  * queue to flush these to completion.
1494                  */
1495                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1496                 blk_cleanup_queue(dev->ctrl.admin_q);
1497                 blk_mq_free_tag_set(&dev->admin_tagset);
1498         }
1499 }
1500
1501 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1502 {
1503         if (!dev->ctrl.admin_q) {
1504                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1505                 dev->admin_tagset.nr_hw_queues = 1;
1506
1507                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1508                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1509                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1510                 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1511                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1512                 dev->admin_tagset.driver_data = dev;
1513
1514                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1515                         return -ENOMEM;
1516                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1517
1518                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1519                 if (IS_ERR(dev->ctrl.admin_q)) {
1520                         blk_mq_free_tag_set(&dev->admin_tagset);
1521                         return -ENOMEM;
1522                 }
1523                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1524                         nvme_dev_remove_admin(dev);
1525                         dev->ctrl.admin_q = NULL;
1526                         return -ENODEV;
1527                 }
1528         } else
1529                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1530
1531         return 0;
1532 }
1533
1534 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1535 {
1536         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1537 }
1538
1539 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1540 {
1541         struct pci_dev *pdev = to_pci_dev(dev->dev);
1542
1543         if (size <= dev->bar_mapped_size)
1544                 return 0;
1545         if (size > pci_resource_len(pdev, 0))
1546                 return -ENOMEM;
1547         if (dev->bar)
1548                 iounmap(dev->bar);
1549         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1550         if (!dev->bar) {
1551                 dev->bar_mapped_size = 0;
1552                 return -ENOMEM;
1553         }
1554         dev->bar_mapped_size = size;
1555         dev->dbs = dev->bar + NVME_REG_DBS;
1556
1557         return 0;
1558 }
1559
1560 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1561 {
1562         int result;
1563         u32 aqa;
1564         struct nvme_queue *nvmeq;
1565
1566         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1567         if (result < 0)
1568                 return result;
1569
1570         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1571                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1572
1573         if (dev->subsystem &&
1574             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1575                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1576
1577         result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1578         if (result < 0)
1579                 return result;
1580
1581         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1582         if (result)
1583                 return result;
1584
1585         nvmeq = &dev->queues[0];
1586         aqa = nvmeq->q_depth - 1;
1587         aqa |= aqa << 16;
1588
1589         writel(aqa, dev->bar + NVME_REG_AQA);
1590         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1591         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1592
1593         result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1594         if (result)
1595                 return result;
1596
1597         nvmeq->cq_vector = 0;
1598         nvme_init_queue(nvmeq, 0);
1599         result = queue_request_irq(nvmeq);
1600         if (result) {
1601                 nvmeq->cq_vector = -1;
1602                 return result;
1603         }
1604
1605         return result;
1606 }
1607
1608 static int nvme_create_io_queues(struct nvme_dev *dev)
1609 {
1610         unsigned i, max;
1611         int ret = 0;
1612
1613         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1614                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1615                         ret = -ENOMEM;
1616                         break;
1617                 }
1618         }
1619
1620         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1621         for (i = dev->online_queues; i <= max; i++) {
1622                 ret = nvme_create_queue(&dev->queues[i], i);
1623                 if (ret)
1624                         break;
1625         }
1626
1627         /*
1628          * Ignore failing Create SQ/CQ commands, we can continue with less
1629          * than the desired amount of queues, and even a controller without
1630          * I/O queues can still be used to issue admin commands.  This might
1631          * be useful to upgrade a buggy firmware for example.
1632          */
1633         return ret >= 0 ? 0 : ret;
1634 }
1635
1636 static ssize_t nvme_cmb_show(struct device *dev,
1637                              struct device_attribute *attr,
1638                              char *buf)
1639 {
1640         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1641
1642         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1643                        ndev->cmbloc, ndev->cmbsz);
1644 }
1645 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1646
1647 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1648 {
1649         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1650
1651         return 1ULL << (12 + 4 * szu);
1652 }
1653
1654 static u32 nvme_cmb_size(struct nvme_dev *dev)
1655 {
1656         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1657 }
1658
1659 static void nvme_map_cmb(struct nvme_dev *dev)
1660 {
1661         u64 size, offset;
1662         resource_size_t bar_size;
1663         struct pci_dev *pdev = to_pci_dev(dev->dev);
1664         int bar;
1665
1666         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1667         if (!dev->cmbsz)
1668                 return;
1669         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1670
1671         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1672         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1673         bar = NVME_CMB_BIR(dev->cmbloc);
1674         bar_size = pci_resource_len(pdev, bar);
1675
1676         if (offset > bar_size)
1677                 return;
1678
1679         /*
1680          * Controllers may support a CMB size larger than their BAR,
1681          * for example, due to being behind a bridge. Reduce the CMB to
1682          * the reported size of the BAR
1683          */
1684         if (size > bar_size - offset)
1685                 size = bar_size - offset;
1686
1687         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1688                 dev_warn(dev->ctrl.device,
1689                          "failed to register the CMB\n");
1690                 return;
1691         }
1692
1693         dev->cmb_size = size;
1694         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1695
1696         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1697                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1698                 pci_p2pmem_publish(pdev, true);
1699
1700         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1701                                     &dev_attr_cmb.attr, NULL))
1702                 dev_warn(dev->ctrl.device,
1703                          "failed to add sysfs attribute for CMB\n");
1704 }
1705
1706 static inline void nvme_release_cmb(struct nvme_dev *dev)
1707 {
1708         if (dev->cmb_size) {
1709                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1710                                              &dev_attr_cmb.attr, NULL);
1711                 dev->cmb_size = 0;
1712         }
1713 }
1714
1715 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1716 {
1717         u64 dma_addr = dev->host_mem_descs_dma;
1718         struct nvme_command c;
1719         int ret;
1720
1721         memset(&c, 0, sizeof(c));
1722         c.features.opcode       = nvme_admin_set_features;
1723         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1724         c.features.dword11      = cpu_to_le32(bits);
1725         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1726                                               ilog2(dev->ctrl.page_size));
1727         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1728         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1729         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1730
1731         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1732         if (ret) {
1733                 dev_warn(dev->ctrl.device,
1734                          "failed to set host mem (err %d, flags %#x).\n",
1735                          ret, bits);
1736         }
1737         return ret;
1738 }
1739
1740 static void nvme_free_host_mem(struct nvme_dev *dev)
1741 {
1742         int i;
1743
1744         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1745                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1746                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1747
1748                 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1749                                 le64_to_cpu(desc->addr));
1750         }
1751
1752         kfree(dev->host_mem_desc_bufs);
1753         dev->host_mem_desc_bufs = NULL;
1754         dma_free_coherent(dev->dev,
1755                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1756                         dev->host_mem_descs, dev->host_mem_descs_dma);
1757         dev->host_mem_descs = NULL;
1758         dev->nr_host_mem_descs = 0;
1759 }
1760
1761 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1762                 u32 chunk_size)
1763 {
1764         struct nvme_host_mem_buf_desc *descs;
1765         u32 max_entries, len;
1766         dma_addr_t descs_dma;
1767         int i = 0;
1768         void **bufs;
1769         u64 size, tmp;
1770
1771         tmp = (preferred + chunk_size - 1);
1772         do_div(tmp, chunk_size);
1773         max_entries = tmp;
1774
1775         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1776                 max_entries = dev->ctrl.hmmaxd;
1777
1778         descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1779                         &descs_dma, GFP_KERNEL);
1780         if (!descs)
1781                 goto out;
1782
1783         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1784         if (!bufs)
1785                 goto out_free_descs;
1786
1787         for (size = 0; size < preferred && i < max_entries; size += len) {
1788                 dma_addr_t dma_addr;
1789
1790                 len = min_t(u64, chunk_size, preferred - size);
1791                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1792                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1793                 if (!bufs[i])
1794                         break;
1795
1796                 descs[i].addr = cpu_to_le64(dma_addr);
1797                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1798                 i++;
1799         }
1800
1801         if (!size)
1802                 goto out_free_bufs;
1803
1804         dev->nr_host_mem_descs = i;
1805         dev->host_mem_size = size;
1806         dev->host_mem_descs = descs;
1807         dev->host_mem_descs_dma = descs_dma;
1808         dev->host_mem_desc_bufs = bufs;
1809         return 0;
1810
1811 out_free_bufs:
1812         while (--i >= 0) {
1813                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1814
1815                 dma_free_coherent(dev->dev, size, bufs[i],
1816                                 le64_to_cpu(descs[i].addr));
1817         }
1818
1819         kfree(bufs);
1820 out_free_descs:
1821         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1822                         descs_dma);
1823 out:
1824         dev->host_mem_descs = NULL;
1825         return -ENOMEM;
1826 }
1827
1828 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1829 {
1830         u32 chunk_size;
1831
1832         /* start big and work our way down */
1833         for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1834              chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1835              chunk_size /= 2) {
1836                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1837                         if (!min || dev->host_mem_size >= min)
1838                                 return 0;
1839                         nvme_free_host_mem(dev);
1840                 }
1841         }
1842
1843         return -ENOMEM;
1844 }
1845
1846 static int nvme_setup_host_mem(struct nvme_dev *dev)
1847 {
1848         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1849         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1850         u64 min = (u64)dev->ctrl.hmmin * 4096;
1851         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1852         int ret;
1853
1854         preferred = min(preferred, max);
1855         if (min > max) {
1856                 dev_warn(dev->ctrl.device,
1857                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1858                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1859                 nvme_free_host_mem(dev);
1860                 return 0;
1861         }
1862
1863         /*
1864          * If we already have a buffer allocated check if we can reuse it.
1865          */
1866         if (dev->host_mem_descs) {
1867                 if (dev->host_mem_size >= min)
1868                         enable_bits |= NVME_HOST_MEM_RETURN;
1869                 else
1870                         nvme_free_host_mem(dev);
1871         }
1872
1873         if (!dev->host_mem_descs) {
1874                 if (nvme_alloc_host_mem(dev, min, preferred)) {
1875                         dev_warn(dev->ctrl.device,
1876                                 "failed to allocate host memory buffer.\n");
1877                         return 0; /* controller must work without HMB */
1878                 }
1879
1880                 dev_info(dev->ctrl.device,
1881                         "allocated %lld MiB host memory buffer.\n",
1882                         dev->host_mem_size >> ilog2(SZ_1M));
1883         }
1884
1885         ret = nvme_set_host_mem(dev, enable_bits);
1886         if (ret)
1887                 nvme_free_host_mem(dev);
1888         return ret;
1889 }
1890
1891 static int nvme_setup_io_queues(struct nvme_dev *dev)
1892 {
1893         struct nvme_queue *adminq = &dev->queues[0];
1894         struct pci_dev *pdev = to_pci_dev(dev->dev);
1895         int result, nr_io_queues;
1896         unsigned long size;
1897
1898         struct irq_affinity affd = {
1899                 .pre_vectors = 1
1900         };
1901
1902         nr_io_queues = num_possible_cpus();
1903         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1904         if (result < 0)
1905                 return result;
1906
1907         if (nr_io_queues == 0)
1908                 return 0;
1909
1910         if (dev->cmb_use_sqes) {
1911                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1912                                 sizeof(struct nvme_command));
1913                 if (result > 0)
1914                         dev->q_depth = result;
1915                 else
1916                         dev->cmb_use_sqes = false;
1917         }
1918
1919         do {
1920                 size = db_bar_size(dev, nr_io_queues);
1921                 result = nvme_remap_bar(dev, size);
1922                 if (!result)
1923                         break;
1924                 if (!--nr_io_queues)
1925                         return -ENOMEM;
1926         } while (1);
1927         adminq->q_db = dev->dbs;
1928
1929         /* Deregister the admin queue's interrupt */
1930         pci_free_irq(pdev, 0, adminq);
1931
1932         /*
1933          * If we enable msix early due to not intx, disable it again before
1934          * setting up the full range we need.
1935          */
1936         pci_free_irq_vectors(pdev);
1937         result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1938                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1939         if (result <= 0)
1940                 return -EIO;
1941         dev->num_vecs = result;
1942         dev->max_qid = max(result - 1, 1);
1943
1944         /*
1945          * Should investigate if there's a performance win from allocating
1946          * more queues than interrupt vectors; it might allow the submission
1947          * path to scale better, even if the receive path is limited by the
1948          * number of interrupts.
1949          */
1950
1951         result = queue_request_irq(adminq);
1952         if (result) {
1953                 adminq->cq_vector = -1;
1954                 return result;
1955         }
1956         return nvme_create_io_queues(dev);
1957 }
1958
1959 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1960 {
1961         struct nvme_queue *nvmeq = req->end_io_data;
1962
1963         blk_mq_free_request(req);
1964         complete(&nvmeq->dev->ioq_wait);
1965 }
1966
1967 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1968 {
1969         struct nvme_queue *nvmeq = req->end_io_data;
1970         u16 start, end;
1971
1972         if (!error) {
1973                 unsigned long flags;
1974
1975                 spin_lock_irqsave(&nvmeq->cq_lock, flags);
1976                 nvme_process_cq(nvmeq, &start, &end, -1);
1977                 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
1978
1979                 nvme_complete_cqes(nvmeq, start, end);
1980         }
1981
1982         nvme_del_queue_end(req, error);
1983 }
1984
1985 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1986 {
1987         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1988         struct request *req;
1989         struct nvme_command cmd;
1990
1991         memset(&cmd, 0, sizeof(cmd));
1992         cmd.delete_queue.opcode = opcode;
1993         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1994
1995         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1996         if (IS_ERR(req))
1997                 return PTR_ERR(req);
1998
1999         req->timeout = ADMIN_TIMEOUT;
2000         req->end_io_data = nvmeq;
2001
2002         blk_execute_rq_nowait(q, NULL, req, false,
2003                         opcode == nvme_admin_delete_cq ?
2004                                 nvme_del_cq_end : nvme_del_queue_end);
2005         return 0;
2006 }
2007
2008 static void nvme_disable_io_queues(struct nvme_dev *dev)
2009 {
2010         int pass, queues = dev->online_queues - 1;
2011         unsigned long timeout;
2012         u8 opcode = nvme_admin_delete_sq;
2013
2014         for (pass = 0; pass < 2; pass++) {
2015                 int sent = 0, i = queues;
2016
2017                 reinit_completion(&dev->ioq_wait);
2018  retry:
2019                 timeout = ADMIN_TIMEOUT;
2020                 for (; i > 0; i--, sent++)
2021                         if (nvme_delete_queue(&dev->queues[i], opcode))
2022                                 break;
2023
2024                 while (sent--) {
2025                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2026                         if (timeout == 0)
2027                                 return;
2028                         if (i)
2029                                 goto retry;
2030                 }
2031                 opcode = nvme_admin_delete_cq;
2032         }
2033 }
2034
2035 /*
2036  * return error value only when tagset allocation failed
2037  */
2038 static int nvme_dev_add(struct nvme_dev *dev)
2039 {
2040         int ret;
2041
2042         if (!dev->ctrl.tagset) {
2043                 dev->tagset.ops = &nvme_mq_ops;
2044                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2045                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2046                 dev->tagset.numa_node = dev_to_node(dev->dev);
2047                 dev->tagset.queue_depth =
2048                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2049                 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2050                 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2051                         dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2052                                         nvme_pci_cmd_size(dev, true));
2053                 }
2054                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2055                 dev->tagset.driver_data = dev;
2056
2057                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2058                 if (ret) {
2059                         dev_warn(dev->ctrl.device,
2060                                 "IO queues tagset allocation failed %d\n", ret);
2061                         return ret;
2062                 }
2063                 dev->ctrl.tagset = &dev->tagset;
2064
2065                 nvme_dbbuf_set(dev);
2066         } else {
2067                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2068
2069                 /* Free previously allocated queues that are no longer usable */
2070                 nvme_free_queues(dev, dev->online_queues);
2071         }
2072
2073         return 0;
2074 }
2075
2076 static int nvme_pci_enable(struct nvme_dev *dev)
2077 {
2078         int result = -ENOMEM;
2079         struct pci_dev *pdev = to_pci_dev(dev->dev);
2080
2081         if (pci_enable_device_mem(pdev))
2082                 return result;
2083
2084         pci_set_master(pdev);
2085
2086         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2087             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2088                 goto disable;
2089
2090         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2091                 result = -ENODEV;
2092                 goto disable;
2093         }
2094
2095         /*
2096          * Some devices and/or platforms don't advertise or work with INTx
2097          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2098          * adjust this later.
2099          */
2100         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2101         if (result < 0)
2102                 return result;
2103
2104         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2105
2106         dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2107                                 io_queue_depth);
2108         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2109         dev->dbs = dev->bar + 4096;
2110
2111         /*
2112          * Temporary fix for the Apple controller found in the MacBook8,1 and
2113          * some MacBook7,1 to avoid controller resets and data loss.
2114          */
2115         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2116                 dev->q_depth = 2;
2117                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2118                         "set queue depth=%u to work around controller resets\n",
2119                         dev->q_depth);
2120         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2121                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2122                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2123                 dev->q_depth = 64;
2124                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2125                         "set queue depth=%u\n", dev->q_depth);
2126         }
2127
2128         nvme_map_cmb(dev);
2129
2130         pci_enable_pcie_error_reporting(pdev);
2131         pci_save_state(pdev);
2132         return 0;
2133
2134  disable:
2135         pci_disable_device(pdev);
2136         return result;
2137 }
2138
2139 static void nvme_dev_unmap(struct nvme_dev *dev)
2140 {
2141         if (dev->bar)
2142                 iounmap(dev->bar);
2143         pci_release_mem_regions(to_pci_dev(dev->dev));
2144 }
2145
2146 static void nvme_pci_disable(struct nvme_dev *dev)
2147 {
2148         struct pci_dev *pdev = to_pci_dev(dev->dev);
2149
2150         nvme_release_cmb(dev);
2151         pci_free_irq_vectors(pdev);
2152
2153         if (pci_is_enabled(pdev)) {
2154                 pci_disable_pcie_error_reporting(pdev);
2155                 pci_disable_device(pdev);
2156         }
2157 }
2158
2159 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2160 {
2161         int i;
2162         bool dead = true;
2163         struct pci_dev *pdev = to_pci_dev(dev->dev);
2164
2165         mutex_lock(&dev->shutdown_lock);
2166         if (pci_is_enabled(pdev)) {
2167                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2168
2169                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2170                     dev->ctrl.state == NVME_CTRL_RESETTING)
2171                         nvme_start_freeze(&dev->ctrl);
2172                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2173                         pdev->error_state  != pci_channel_io_normal);
2174         }
2175
2176         /*
2177          * Give the controller a chance to complete all entered requests if
2178          * doing a safe shutdown.
2179          */
2180         if (!dead) {
2181                 if (shutdown)
2182                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2183         }
2184
2185         nvme_stop_queues(&dev->ctrl);
2186
2187         if (!dead && dev->ctrl.queue_count > 0) {
2188                 nvme_disable_io_queues(dev);
2189                 nvme_disable_admin_queue(dev, shutdown);
2190         }
2191         for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2192                 nvme_suspend_queue(&dev->queues[i]);
2193
2194         nvme_pci_disable(dev);
2195
2196         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2197         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2198
2199         /*
2200          * The driver will not be starting up queues again if shutting down so
2201          * must flush all entered requests to their failed completion to avoid
2202          * deadlocking blk-mq hot-cpu notifier.
2203          */
2204         if (shutdown)
2205                 nvme_start_queues(&dev->ctrl);
2206         mutex_unlock(&dev->shutdown_lock);
2207 }
2208
2209 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2210 {
2211         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2212                                                 PAGE_SIZE, PAGE_SIZE, 0);
2213         if (!dev->prp_page_pool)
2214                 return -ENOMEM;
2215
2216         /* Optimisation for I/Os between 4k and 128k */
2217         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2218                                                 256, 256, 0);
2219         if (!dev->prp_small_pool) {
2220                 dma_pool_destroy(dev->prp_page_pool);
2221                 return -ENOMEM;
2222         }
2223         return 0;
2224 }
2225
2226 static void nvme_release_prp_pools(struct nvme_dev *dev)
2227 {
2228         dma_pool_destroy(dev->prp_page_pool);
2229         dma_pool_destroy(dev->prp_small_pool);
2230 }
2231
2232 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2233 {
2234         struct nvme_dev *dev = to_nvme_dev(ctrl);
2235
2236         nvme_dbbuf_dma_free(dev);
2237         put_device(dev->dev);
2238         if (dev->tagset.tags)
2239                 blk_mq_free_tag_set(&dev->tagset);
2240         if (dev->ctrl.admin_q)
2241                 blk_put_queue(dev->ctrl.admin_q);
2242         kfree(dev->queues);
2243         free_opal_dev(dev->ctrl.opal_dev);
2244         mempool_destroy(dev->iod_mempool);
2245         kfree(dev);
2246 }
2247
2248 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2249 {
2250         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2251
2252         nvme_get_ctrl(&dev->ctrl);
2253         nvme_dev_disable(dev, false);
2254         nvme_kill_queues(&dev->ctrl);
2255         if (!queue_work(nvme_wq, &dev->remove_work))
2256                 nvme_put_ctrl(&dev->ctrl);
2257 }
2258
2259 static void nvme_reset_work(struct work_struct *work)
2260 {
2261         struct nvme_dev *dev =
2262                 container_of(work, struct nvme_dev, ctrl.reset_work);
2263         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2264         int result = -ENODEV;
2265         enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2266
2267         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2268                 goto out;
2269
2270         /*
2271          * If we're called to reset a live controller first shut it down before
2272          * moving on.
2273          */
2274         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2275                 nvme_dev_disable(dev, false);
2276
2277         /*
2278          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2279          * initializing procedure here.
2280          */
2281         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2282                 dev_warn(dev->ctrl.device,
2283                         "failed to mark controller CONNECTING\n");
2284                 goto out;
2285         }
2286
2287         result = nvme_pci_enable(dev);
2288         if (result)
2289                 goto out;
2290
2291         result = nvme_pci_configure_admin_queue(dev);
2292         if (result)
2293                 goto out;
2294
2295         result = nvme_alloc_admin_tags(dev);
2296         if (result)
2297                 goto out;
2298
2299         /*
2300          * Limit the max command size to prevent iod->sg allocations going
2301          * over a single page.
2302          */
2303         dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2304         dev->ctrl.max_segments = NVME_MAX_SEGS;
2305
2306         result = nvme_init_identify(&dev->ctrl);
2307         if (result)
2308                 goto out;
2309
2310         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2311                 if (!dev->ctrl.opal_dev)
2312                         dev->ctrl.opal_dev =
2313                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2314                 else if (was_suspend)
2315                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2316         } else {
2317                 free_opal_dev(dev->ctrl.opal_dev);
2318                 dev->ctrl.opal_dev = NULL;
2319         }
2320
2321         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2322                 result = nvme_dbbuf_dma_alloc(dev);
2323                 if (result)
2324                         dev_warn(dev->dev,
2325                                  "unable to allocate dma for dbbuf\n");
2326         }
2327
2328         if (dev->ctrl.hmpre) {
2329                 result = nvme_setup_host_mem(dev);
2330                 if (result < 0)
2331                         goto out;
2332         }
2333
2334         result = nvme_setup_io_queues(dev);
2335         if (result)
2336                 goto out;
2337
2338         /*
2339          * Keep the controller around but remove all namespaces if we don't have
2340          * any working I/O queue.
2341          */
2342         if (dev->online_queues < 2) {
2343                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2344                 nvme_kill_queues(&dev->ctrl);
2345                 nvme_remove_namespaces(&dev->ctrl);
2346                 new_state = NVME_CTRL_ADMIN_ONLY;
2347         } else {
2348                 nvme_start_queues(&dev->ctrl);
2349                 nvme_wait_freeze(&dev->ctrl);
2350                 /* hit this only when allocate tagset fails */
2351                 if (nvme_dev_add(dev))
2352                         new_state = NVME_CTRL_ADMIN_ONLY;
2353                 nvme_unfreeze(&dev->ctrl);
2354         }
2355
2356         /*
2357          * If only admin queue live, keep it to do further investigation or
2358          * recovery.
2359          */
2360         if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2361                 dev_warn(dev->ctrl.device,
2362                         "failed to mark controller state %d\n", new_state);
2363                 goto out;
2364         }
2365
2366         nvme_start_ctrl(&dev->ctrl);
2367         return;
2368
2369  out:
2370         nvme_remove_dead_ctrl(dev, result);
2371 }
2372
2373 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2374 {
2375         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2376         struct pci_dev *pdev = to_pci_dev(dev->dev);
2377
2378         if (pci_get_drvdata(pdev))
2379                 device_release_driver(&pdev->dev);
2380         nvme_put_ctrl(&dev->ctrl);
2381 }
2382
2383 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2384 {
2385         *val = readl(to_nvme_dev(ctrl)->bar + off);
2386         return 0;
2387 }
2388
2389 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2390 {
2391         writel(val, to_nvme_dev(ctrl)->bar + off);
2392         return 0;
2393 }
2394
2395 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2396 {
2397         *val = readq(to_nvme_dev(ctrl)->bar + off);
2398         return 0;
2399 }
2400
2401 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2402 {
2403         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2404
2405         return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2406 }
2407
2408 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2409         .name                   = "pcie",
2410         .module                 = THIS_MODULE,
2411         .flags                  = NVME_F_METADATA_SUPPORTED |
2412                                   NVME_F_PCI_P2PDMA,
2413         .reg_read32             = nvme_pci_reg_read32,
2414         .reg_write32            = nvme_pci_reg_write32,
2415         .reg_read64             = nvme_pci_reg_read64,
2416         .free_ctrl              = nvme_pci_free_ctrl,
2417         .submit_async_event     = nvme_pci_submit_async_event,
2418         .get_address            = nvme_pci_get_address,
2419 };
2420
2421 static int nvme_dev_map(struct nvme_dev *dev)
2422 {
2423         struct pci_dev *pdev = to_pci_dev(dev->dev);
2424
2425         if (pci_request_mem_regions(pdev, "nvme"))
2426                 return -ENODEV;
2427
2428         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2429                 goto release;
2430
2431         return 0;
2432   release:
2433         pci_release_mem_regions(pdev);
2434         return -ENODEV;
2435 }
2436
2437 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2438 {
2439         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2440                 /*
2441                  * Several Samsung devices seem to drop off the PCIe bus
2442                  * randomly when APST is on and uses the deepest sleep state.
2443                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2444                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2445                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2446                  * laptops.
2447                  */
2448                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2449                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2450                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2451                         return NVME_QUIRK_NO_DEEPEST_PS;
2452         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2453                 /*
2454                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2455                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2456                  * within few minutes after bootup on a Coffee Lake board -
2457                  * ASUS PRIME Z370-A
2458                  */
2459                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2460                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2461                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2462                         return NVME_QUIRK_NO_APST;
2463         }
2464
2465         return 0;
2466 }
2467
2468 static void nvme_async_probe(void *data, async_cookie_t cookie)
2469 {
2470         struct nvme_dev *dev = data;
2471
2472         nvme_reset_ctrl_sync(&dev->ctrl);
2473         flush_work(&dev->ctrl.scan_work);
2474         nvme_put_ctrl(&dev->ctrl);
2475 }
2476
2477 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2478 {
2479         int node, result = -ENOMEM;
2480         struct nvme_dev *dev;
2481         unsigned long quirks = id->driver_data;
2482         size_t alloc_size;
2483
2484         node = dev_to_node(&pdev->dev);
2485         if (node == NUMA_NO_NODE)
2486                 set_dev_node(&pdev->dev, first_memory_node);
2487
2488         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2489         if (!dev)
2490                 return -ENOMEM;
2491
2492         dev->queues = kcalloc_node(num_possible_cpus() + 1,
2493                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2494         if (!dev->queues)
2495                 goto free;
2496
2497         dev->dev = get_device(&pdev->dev);
2498         pci_set_drvdata(pdev, dev);
2499
2500         result = nvme_dev_map(dev);
2501         if (result)
2502                 goto put_pci;
2503
2504         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2505         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2506         mutex_init(&dev->shutdown_lock);
2507         init_completion(&dev->ioq_wait);
2508
2509         result = nvme_setup_prp_pools(dev);
2510         if (result)
2511                 goto unmap;
2512
2513         quirks |= check_vendor_combination_bug(pdev);
2514
2515         /*
2516          * Double check that our mempool alloc size will cover the biggest
2517          * command we support.
2518          */
2519         alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2520                                                 NVME_MAX_SEGS, true);
2521         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2522
2523         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2524                                                 mempool_kfree,
2525                                                 (void *) alloc_size,
2526                                                 GFP_KERNEL, node);
2527         if (!dev->iod_mempool) {
2528                 result = -ENOMEM;
2529                 goto release_pools;
2530         }
2531
2532         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2533                         quirks);
2534         if (result)
2535                 goto release_mempool;
2536
2537         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2538
2539         nvme_get_ctrl(&dev->ctrl);
2540         async_schedule(nvme_async_probe, dev);
2541
2542         return 0;
2543
2544  release_mempool:
2545         mempool_destroy(dev->iod_mempool);
2546  release_pools:
2547         nvme_release_prp_pools(dev);
2548  unmap:
2549         nvme_dev_unmap(dev);
2550  put_pci:
2551         put_device(dev->dev);
2552  free:
2553         kfree(dev->queues);
2554         kfree(dev);
2555         return result;
2556 }
2557
2558 static void nvme_reset_prepare(struct pci_dev *pdev)
2559 {
2560         struct nvme_dev *dev = pci_get_drvdata(pdev);
2561         nvme_dev_disable(dev, false);
2562 }
2563
2564 static void nvme_reset_done(struct pci_dev *pdev)
2565 {
2566         struct nvme_dev *dev = pci_get_drvdata(pdev);
2567         nvme_reset_ctrl_sync(&dev->ctrl);
2568 }
2569
2570 static void nvme_shutdown(struct pci_dev *pdev)
2571 {
2572         struct nvme_dev *dev = pci_get_drvdata(pdev);
2573         nvme_dev_disable(dev, true);
2574 }
2575
2576 /*
2577  * The driver's remove may be called on a device in a partially initialized
2578  * state. This function must not have any dependencies on the device state in
2579  * order to proceed.
2580  */
2581 static void nvme_remove(struct pci_dev *pdev)
2582 {
2583         struct nvme_dev *dev = pci_get_drvdata(pdev);
2584
2585         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2586         pci_set_drvdata(pdev, NULL);
2587
2588         if (!pci_device_is_present(pdev)) {
2589                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2590                 nvme_dev_disable(dev, true);
2591                 nvme_dev_remove_admin(dev);
2592         }
2593
2594         flush_work(&dev->ctrl.reset_work);
2595         nvme_stop_ctrl(&dev->ctrl);
2596         nvme_remove_namespaces(&dev->ctrl);
2597         nvme_dev_disable(dev, true);
2598         nvme_free_host_mem(dev);
2599         nvme_dev_remove_admin(dev);
2600         nvme_free_queues(dev, 0);
2601         nvme_uninit_ctrl(&dev->ctrl);
2602         nvme_release_prp_pools(dev);
2603         nvme_dev_unmap(dev);
2604         nvme_put_ctrl(&dev->ctrl);
2605 }
2606
2607 #ifdef CONFIG_PM_SLEEP
2608 static int nvme_suspend(struct device *dev)
2609 {
2610         struct pci_dev *pdev = to_pci_dev(dev);
2611         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2612
2613         nvme_dev_disable(ndev, true);
2614         return 0;
2615 }
2616
2617 static int nvme_resume(struct device *dev)
2618 {
2619         struct pci_dev *pdev = to_pci_dev(dev);
2620         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2621
2622         nvme_reset_ctrl(&ndev->ctrl);
2623         return 0;
2624 }
2625 #endif
2626
2627 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2628
2629 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2630                                                 pci_channel_state_t state)
2631 {
2632         struct nvme_dev *dev = pci_get_drvdata(pdev);
2633
2634         /*
2635          * A frozen channel requires a reset. When detected, this method will
2636          * shutdown the controller to quiesce. The controller will be restarted
2637          * after the slot reset through driver's slot_reset callback.
2638          */
2639         switch (state) {
2640         case pci_channel_io_normal:
2641                 return PCI_ERS_RESULT_CAN_RECOVER;
2642         case pci_channel_io_frozen:
2643                 dev_warn(dev->ctrl.device,
2644                         "frozen state error detected, reset controller\n");
2645                 nvme_dev_disable(dev, false);
2646                 return PCI_ERS_RESULT_NEED_RESET;
2647         case pci_channel_io_perm_failure:
2648                 dev_warn(dev->ctrl.device,
2649                         "failure state error detected, request disconnect\n");
2650                 return PCI_ERS_RESULT_DISCONNECT;
2651         }
2652         return PCI_ERS_RESULT_NEED_RESET;
2653 }
2654
2655 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2656 {
2657         struct nvme_dev *dev = pci_get_drvdata(pdev);
2658
2659         dev_info(dev->ctrl.device, "restart after slot reset\n");
2660         pci_restore_state(pdev);
2661         nvme_reset_ctrl(&dev->ctrl);
2662         return PCI_ERS_RESULT_RECOVERED;
2663 }
2664
2665 static void nvme_error_resume(struct pci_dev *pdev)
2666 {
2667         struct nvme_dev *dev = pci_get_drvdata(pdev);
2668
2669         flush_work(&dev->ctrl.reset_work);
2670 }
2671
2672 static const struct pci_error_handlers nvme_err_handler = {
2673         .error_detected = nvme_error_detected,
2674         .slot_reset     = nvme_slot_reset,
2675         .resume         = nvme_error_resume,
2676         .reset_prepare  = nvme_reset_prepare,
2677         .reset_done     = nvme_reset_done,
2678 };
2679
2680 static const struct pci_device_id nvme_id_table[] = {
2681         { PCI_VDEVICE(INTEL, 0x0953),
2682                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2683                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2684         { PCI_VDEVICE(INTEL, 0x0a53),
2685                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2686                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2687         { PCI_VDEVICE(INTEL, 0x0a54),
2688                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2689                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2690         { PCI_VDEVICE(INTEL, 0x0a55),
2691                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2692                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2693         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2694                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2695                                 NVME_QUIRK_MEDIUM_PRIO_SQ },
2696         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2697                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2698         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
2699                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2700         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2701                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2702         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
2703                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2704         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2705                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2706         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
2707                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2708         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
2709                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2710         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
2711                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2712         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
2713                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2714         { PCI_DEVICE(0x1d1d, 0x2601),   /* CNEX Granby */
2715                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2716         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2717         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2718         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2719         { 0, }
2720 };
2721 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2722
2723 static struct pci_driver nvme_driver = {
2724         .name           = "nvme",
2725         .id_table       = nvme_id_table,
2726         .probe          = nvme_probe,
2727         .remove         = nvme_remove,
2728         .shutdown       = nvme_shutdown,
2729         .driver         = {
2730                 .pm     = &nvme_dev_pm_ops,
2731         },
2732         .sriov_configure = pci_sriov_configure_simple,
2733         .err_handler    = &nvme_err_handler,
2734 };
2735
2736 static int __init nvme_init(void)
2737 {
2738         return pci_register_driver(&nvme_driver);
2739 }
2740
2741 static void __exit nvme_exit(void)
2742 {
2743         pci_unregister_driver(&nvme_driver);
2744         flush_workqueue(nvme_wq);
2745         _nvme_check_size();
2746 }
2747
2748 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2749 MODULE_LICENSE("GPL");
2750 MODULE_VERSION("1.0");
2751 module_init(nvme_init);
2752 module_exit(nvme_exit);