drivers/pci/pcie/dpc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCI Express Downstream Port Containment services driver
   4  * Author: Keith Busch <keith.busch@intel.com>
   5  *
   6  * Copyright (C) 2016 Intel Corp.
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/init.h>
  12 #include <linux/pci.h>
  13
  14 #include "portdrv.h"
  15 #include "../pci.h"
  16 #include "aer/aerdrv.h"
  17
  18 struct dpc_dev {
  19         struct pcie_device      *dev;
  20         struct work_struct      work;
  21         u16                     cap_pos;
  22         bool                    rp_extensions;
  23         u32                     rp_pio_status;
  24         u8                      rp_log_size;
  25 };
  26
  27 static const char * const rp_pio_error_string[] = {
  28         "Configuration Request received UR Completion",  /* Bit Position 0  */
  29         "Configuration Request received CA Completion",  /* Bit Position 1  */
  30         "Configuration Request Completion Timeout",      /* Bit Position 2  */
  31         NULL,
  32         NULL,
  33         NULL,
  34         NULL,
  35         NULL,
  36         "I/O Request received UR Completion",            /* Bit Position 8  */
  37         "I/O Request received CA Completion",            /* Bit Position 9  */
  38         "I/O Request Completion Timeout",                /* Bit Position 10 */
  39         NULL,
  40         NULL,
  41         NULL,
  42         NULL,
  43         NULL,
  44         "Memory Request received UR Completion",         /* Bit Position 16 */
  45         "Memory Request received CA Completion",         /* Bit Position 17 */
  46         "Memory Request Completion Timeout",             /* Bit Position 18 */
  47 };
  48
  49 static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
  50 {
  51         unsigned long timeout = jiffies + HZ;
  52         struct pci_dev *pdev = dpc->dev->port;
  53         struct device *dev = &dpc->dev->device;
  54         u16 cap = dpc->cap_pos, status;
  55
  56         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
  57         while (status & PCI_EXP_DPC_RP_BUSY &&
  58                                         !time_after(jiffies, timeout)) {
  59                 msleep(10);
  60                 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
  61         }
  62         if (status & PCI_EXP_DPC_RP_BUSY) {
  63                 dev_warn(dev, "DPC root port still busy\n");
  64                 return -EBUSY;
  65         }
  66         return 0;
  67 }
  68
  69 static void dpc_wait_link_inactive(struct dpc_dev *dpc)
  70 {
  71         unsigned long timeout = jiffies + HZ;
  72         struct pci_dev *pdev = dpc->dev->port;
  73         struct device *dev = &dpc->dev->device;
  74         u16 lnk_status;
  75
  76         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
  77         while (lnk_status & PCI_EXP_LNKSTA_DLLLA &&
  78                                         !time_after(jiffies, timeout)) {
  79                 msleep(10);
  80                 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
  81         }
  82         if (lnk_status & PCI_EXP_LNKSTA_DLLLA)
  83                 dev_warn(dev, "Link state not disabled for DPC event\n");
  84 }
  85
  86 static void dpc_work(struct work_struct *work)
  87 {
  88         struct dpc_dev *dpc = container_of(work, struct dpc_dev, work);
  89         struct pci_dev *dev, *temp, *pdev = dpc->dev->port;
  90         struct pci_bus *parent = pdev->subordinate;
  91         u16 cap = dpc->cap_pos, ctl;
  92
  93         pci_lock_rescan_remove();
  94         list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
  95                                          bus_list) {
  96                 pci_dev_get(dev);
  97                 pci_dev_set_disconnected(dev, NULL);
  98                 if (pci_has_subordinate(dev))
  99                         pci_walk_bus(dev->subordinate,
 100                                      pci_dev_set_disconnected, NULL);
 101                 pci_stop_and_remove_bus_device(dev);
 102                 pci_dev_put(dev);
 103         }
 104         pci_unlock_rescan_remove();
 105
 106         dpc_wait_link_inactive(dpc);
 107         if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
 108                 return;
 109         if (dpc->rp_extensions && dpc->rp_pio_status) {
 110                 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS,
 111                                        dpc->rp_pio_status);
 112                 dpc->rp_pio_status = 0;
 113         }
 114
 115         pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
 116                 PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
 117
 118         pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
 119         pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
 120                               ctl | PCI_EXP_DPC_CTL_INT_EN);
 121 }
 122
 123 static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
 124 {
 125         struct device *dev = &dpc->dev->device;
 126         struct pci_dev *pdev = dpc->dev->port;
 127         u16 cap = dpc->cap_pos, dpc_status, first_error;
 128         u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
 129         int i;
 130
 131         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
 132         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
 133         dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
 134                 status, mask);
 135
 136         dpc->rp_pio_status = status;
 137
 138         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
 139         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
 140         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
 141         dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
 142                 sev, syserr, exc);
 143
 144         /* Get First Error Pointer */
 145         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
 146         first_error = (dpc_status & 0x1f00) >> 8;
 147
 148         status &= ~mask;
 149         for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
 150                 if (status & (1 << i))
 151                         dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
 152                                 first_error == i ? " (First)" : "");
 153         }
 154
 155         if (dpc->rp_log_size < 4)
 156                 return;
 157         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
 158                               &dw0);
 159         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
 160                               &dw1);
 161         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
 162                               &dw2);
 163         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
 164                               &dw3);
 165         dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
 166                 dw0, dw1, dw2, dw3);
 167
 168         if (dpc->rp_log_size < 5)
 169                 return;
 170         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
 171         dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
 172
 173         for (i = 0; i < dpc->rp_log_size - 5; i++) {
 174                 pci_read_config_dword(pdev,
 175                         cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
 176                 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
 177         }
 178 }
 179
 180 static irqreturn_t dpc_irq(int irq, void *context)
 181 {
 182         struct dpc_dev *dpc = (struct dpc_dev *)context;
 183         struct pci_dev *pdev = dpc->dev->port;
 184         struct device *dev = &dpc->dev->device;
 185         u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason;
 186
 187         pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
 188
 189         if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0))
 190                 return IRQ_NONE;
 191
 192         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 193
 194         if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT))
 195                 return IRQ_NONE;
 196
 197         if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) {
 198                 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
 199                                       PCI_EXP_DPC_STATUS_INTERRUPT);
 200                 return IRQ_HANDLED;
 201         }
 202
 203         pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
 204                               ctl & ~PCI_EXP_DPC_CTL_INT_EN);
 205
 206         pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID,
 207                              &source);
 208
 209         dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
 210                 status, source);
 211
 212         reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
 213         ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
 214
 215         dev_warn(dev, "DPC %s detected, remove downstream devices\n",
 216                  (reason == 0) ? "unmasked uncorrectable error" :
 217                  (reason == 1) ? "ERR_NONFATAL" :
 218                  (reason == 2) ? "ERR_FATAL" :
 219                  (ext_reason == 0) ? "RP PIO error" :
 220                  (ext_reason == 1) ? "software trigger" :
 221                                      "reserved error");
 222         /* show RP PIO error detail information */
 223         if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
 224                 dpc_process_rp_pio_error(dpc);
 225
 226         schedule_work(&dpc->work);
 227
 228         return IRQ_HANDLED;
 229 }
 230
 231 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
 232 static int dpc_probe(struct pcie_device *dev)
 233 {
 234         struct dpc_dev *dpc;
 235         struct pci_dev *pdev = dev->port;
 236         struct device *device = &dev->device;
 237         int status;
 238         u16 ctl, cap;
 239
 240         if (pcie_aer_get_firmware_first(pdev))
 241                 return -ENOTSUPP;
 242
 243         dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
 244         if (!dpc)
 245                 return -ENOMEM;
 246
 247         dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
 248         dpc->dev = dev;
 249         INIT_WORK(&dpc->work, dpc_work);
 250         set_service_data(dev, dpc);
 251
 252         status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
 253                                   "pcie-dpc", dpc);
 254         if (status) {
 255                 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
 256                          status);
 257                 return status;
 258         }
 259
 260         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
 261         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 262
 263         dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
 264         if (dpc->rp_extensions) {
 265                 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
 266                 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
 267                         dev_err(device, "RP PIO log size %u is invalid\n",
 268                                 dpc->rp_log_size);
 269                         dpc->rp_log_size = 0;
 270                 }
 271         }
 272
 273         ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
 274         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
 275
 276         dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
 277                 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
 278                 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
 279                 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
 280                 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
 281         return status;
 282 }
 283
 284 static void dpc_remove(struct pcie_device *dev)
 285 {
 286         struct dpc_dev *dpc = get_service_data(dev);
 287         struct pci_dev *pdev = dev->port;
 288         u16 ctl;
 289
 290         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 291         ctl &= ~(PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN);
 292         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
 293 }
 294
 295 static struct pcie_port_service_driver dpcdriver = {
 296         .name           = "dpc",
 297         .port_type      = PCIE_ANY_PORT,
 298         .service        = PCIE_PORT_SERVICE_DPC,
 299         .probe          = dpc_probe,
 300         .remove         = dpc_remove,
 301 };
 302
 303 static int __init dpc_service_init(void)
 304 {
 305         return pcie_port_service_register(&dpcdriver);
 306 }
 307 device_initcall(dpc_service_init);