7b96169a808ca03ee24fe6d192b277e8557fa1cb
[muen/linux.git] / drivers / pci / pcie / pcie-dpc.c
1 /*
2  * PCI Express Downstream Port Containment services driver
3  * Author: Keith Busch <keith.busch@intel.com>
4  *
5  * Copyright (C) 2016 Intel Corp.
6  *
7  * This file is subject to the terms and conditions of the GNU General Public
8  * License.  See the file "COPYING" in the main directory of this archive
9  * for more details.
10  */
11
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pcieport_if.h>
17 #include "../pci.h"
18 #include "aer/aerdrv.h"
19
20 struct rp_pio_header_log_regs {
21         u32 dw0;
22         u32 dw1;
23         u32 dw2;
24         u32 dw3;
25 };
26
27 struct dpc_rp_pio_regs {
28         u32 status;
29         u32 mask;
30         u32 severity;
31         u32 syserror;
32         u32 exception;
33
34         struct rp_pio_header_log_regs header_log;
35         u32 impspec_log;
36         u32 tlp_prefix_log[4];
37         u16 first_error;
38 };
39
40 struct dpc_dev {
41         struct pcie_device      *dev;
42         struct work_struct      work;
43         u16                     cap_pos;
44         bool                    rp_extensions;
45         u32                     rp_pio_status;
46         u8                      rp_log_size;
47 };
48
49 static const char * const rp_pio_error_string[] = {
50         "Configuration Request received UR Completion",  /* Bit Position 0  */
51         "Configuration Request received CA Completion",  /* Bit Position 1  */
52         "Configuration Request Completion Timeout",      /* Bit Position 2  */
53         NULL,
54         NULL,
55         NULL,
56         NULL,
57         NULL,
58         "I/O Request received UR Completion",            /* Bit Position 8  */
59         "I/O Request received CA Completion",            /* Bit Position 9  */
60         "I/O Request Completion Timeout",                /* Bit Position 10 */
61         NULL,
62         NULL,
63         NULL,
64         NULL,
65         NULL,
66         "Memory Request received UR Completion",         /* Bit Position 16 */
67         "Memory Request received CA Completion",         /* Bit Position 17 */
68         "Memory Request Completion Timeout",             /* Bit Position 18 */
69 };
70
71 static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
72 {
73         unsigned long timeout = jiffies + HZ;
74         struct pci_dev *pdev = dpc->dev->port;
75         struct device *dev = &dpc->dev->device;
76         u16 cap = dpc->cap_pos, status;
77
78         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
79         while (status & PCI_EXP_DPC_RP_BUSY &&
80                                         !time_after(jiffies, timeout)) {
81                 msleep(10);
82                 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
83         }
84         if (status & PCI_EXP_DPC_RP_BUSY) {
85                 dev_warn(dev, "DPC root port still busy\n");
86                 return -EBUSY;
87         }
88         return 0;
89 }
90
91 static void dpc_wait_link_inactive(struct dpc_dev *dpc)
92 {
93         unsigned long timeout = jiffies + HZ;
94         struct pci_dev *pdev = dpc->dev->port;
95         struct device *dev = &dpc->dev->device;
96         u16 lnk_status;
97
98         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
99         while (lnk_status & PCI_EXP_LNKSTA_DLLLA &&
100                                         !time_after(jiffies, timeout)) {
101                 msleep(10);
102                 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
103         }
104         if (lnk_status & PCI_EXP_LNKSTA_DLLLA)
105                 dev_warn(dev, "Link state not disabled for DPC event\n");
106 }
107
108 static void dpc_work(struct work_struct *work)
109 {
110         struct dpc_dev *dpc = container_of(work, struct dpc_dev, work);
111         struct pci_dev *dev, *temp, *pdev = dpc->dev->port;
112         struct pci_bus *parent = pdev->subordinate;
113         u16 cap = dpc->cap_pos, ctl;
114
115         pci_lock_rescan_remove();
116         list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
117                                          bus_list) {
118                 pci_dev_get(dev);
119                 pci_dev_set_disconnected(dev, NULL);
120                 if (pci_has_subordinate(dev))
121                         pci_walk_bus(dev->subordinate,
122                                      pci_dev_set_disconnected, NULL);
123                 pci_stop_and_remove_bus_device(dev);
124                 pci_dev_put(dev);
125         }
126         pci_unlock_rescan_remove();
127
128         dpc_wait_link_inactive(dpc);
129         if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
130                 return;
131         if (dpc->rp_extensions && dpc->rp_pio_status) {
132                 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS,
133                                        dpc->rp_pio_status);
134                 dpc->rp_pio_status = 0;
135         }
136
137         pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
138                 PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
139
140         pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
141         pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
142                               ctl | PCI_EXP_DPC_CTL_INT_EN);
143 }
144
145 static void dpc_rp_pio_get_info(struct dpc_dev *dpc,
146                                 struct dpc_rp_pio_regs *rp_pio)
147 {
148         struct device *dev = &dpc->dev->device;
149         struct pci_dev *pdev = dpc->dev->port;
150         int i;
151         u16 cap = dpc->cap_pos, dpc_status;
152         u32 status;
153
154         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS,
155                               &rp_pio->status);
156         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK,
157                               &rp_pio->mask);
158         dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
159                 rp_pio->status, rp_pio->mask);
160
161         dpc->rp_pio_status = rp_pio->status;
162
163         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY,
164                               &rp_pio->severity);
165         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR,
166                               &rp_pio->syserror);
167         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION,
168                               &rp_pio->exception);
169         dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
170                 rp_pio->severity, rp_pio->syserror, rp_pio->exception);
171
172         /* Get First Error Pointer */
173         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
174         rp_pio->first_error = (dpc_status & 0x1f00) >> 8;
175
176         status = (rp_pio->status & ~rp_pio->mask);
177         for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
178                 if (status & (1 << i))
179                         dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
180                                 rp_pio->first_error == i ? " (First)" : "");
181         }
182
183         if (dpc->rp_log_size < 4)
184                 return;
185         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
186                               &rp_pio->header_log.dw0);
187         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
188                               &rp_pio->header_log.dw1);
189         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
190                               &rp_pio->header_log.dw2);
191         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
192                               &rp_pio->header_log.dw3);
193         dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
194                 rp_pio->header_log.dw0, rp_pio->header_log.dw1,
195                 rp_pio->header_log.dw2, rp_pio->header_log.dw3);
196
197         if (dpc->rp_log_size < 5)
198                 return;
199         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG,
200                               &rp_pio->impspec_log);
201         dev_err(dev, "RP PIO ImpSpec Log %#010x\n", rp_pio->impspec_log);
202
203         for (i = 0; i < dpc->rp_log_size - 5; i++) {
204                 pci_read_config_dword(pdev,
205                         cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
206                         &rp_pio->tlp_prefix_log[i]);
207                 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i,
208                         rp_pio->tlp_prefix_log[i]);
209         }
210 }
211
212 static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
213 {
214         struct dpc_rp_pio_regs rp_pio_regs;
215
216         dpc_rp_pio_get_info(dpc, &rp_pio_regs);
217
218 }
219
220 static irqreturn_t dpc_irq(int irq, void *context)
221 {
222         struct dpc_dev *dpc = (struct dpc_dev *)context;
223         struct pci_dev *pdev = dpc->dev->port;
224         struct device *dev = &dpc->dev->device;
225         u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason;
226
227         pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
228
229         if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0))
230                 return IRQ_NONE;
231
232         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
233
234         if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT))
235                 return IRQ_NONE;
236
237         if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) {
238                 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
239                                       PCI_EXP_DPC_STATUS_INTERRUPT);
240                 return IRQ_HANDLED;
241         }
242
243         pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
244                               ctl & ~PCI_EXP_DPC_CTL_INT_EN);
245
246         pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID,
247                              &source);
248
249         dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
250                 status, source);
251
252         reason = (status >> 1) & 0x3;
253         ext_reason = (status >> 5) & 0x3;
254
255         dev_warn(dev, "DPC %s detected, remove downstream devices\n",
256                  (reason == 0) ? "unmasked uncorrectable error" :
257                  (reason == 1) ? "ERR_NONFATAL" :
258                  (reason == 2) ? "ERR_FATAL" :
259                  (ext_reason == 0) ? "RP PIO error" :
260                  (ext_reason == 1) ? "software trigger" :
261                                      "reserved error");
262         /* show RP PIO error detail information */
263         if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
264                 dpc_process_rp_pio_error(dpc);
265
266         schedule_work(&dpc->work);
267
268         return IRQ_HANDLED;
269 }
270
271 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
272 static int dpc_probe(struct pcie_device *dev)
273 {
274         struct dpc_dev *dpc;
275         struct pci_dev *pdev = dev->port;
276         struct device *device = &dev->device;
277         int status;
278         u16 ctl, cap;
279
280         if (pcie_aer_get_firmware_first(pdev))
281                 return -ENOTSUPP;
282
283         dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
284         if (!dpc)
285                 return -ENOMEM;
286
287         dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
288         dpc->dev = dev;
289         INIT_WORK(&dpc->work, dpc_work);
290         set_service_data(dev, dpc);
291
292         status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
293                                   "pcie-dpc", dpc);
294         if (status) {
295                 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
296                          status);
297                 return status;
298         }
299
300         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
301         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
302
303         dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
304         if (dpc->rp_extensions) {
305                 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
306                 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
307                         dev_err(device, "RP PIO log size %u is invalid\n",
308                                 dpc->rp_log_size);
309                         dpc->rp_log_size = 0;
310                 }
311         }
312
313         ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
314         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
315
316         dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
317                 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
318                 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
319                 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
320                 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
321         return status;
322 }
323
324 static void dpc_remove(struct pcie_device *dev)
325 {
326         struct dpc_dev *dpc = get_service_data(dev);
327         struct pci_dev *pdev = dev->port;
328         u16 ctl;
329
330         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
331         ctl &= ~(PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN);
332         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
333 }
334
335 static struct pcie_port_service_driver dpcdriver = {
336         .name           = "dpc",
337         .port_type      = PCIE_ANY_PORT,
338         .service        = PCIE_PORT_SERVICE_DPC,
339         .probe          = dpc_probe,
340         .remove         = dpc_remove,
341 };
342
343 static int __init dpc_service_init(void)
344 {
345         return pcie_port_service_register(&dpcdriver);
346 }
347 device_initcall(dpc_service_init);