PCI/DPC: Add and use DPC Status register field definitions
[muen/linux.git] / drivers / pci / pcie / pcie-dpc.c
1 /*
2  * PCI Express Downstream Port Containment services driver
3  * Author: Keith Busch <keith.busch@intel.com>
4  *
5  * Copyright (C) 2016 Intel Corp.
6  *
7  * This file is subject to the terms and conditions of the GNU General Public
8  * License.  See the file "COPYING" in the main directory of this archive
9  * for more details.
10  */
11
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pcieport_if.h>
17 #include "../pci.h"
18 #include "aer/aerdrv.h"
19
20 struct dpc_dev {
21         struct pcie_device      *dev;
22         struct work_struct      work;
23         u16                     cap_pos;
24         bool                    rp_extensions;
25         u32                     rp_pio_status;
26         u8                      rp_log_size;
27 };
28
29 static const char * const rp_pio_error_string[] = {
30         "Configuration Request received UR Completion",  /* Bit Position 0  */
31         "Configuration Request received CA Completion",  /* Bit Position 1  */
32         "Configuration Request Completion Timeout",      /* Bit Position 2  */
33         NULL,
34         NULL,
35         NULL,
36         NULL,
37         NULL,
38         "I/O Request received UR Completion",            /* Bit Position 8  */
39         "I/O Request received CA Completion",            /* Bit Position 9  */
40         "I/O Request Completion Timeout",                /* Bit Position 10 */
41         NULL,
42         NULL,
43         NULL,
44         NULL,
45         NULL,
46         "Memory Request received UR Completion",         /* Bit Position 16 */
47         "Memory Request received CA Completion",         /* Bit Position 17 */
48         "Memory Request Completion Timeout",             /* Bit Position 18 */
49 };
50
51 static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
52 {
53         unsigned long timeout = jiffies + HZ;
54         struct pci_dev *pdev = dpc->dev->port;
55         struct device *dev = &dpc->dev->device;
56         u16 cap = dpc->cap_pos, status;
57
58         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
59         while (status & PCI_EXP_DPC_RP_BUSY &&
60                                         !time_after(jiffies, timeout)) {
61                 msleep(10);
62                 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
63         }
64         if (status & PCI_EXP_DPC_RP_BUSY) {
65                 dev_warn(dev, "DPC root port still busy\n");
66                 return -EBUSY;
67         }
68         return 0;
69 }
70
71 static void dpc_wait_link_inactive(struct dpc_dev *dpc)
72 {
73         unsigned long timeout = jiffies + HZ;
74         struct pci_dev *pdev = dpc->dev->port;
75         struct device *dev = &dpc->dev->device;
76         u16 lnk_status;
77
78         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
79         while (lnk_status & PCI_EXP_LNKSTA_DLLLA &&
80                                         !time_after(jiffies, timeout)) {
81                 msleep(10);
82                 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
83         }
84         if (lnk_status & PCI_EXP_LNKSTA_DLLLA)
85                 dev_warn(dev, "Link state not disabled for DPC event\n");
86 }
87
88 static void dpc_work(struct work_struct *work)
89 {
90         struct dpc_dev *dpc = container_of(work, struct dpc_dev, work);
91         struct pci_dev *dev, *temp, *pdev = dpc->dev->port;
92         struct pci_bus *parent = pdev->subordinate;
93         u16 cap = dpc->cap_pos, ctl;
94
95         pci_lock_rescan_remove();
96         list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
97                                          bus_list) {
98                 pci_dev_get(dev);
99                 pci_dev_set_disconnected(dev, NULL);
100                 if (pci_has_subordinate(dev))
101                         pci_walk_bus(dev->subordinate,
102                                      pci_dev_set_disconnected, NULL);
103                 pci_stop_and_remove_bus_device(dev);
104                 pci_dev_put(dev);
105         }
106         pci_unlock_rescan_remove();
107
108         dpc_wait_link_inactive(dpc);
109         if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
110                 return;
111         if (dpc->rp_extensions && dpc->rp_pio_status) {
112                 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS,
113                                        dpc->rp_pio_status);
114                 dpc->rp_pio_status = 0;
115         }
116
117         pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
118                 PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
119
120         pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
121         pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
122                               ctl | PCI_EXP_DPC_CTL_INT_EN);
123 }
124
125 static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
126 {
127         struct device *dev = &dpc->dev->device;
128         struct pci_dev *pdev = dpc->dev->port;
129         u16 cap = dpc->cap_pos, dpc_status, first_error;
130         u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
131         int i;
132
133         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
134         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
135         dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
136                 status, mask);
137
138         dpc->rp_pio_status = status;
139
140         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
141         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
142         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
143         dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
144                 sev, syserr, exc);
145
146         /* Get First Error Pointer */
147         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
148         first_error = (dpc_status & 0x1f00) >> 8;
149
150         status &= ~mask;
151         for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
152                 if (status & (1 << i))
153                         dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
154                                 first_error == i ? " (First)" : "");
155         }
156
157         if (dpc->rp_log_size < 4)
158                 return;
159         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
160                               &dw0);
161         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
162                               &dw1);
163         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
164                               &dw2);
165         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
166                               &dw3);
167         dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
168                 dw0, dw1, dw2, dw3);
169
170         if (dpc->rp_log_size < 5)
171                 return;
172         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
173         dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
174
175         for (i = 0; i < dpc->rp_log_size - 5; i++) {
176                 pci_read_config_dword(pdev,
177                         cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
178                 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
179         }
180 }
181
182 static irqreturn_t dpc_irq(int irq, void *context)
183 {
184         struct dpc_dev *dpc = (struct dpc_dev *)context;
185         struct pci_dev *pdev = dpc->dev->port;
186         struct device *dev = &dpc->dev->device;
187         u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason;
188
189         pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
190
191         if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0))
192                 return IRQ_NONE;
193
194         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
195
196         if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT))
197                 return IRQ_NONE;
198
199         if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) {
200                 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
201                                       PCI_EXP_DPC_STATUS_INTERRUPT);
202                 return IRQ_HANDLED;
203         }
204
205         pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
206                               ctl & ~PCI_EXP_DPC_CTL_INT_EN);
207
208         pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID,
209                              &source);
210
211         dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
212                 status, source);
213
214         reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
215         ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
216
217         dev_warn(dev, "DPC %s detected, remove downstream devices\n",
218                  (reason == 0) ? "unmasked uncorrectable error" :
219                  (reason == 1) ? "ERR_NONFATAL" :
220                  (reason == 2) ? "ERR_FATAL" :
221                  (ext_reason == 0) ? "RP PIO error" :
222                  (ext_reason == 1) ? "software trigger" :
223                                      "reserved error");
224         /* show RP PIO error detail information */
225         if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
226                 dpc_process_rp_pio_error(dpc);
227
228         schedule_work(&dpc->work);
229
230         return IRQ_HANDLED;
231 }
232
233 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
234 static int dpc_probe(struct pcie_device *dev)
235 {
236         struct dpc_dev *dpc;
237         struct pci_dev *pdev = dev->port;
238         struct device *device = &dev->device;
239         int status;
240         u16 ctl, cap;
241
242         if (pcie_aer_get_firmware_first(pdev))
243                 return -ENOTSUPP;
244
245         dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
246         if (!dpc)
247                 return -ENOMEM;
248
249         dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
250         dpc->dev = dev;
251         INIT_WORK(&dpc->work, dpc_work);
252         set_service_data(dev, dpc);
253
254         status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
255                                   "pcie-dpc", dpc);
256         if (status) {
257                 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
258                          status);
259                 return status;
260         }
261
262         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
263         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
264
265         dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
266         if (dpc->rp_extensions) {
267                 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
268                 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
269                         dev_err(device, "RP PIO log size %u is invalid\n",
270                                 dpc->rp_log_size);
271                         dpc->rp_log_size = 0;
272                 }
273         }
274
275         ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
276         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
277
278         dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
279                 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
280                 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
281                 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
282                 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
283         return status;
284 }
285
286 static void dpc_remove(struct pcie_device *dev)
287 {
288         struct dpc_dev *dpc = get_service_data(dev);
289         struct pci_dev *pdev = dev->port;
290         u16 ctl;
291
292         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
293         ctl &= ~(PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN);
294         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
295 }
296
297 static struct pcie_port_service_driver dpcdriver = {
298         .name           = "dpc",
299         .port_type      = PCIE_ANY_PORT,
300         .service        = PCIE_PORT_SERVICE_DPC,
301         .probe          = dpc_probe,
302         .remove         = dpc_remove,
303 };
304
305 static int __init dpc_service_init(void)
306 {
307         return pcie_port_service_register(&dpcdriver);
308 }
309 device_initcall(dpc_service_init);