50a0fc8305f1c78ee9c029d8d62763926ec357bf
[muen/linux.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2  * Copyright (c) 2016 Linaro Ltd.
3  * Copyright (c) 2016 Hisilicon Limited.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE              0x0
17 #define IOST_BASE_ADDR_LO               0x8
18 #define IOST_BASE_ADDR_HI               0xc
19 #define ITCT_BASE_ADDR_LO               0x10
20 #define ITCT_BASE_ADDR_HI               0x14
21 #define IO_BROKEN_MSG_ADDR_LO           0x18
22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
23 #define PHY_CONTEXT                     0x20
24 #define PHY_STATE                       0x24
25 #define PHY_PORT_NUM_MA                 0x28
26 #define PORT_STATE                      0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE                   0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
33 #define AXI_AHB_CLK_CFG                 0x3c
34 #define ITCT_CLR                        0x44
35 #define ITCT_CLR_EN_OFF                 16
36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF                    0
38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1                       0x48
40 #define AXI_USER2                       0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
47 #define HGC_GET_ITV_TIME                0x90
48 #define DEVICE_MSG_WORK_MODE            0x94
49 #define OPENA_WT_CONTI_TIME             0x9c
50 #define I_T_NEXUS_LOSS_TIME             0xa0
51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
54 #define CFG_AGING_TIME                  0xbc
55 #define HGC_DFX_CFG2                    0xc0
56 #define HGC_IOMB_PROC1_STATUS   0x104
57 #define CFG_1US_TIMER_TRSH              0xcc
58 #define HGC_LM_DFX_STATUS2              0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF         0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61                                          HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF         12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64                                          HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR                0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR               0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF        0
72 #define HGC_IOST_ECC_1B_ADDR_MSK        (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF        16
74 #define HGC_IOST_ECC_MB_ADDR_MSK        (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR                0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO              0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
84 #define HGC_ITCT_ECC_ADDR               0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF                0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK                (0x3ff << \
87                                                  HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF                16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK                (0x3ff << \
90                                                  HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO   0x154
92 #define AXI_ERR_INFO_OFF                0
93 #define AXI_ERR_INFO_MSK                (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF               8
95 #define FIFO_ERR_INFO_MSK               (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN                     0x19c
97 #define OQ_INT_COAL_TIME                0x1a0
98 #define OQ_INT_COAL_CNT                 0x1a4
99 #define ENT_INT_COAL_TIME               0x1a8
100 #define ENT_INT_COAL_CNT                0x1ac
101 #define OQ_INT_SRC                      0x1b0
102 #define OQ_INT_SRC_MSK                  0x1b4
103 #define ENT_INT_SRC1                    0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2                    0x1bc
109 #define ENT_INT_SRC3                    0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
113 #define ENT_INT_SRC3_AXI_OFF                    11
114 #define ENT_INT_SRC3_FIFO_OFF                   12
115 #define ENT_INT_SRC3_LM_OFF                             14
116 #define ENT_INT_SRC3_ITC_INT_OFF        15
117 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF            16
119 #define ENT_INT_SRC_MSK1                0x1c4
120 #define ENT_INT_SRC_MSK2                0x1c8
121 #define ENT_INT_SRC_MSK3                0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR                    0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF             0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF             1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF    2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF    3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF    4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF    5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF        6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF        7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF        8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF        9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF             10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF             11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF        12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF        13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF        14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF        15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF        16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF        17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF        18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF        19
145 #define SAS_ECC_INTR_MSK                0x1ec
146 #define HGC_ERR_STAT_EN                 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
149 #define DLVRY_Q_0_DEPTH                 0x268
150 #define DLVRY_Q_0_WR_PTR                0x26c
151 #define DLVRY_Q_0_RD_PTR                0x270
152 #define HYPER_STREAM_ID_EN_CFG          0xc80
153 #define OQ0_INT_SRC_MSK                 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
156 #define COMPL_Q_0_DEPTH                 0x4e8
157 #define COMPL_Q_0_WR_PTR                0x4ec
158 #define COMPL_Q_0_RD_PTR                0x4f0
159 #define HGC_RXM_DFX_STATUS14    0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF           0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK           (0x1ff << \
162                                                  HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF           9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK           (0x1ff << \
165                                                  HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF           18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK           (0x1ff << \
168                                                  HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15    0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF           0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK           (0x1ff << \
172                                                  HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE                       (0x2000)
175
176 #define PHY_CFG                         (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF                 0
179 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF              2
181 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF      0
184 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL                        (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF              0
187 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
189 #define SL_CFG                          (PORT_BASE + 0x84)
190 #define PHY_PCN                         (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
192 #define SL_CONTROL                      (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF        0
194 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF              17
196 #define SL_CONTROL_CTA_MSK              (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF                1
199 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
207 #define TXID_AUTO                       (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF               1
209 #define TXID_AUTO_CT3_MSK               (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF               11
211 #define TXID_AUTO_CTB_MSK               (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF                  2
213 #define TX_HARDRST_MSK                  (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
222 #define CON_CONTROL                     (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF        0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK        \
225                 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
227 #define CHL_INT0                        (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF            4
235 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF            5
237 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1                        (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT2                        (PORT_BASE + 0x1bc)
244 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
245 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
246 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
247 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
248 #define DMA_TX_DFX0                             (PORT_BASE + 0x200)
249 #define DMA_TX_DFX1                             (PORT_BASE + 0x204)
250 #define DMA_TX_DFX1_IPTT_OFF            0
251 #define DMA_TX_DFX1_IPTT_MSK            (0xffff << DMA_TX_DFX1_IPTT_OFF)
252 #define DMA_TX_FIFO_DFX0                (PORT_BASE + 0x240)
253 #define PORT_DFX0                               (PORT_BASE + 0x258)
254 #define LINK_DFX2                                       (PORT_BASE + 0X264)
255 #define LINK_DFX2_RCVR_HOLD_STS_OFF     9
256 #define LINK_DFX2_RCVR_HOLD_STS_MSK     (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
257 #define LINK_DFX2_SEND_HOLD_STS_OFF     10
258 #define LINK_DFX2_SEND_HOLD_STS_MSK     (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
259 #define SAS_ERR_CNT4_REG                (PORT_BASE + 0x290)
260 #define SAS_ERR_CNT6_REG                (PORT_BASE + 0x298)
261 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
262 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
263 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
264 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
265 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
266 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
267 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
268 #define DMA_TX_STATUS_BUSY_OFF          0
269 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
270 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
271 #define DMA_RX_STATUS_BUSY_OFF          0
272 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
273
274 #define AXI_CFG                         (0x5100)
275 #define AM_CFG_MAX_TRANS                (0x5010)
276 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
277
278 #define AXI_MASTER_CFG_BASE             (0x5000)
279 #define AM_CTRL_GLOBAL                  (0x0)
280 #define AM_CURR_TRANS_RETURN    (0x150)
281
282 /* HW dma structures */
283 /* Delivery queue header */
284 /* dw0 */
285 #define CMD_HDR_ABORT_FLAG_OFF          0
286 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
289 #define CMD_HDR_RESP_REPORT_OFF         5
290 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
291 #define CMD_HDR_TLR_CTRL_OFF            6
292 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
293 #define CMD_HDR_PORT_OFF                18
294 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
295 #define CMD_HDR_PRIORITY_OFF            27
296 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
297 #define CMD_HDR_CMD_OFF                 29
298 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
299 /* dw1 */
300 #define CMD_HDR_DIR_OFF                 5
301 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
302 #define CMD_HDR_RESET_OFF               7
303 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
304 #define CMD_HDR_VDTL_OFF                10
305 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
306 #define CMD_HDR_FRAME_TYPE_OFF          11
307 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
308 #define CMD_HDR_DEV_ID_OFF              16
309 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
310 /* dw2 */
311 #define CMD_HDR_CFL_OFF                 0
312 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
313 #define CMD_HDR_NCQ_TAG_OFF             10
314 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
315 #define CMD_HDR_MRFL_OFF                15
316 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
317 #define CMD_HDR_SG_MOD_OFF              24
318 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
319 #define CMD_HDR_FIRST_BURST_OFF         26
320 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
321 /* dw3 */
322 #define CMD_HDR_IPTT_OFF                0
323 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
324 /* dw6 */
325 #define CMD_HDR_DIF_SGL_LEN_OFF         0
326 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
327 #define CMD_HDR_DATA_SGL_LEN_OFF        16
328 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
329 #define CMD_HDR_ABORT_IPTT_OFF          16
330 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
331
332 /* Completion header */
333 /* dw0 */
334 #define CMPLT_HDR_ERR_PHASE_OFF 2
335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
336 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
337 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
338 #define CMPLT_HDR_ERX_OFF               12
339 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
340 #define CMPLT_HDR_ABORT_STAT_OFF        13
341 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
342 /* abort_stat */
343 #define STAT_IO_NOT_VALID               0x1
344 #define STAT_IO_NO_DEVICE               0x2
345 #define STAT_IO_COMPLETE                0x3
346 #define STAT_IO_ABORTED                 0x4
347 /* dw1 */
348 #define CMPLT_HDR_IPTT_OFF              0
349 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
350 #define CMPLT_HDR_DEV_ID_OFF            16
351 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
352
353 /* ITCT header */
354 /* qw0 */
355 #define ITCT_HDR_DEV_TYPE_OFF           0
356 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
357 #define ITCT_HDR_VALID_OFF              2
358 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
359 #define ITCT_HDR_MCR_OFF                5
360 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
361 #define ITCT_HDR_VLN_OFF                9
362 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
363 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
364 #define ITCT_HDR_SMP_TIMEOUT_8US        1
365 #define ITCT_HDR_SMP_TIMEOUT            (ITCT_HDR_SMP_TIMEOUT_8US * \
366                                          250) /* 2ms */
367 #define ITCT_HDR_AWT_CONTINUE_OFF       25
368 #define ITCT_HDR_PORT_ID_OFF            28
369 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
370 /* qw2 */
371 #define ITCT_HDR_INLT_OFF               0
372 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
373 #define ITCT_HDR_BITLT_OFF              16
374 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
375 #define ITCT_HDR_MCTLT_OFF              32
376 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
377 #define ITCT_HDR_RTOLT_OFF              48
378 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
379
380 #define HISI_SAS_FATAL_INT_NR   2
381
382 struct hisi_sas_complete_v2_hdr {
383         __le32 dw0;
384         __le32 dw1;
385         __le32 act;
386         __le32 dw3;
387 };
388
389 struct hisi_sas_err_record_v2 {
390         /* dw0 */
391         __le32 trans_tx_fail_type;
392
393         /* dw1 */
394         __le32 trans_rx_fail_type;
395
396         /* dw2 */
397         __le16 dma_tx_err_type;
398         __le16 sipc_rx_err_type;
399
400         /* dw3 */
401         __le32 dma_rx_err_type;
402 };
403
404 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
405         {
406                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
407                 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
408                 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
409                 .msg = "hgc_dqe_acc1b_intr found: \
410                                 Ram address is 0x%08X\n",
411                 .reg = HGC_DQE_ECC_ADDR,
412         },
413         {
414                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
415                 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
416                 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
417                 .msg = "hgc_iost_acc1b_intr found: \
418                                 Ram address is 0x%08X\n",
419                 .reg = HGC_IOST_ECC_ADDR,
420         },
421         {
422                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
423                 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
424                 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
425                 .msg = "hgc_itct_acc1b_intr found: \
426                                 Ram address is 0x%08X\n",
427                 .reg = HGC_ITCT_ECC_ADDR,
428         },
429         {
430                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
431                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
432                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
433                 .msg = "hgc_iostl_acc1b_intr found:  \
434                                 memory address is 0x%08X\n",
435                 .reg = HGC_LM_DFX_STATUS2,
436         },
437         {
438                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
439                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
440                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
441                 .msg = "hgc_itctl_acc1b_intr found: \
442                                 memory address is 0x%08X\n",
443                 .reg = HGC_LM_DFX_STATUS2,
444         },
445         {
446                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
447                 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
448                 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
449                 .msg = "hgc_cqe_acc1b_intr found: \
450                                 Ram address is 0x%08X\n",
451                 .reg = HGC_CQE_ECC_ADDR,
452         },
453         {
454                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
455                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
456                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
457                 .msg = "rxm_mem0_acc1b_intr found: \
458                                 memory address is 0x%08X\n",
459                 .reg = HGC_RXM_DFX_STATUS14,
460         },
461         {
462                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
463                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
464                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
465                 .msg = "rxm_mem1_acc1b_intr found: \
466                                 memory address is 0x%08X\n",
467                 .reg = HGC_RXM_DFX_STATUS14,
468         },
469         {
470                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
471                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
472                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
473                 .msg = "rxm_mem2_acc1b_intr found: \
474                                 memory address is 0x%08X\n",
475                 .reg = HGC_RXM_DFX_STATUS14,
476         },
477         {
478                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
479                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
480                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
481                 .msg = "rxm_mem3_acc1b_intr found: \
482                                 memory address is 0x%08X\n",
483                 .reg = HGC_RXM_DFX_STATUS15,
484         },
485 };
486
487 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
488         {
489                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
490                 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
491                 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
492                 .msg = "hgc_dqe_accbad_intr (0x%x) found: \
493                                 Ram address is 0x%08X\n",
494                 .reg = HGC_DQE_ECC_ADDR,
495         },
496         {
497                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
498                 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
499                 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
500                 .msg = "hgc_iost_accbad_intr (0x%x) found: \
501                                 Ram address is 0x%08X\n",
502                 .reg = HGC_IOST_ECC_ADDR,
503         },
504         {
505                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
506                 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
507                 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
508                 .msg = "hgc_itct_accbad_intr (0x%x) found: \
509                                 Ram address is 0x%08X\n",
510                 .reg = HGC_ITCT_ECC_ADDR,
511         },
512         {
513                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
514                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
515                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
516                 .msg = "hgc_iostl_accbad_intr (0x%x) found: \
517                                 memory address is 0x%08X\n",
518                 .reg = HGC_LM_DFX_STATUS2,
519         },
520         {
521                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
522                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
523                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
524                 .msg = "hgc_itctl_accbad_intr (0x%x) found: \
525                                 memory address is 0x%08X\n",
526                 .reg = HGC_LM_DFX_STATUS2,
527         },
528         {
529                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
530                 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
531                 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
532                 .msg = "hgc_cqe_accbad_intr (0x%x) found: \
533                                 Ram address is 0x%08X\n",
534                 .reg = HGC_CQE_ECC_ADDR,
535         },
536         {
537                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
538                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
539                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
540                 .msg = "rxm_mem0_accbad_intr (0x%x) found: \
541                         memory address is 0x%08X\n",
542                 .reg = HGC_RXM_DFX_STATUS14,
543         },
544         {
545                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
546                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
547                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
548                 .msg = "rxm_mem1_accbad_intr (0x%x) found: \
549                         memory address is 0x%08X\n",
550                 .reg = HGC_RXM_DFX_STATUS14,
551         },
552         {
553                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
554                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
555                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
556                 .msg = "rxm_mem2_accbad_intr (0x%x) found: \
557                                 memory address is 0x%08X\n",
558                 .reg = HGC_RXM_DFX_STATUS14,
559         },
560         {
561                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
562                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
563                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
564                 .msg = "rxm_mem3_accbad_intr (0x%x) found: \
565                                 memory address is 0x%08X\n",
566                 .reg = HGC_RXM_DFX_STATUS15,
567         },
568 };
569
570 enum {
571         HISI_SAS_PHY_PHY_UPDOWN,
572         HISI_SAS_PHY_CHNL_INT,
573         HISI_SAS_PHY_INT_NR
574 };
575
576 enum {
577         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
578         TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
579         DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
580         SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
581         DMA_RX_ERR_BASE = 0x60, /* dw3 */
582
583         /* trans tx*/
584         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
585         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
586         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
587         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
588         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
589         RESERVED0, /* 0x5 */
590         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
591         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
592         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
593         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
594         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
595         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
596         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
597         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
598         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
599         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
600         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
601         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
602         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
603         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
604         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
605         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
606         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
607         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
608         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
609         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
610         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
611         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
612         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
613         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
614         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
615         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
616         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
617         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
618         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
619
620         /* trans rx */
621         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
622         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
623         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
624         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
625         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
626         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
627         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
628         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
629         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
630         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
631         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
632         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
633         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
634         RESERVED1, /* 0x2b */
635         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
636         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
637         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
638         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
639         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
640         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
641         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
642         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
643         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
644         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
645         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
646         RESERVED2, /* 0x34 */
647         RESERVED3, /* 0x35 */
648         RESERVED4, /* 0x36 */
649         RESERVED5, /* 0x37 */
650         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
651         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
652         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
653         RESERVED6, /* 0x3b */
654         RESERVED7, /* 0x3c */
655         RESERVED8, /* 0x3d */
656         RESERVED9, /* 0x3e */
657         TRANS_RX_R_ERR, /* 0x3f */
658
659         /* dma tx */
660         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
661         DMA_TX_DIF_APP_ERR, /* 0x41 */
662         DMA_TX_DIF_RPP_ERR, /* 0x42 */
663         DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
664         DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
665         DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
666         DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
667         DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
668         DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
669         DMA_TX_RAM_ECC_ERR, /* 0x49 */
670         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
671         DMA_TX_MAX_ERR_CODE,
672
673         /* sipc rx */
674         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
675         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
676         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
677         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
678         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
679         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
680         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
681         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
682         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
683         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
684         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
685         SIPC_RX_MAX_ERR_CODE,
686
687         /* dma rx */
688         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
689         DMA_RX_DIF_APP_ERR, /* 0x61 */
690         DMA_RX_DIF_RPP_ERR, /* 0x62 */
691         DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
692         DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
693         DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
694         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
695         DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
696         RESERVED10, /* 0x68 */
697         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
698         DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
699         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
700         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
701         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
702         DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
703         DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
704         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
705         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
706         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
707         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
708         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
709         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
710         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
711         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
712         DMA_RX_RAM_ECC_ERR, /* 0x78 */
713         DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
714         DMA_RX_MAX_ERR_CODE,
715 };
716
717 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
718 #define HISI_MAX_SATA_SUPPORT_V2_HW     (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
719
720 #define DIR_NO_DATA 0
721 #define DIR_TO_INI 1
722 #define DIR_TO_DEVICE 2
723 #define DIR_RESERVED 3
724
725 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
726                 err_phase == 0x4 || err_phase == 0x8 ||\
727                 err_phase == 0x6 || err_phase == 0xa)
728 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
729                 err_phase == 0x20 || err_phase == 0x40)
730
731 static void link_timeout_disable_link(unsigned long data);
732
733 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
734 {
735         void __iomem *regs = hisi_hba->regs + off;
736
737         return readl(regs);
738 }
739
740 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
741 {
742         void __iomem *regs = hisi_hba->regs + off;
743
744         return readl_relaxed(regs);
745 }
746
747 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
748 {
749         void __iomem *regs = hisi_hba->regs + off;
750
751         writel(val, regs);
752 }
753
754 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
755                                  u32 off, u32 val)
756 {
757         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
758
759         writel(val, regs);
760 }
761
762 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
763                                       int phy_no, u32 off)
764 {
765         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
766
767         return readl(regs);
768 }
769
770 /* This function needs to be protected from pre-emption. */
771 static int
772 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
773                              struct domain_device *device)
774 {
775         int sata_dev = dev_is_sata(device);
776         void *bitmap = hisi_hba->slot_index_tags;
777         struct hisi_sas_device *sas_dev = device->lldd_dev;
778         int sata_idx = sas_dev->sata_idx;
779         int start, end;
780
781         if (!sata_dev) {
782                 /*
783                  * STP link SoC bug workaround: index starts from 1.
784                  * additionally, we can only allocate odd IPTT(1~4095)
785                  * for SAS/SMP device.
786                  */
787                 start = 1;
788                 end = hisi_hba->slot_index_count;
789         } else {
790                 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
791                         return -EINVAL;
792
793                 /*
794                  * For SATA device: allocate even IPTT in this interval
795                  * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
796                  * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
797                  * SoC bug workaround. So we ignore the first 32 even IPTTs.
798                  */
799                 start = 64 * (sata_idx + 1);
800                 end = 64 * (sata_idx + 2);
801         }
802
803         while (1) {
804                 start = find_next_zero_bit(bitmap,
805                                         hisi_hba->slot_index_count, start);
806                 if (start >= end)
807                         return -SAS_QUEUE_FULL;
808                 /*
809                   * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
810                   */
811                 if (sata_dev ^ (start & 1))
812                         break;
813                 start++;
814         }
815
816         set_bit(start, bitmap);
817         *slot_idx = start;
818         return 0;
819 }
820
821 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
822 {
823         unsigned int index;
824         struct device *dev = hisi_hba->dev;
825         void *bitmap = hisi_hba->sata_dev_bitmap;
826
827         index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
828         if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
829                 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
830                 return false;
831         }
832
833         set_bit(index, bitmap);
834         *idx = index;
835         return true;
836 }
837
838
839 static struct
840 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
841 {
842         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
843         struct hisi_sas_device *sas_dev = NULL;
844         int i, sata_dev = dev_is_sata(device);
845         int sata_idx = -1;
846         unsigned long flags;
847
848         spin_lock_irqsave(&hisi_hba->lock, flags);
849
850         if (sata_dev)
851                 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
852                         goto out;
853
854         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
855                 /*
856                  * SATA device id bit0 should be 0
857                  */
858                 if (sata_dev && (i & 1))
859                         continue;
860                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
861                         int queue = i % hisi_hba->queue_count;
862                         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
863
864                         hisi_hba->devices[i].device_id = i;
865                         sas_dev = &hisi_hba->devices[i];
866                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
867                         sas_dev->dev_type = device->dev_type;
868                         sas_dev->hisi_hba = hisi_hba;
869                         sas_dev->sas_device = device;
870                         sas_dev->sata_idx = sata_idx;
871                         sas_dev->dq = dq;
872                         INIT_LIST_HEAD(&hisi_hba->devices[i].list);
873                         break;
874                 }
875         }
876
877 out:
878         spin_unlock_irqrestore(&hisi_hba->lock, flags);
879
880         return sas_dev;
881 }
882
883 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
884 {
885         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
886
887         cfg &= ~PHY_CFG_DC_OPT_MSK;
888         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
889         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
890 }
891
892 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
893 {
894         struct sas_identify_frame identify_frame;
895         u32 *identify_buffer;
896
897         memset(&identify_frame, 0, sizeof(identify_frame));
898         identify_frame.dev_type = SAS_END_DEVICE;
899         identify_frame.frame_type = 0;
900         identify_frame._un1 = 1;
901         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
902         identify_frame.target_bits = SAS_PROTOCOL_NONE;
903         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
904         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
905         identify_frame.phy_id = phy_no;
906         identify_buffer = (u32 *)(&identify_frame);
907
908         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
909                         __swab32(identify_buffer[0]));
910         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
911                         __swab32(identify_buffer[1]));
912         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
913                         __swab32(identify_buffer[2]));
914         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
915                         __swab32(identify_buffer[3]));
916         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
917                         __swab32(identify_buffer[4]));
918         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
919                         __swab32(identify_buffer[5]));
920 }
921
922 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
923                              struct hisi_sas_device *sas_dev)
924 {
925         struct domain_device *device = sas_dev->sas_device;
926         struct device *dev = hisi_hba->dev;
927         u64 qw0, device_id = sas_dev->device_id;
928         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
929         struct domain_device *parent_dev = device->parent;
930         struct asd_sas_port *sas_port = device->port;
931         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
932
933         memset(itct, 0, sizeof(*itct));
934
935         /* qw0 */
936         qw0 = 0;
937         switch (sas_dev->dev_type) {
938         case SAS_END_DEVICE:
939         case SAS_EDGE_EXPANDER_DEVICE:
940         case SAS_FANOUT_EXPANDER_DEVICE:
941                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
942                 break;
943         case SAS_SATA_DEV:
944         case SAS_SATA_PENDING:
945                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
946                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
947                 else
948                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
949                 break;
950         default:
951                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
952                          sas_dev->dev_type);
953         }
954
955         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
956                 (device->linkrate << ITCT_HDR_MCR_OFF) |
957                 (1 << ITCT_HDR_VLN_OFF) |
958                 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
959                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
960                 (port->id << ITCT_HDR_PORT_ID_OFF));
961         itct->qw0 = cpu_to_le64(qw0);
962
963         /* qw1 */
964         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
965         itct->sas_addr = __swab64(itct->sas_addr);
966
967         /* qw2 */
968         if (!dev_is_sata(device))
969                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
970                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
971                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
972                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
973 }
974
975 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
976                               struct hisi_sas_device *sas_dev)
977 {
978         DECLARE_COMPLETION_ONSTACK(completion);
979         u64 dev_id = sas_dev->device_id;
980         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
981         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
982         int i;
983
984         sas_dev->completion = &completion;
985
986         /* SoC bug workaround */
987         if (dev_is_sata(sas_dev->sas_device))
988                 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
989
990         /* clear the itct interrupt state */
991         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
992                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
993                                  ENT_INT_SRC3_ITC_INT_MSK);
994
995         for (i = 0; i < 2; i++) {
996                 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
997                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
998                 wait_for_completion(sas_dev->completion);
999
1000                 memset(itct, 0, sizeof(struct hisi_sas_itct));
1001         }
1002 }
1003
1004 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1005 {
1006         int i, reset_val;
1007         u32 val;
1008         unsigned long end_time;
1009         struct device *dev = hisi_hba->dev;
1010
1011         /* The mask needs to be set depending on the number of phys */
1012         if (hisi_hba->n_phy == 9)
1013                 reset_val = 0x1fffff;
1014         else
1015                 reset_val = 0x7ffff;
1016
1017         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1018
1019         /* Disable all of the PHYs */
1020         for (i = 0; i < hisi_hba->n_phy; i++) {
1021                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1022
1023                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1024                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1025         }
1026         udelay(50);
1027
1028         /* Ensure DMA tx & rx idle */
1029         for (i = 0; i < hisi_hba->n_phy; i++) {
1030                 u32 dma_tx_status, dma_rx_status;
1031
1032                 end_time = jiffies + msecs_to_jiffies(1000);
1033
1034                 while (1) {
1035                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1036                                                             DMA_TX_STATUS);
1037                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1038                                                             DMA_RX_STATUS);
1039
1040                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1041                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1042                                 break;
1043
1044                         msleep(20);
1045                         if (time_after(jiffies, end_time))
1046                                 return -EIO;
1047                 }
1048         }
1049
1050         /* Ensure axi bus idle */
1051         end_time = jiffies + msecs_to_jiffies(1000);
1052         while (1) {
1053                 u32 axi_status =
1054                         hisi_sas_read32(hisi_hba, AXI_CFG);
1055
1056                 if (axi_status == 0)
1057                         break;
1058
1059                 msleep(20);
1060                 if (time_after(jiffies, end_time))
1061                         return -EIO;
1062         }
1063
1064         if (ACPI_HANDLE(dev)) {
1065                 acpi_status s;
1066
1067                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1068                 if (ACPI_FAILURE(s)) {
1069                         dev_err(dev, "Reset failed\n");
1070                         return -EIO;
1071                 }
1072         } else if (hisi_hba->ctrl) {
1073                 /* reset and disable clock*/
1074                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1075                                 reset_val);
1076                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1077                                 reset_val);
1078                 msleep(1);
1079                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1080                 if (reset_val != (val & reset_val)) {
1081                         dev_err(dev, "SAS reset fail.\n");
1082                         return -EIO;
1083                 }
1084
1085                 /* De-reset and enable clock*/
1086                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1087                                 reset_val);
1088                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1089                                 reset_val);
1090                 msleep(1);
1091                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1092                                 &val);
1093                 if (val & reset_val) {
1094                         dev_err(dev, "SAS de-reset fail.\n");
1095                         return -EIO;
1096                 }
1097         } else
1098                 dev_warn(dev, "no reset method\n");
1099
1100         return 0;
1101 }
1102
1103 /* This function needs to be called after resetting SAS controller. */
1104 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1105 {
1106         u32 cfg;
1107         int phy_no;
1108
1109         hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1110         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1111                 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1112                 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1113                         continue;
1114
1115                 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1116                 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1117         }
1118 }
1119
1120 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1121 {
1122         int phy_no;
1123         u32 dma_tx_dfx1;
1124
1125         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1126                 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1127                         continue;
1128
1129                 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1130                                                 DMA_TX_DFX1);
1131                 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1132                         u32 cfg = hisi_sas_phy_read32(hisi_hba,
1133                                 phy_no, CON_CONTROL);
1134
1135                         cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1136                         hisi_sas_phy_write32(hisi_hba, phy_no,
1137                                 CON_CONTROL, cfg);
1138                         clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1139                 }
1140         }
1141 }
1142
1143 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1144 {
1145         struct device *dev = hisi_hba->dev;
1146         int i;
1147
1148         /* Global registers init */
1149
1150         /* Deal with am-max-transmissions quirk */
1151         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1152                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1153                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1154                                  0x2020);
1155         } /* Else, use defaults -> do nothing */
1156
1157         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1158                          (u32)((1ULL << hisi_hba->queue_count) - 1));
1159         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1160         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1161         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1162         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1163         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1164         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1165         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1166         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1167         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1168         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1169         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1170         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1171         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1172         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1173         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1174         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1175         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1176         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1177         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1178         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1179         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1180         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1181         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1182         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1183         for (i = 0; i < hisi_hba->queue_count; i++)
1184                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1185
1186         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1187         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1188
1189         for (i = 0; i < hisi_hba->n_phy; i++) {
1190                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1191                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1192                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1193                 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1194                 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1195                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1196                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1197                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1198                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1199                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1200                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1201                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
1202                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1203                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1204                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1205                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1206                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1207                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1208                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1209                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1210                 if (hisi_hba->refclk_frequency_mhz == 66)
1211                         hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1212                 /* else, do nothing -> leave it how you found it */
1213         }
1214
1215         for (i = 0; i < hisi_hba->queue_count; i++) {
1216                 /* Delivery queue */
1217                 hisi_sas_write32(hisi_hba,
1218                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1219                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1220
1221                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1222                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1223
1224                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1225                                  HISI_SAS_QUEUE_SLOTS);
1226
1227                 /* Completion queue */
1228                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1229                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1230
1231                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1232                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1233
1234                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1235                                  HISI_SAS_QUEUE_SLOTS);
1236         }
1237
1238         /* itct */
1239         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1240                          lower_32_bits(hisi_hba->itct_dma));
1241
1242         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1243                          upper_32_bits(hisi_hba->itct_dma));
1244
1245         /* iost */
1246         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1247                          lower_32_bits(hisi_hba->iost_dma));
1248
1249         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1250                          upper_32_bits(hisi_hba->iost_dma));
1251
1252         /* breakpoint */
1253         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1254                          lower_32_bits(hisi_hba->breakpoint_dma));
1255
1256         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1257                          upper_32_bits(hisi_hba->breakpoint_dma));
1258
1259         /* SATA broken msg */
1260         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1261                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
1262
1263         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1264                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
1265
1266         /* SATA initial fis */
1267         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1268                          lower_32_bits(hisi_hba->initial_fis_dma));
1269
1270         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1271                          upper_32_bits(hisi_hba->initial_fis_dma));
1272 }
1273
1274 static void link_timeout_enable_link(unsigned long data)
1275 {
1276         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1277         int i, reg_val;
1278
1279         for (i = 0; i < hisi_hba->n_phy; i++) {
1280                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1281                         continue;
1282
1283                 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1284                 if (!(reg_val & BIT(0))) {
1285                         hisi_sas_phy_write32(hisi_hba, i,
1286                                         CON_CONTROL, 0x7);
1287                         break;
1288                 }
1289         }
1290
1291         hisi_hba->timer.function = link_timeout_disable_link;
1292         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1293 }
1294
1295 static void link_timeout_disable_link(unsigned long data)
1296 {
1297         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1298         int i, reg_val;
1299
1300         reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1301         for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1302                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1303                         continue;
1304
1305                 if (reg_val & BIT(i)) {
1306                         hisi_sas_phy_write32(hisi_hba, i,
1307                                         CON_CONTROL, 0x6);
1308                         break;
1309                 }
1310         }
1311
1312         hisi_hba->timer.function = link_timeout_enable_link;
1313         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1314 }
1315
1316 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1317 {
1318         hisi_hba->timer.data = (unsigned long)hisi_hba;
1319         hisi_hba->timer.function = link_timeout_disable_link;
1320         hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1321         add_timer(&hisi_hba->timer);
1322 }
1323
1324 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1325 {
1326         struct device *dev = hisi_hba->dev;
1327         int rc;
1328
1329         rc = reset_hw_v2_hw(hisi_hba);
1330         if (rc) {
1331                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1332                 return rc;
1333         }
1334
1335         msleep(100);
1336         init_reg_v2_hw(hisi_hba);
1337
1338         return 0;
1339 }
1340
1341 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1342 {
1343         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1344
1345         cfg |= PHY_CFG_ENA_MSK;
1346         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1347 }
1348
1349 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1350 {
1351         u32 context;
1352
1353         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1354         if (context & (1 << phy_no))
1355                 return true;
1356
1357         return false;
1358 }
1359
1360 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1361 {
1362         u32 dfx_val;
1363
1364         dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1365
1366         if (dfx_val & BIT(16))
1367                 return false;
1368
1369         return true;
1370 }
1371
1372 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1373 {
1374         int i, max_loop = 1000;
1375         struct device *dev = hisi_hba->dev;
1376         u32 status, axi_status, dfx_val, dfx_tx_val;
1377
1378         for (i = 0; i < max_loop; i++) {
1379                 status = hisi_sas_read32_relaxed(hisi_hba,
1380                         AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1381
1382                 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1383                 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1384                 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1385                         phy_no, DMA_TX_FIFO_DFX0);
1386
1387                 if ((status == 0x3) && (axi_status == 0x0) &&
1388                     (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1389                         return true;
1390                 udelay(10);
1391         }
1392         dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1393                         phy_no, status, axi_status,
1394                         dfx_val, dfx_tx_val);
1395         return false;
1396 }
1397
1398 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1399 {
1400         int i, max_loop = 1000;
1401         struct device *dev = hisi_hba->dev;
1402         u32 status, tx_dfx0;
1403
1404         for (i = 0; i < max_loop; i++) {
1405                 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1406                 status = (status & 0x3fc0) >> 6;
1407
1408                 if (status != 0x1)
1409                         return true;
1410
1411                 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1412                 if ((tx_dfx0 & 0x1ff) == 0x2)
1413                         return true;
1414                 udelay(10);
1415         }
1416         dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1417                         phy_no, status, tx_dfx0);
1418         return false;
1419 }
1420
1421 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1422 {
1423         if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1424                 return true;
1425
1426         if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1427                 return false;
1428
1429         if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1430                 return false;
1431
1432         return true;
1433 }
1434
1435
1436 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1437 {
1438         u32 cfg, axi_val, dfx0_val, txid_auto;
1439         struct device *dev = hisi_hba->dev;
1440
1441         /* Close axi bus. */
1442         axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1443                                 AM_CTRL_GLOBAL);
1444         axi_val |= 0x1;
1445         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1446                 AM_CTRL_GLOBAL, axi_val);
1447
1448         if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1449                 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1450                         goto do_disable;
1451
1452                 /* Reset host controller. */
1453                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1454                 return;
1455         }
1456
1457         dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1458         dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1459         if (dfx0_val != 0x4)
1460                 goto do_disable;
1461
1462         if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1463                 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1464                         phy_no);
1465                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1466                                         TXID_AUTO);
1467                 txid_auto |= TXID_AUTO_CTB_MSK;
1468                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1469                                         txid_auto);
1470         }
1471
1472 do_disable:
1473         cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1474         cfg &= ~PHY_CFG_ENA_MSK;
1475         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1476
1477         /* Open axi bus. */
1478         axi_val &= ~0x1;
1479         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1480                 AM_CTRL_GLOBAL, axi_val);
1481 }
1482
1483 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1484 {
1485         config_id_frame_v2_hw(hisi_hba, phy_no);
1486         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1487         enable_phy_v2_hw(hisi_hba, phy_no);
1488 }
1489
1490 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1491 {
1492         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1493         u32 txid_auto;
1494
1495         disable_phy_v2_hw(hisi_hba, phy_no);
1496         if (phy->identify.device_type == SAS_END_DEVICE) {
1497                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1498                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1499                                         txid_auto | TX_HARDRST_MSK);
1500         }
1501         msleep(100);
1502         start_phy_v2_hw(hisi_hba, phy_no);
1503 }
1504
1505 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1506 {
1507         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1508         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1509         struct sas_phy *sphy = sas_phy->phy;
1510         u32 err4_reg_val, err6_reg_val;
1511
1512         /* loss dword syn, phy reset problem */
1513         err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1514
1515         /* disparity err, invalid dword */
1516         err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1517
1518         sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1519         sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1520         sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1521         sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1522 }
1523
1524 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1525 {
1526         int i;
1527
1528         for (i = 0; i < hisi_hba->n_phy; i++) {
1529                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1530                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1531
1532                 if (!sas_phy->phy->enabled)
1533                         continue;
1534
1535                 start_phy_v2_hw(hisi_hba, i);
1536         }
1537 }
1538
1539 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1540 {
1541         u32 sl_control;
1542
1543         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1544         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1545         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1546         msleep(1);
1547         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1548         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1549         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1550 }
1551
1552 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1553 {
1554         return SAS_LINK_RATE_12_0_GBPS;
1555 }
1556
1557 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1558                 struct sas_phy_linkrates *r)
1559 {
1560         u32 prog_phy_link_rate =
1561                 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1562         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1563         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1564         int i;
1565         enum sas_linkrate min, max;
1566         u32 rate_mask = 0;
1567
1568         if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1569                 max = sas_phy->phy->maximum_linkrate;
1570                 min = r->minimum_linkrate;
1571         } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1572                 max = r->maximum_linkrate;
1573                 min = sas_phy->phy->minimum_linkrate;
1574         } else
1575                 return;
1576
1577         sas_phy->phy->maximum_linkrate = max;
1578         sas_phy->phy->minimum_linkrate = min;
1579
1580         min -= SAS_LINK_RATE_1_5_GBPS;
1581         max -= SAS_LINK_RATE_1_5_GBPS;
1582
1583         for (i = 0; i <= max; i++)
1584                 rate_mask |= 1 << (i * 2);
1585
1586         prog_phy_link_rate &= ~0xff;
1587         prog_phy_link_rate |= rate_mask;
1588
1589         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1590                         prog_phy_link_rate);
1591
1592         phy_hard_reset_v2_hw(hisi_hba, phy_no);
1593 }
1594
1595 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1596 {
1597         int i, bitmap = 0;
1598         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1599         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1600
1601         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1602                 if (phy_state & 1 << i)
1603                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1604                                 bitmap |= 1 << i;
1605
1606         if (hisi_hba->n_phy == 9) {
1607                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1608
1609                 if (phy_state & 1 << 8)
1610                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1611                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1612                                 bitmap |= 1 << 9;
1613         }
1614
1615         return bitmap;
1616 }
1617
1618 /*
1619  * The callpath to this function and upto writing the write
1620  * queue pointer should be safe from interruption.
1621  */
1622 static int
1623 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1624 {
1625         struct device *dev = hisi_hba->dev;
1626         int queue = dq->id;
1627         u32 r, w;
1628
1629         w = dq->wr_point;
1630         r = hisi_sas_read32_relaxed(hisi_hba,
1631                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1632         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1633                 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1634                                 queue, r, w);
1635                 return -EAGAIN;
1636         }
1637
1638         return 0;
1639 }
1640
1641 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1642 {
1643         struct hisi_hba *hisi_hba = dq->hisi_hba;
1644         int dlvry_queue = dq->slot_prep->dlvry_queue;
1645         int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1646
1647         dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1648         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1649                          dq->wr_point);
1650 }
1651
1652 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1653                               struct hisi_sas_slot *slot,
1654                               struct hisi_sas_cmd_hdr *hdr,
1655                               struct scatterlist *scatter,
1656                               int n_elem)
1657 {
1658         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1659         struct device *dev = hisi_hba->dev;
1660         struct scatterlist *sg;
1661         int i;
1662
1663         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1664                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1665                         n_elem);
1666                 return -EINVAL;
1667         }
1668
1669         for_each_sg(scatter, sg, n_elem, i) {
1670                 struct hisi_sas_sge *entry = &sge_page->sge[i];
1671
1672                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1673                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1674                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1675                 entry->data_off = 0;
1676         }
1677
1678         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1679
1680         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1681
1682         return 0;
1683 }
1684
1685 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1686                           struct hisi_sas_slot *slot)
1687 {
1688         struct sas_task *task = slot->task;
1689         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1690         struct domain_device *device = task->dev;
1691         struct device *dev = hisi_hba->dev;
1692         struct hisi_sas_port *port = slot->port;
1693         struct scatterlist *sg_req, *sg_resp;
1694         struct hisi_sas_device *sas_dev = device->lldd_dev;
1695         dma_addr_t req_dma_addr;
1696         unsigned int req_len, resp_len;
1697         int elem, rc;
1698
1699         /*
1700         * DMA-map SMP request, response buffers
1701         */
1702         /* req */
1703         sg_req = &task->smp_task.smp_req;
1704         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1705         if (!elem)
1706                 return -ENOMEM;
1707         req_len = sg_dma_len(sg_req);
1708         req_dma_addr = sg_dma_address(sg_req);
1709
1710         /* resp */
1711         sg_resp = &task->smp_task.smp_resp;
1712         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1713         if (!elem) {
1714                 rc = -ENOMEM;
1715                 goto err_out_req;
1716         }
1717         resp_len = sg_dma_len(sg_resp);
1718         if ((req_len & 0x3) || (resp_len & 0x3)) {
1719                 rc = -EINVAL;
1720                 goto err_out_resp;
1721         }
1722
1723         /* create header */
1724         /* dw0 */
1725         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1726                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1727                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1728
1729         /* map itct entry */
1730         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1731                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1732                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1733
1734         /* dw2 */
1735         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1736                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1737                                CMD_HDR_MRFL_OFF));
1738
1739         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1740
1741         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1742         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1743
1744         return 0;
1745
1746 err_out_resp:
1747         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1748                      DMA_FROM_DEVICE);
1749 err_out_req:
1750         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1751                      DMA_TO_DEVICE);
1752         return rc;
1753 }
1754
1755 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1756                           struct hisi_sas_slot *slot, int is_tmf,
1757                           struct hisi_sas_tmf_task *tmf)
1758 {
1759         struct sas_task *task = slot->task;
1760         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1761         struct domain_device *device = task->dev;
1762         struct hisi_sas_device *sas_dev = device->lldd_dev;
1763         struct hisi_sas_port *port = slot->port;
1764         struct sas_ssp_task *ssp_task = &task->ssp_task;
1765         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1766         int has_data = 0, rc, priority = is_tmf;
1767         u8 *buf_cmd;
1768         u32 dw1 = 0, dw2 = 0;
1769
1770         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1771                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1772                                (port->id << CMD_HDR_PORT_OFF) |
1773                                (priority << CMD_HDR_PRIORITY_OFF) |
1774                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1775
1776         dw1 = 1 << CMD_HDR_VDTL_OFF;
1777         if (is_tmf) {
1778                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1779                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1780         } else {
1781                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1782                 switch (scsi_cmnd->sc_data_direction) {
1783                 case DMA_TO_DEVICE:
1784                         has_data = 1;
1785                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1786                         break;
1787                 case DMA_FROM_DEVICE:
1788                         has_data = 1;
1789                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1790                         break;
1791                 default:
1792                         dw1 &= ~CMD_HDR_DIR_MSK;
1793                 }
1794         }
1795
1796         /* map itct entry */
1797         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1798         hdr->dw1 = cpu_to_le32(dw1);
1799
1800         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1801               + 3) / 4) << CMD_HDR_CFL_OFF) |
1802               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1803               (2 << CMD_HDR_SG_MOD_OFF);
1804         hdr->dw2 = cpu_to_le32(dw2);
1805
1806         hdr->transfer_tags = cpu_to_le32(slot->idx);
1807
1808         if (has_data) {
1809                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1810                                         slot->n_elem);
1811                 if (rc)
1812                         return rc;
1813         }
1814
1815         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1816         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1817         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1818
1819         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1820                 sizeof(struct ssp_frame_hdr);
1821
1822         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1823         if (!is_tmf) {
1824                 buf_cmd[9] = task->ssp_task.task_attr |
1825                                 (task->ssp_task.task_prio << 3);
1826                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1827                                 task->ssp_task.cmd->cmd_len);
1828         } else {
1829                 buf_cmd[10] = tmf->tmf;
1830                 switch (tmf->tmf) {
1831                 case TMF_ABORT_TASK:
1832                 case TMF_QUERY_TASK:
1833                         buf_cmd[12] =
1834                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1835                         buf_cmd[13] =
1836                                 tmf->tag_of_task_to_be_managed & 0xff;
1837                         break;
1838                 default:
1839                         break;
1840                 }
1841         }
1842
1843         return 0;
1844 }
1845
1846 #define TRANS_TX_ERR    0
1847 #define TRANS_RX_ERR    1
1848 #define DMA_TX_ERR              2
1849 #define SIPC_RX_ERR             3
1850 #define DMA_RX_ERR              4
1851
1852 #define DMA_TX_ERR_OFF  0
1853 #define DMA_TX_ERR_MSK  (0xffff << DMA_TX_ERR_OFF)
1854 #define SIPC_RX_ERR_OFF 16
1855 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1856
1857 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1858 {
1859         static const u8 trans_tx_err_code_prio[] = {
1860                 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1861                 TRANS_TX_ERR_PHY_NOT_ENABLE,
1862                 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1863                 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1864                 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1865                 RESERVED0,
1866                 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1867                 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1868                 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1869                 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1870                 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1871                 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1872                 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1873                 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1874                 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1875                 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1876                 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1877                 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1878                 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1879                 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1880                 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1881                 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1882                 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1883                 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1884                 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1885                 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1886                 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1887                 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1888                 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1889                 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1890                 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1891         };
1892         int index, i;
1893
1894         for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1895                 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1896                 if (err_msk & (1 << index))
1897                         return trans_tx_err_code_prio[i];
1898         }
1899         return -1;
1900 }
1901
1902 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1903 {
1904         static const u8 trans_rx_err_code_prio[] = {
1905                 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1906                 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1907                 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1908                 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1909                 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1910                 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1911                 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1912                 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1913                 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1914                 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1915                 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1916                 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1917                 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1918                 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1919                 RESERVED1,
1920                 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1921                 TRANS_RX_ERR_WITH_DATA_LEN0,
1922                 TRANS_RX_ERR_WITH_BAD_HASH,
1923                 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1924                 TRANS_RX_SSP_FRM_LEN_ERR,
1925                 RESERVED2,
1926                 RESERVED3,
1927                 RESERVED4,
1928                 RESERVED5,
1929                 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1930                 TRANS_RX_SMP_FRM_LEN_ERR,
1931                 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1932                 RESERVED6,
1933                 RESERVED7,
1934                 RESERVED8,
1935                 RESERVED9,
1936                 TRANS_RX_R_ERR,
1937         };
1938         int index, i;
1939
1940         for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1941                 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1942                 if (err_msk & (1 << index))
1943                         return trans_rx_err_code_prio[i];
1944         }
1945         return -1;
1946 }
1947
1948 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1949 {
1950         static const u8 dma_tx_err_code_prio[] = {
1951                 DMA_TX_UNEXP_XFER_ERR,
1952                 DMA_TX_UNEXP_RETRANS_ERR,
1953                 DMA_TX_XFER_LEN_OVERFLOW,
1954                 DMA_TX_XFER_OFFSET_ERR,
1955                 DMA_TX_RAM_ECC_ERR,
1956                 DMA_TX_DIF_LEN_ALIGN_ERR,
1957                 DMA_TX_DIF_CRC_ERR,
1958                 DMA_TX_DIF_APP_ERR,
1959                 DMA_TX_DIF_RPP_ERR,
1960                 DMA_TX_DATA_SGL_OVERFLOW,
1961                 DMA_TX_DIF_SGL_OVERFLOW,
1962         };
1963         int index, i;
1964
1965         for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1966                 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1967                 err_msk = err_msk & DMA_TX_ERR_MSK;
1968                 if (err_msk & (1 << index))
1969                         return dma_tx_err_code_prio[i];
1970         }
1971         return -1;
1972 }
1973
1974 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1975 {
1976         static const u8 sipc_rx_err_code_prio[] = {
1977                 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1978                 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1979                 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1980                 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1981                 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1982                 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1983                 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1984                 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1985                 SIPC_RX_SATA_UNEXP_FIS_ERR,
1986                 SIPC_RX_WRSETUP_ESTATUS_ERR,
1987                 SIPC_RX_DATA_UNDERFLOW_ERR,
1988         };
1989         int index, i;
1990
1991         for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1992                 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1993                 err_msk = err_msk & SIPC_RX_ERR_MSK;
1994                 if (err_msk & (1 << (index + 0x10)))
1995                         return sipc_rx_err_code_prio[i];
1996         }
1997         return -1;
1998 }
1999
2000 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2001 {
2002         static const u8 dma_rx_err_code_prio[] = {
2003                 DMA_RX_UNKNOWN_FRM_ERR,
2004                 DMA_RX_DATA_LEN_OVERFLOW,
2005                 DMA_RX_DATA_LEN_UNDERFLOW,
2006                 DMA_RX_DATA_OFFSET_ERR,
2007                 RESERVED10,
2008                 DMA_RX_SATA_FRAME_TYPE_ERR,
2009                 DMA_RX_RESP_BUF_OVERFLOW,
2010                 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2011                 DMA_RX_UNEXP_NORM_RESP_ERR,
2012                 DMA_RX_UNEXP_RDFRAME_ERR,
2013                 DMA_RX_PIO_DATA_LEN_ERR,
2014                 DMA_RX_RDSETUP_STATUS_ERR,
2015                 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2016                 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2017                 DMA_RX_RDSETUP_LEN_ODD_ERR,
2018                 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2019                 DMA_RX_RDSETUP_LEN_OVER_ERR,
2020                 DMA_RX_RDSETUP_OFFSET_ERR,
2021                 DMA_RX_RDSETUP_ACTIVE_ERR,
2022                 DMA_RX_RDSETUP_ESTATUS_ERR,
2023                 DMA_RX_RAM_ECC_ERR,
2024                 DMA_RX_DIF_CRC_ERR,
2025                 DMA_RX_DIF_APP_ERR,
2026                 DMA_RX_DIF_RPP_ERR,
2027                 DMA_RX_DATA_SGL_OVERFLOW,
2028                 DMA_RX_DIF_SGL_OVERFLOW,
2029         };
2030         int index, i;
2031
2032         for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2033                 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2034                 if (err_msk & (1 << index))
2035                         return dma_rx_err_code_prio[i];
2036         }
2037         return -1;
2038 }
2039
2040 /* by default, task resp is complete */
2041 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2042                            struct sas_task *task,
2043                            struct hisi_sas_slot *slot,
2044                            int err_phase)
2045 {
2046         struct task_status_struct *ts = &task->task_status;
2047         struct hisi_sas_err_record_v2 *err_record =
2048                         hisi_sas_status_buf_addr_mem(slot);
2049         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2050         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2051         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2052         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2053         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2054         int error = -1;
2055
2056         if (err_phase == 1) {
2057                 /* error in TX phase, the priority of error is: DW2 > DW0 */
2058                 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2059                 if (error == -1)
2060                         error = parse_trans_tx_err_code_v2_hw(
2061                                         trans_tx_fail_type);
2062         } else if (err_phase == 2) {
2063                 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2064                 error = parse_trans_rx_err_code_v2_hw(
2065                                         trans_rx_fail_type);
2066                 if (error == -1) {
2067                         error = parse_dma_rx_err_code_v2_hw(
2068                                         dma_rx_err_type);
2069                         if (error == -1)
2070                                 error = parse_sipc_rx_err_code_v2_hw(
2071                                                 sipc_rx_err_type);
2072                 }
2073         }
2074
2075         switch (task->task_proto) {
2076         case SAS_PROTOCOL_SSP:
2077         {
2078                 switch (error) {
2079                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2080                 {
2081                         ts->stat = SAS_OPEN_REJECT;
2082                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2083                         break;
2084                 }
2085                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2086                 {
2087                         ts->stat = SAS_OPEN_REJECT;
2088                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2089                         break;
2090                 }
2091                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2092                 {
2093                         ts->stat = SAS_OPEN_REJECT;
2094                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2095                         break;
2096                 }
2097                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2098                 {
2099                         ts->stat = SAS_OPEN_REJECT;
2100                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2101                         break;
2102                 }
2103                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2104                 {
2105                         ts->stat = SAS_OPEN_REJECT;
2106                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2107                         break;
2108                 }
2109                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2110                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2111                 case DMA_RX_RESP_BUF_OVERFLOW:
2112                 {
2113                         ts->stat = SAS_OPEN_REJECT;
2114                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2115                         break;
2116                 }
2117                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2118                 {
2119                         /* not sure */
2120                         ts->stat = SAS_DEV_NO_RESPONSE;
2121                         break;
2122                 }
2123                 case DMA_RX_DATA_LEN_OVERFLOW:
2124                 {
2125                         ts->stat = SAS_DATA_OVERRUN;
2126                         ts->residual = 0;
2127                         break;
2128                 }
2129                 case DMA_RX_DATA_LEN_UNDERFLOW:
2130                 {
2131                         ts->residual = trans_tx_fail_type;
2132                         ts->stat = SAS_DATA_UNDERRUN;
2133                         break;
2134                 }
2135                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2136                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2137                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2138                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2139                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2140                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2141                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2142                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2143                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2144                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2145                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2146                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2147                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2148                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2149                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2150                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2151                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2152                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2153                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2154                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2155                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2156                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2157                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2158                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2159                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2160                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2161                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2162                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2163                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2164                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2165                 case TRANS_TX_ERR_FRAME_TXED:
2166                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2167                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2168                 case TRANS_RX_ERR_WITH_BAD_HASH:
2169                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2170                 case TRANS_RX_SSP_FRM_LEN_ERR:
2171                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2172                 case DMA_TX_DATA_SGL_OVERFLOW:
2173                 case DMA_TX_UNEXP_XFER_ERR:
2174                 case DMA_TX_UNEXP_RETRANS_ERR:
2175                 case DMA_TX_XFER_LEN_OVERFLOW:
2176                 case DMA_TX_XFER_OFFSET_ERR:
2177                 case SIPC_RX_DATA_UNDERFLOW_ERR:
2178                 case DMA_RX_DATA_SGL_OVERFLOW:
2179                 case DMA_RX_DATA_OFFSET_ERR:
2180                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2181                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2182                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2183                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2184                 case DMA_RX_UNKNOWN_FRM_ERR:
2185                 {
2186                         /* This will request a retry */
2187                         ts->stat = SAS_QUEUE_FULL;
2188                         slot->abort = 1;
2189                         break;
2190                 }
2191                 default:
2192                         break;
2193                 }
2194         }
2195                 break;
2196         case SAS_PROTOCOL_SMP:
2197                 ts->stat = SAM_STAT_CHECK_CONDITION;
2198                 break;
2199
2200         case SAS_PROTOCOL_SATA:
2201         case SAS_PROTOCOL_STP:
2202         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2203         {
2204                 switch (error) {
2205                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2206                 {
2207                         ts->stat = SAS_OPEN_REJECT;
2208                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2209                         break;
2210                 }
2211                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2212                 {
2213                         ts->resp = SAS_TASK_UNDELIVERED;
2214                         ts->stat = SAS_DEV_NO_RESPONSE;
2215                         break;
2216                 }
2217                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2218                 {
2219                         ts->stat = SAS_OPEN_REJECT;
2220                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2221                         break;
2222                 }
2223                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2224                 {
2225                         ts->stat = SAS_OPEN_REJECT;
2226                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2227                         break;
2228                 }
2229                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2230                 {
2231                         ts->stat = SAS_OPEN_REJECT;
2232                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2233                         break;
2234                 }
2235                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2236                 {
2237                         ts->stat = SAS_OPEN_REJECT;
2238                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2239                         break;
2240                 }
2241                 case DMA_RX_RESP_BUF_OVERFLOW:
2242                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2243                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2244                 {
2245                         ts->stat = SAS_OPEN_REJECT;
2246                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2247                         break;
2248                 }
2249                 case DMA_RX_DATA_LEN_OVERFLOW:
2250                 {
2251                         ts->stat = SAS_DATA_OVERRUN;
2252                         ts->residual = 0;
2253                         break;
2254                 }
2255                 case DMA_RX_DATA_LEN_UNDERFLOW:
2256                 {
2257                         ts->residual = trans_tx_fail_type;
2258                         ts->stat = SAS_DATA_UNDERRUN;
2259                         break;
2260                 }
2261                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2262                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2263                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2264                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2265                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2266                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2267                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2268                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2269                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2270                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2271                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2272                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2273                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2274                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2275                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2276                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2277                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2278                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2279                 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2280                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2281                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2282                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2283                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2284                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2285                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2286                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2287                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2288                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2289                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2290                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2291                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2292                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2293                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2294                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2295                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2296                 case TRANS_RX_ERR_WITH_BAD_HASH:
2297                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2298                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2299                 case DMA_TX_DATA_SGL_OVERFLOW:
2300                 case DMA_TX_UNEXP_XFER_ERR:
2301                 case DMA_TX_UNEXP_RETRANS_ERR:
2302                 case DMA_TX_XFER_LEN_OVERFLOW:
2303                 case DMA_TX_XFER_OFFSET_ERR:
2304                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2305                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2306                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2307                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2308                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2309                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2310                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2311                 case DMA_RX_DATA_SGL_OVERFLOW:
2312                 case DMA_RX_DATA_OFFSET_ERR:
2313                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2314                 case DMA_RX_UNEXP_RDFRAME_ERR:
2315                 case DMA_RX_PIO_DATA_LEN_ERR:
2316                 case DMA_RX_RDSETUP_STATUS_ERR:
2317                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2318                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2319                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2320                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2321                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2322                 case DMA_RX_RDSETUP_OFFSET_ERR:
2323                 case DMA_RX_RDSETUP_ACTIVE_ERR:
2324                 case DMA_RX_RDSETUP_ESTATUS_ERR:
2325                 case DMA_RX_UNKNOWN_FRM_ERR:
2326                 case TRANS_RX_SSP_FRM_LEN_ERR:
2327                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2328                 {
2329                         slot->abort = 1;
2330                         ts->stat = SAS_PHY_DOWN;
2331                         break;
2332                 }
2333                 default:
2334                 {
2335                         ts->stat = SAS_PROTO_RESPONSE;
2336                         break;
2337                 }
2338                 }
2339                 hisi_sas_sata_done(task, slot);
2340         }
2341                 break;
2342         default:
2343                 break;
2344         }
2345 }
2346
2347 static int
2348 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2349 {
2350         struct sas_task *task = slot->task;
2351         struct hisi_sas_device *sas_dev;
2352         struct device *dev = hisi_hba->dev;
2353         struct task_status_struct *ts;
2354         struct domain_device *device;
2355         enum exec_status sts;
2356         struct hisi_sas_complete_v2_hdr *complete_queue =
2357                         hisi_hba->complete_hdr[slot->cmplt_queue];
2358         struct hisi_sas_complete_v2_hdr *complete_hdr =
2359                         &complete_queue[slot->cmplt_queue_slot];
2360         unsigned long flags;
2361         int aborted;
2362
2363         if (unlikely(!task || !task->lldd_task || !task->dev))
2364                 return -EINVAL;
2365
2366         ts = &task->task_status;
2367         device = task->dev;
2368         sas_dev = device->lldd_dev;
2369
2370         spin_lock_irqsave(&task->task_state_lock, flags);
2371         aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2372         task->task_state_flags &=
2373                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2374         spin_unlock_irqrestore(&task->task_state_lock, flags);
2375
2376         memset(ts, 0, sizeof(*ts));
2377         ts->resp = SAS_TASK_COMPLETE;
2378
2379         if (unlikely(aborted)) {
2380                 ts->stat = SAS_ABORTED_TASK;
2381                 spin_lock_irqsave(&hisi_hba->lock, flags);
2382                 hisi_sas_slot_task_free(hisi_hba, task, slot);
2383                 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2384                 return -1;
2385         }
2386
2387         if (unlikely(!sas_dev)) {
2388                 dev_dbg(dev, "slot complete: port has no device\n");
2389                 ts->stat = SAS_PHY_DOWN;
2390                 goto out;
2391         }
2392
2393         /* Use SAS+TMF status codes */
2394         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2395                         >> CMPLT_HDR_ABORT_STAT_OFF) {
2396         case STAT_IO_ABORTED:
2397                 /* this io has been aborted by abort command */
2398                 ts->stat = SAS_ABORTED_TASK;
2399                 goto out;
2400         case STAT_IO_COMPLETE:
2401                 /* internal abort command complete */
2402                 ts->stat = TMF_RESP_FUNC_SUCC;
2403                 del_timer(&slot->internal_abort_timer);
2404                 goto out;
2405         case STAT_IO_NO_DEVICE:
2406                 ts->stat = TMF_RESP_FUNC_COMPLETE;
2407                 del_timer(&slot->internal_abort_timer);
2408                 goto out;
2409         case STAT_IO_NOT_VALID:
2410                 /* abort single io, controller don't find
2411                  * the io need to abort
2412                  */
2413                 ts->stat = TMF_RESP_FUNC_FAILED;
2414                 del_timer(&slot->internal_abort_timer);
2415                 goto out;
2416         default:
2417                 break;
2418         }
2419
2420         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2421                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2422                 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2423                                 >> CMPLT_HDR_ERR_PHASE_OFF;
2424
2425                 /* Analyse error happens on which phase TX or RX */
2426                 if (ERR_ON_TX_PHASE(err_phase))
2427                         slot_err_v2_hw(hisi_hba, task, slot, 1);
2428                 else if (ERR_ON_RX_PHASE(err_phase))
2429                         slot_err_v2_hw(hisi_hba, task, slot, 2);
2430
2431                 if (unlikely(slot->abort))
2432                         return ts->stat;
2433                 goto out;
2434         }
2435
2436         switch (task->task_proto) {
2437         case SAS_PROTOCOL_SSP:
2438         {
2439                 struct hisi_sas_status_buffer *status_buffer =
2440                                 hisi_sas_status_buf_addr_mem(slot);
2441                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2442                                 &status_buffer->iu[0];
2443
2444                 sas_ssp_task_response(dev, task, iu);
2445                 break;
2446         }
2447         case SAS_PROTOCOL_SMP:
2448         {
2449                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2450                 void *to;
2451
2452                 ts->stat = SAM_STAT_GOOD;
2453                 to = kmap_atomic(sg_page(sg_resp));
2454
2455                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2456                              DMA_FROM_DEVICE);
2457                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2458                              DMA_TO_DEVICE);
2459                 memcpy(to + sg_resp->offset,
2460                        hisi_sas_status_buf_addr_mem(slot) +
2461                        sizeof(struct hisi_sas_err_record),
2462                        sg_dma_len(sg_resp));
2463                 kunmap_atomic(to);
2464                 break;
2465         }
2466         case SAS_PROTOCOL_SATA:
2467         case SAS_PROTOCOL_STP:
2468         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2469         {
2470                 ts->stat = SAM_STAT_GOOD;
2471                 hisi_sas_sata_done(task, slot);
2472                 break;
2473         }
2474         default:
2475                 ts->stat = SAM_STAT_CHECK_CONDITION;
2476                 break;
2477         }
2478
2479         if (!slot->port->port_attached) {
2480                 dev_err(dev, "slot complete: port %d has removed\n",
2481                         slot->port->sas_port.id);
2482                 ts->stat = SAS_PHY_DOWN;
2483         }
2484
2485 out:
2486         spin_lock_irqsave(&task->task_state_lock, flags);
2487         task->task_state_flags |= SAS_TASK_STATE_DONE;
2488         spin_unlock_irqrestore(&task->task_state_lock, flags);
2489         spin_lock_irqsave(&hisi_hba->lock, flags);
2490         hisi_sas_slot_task_free(hisi_hba, task, slot);
2491         spin_unlock_irqrestore(&hisi_hba->lock, flags);
2492         sts = ts->stat;
2493
2494         if (task->task_done)
2495                 task->task_done(task);
2496
2497         return sts;
2498 }
2499
2500 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2501                           struct hisi_sas_slot *slot)
2502 {
2503         struct sas_task *task = slot->task;
2504         struct domain_device *device = task->dev;
2505         struct domain_device *parent_dev = device->parent;
2506         struct hisi_sas_device *sas_dev = device->lldd_dev;
2507         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2508         struct asd_sas_port *sas_port = device->port;
2509         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2510         u8 *buf_cmd;
2511         int has_data = 0, rc = 0, hdr_tag = 0;
2512         u32 dw1 = 0, dw2 = 0;
2513
2514         /* create header */
2515         /* dw0 */
2516         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2517         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2518                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2519         else
2520                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2521
2522         /* dw1 */
2523         switch (task->data_dir) {
2524         case DMA_TO_DEVICE:
2525                 has_data = 1;
2526                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2527                 break;
2528         case DMA_FROM_DEVICE:
2529                 has_data = 1;
2530                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2531                 break;
2532         default:
2533                 dw1 &= ~CMD_HDR_DIR_MSK;
2534         }
2535
2536         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2537                         (task->ata_task.fis.control & ATA_SRST))
2538                 dw1 |= 1 << CMD_HDR_RESET_OFF;
2539
2540         dw1 |= (hisi_sas_get_ata_protocol(
2541                 task->ata_task.fis.command, task->data_dir))
2542                 << CMD_HDR_FRAME_TYPE_OFF;
2543         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2544         hdr->dw1 = cpu_to_le32(dw1);
2545
2546         /* dw2 */
2547         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2548                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2549                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2550         }
2551
2552         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2553                         2 << CMD_HDR_SG_MOD_OFF;
2554         hdr->dw2 = cpu_to_le32(dw2);
2555
2556         /* dw3 */
2557         hdr->transfer_tags = cpu_to_le32(slot->idx);
2558
2559         if (has_data) {
2560                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2561                                         slot->n_elem);
2562                 if (rc)
2563                         return rc;
2564         }
2565
2566         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2567         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2568         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2569
2570         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2571
2572         if (likely(!task->ata_task.device_control_reg_update))
2573                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2574         /* fill in command FIS */
2575         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2576
2577         return 0;
2578 }
2579
2580 static void hisi_sas_internal_abort_quirk_timeout(unsigned long data)
2581 {
2582         struct hisi_sas_slot *slot = (struct hisi_sas_slot *)data;
2583         struct hisi_sas_port *port = slot->port;
2584         struct asd_sas_port *asd_sas_port;
2585         struct asd_sas_phy *sas_phy;
2586
2587         if (!port)
2588                 return;
2589
2590         asd_sas_port = &port->sas_port;
2591
2592         /* Kick the hardware - send break command */
2593         list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2594                 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2595                 struct hisi_hba *hisi_hba = phy->hisi_hba;
2596                 int phy_no = sas_phy->id;
2597                 u32 link_dfx2;
2598
2599                 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2600                 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2601                     (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2602                         u32 txid_auto;
2603
2604                         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2605                                                         TXID_AUTO);
2606                         txid_auto |= TXID_AUTO_CTB_MSK;
2607                         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2608                                              txid_auto);
2609                         return;
2610                 }
2611         }
2612 }
2613
2614 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2615                 struct hisi_sas_slot *slot,
2616                 int device_id, int abort_flag, int tag_to_abort)
2617 {
2618         struct sas_task *task = slot->task;
2619         struct domain_device *dev = task->dev;
2620         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2621         struct hisi_sas_port *port = slot->port;
2622         struct timer_list *timer = &slot->internal_abort_timer;
2623
2624         /* setup the quirk timer */
2625         setup_timer(timer, hisi_sas_internal_abort_quirk_timeout,
2626                     (unsigned long)slot);
2627         /* Set the timeout to 10ms less than internal abort timeout */
2628         mod_timer(timer, jiffies + msecs_to_jiffies(100));
2629
2630         /* dw0 */
2631         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2632                                (port->id << CMD_HDR_PORT_OFF) |
2633                                ((dev_is_sata(dev) ? 1:0) <<
2634                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2635                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2636
2637         /* dw1 */
2638         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2639
2640         /* dw7 */
2641         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2642         hdr->transfer_tags = cpu_to_le32(slot->idx);
2643
2644         return 0;
2645 }
2646
2647 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2648 {
2649         int i, res = IRQ_HANDLED;
2650         u32 port_id, link_rate, hard_phy_linkrate;
2651         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2652         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2653         struct device *dev = hisi_hba->dev;
2654         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2655         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2656
2657         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2658
2659         if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2660                 goto end;
2661
2662         if (phy_no == 8) {
2663                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2664
2665                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2666                           PORT_STATE_PHY8_PORT_NUM_OFF;
2667                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2668                             PORT_STATE_PHY8_CONN_RATE_OFF;
2669         } else {
2670                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2671                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2672                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2673                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2674         }
2675
2676         if (port_id == 0xf) {
2677                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2678                 res = IRQ_NONE;
2679                 goto end;
2680         }
2681
2682         for (i = 0; i < 6; i++) {
2683                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2684                                                RX_IDAF_DWORD0 + (i * 4));
2685                 frame_rcvd[i] = __swab32(idaf);
2686         }
2687
2688         sas_phy->linkrate = link_rate;
2689         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2690                                                 HARD_PHY_LINKRATE);
2691         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2692         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2693
2694         sas_phy->oob_mode = SAS_OOB_MODE;
2695         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2696         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2697         phy->port_id = port_id;
2698         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2699         phy->phy_type |= PORT_TYPE_SAS;
2700         phy->phy_attached = 1;
2701         phy->identify.device_type = id->dev_type;
2702         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
2703         if (phy->identify.device_type == SAS_END_DEVICE)
2704                 phy->identify.target_port_protocols =
2705                         SAS_PROTOCOL_SSP;
2706         else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2707                 phy->identify.target_port_protocols =
2708                         SAS_PROTOCOL_SMP;
2709                 if (!timer_pending(&hisi_hba->timer))
2710                         set_link_timer_quirk(hisi_hba);
2711         }
2712         queue_work(hisi_hba->wq, &phy->phyup_ws);
2713
2714 end:
2715         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2716                              CHL_INT0_SL_PHY_ENABLE_MSK);
2717         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2718
2719         return res;
2720 }
2721
2722 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2723 {
2724         u32 port_state;
2725
2726         port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2727         if (port_state & 0x1ff)
2728                 return true;
2729
2730         return false;
2731 }
2732
2733 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2734 {
2735         u32 phy_state, sl_ctrl, txid_auto;
2736         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2737         struct hisi_sas_port *port = phy->port;
2738
2739         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2740
2741         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2742         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2743
2744         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2745         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2746                              sl_ctrl & ~SL_CONTROL_CTA_MSK);
2747         if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2748                 if (!check_any_wideports_v2_hw(hisi_hba) &&
2749                                 timer_pending(&hisi_hba->timer))
2750                         del_timer(&hisi_hba->timer);
2751
2752         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2753         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2754                              txid_auto | TXID_AUTO_CT3_MSK);
2755
2756         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2757         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2758
2759         return IRQ_HANDLED;
2760 }
2761
2762 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2763 {
2764         struct hisi_hba *hisi_hba = p;
2765         u32 irq_msk;
2766         int phy_no = 0;
2767         irqreturn_t res = IRQ_NONE;
2768
2769         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2770                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2771         while (irq_msk) {
2772                 if (irq_msk  & 1) {
2773                         u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2774                                             CHL_INT0);
2775
2776                         switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2777                                         CHL_INT0_SL_PHY_ENABLE_MSK)) {
2778
2779                         case CHL_INT0_SL_PHY_ENABLE_MSK:
2780                                 /* phy up */
2781                                 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2782                                     IRQ_HANDLED)
2783                                         res = IRQ_HANDLED;
2784                                 break;
2785
2786                         case CHL_INT0_NOT_RDY_MSK:
2787                                 /* phy down */
2788                                 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2789                                     IRQ_HANDLED)
2790                                         res = IRQ_HANDLED;
2791                                 break;
2792
2793                         case (CHL_INT0_NOT_RDY_MSK |
2794                                         CHL_INT0_SL_PHY_ENABLE_MSK):
2795                                 reg_value = hisi_sas_read32(hisi_hba,
2796                                                 PHY_STATE);
2797                                 if (reg_value & BIT(phy_no)) {
2798                                         /* phy up */
2799                                         if (phy_up_v2_hw(phy_no, hisi_hba) ==
2800                                             IRQ_HANDLED)
2801                                                 res = IRQ_HANDLED;
2802                                 } else {
2803                                         /* phy down */
2804                                         if (phy_down_v2_hw(phy_no, hisi_hba) ==
2805                                             IRQ_HANDLED)
2806                                                 res = IRQ_HANDLED;
2807                                 }
2808                                 break;
2809
2810                         default:
2811                                 break;
2812                         }
2813
2814                 }
2815                 irq_msk >>= 1;
2816                 phy_no++;
2817         }
2818
2819         return res;
2820 }
2821
2822 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2823 {
2824         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2825         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2826         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2827         u32 bcast_status;
2828
2829         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2830         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2831         if (bcast_status & RX_BCAST_CHG_MSK)
2832                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2833         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2834                              CHL_INT0_SL_RX_BCST_ACK_MSK);
2835         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2836 }
2837
2838 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2839 {
2840         struct hisi_hba *hisi_hba = p;
2841         struct device *dev = hisi_hba->dev;
2842         u32 ent_msk, ent_tmp, irq_msk;
2843         int phy_no = 0;
2844
2845         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2846         ent_tmp = ent_msk;
2847         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2848         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2849
2850         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2851                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2852
2853         while (irq_msk) {
2854                 if (irq_msk & (1 << phy_no)) {
2855                         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2856                                                              CHL_INT0);
2857                         u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2858                                                              CHL_INT1);
2859                         u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2860                                                              CHL_INT2);
2861
2862                         if (irq_value1) {
2863                                 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2864                                                   CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2865                                         panic("%s: DMAC RX/TX ecc bad error!\
2866                                                (0x%x)",
2867                                               dev_name(dev), irq_value1);
2868
2869                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2870                                                      CHL_INT1, irq_value1);
2871                         }
2872
2873                         if (irq_value2)
2874                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2875                                                      CHL_INT2, irq_value2);
2876
2877
2878                         if (irq_value0) {
2879                                 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2880                                         phy_bcast_v2_hw(phy_no, hisi_hba);
2881
2882                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2883                                                 CHL_INT0, irq_value0
2884                                                 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2885                                                 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2886                                                 & (~CHL_INT0_NOT_RDY_MSK));
2887                         }
2888                 }
2889                 irq_msk &= ~(1 << phy_no);
2890                 phy_no++;
2891         }
2892
2893         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2894
2895         return IRQ_HANDLED;
2896 }
2897
2898 static void
2899 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2900 {
2901         struct device *dev = hisi_hba->dev;
2902         const struct hisi_sas_hw_error *ecc_error;
2903         u32 val;
2904         int i;
2905
2906         for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2907                 ecc_error = &one_bit_ecc_errors[i];
2908                 if (irq_value & ecc_error->irq_msk) {
2909                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2910                         val &= ecc_error->msk;
2911                         val >>= ecc_error->shift;
2912                         dev_warn(dev, ecc_error->msg, val);
2913                 }
2914         }
2915 }
2916
2917 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2918                 u32 irq_value)
2919 {
2920         struct device *dev = hisi_hba->dev;
2921         const struct hisi_sas_hw_error *ecc_error;
2922         u32 val;
2923         int i;
2924
2925         for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2926                 ecc_error = &multi_bit_ecc_errors[i];
2927                 if (irq_value & ecc_error->irq_msk) {
2928                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2929                         val &= ecc_error->msk;
2930                         val >>= ecc_error->shift;
2931                         dev_warn(dev, ecc_error->msg, irq_value, val);
2932                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2933                 }
2934         }
2935
2936         return;
2937 }
2938
2939 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2940 {
2941         struct hisi_hba *hisi_hba = p;
2942         u32 irq_value, irq_msk;
2943
2944         irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2945         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2946
2947         irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2948         if (irq_value) {
2949                 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2950                 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2951         }
2952
2953         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2954         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2955
2956         return IRQ_HANDLED;
2957 }
2958
2959 #define AXI_ERR_NR      8
2960 static const char axi_err_info[AXI_ERR_NR][32] = {
2961         "IOST_AXI_W_ERR",
2962         "IOST_AXI_R_ERR",
2963         "ITCT_AXI_W_ERR",
2964         "ITCT_AXI_R_ERR",
2965         "SATA_AXI_W_ERR",
2966         "SATA_AXI_R_ERR",
2967         "DQE_AXI_R_ERR",
2968         "CQE_AXI_W_ERR"
2969 };
2970
2971 #define FIFO_ERR_NR     5
2972 static const char fifo_err_info[FIFO_ERR_NR][32] = {
2973         "CQE_WINFO_FIFO",
2974         "CQE_MSG_FIFIO",
2975         "GETDQE_FIFO",
2976         "CMDP_FIFO",
2977         "AWTCTRL_FIFO"
2978 };
2979
2980 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
2981 {
2982         struct hisi_hba *hisi_hba = p;
2983         u32 irq_value, irq_msk, err_value;
2984         struct device *dev = hisi_hba->dev;
2985
2986         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2987         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
2988
2989         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2990         if (irq_value) {
2991                 if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) {
2992                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2993                                         1 << ENT_INT_SRC3_WP_DEPTH_OFF);
2994                         dev_warn(dev, "write pointer and depth error (0x%x) \
2995                                found!\n",
2996                                irq_value);
2997                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2998                 }
2999
3000                 if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) {
3001                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3002                                          1 <<
3003                                          ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF);
3004                         dev_warn(dev, "iptt no match slot error (0x%x) found!\n",
3005                               irq_value);
3006                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3007                 }
3008
3009                 if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF)) {
3010                         dev_warn(dev, "read pointer and depth error (0x%x) \
3011                                found!\n",
3012                                irq_value);
3013                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3014                 }
3015
3016                 if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) {
3017                         int i;
3018
3019                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3020                                         1 << ENT_INT_SRC3_AXI_OFF);
3021                         err_value = hisi_sas_read32(hisi_hba,
3022                                                     HGC_AXI_FIFO_ERR_INFO);
3023
3024                         for (i = 0; i < AXI_ERR_NR; i++) {
3025                                 if (err_value & BIT(i)) {
3026                                         dev_warn(dev, "%s (0x%x) found!\n",
3027                                               axi_err_info[i], irq_value);
3028                                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3029                                 }
3030                         }
3031                 }
3032
3033                 if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) {
3034                         int i;
3035
3036                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3037                                         1 << ENT_INT_SRC3_FIFO_OFF);
3038                         err_value = hisi_sas_read32(hisi_hba,
3039                                                     HGC_AXI_FIFO_ERR_INFO);
3040
3041                         for (i = 0; i < FIFO_ERR_NR; i++) {
3042                                 if (err_value & BIT(AXI_ERR_NR + i)) {
3043                                         dev_warn(dev, "%s (0x%x) found!\n",
3044                                               fifo_err_info[i], irq_value);
3045                                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3046                                 }
3047                         }
3048
3049                 }
3050
3051                 if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) {
3052                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3053                                         1 << ENT_INT_SRC3_LM_OFF);
3054                         dev_warn(dev, "LM add/fetch list error (0x%x) found!\n",
3055                               irq_value);
3056                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3057                 }
3058
3059                 if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) {
3060                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3061                                         1 << ENT_INT_SRC3_ABT_OFF);
3062                         dev_warn(dev, "SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
3063                               irq_value);
3064                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3065                 }
3066
3067                 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3068                         u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3069                         u32 dev_id = reg_val & ITCT_DEV_MSK;
3070                         struct hisi_sas_device *sas_dev =
3071                                         &hisi_hba->devices[dev_id];
3072
3073                         hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3074                         dev_dbg(dev, "clear ITCT ok\n");
3075                         complete(sas_dev->completion);
3076                 }
3077         }
3078
3079         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3080         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3081
3082         return IRQ_HANDLED;
3083 }
3084
3085 static void cq_tasklet_v2_hw(unsigned long val)
3086 {
3087         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3088         struct hisi_hba *hisi_hba = cq->hisi_hba;
3089         struct hisi_sas_slot *slot;
3090         struct hisi_sas_itct *itct;
3091         struct hisi_sas_complete_v2_hdr *complete_queue;
3092         u32 rd_point = cq->rd_point, wr_point, dev_id;
3093         int queue = cq->id;
3094         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3095
3096         if (unlikely(hisi_hba->reject_stp_links_msk))
3097                 phys_try_accept_stp_links_v2_hw(hisi_hba);
3098
3099         complete_queue = hisi_hba->complete_hdr[queue];
3100
3101         spin_lock(&dq->lock);
3102         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3103                                    (0x14 * queue));
3104
3105         while (rd_point != wr_point) {
3106                 struct hisi_sas_complete_v2_hdr *complete_hdr;
3107                 int iptt;
3108
3109                 complete_hdr = &complete_queue[rd_point];
3110
3111                 /* Check for NCQ completion */
3112                 if (complete_hdr->act) {
3113                         u32 act_tmp = complete_hdr->act;
3114                         int ncq_tag_count = ffs(act_tmp);
3115
3116                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3117                                  CMPLT_HDR_DEV_ID_OFF;
3118                         itct = &hisi_hba->itct[dev_id];
3119
3120                         /* The NCQ tags are held in the itct header */
3121                         while (ncq_tag_count) {
3122                                 __le64 *ncq_tag = &itct->qw4_15[0];
3123
3124                                 ncq_tag_count -= 1;
3125                                 iptt = (ncq_tag[ncq_tag_count / 5]
3126                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
3127
3128                                 slot = &hisi_hba->slot_info[iptt];
3129                                 slot->cmplt_queue_slot = rd_point;
3130                                 slot->cmplt_queue = queue;
3131                                 slot_complete_v2_hw(hisi_hba, slot);
3132
3133                                 act_tmp &= ~(1 << ncq_tag_count);
3134                                 ncq_tag_count = ffs(act_tmp);
3135                         }
3136                 } else {
3137                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3138                         slot = &hisi_hba->slot_info[iptt];
3139                         slot->cmplt_queue_slot = rd_point;
3140                         slot->cmplt_queue = queue;
3141                         slot_complete_v2_hw(hisi_hba, slot);
3142                 }
3143
3144                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3145                         rd_point = 0;
3146         }
3147
3148         /* update rd_point */
3149         cq->rd_point = rd_point;
3150         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3151         spin_unlock(&dq->lock);
3152 }
3153
3154 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3155 {
3156         struct hisi_sas_cq *cq = p;
3157         struct hisi_hba *hisi_hba = cq->hisi_hba;
3158         int queue = cq->id;
3159
3160         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3161
3162         tasklet_schedule(&cq->tasklet);
3163
3164         return IRQ_HANDLED;
3165 }
3166
3167 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3168 {
3169         struct hisi_sas_phy *phy = p;
3170         struct hisi_hba *hisi_hba = phy->hisi_hba;
3171         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3172         struct device *dev = hisi_hba->dev;
3173         struct  hisi_sas_initial_fis *initial_fis;
3174         struct dev_to_host_fis *fis;
3175         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3176         irqreturn_t res = IRQ_HANDLED;
3177         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3178         int phy_no, offset;
3179
3180         phy_no = sas_phy->id;
3181         initial_fis = &hisi_hba->initial_fis[phy_no];
3182         fis = &initial_fis->fis;
3183
3184         offset = 4 * (phy_no / 4);
3185         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3186         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3187                          ent_msk | 1 << ((phy_no % 4) * 8));
3188
3189         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3190         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3191                              (phy_no % 4)));
3192         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3193         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3194                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3195                 res = IRQ_NONE;
3196                 goto end;
3197         }
3198
3199         /* check ERR bit of Status Register */
3200         if (fis->status & ATA_ERR) {
3201                 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3202                                 fis->status);
3203                 disable_phy_v2_hw(hisi_hba, phy_no);
3204                 enable_phy_v2_hw(hisi_hba, phy_no);
3205                 res = IRQ_NONE;
3206                 goto end;
3207         }
3208
3209         if (unlikely(phy_no == 8)) {
3210                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3211
3212                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3213                           PORT_STATE_PHY8_PORT_NUM_OFF;
3214                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3215                             PORT_STATE_PHY8_CONN_RATE_OFF;
3216         } else {
3217                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3218                 port_id = (port_id >> (4 * phy_no)) & 0xf;
3219                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3220                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3221         }
3222
3223         if (port_id == 0xf) {
3224                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3225                 res = IRQ_NONE;
3226                 goto end;
3227         }
3228
3229         sas_phy->linkrate = link_rate;
3230         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3231                                                 HARD_PHY_LINKRATE);
3232         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3233         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3234
3235         sas_phy->oob_mode = SATA_OOB_MODE;
3236         /* Make up some unique SAS address */
3237         attached_sas_addr[0] = 0x50;
3238         attached_sas_addr[7] = phy_no;
3239         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3240         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3241         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3242         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3243         phy->port_id = port_id;
3244         phy->phy_type |= PORT_TYPE_SATA;
3245         phy->phy_attached = 1;
3246         phy->identify.device_type = SAS_SATA_DEV;
3247         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3248         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3249         queue_work(hisi_hba->wq, &phy->phyup_ws);
3250
3251 end:
3252         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3253         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3254
3255         return res;
3256 }
3257
3258 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3259         int_phy_updown_v2_hw,
3260         int_chnl_int_v2_hw,
3261 };
3262
3263 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3264         fatal_ecc_int_v2_hw,
3265         fatal_axi_int_v2_hw
3266 };
3267
3268 /**
3269  * There is a limitation in the hip06 chipset that we need
3270  * to map in all mbigen interrupts, even if they are not used.
3271  */
3272 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3273 {
3274         struct platform_device *pdev = hisi_hba->platform_dev;
3275         struct device *dev = &pdev->dev;
3276         int irq, rc, irq_map[128];
3277         int i, phy_no, fatal_no, queue_no, k;
3278
3279         for (i = 0; i < 128; i++)
3280                 irq_map[i] = platform_get_irq(pdev, i);
3281
3282         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3283                 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3284                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3285                                       DRV_NAME " phy", hisi_hba);
3286                 if (rc) {
3287                         dev_err(dev, "irq init: could not request "
3288                                 "phy interrupt %d, rc=%d\n",
3289                                 irq, rc);
3290                         rc = -ENOENT;
3291                         goto free_phy_int_irqs;
3292                 }
3293         }
3294
3295         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3296                 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3297
3298                 irq = irq_map[phy_no + 72];
3299                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3300                                       DRV_NAME " sata", phy);
3301                 if (rc) {
3302                         dev_err(dev, "irq init: could not request "
3303                                 "sata interrupt %d, rc=%d\n",
3304                                 irq, rc);
3305                         rc = -ENOENT;
3306                         goto free_sata_int_irqs;
3307                 }
3308         }
3309
3310         for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3311                 irq = irq_map[fatal_no + 81];
3312                 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3313                                       DRV_NAME " fatal", hisi_hba);
3314                 if (rc) {
3315                         dev_err(dev,
3316                                 "irq init: could not request fatal interrupt %d, rc=%d\n",
3317                                 irq, rc);
3318                         rc = -ENOENT;
3319                         goto free_fatal_int_irqs;
3320                 }
3321         }
3322
3323         for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3324                 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3325                 struct tasklet_struct *t = &cq->tasklet;
3326
3327                 irq = irq_map[queue_no + 96];
3328                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3329                                       DRV_NAME " cq", cq);
3330                 if (rc) {
3331                         dev_err(dev,
3332                                 "irq init: could not request cq interrupt %d, rc=%d\n",
3333                                 irq, rc);
3334                         rc = -ENOENT;
3335                         goto free_cq_int_irqs;
3336                 }
3337                 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3338         }
3339
3340         return 0;
3341
3342 free_cq_int_irqs:
3343         for (k = 0; k < queue_no; k++) {
3344                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3345
3346                 free_irq(irq_map[k + 96], cq);
3347                 tasklet_kill(&cq->tasklet);
3348         }
3349 free_fatal_int_irqs:
3350         for (k = 0; k < fatal_no; k++)
3351                 free_irq(irq_map[k + 81], hisi_hba);
3352 free_sata_int_irqs:
3353         for (k = 0; k < phy_no; k++) {
3354                 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3355
3356                 free_irq(irq_map[k + 72], phy);
3357         }
3358 free_phy_int_irqs:
3359         for (k = 0; k < i; k++)
3360                 free_irq(irq_map[k + 1], hisi_hba);
3361         return rc;
3362 }
3363
3364 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3365 {
3366         int rc;
3367
3368         memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3369
3370         rc = hw_init_v2_hw(hisi_hba);
3371         if (rc)
3372                 return rc;
3373
3374         rc = interrupt_init_v2_hw(hisi_hba);
3375         if (rc)
3376                 return rc;
3377
3378         return 0;
3379 }
3380
3381 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3382 {
3383         struct platform_device *pdev = hisi_hba->platform_dev;
3384         int i;
3385
3386         for (i = 0; i < hisi_hba->queue_count; i++)
3387                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3388
3389         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3390         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3391         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3392         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3393
3394         for (i = 0; i < hisi_hba->n_phy; i++) {
3395                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3396                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3397         }
3398
3399         for (i = 0; i < 128; i++)
3400                 synchronize_irq(platform_get_irq(pdev, i));
3401 }
3402
3403
3404 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3405 {
3406         return hisi_sas_read32(hisi_hba, PHY_STATE);
3407 }
3408
3409 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3410 {
3411         struct device *dev = hisi_hba->dev;
3412         int rc, cnt;
3413
3414         interrupt_disable_v2_hw(hisi_hba);
3415         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3416
3417         hisi_sas_stop_phys(hisi_hba);
3418
3419         mdelay(10);
3420
3421         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3422
3423         /* wait until bus idle */
3424         cnt = 0;
3425         while (1) {
3426                 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3427                                 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3428
3429                 if (status == 0x3)
3430                         break;
3431
3432                 udelay(10);
3433                 if (cnt++ > 10) {
3434                         dev_info(dev, "wait axi bus state to idle timeout!\n");
3435                         return -1;
3436                 }
3437         }
3438
3439         hisi_sas_init_mem(hisi_hba);
3440
3441         rc = hw_init_v2_hw(hisi_hba);
3442         if (rc)
3443                 return rc;
3444
3445         phys_reject_stp_links_v2_hw(hisi_hba);
3446
3447         return 0;
3448 }
3449
3450 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3451         .hw_init = hisi_sas_v2_init,
3452         .setup_itct = setup_itct_v2_hw,
3453         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3454         .alloc_dev = alloc_dev_quirk_v2_hw,
3455         .sl_notify = sl_notify_v2_hw,
3456         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3457         .free_device = free_device_v2_hw,
3458         .prep_smp = prep_smp_v2_hw,
3459         .prep_ssp = prep_ssp_v2_hw,
3460         .prep_stp = prep_ata_v2_hw,
3461         .prep_abort = prep_abort_v2_hw,
3462         .get_free_slot = get_free_slot_v2_hw,
3463         .start_delivery = start_delivery_v2_hw,
3464         .slot_complete = slot_complete_v2_hw,
3465         .phys_init = phys_init_v2_hw,
3466         .phy_start = start_phy_v2_hw,
3467         .phy_disable = disable_phy_v2_hw,
3468         .phy_hard_reset = phy_hard_reset_v2_hw,
3469         .get_events = phy_get_events_v2_hw,
3470         .phy_set_linkrate = phy_set_linkrate_v2_hw,
3471         .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3472         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3473         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3474         .soft_reset = soft_reset_v2_hw,
3475         .get_phys_state = get_phys_state_v2_hw,
3476 };
3477
3478 static int hisi_sas_v2_probe(struct platform_device *pdev)
3479 {
3480         /*
3481          * Check if we should defer the probe before we probe the
3482          * upper layer, as it's hard to defer later on.
3483          */
3484         int ret = platform_get_irq(pdev, 0);
3485
3486         if (ret < 0) {
3487                 if (ret != -EPROBE_DEFER)
3488                         dev_err(&pdev->dev, "cannot obtain irq\n");
3489                 return ret;
3490         }
3491
3492         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3493 }
3494
3495 static int hisi_sas_v2_remove(struct platform_device *pdev)
3496 {
3497         struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3498         struct hisi_hba *hisi_hba = sha->lldd_ha;
3499         int i;
3500
3501         if (timer_pending(&hisi_hba->timer))
3502                 del_timer(&hisi_hba->timer);
3503
3504         for (i = 0; i < hisi_hba->queue_count; i++) {
3505                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
3506
3507                 tasklet_kill(&cq->tasklet);
3508         }
3509
3510         return hisi_sas_remove(pdev);
3511 }
3512
3513 static const struct of_device_id sas_v2_of_match[] = {
3514         { .compatible = "hisilicon,hip06-sas-v2",},
3515         { .compatible = "hisilicon,hip07-sas-v2",},
3516         {},
3517 };
3518 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3519
3520 static const struct acpi_device_id sas_v2_acpi_match[] = {
3521         { "HISI0162", 0 },
3522         { }
3523 };
3524
3525 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3526
3527 static struct platform_driver hisi_sas_v2_driver = {
3528         .probe = hisi_sas_v2_probe,
3529         .remove = hisi_sas_v2_remove,
3530         .driver = {
3531                 .name = DRV_NAME,
3532                 .of_match_table = sas_v2_of_match,
3533                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3534         },
3535 };
3536
3537 module_platform_driver(hisi_sas_v2_driver);
3538
3539 MODULE_LICENSE("GPL");
3540 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3541 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3542 MODULE_ALIAS("platform:" DRV_NAME);