drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_LM_DFX_STATUS2              0x128
  59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF         0
  60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
  61                                          HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF         12
  63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
  64                                          HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  65 #define HGC_CQE_ECC_ADDR                0x13c
  66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
  67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
  69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  70 #define HGC_IOST_ECC_ADDR               0x140
  71 #define HGC_IOST_ECC_1B_ADDR_OFF        0
  72 #define HGC_IOST_ECC_1B_ADDR_MSK        (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  73 #define HGC_IOST_ECC_MB_ADDR_OFF        16
  74 #define HGC_IOST_ECC_MB_ADDR_MSK        (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  75 #define HGC_DQE_ECC_ADDR                0x144
  76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
  77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
  79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  80 #define HGC_INVLD_DQE_INFO              0x148
  81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  84 #define HGC_ITCT_ECC_ADDR               0x150
  85 #define HGC_ITCT_ECC_1B_ADDR_OFF                0
  86 #define HGC_ITCT_ECC_1B_ADDR_MSK                (0x3ff << \
  87                                                  HGC_ITCT_ECC_1B_ADDR_OFF)
  88 #define HGC_ITCT_ECC_MB_ADDR_OFF                16
  89 #define HGC_ITCT_ECC_MB_ADDR_MSK                (0x3ff << \
  90                                                  HGC_ITCT_ECC_MB_ADDR_OFF)
  91 #define HGC_AXI_FIFO_ERR_INFO   0x154
  92 #define AXI_ERR_INFO_OFF                0
  93 #define AXI_ERR_INFO_MSK                (0xff << AXI_ERR_INFO_OFF)
  94 #define FIFO_ERR_INFO_OFF               8
  95 #define FIFO_ERR_INFO_MSK               (0xff << FIFO_ERR_INFO_OFF)
  96 #define INT_COAL_EN                     0x19c
  97 #define OQ_INT_COAL_TIME                0x1a0
  98 #define OQ_INT_COAL_CNT                 0x1a4
  99 #define ENT_INT_COAL_TIME               0x1a8
 100 #define ENT_INT_COAL_CNT                0x1ac
 101 #define OQ_INT_SRC                      0x1b0
 102 #define OQ_INT_SRC_MSK                  0x1b4
 103 #define ENT_INT_SRC1                    0x1b8
 104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
 105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
 106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
 107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
 108 #define ENT_INT_SRC2                    0x1bc
 109 #define ENT_INT_SRC3                    0x1c0
 110 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
 111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
 112 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
 113 #define ENT_INT_SRC3_AXI_OFF                    11
 114 #define ENT_INT_SRC3_FIFO_OFF                   12
 115 #define ENT_INT_SRC3_LM_OFF                             14
 116 #define ENT_INT_SRC3_ITC_INT_OFF        15
 117 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
 118 #define ENT_INT_SRC3_ABT_OFF            16
 119 #define ENT_INT_SRC_MSK1                0x1c4
 120 #define ENT_INT_SRC_MSK2                0x1c8
 121 #define ENT_INT_SRC_MSK3                0x1cc
 122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
 123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
 124 #define SAS_ECC_INTR                    0x1e8
 125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF             0
 126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF             1
 127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF    2
 128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF    3
 129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF    4
 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF    5
 131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF        6
 132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF        7
 133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF        8
 134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF        9
 135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF             10
 136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF             11
 137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF        12
 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF        13
 139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF        14
 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF        15
 141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF        16
 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF        17
 143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF        18
 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF        19
 145 #define SAS_ECC_INTR_MSK                0x1ec
 146 #define HGC_ERR_STAT_EN                 0x238
 147 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 148 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 149 #define DLVRY_Q_0_DEPTH                 0x268
 150 #define DLVRY_Q_0_WR_PTR                0x26c
 151 #define DLVRY_Q_0_RD_PTR                0x270
 152 #define HYPER_STREAM_ID_EN_CFG          0xc80
 153 #define OQ0_INT_SRC_MSK                 0xc90
 154 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 155 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 156 #define COMPL_Q_0_DEPTH                 0x4e8
 157 #define COMPL_Q_0_WR_PTR                0x4ec
 158 #define COMPL_Q_0_RD_PTR                0x4f0
 159 #define HGC_RXM_DFX_STATUS14    0xae8
 160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF           0
 161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK           (0x1ff << \
 162                                                  HGC_RXM_DFX_STATUS14_MEM0_OFF)
 163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF           9
 164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK           (0x1ff << \
 165                                                  HGC_RXM_DFX_STATUS14_MEM1_OFF)
 166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF           18
 167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK           (0x1ff << \
 168                                                  HGC_RXM_DFX_STATUS14_MEM2_OFF)
 169 #define HGC_RXM_DFX_STATUS15    0xaec
 170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF           0
 171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK           (0x1ff << \
 172                                                  HGC_RXM_DFX_STATUS15_MEM3_OFF)
 173 /* phy registers need init */
 174 #define PORT_BASE                       (0x2000)
 175
 176 #define PHY_CFG                         (PORT_BASE + 0x0)
 177 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 178 #define PHY_CFG_ENA_OFF                 0
 179 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 180 #define PHY_CFG_DC_OPT_OFF              2
 181 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 182 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 183 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 184 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 185 #define PHY_CTRL                        (PORT_BASE + 0x14)
 186 #define PHY_CTRL_RESET_OFF              0
 187 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 188 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 189 #define SL_CFG                          (PORT_BASE + 0x84)
 190 #define PHY_PCN                         (PORT_BASE + 0x44)
 191 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 192 #define SL_CONTROL                      (PORT_BASE + 0x94)
 193 #define SL_CONTROL_NOTIFY_EN_OFF        0
 194 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 195 #define SL_CONTROL_CTA_OFF              17
 196 #define SL_CONTROL_CTA_MSK              (0x1 << SL_CONTROL_CTA_OFF)
 197 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 198 #define RX_BCAST_CHG_OFF                1
 199 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 200 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 201 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 202 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 203 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 204 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 205 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 206 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 207 #define TXID_AUTO                       (PORT_BASE + 0xb8)
 208 #define TXID_AUTO_CT3_OFF               1
 209 #define TXID_AUTO_CT3_MSK               (0x1 << TXID_AUTO_CT3_OFF)
 210 #define TXID_AUTO_CTB_OFF               11
 211 #define TXID_AUTO_CTB_MSK               (0x1 << TXID_AUTO_CTB_OFF)
 212 #define TX_HARDRST_OFF                  2
 213 #define TX_HARDRST_MSK                  (0x1 << TX_HARDRST_OFF)
 214 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 215 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 216 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 217 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 218 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 219 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 220 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 221 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 222 #define CON_CONTROL                     (PORT_BASE + 0x118)
 223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF        0
 224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK        \
 225                 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
 226 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 227 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 228 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 229 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 230 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 231 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 232 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 233 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 234 #define CHL_INT0_NOT_RDY_OFF            4
 235 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 236 #define CHL_INT0_PHY_RDY_OFF            5
 237 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 238 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 243 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 244 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 245 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 246 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 247 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 248 #define DMA_TX_DFX0                             (PORT_BASE + 0x200)
 249 #define DMA_TX_DFX1                             (PORT_BASE + 0x204)
 250 #define DMA_TX_DFX1_IPTT_OFF            0
 251 #define DMA_TX_DFX1_IPTT_MSK            (0xffff << DMA_TX_DFX1_IPTT_OFF)
 252 #define DMA_TX_FIFO_DFX0                (PORT_BASE + 0x240)
 253 #define PORT_DFX0                               (PORT_BASE + 0x258)
 254 #define LINK_DFX2                                       (PORT_BASE + 0X264)
 255 #define LINK_DFX2_RCVR_HOLD_STS_OFF     9
 256 #define LINK_DFX2_RCVR_HOLD_STS_MSK     (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
 257 #define LINK_DFX2_SEND_HOLD_STS_OFF     10
 258 #define LINK_DFX2_SEND_HOLD_STS_MSK     (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
 259 #define SAS_ERR_CNT4_REG                (PORT_BASE + 0x290)
 260 #define SAS_ERR_CNT6_REG                (PORT_BASE + 0x298)
 261 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 262 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 263 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 264 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 265 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 266 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 267 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 268 #define DMA_TX_STATUS_BUSY_OFF          0
 269 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 270 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 271 #define DMA_RX_STATUS_BUSY_OFF          0
 272 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 273
 274 #define AXI_CFG                         (0x5100)
 275 #define AM_CFG_MAX_TRANS                (0x5010)
 276 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 277
 278 #define AXI_MASTER_CFG_BASE             (0x5000)
 279 #define AM_CTRL_GLOBAL                  (0x0)
 280 #define AM_CURR_TRANS_RETURN    (0x150)
 281
 282 /* HW dma structures */
 283 /* Delivery queue header */
 284 /* dw0 */
 285 #define CMD_HDR_ABORT_FLAG_OFF          0
 286 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 289 #define CMD_HDR_RESP_REPORT_OFF         5
 290 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 291 #define CMD_HDR_TLR_CTRL_OFF            6
 292 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 293 #define CMD_HDR_PORT_OFF                18
 294 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 295 #define CMD_HDR_PRIORITY_OFF            27
 296 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 297 #define CMD_HDR_CMD_OFF                 29
 298 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 299 /* dw1 */
 300 #define CMD_HDR_DIR_OFF                 5
 301 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 302 #define CMD_HDR_RESET_OFF               7
 303 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 304 #define CMD_HDR_VDTL_OFF                10
 305 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 306 #define CMD_HDR_FRAME_TYPE_OFF          11
 307 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 308 #define CMD_HDR_DEV_ID_OFF              16
 309 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 310 /* dw2 */
 311 #define CMD_HDR_CFL_OFF                 0
 312 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 313 #define CMD_HDR_NCQ_TAG_OFF             10
 314 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 315 #define CMD_HDR_MRFL_OFF                15
 316 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 317 #define CMD_HDR_SG_MOD_OFF              24
 318 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 319 #define CMD_HDR_FIRST_BURST_OFF         26
 320 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 321 /* dw3 */
 322 #define CMD_HDR_IPTT_OFF                0
 323 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 324 /* dw6 */
 325 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 326 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 327 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 328 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 329 #define CMD_HDR_ABORT_IPTT_OFF          16
 330 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 331
 332 /* Completion header */
 333 /* dw0 */
 334 #define CMPLT_HDR_ERR_PHASE_OFF 2
 335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
 336 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 337 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 338 #define CMPLT_HDR_ERX_OFF               12
 339 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 340 #define CMPLT_HDR_ABORT_STAT_OFF        13
 341 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 342 /* abort_stat */
 343 #define STAT_IO_NOT_VALID               0x1
 344 #define STAT_IO_NO_DEVICE               0x2
 345 #define STAT_IO_COMPLETE                0x3
 346 #define STAT_IO_ABORTED                 0x4
 347 /* dw1 */
 348 #define CMPLT_HDR_IPTT_OFF              0
 349 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 350 #define CMPLT_HDR_DEV_ID_OFF            16
 351 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 352
 353 /* ITCT header */
 354 /* qw0 */
 355 #define ITCT_HDR_DEV_TYPE_OFF           0
 356 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 357 #define ITCT_HDR_VALID_OFF              2
 358 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 359 #define ITCT_HDR_MCR_OFF                5
 360 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 361 #define ITCT_HDR_VLN_OFF                9
 362 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 363 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 364 #define ITCT_HDR_SMP_TIMEOUT_8US        1
 365 #define ITCT_HDR_SMP_TIMEOUT            (ITCT_HDR_SMP_TIMEOUT_8US * \
 366                                          250) /* 2ms */
 367 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 368 #define ITCT_HDR_PORT_ID_OFF            28
 369 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 370 /* qw2 */
 371 #define ITCT_HDR_INLT_OFF               0
 372 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 373 #define ITCT_HDR_BITLT_OFF              16
 374 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 375 #define ITCT_HDR_MCTLT_OFF              32
 376 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 377 #define ITCT_HDR_RTOLT_OFF              48
 378 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 379
 380 #define HISI_SAS_FATAL_INT_NR   2
 381
 382 struct hisi_sas_complete_v2_hdr {
 383         __le32 dw0;
 384         __le32 dw1;
 385         __le32 act;
 386         __le32 dw3;
 387 };
 388
 389 struct hisi_sas_err_record_v2 {
 390         /* dw0 */
 391         __le32 trans_tx_fail_type;
 392
 393         /* dw1 */
 394         __le32 trans_rx_fail_type;
 395
 396         /* dw2 */
 397         __le16 dma_tx_err_type;
 398         __le16 sipc_rx_err_type;
 399
 400         /* dw3 */
 401         __le32 dma_rx_err_type;
 402 };
 403
 404 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
 405         {
 406                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
 407                 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
 408                 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
 409                 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
 410                 .reg = HGC_DQE_ECC_ADDR,
 411         },
 412         {
 413                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
 414                 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
 415                 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
 416                 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
 417                 .reg = HGC_IOST_ECC_ADDR,
 418         },
 419         {
 420                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
 421                 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
 422                 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
 423                 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
 424                 .reg = HGC_ITCT_ECC_ADDR,
 425         },
 426         {
 427                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
 428                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 429                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 430                 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
 431                 .reg = HGC_LM_DFX_STATUS2,
 432         },
 433         {
 434                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
 435                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 436                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 437                 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
 438                 .reg = HGC_LM_DFX_STATUS2,
 439         },
 440         {
 441                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
 442                 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
 443                 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
 444                 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
 445                 .reg = HGC_CQE_ECC_ADDR,
 446         },
 447         {
 448                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
 449                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 450                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 451                 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
 452                 .reg = HGC_RXM_DFX_STATUS14,
 453         },
 454         {
 455                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
 456                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 457                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 458                 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
 459                 .reg = HGC_RXM_DFX_STATUS14,
 460         },
 461         {
 462                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
 463                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 464                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 465                 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
 466                 .reg = HGC_RXM_DFX_STATUS14,
 467         },
 468         {
 469                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
 470                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 471                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 472                 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
 473                 .reg = HGC_RXM_DFX_STATUS15,
 474         },
 475 };
 476
 477 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
 478         {
 479                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
 480                 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
 481                 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
 482                 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 483                 .reg = HGC_DQE_ECC_ADDR,
 484         },
 485         {
 486                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
 487                 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
 488                 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
 489                 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 490                 .reg = HGC_IOST_ECC_ADDR,
 491         },
 492         {
 493                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
 494                 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
 495                 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
 496                 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 497                 .reg = HGC_ITCT_ECC_ADDR,
 498         },
 499         {
 500                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
 501                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 502                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 503                 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 504                 .reg = HGC_LM_DFX_STATUS2,
 505         },
 506         {
 507                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
 508                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 509                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 510                 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 511                 .reg = HGC_LM_DFX_STATUS2,
 512         },
 513         {
 514                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
 515                 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
 516                 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
 517                 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 518                 .reg = HGC_CQE_ECC_ADDR,
 519         },
 520         {
 521                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
 522                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 523                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 524                 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 525                 .reg = HGC_RXM_DFX_STATUS14,
 526         },
 527         {
 528                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
 529                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 530                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 531                 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 532                 .reg = HGC_RXM_DFX_STATUS14,
 533         },
 534         {
 535                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
 536                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 537                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 538                 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 539                 .reg = HGC_RXM_DFX_STATUS14,
 540         },
 541         {
 542                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
 543                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 544                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 545                 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 546                 .reg = HGC_RXM_DFX_STATUS15,
 547         },
 548 };
 549
 550 enum {
 551         HISI_SAS_PHY_PHY_UPDOWN,
 552         HISI_SAS_PHY_CHNL_INT,
 553         HISI_SAS_PHY_INT_NR
 554 };
 555
 556 enum {
 557         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 558         TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
 559         DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
 560         SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
 561         DMA_RX_ERR_BASE = 0x60, /* dw3 */
 562
 563         /* trans tx*/
 564         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 565         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 566         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 567         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 568         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 569         RESERVED0, /* 0x5 */
 570         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 571         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 572         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 573         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 574         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 575         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 576         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 577         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 578         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 579         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 580         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 581         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 582         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 583         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 584         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 585         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 586         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 587         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 588         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 589         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 590         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 591         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 592         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 593         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 594         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 595         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 596         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 597         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 598         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 599
 600         /* trans rx */
 601         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
 602         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
 603         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
 604         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
 605         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
 606         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
 607         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
 608         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
 609         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
 610         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
 611         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
 612         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
 613         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
 614         RESERVED1, /* 0x2b */
 615         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
 616         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
 617         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
 618         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
 619         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
 620         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
 621         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
 622         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
 623         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
 624         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
 625         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
 626         RESERVED2, /* 0x34 */
 627         RESERVED3, /* 0x35 */
 628         RESERVED4, /* 0x36 */
 629         RESERVED5, /* 0x37 */
 630         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
 631         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
 632         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
 633         RESERVED6, /* 0x3b */
 634         RESERVED7, /* 0x3c */
 635         RESERVED8, /* 0x3d */
 636         RESERVED9, /* 0x3e */
 637         TRANS_RX_R_ERR, /* 0x3f */
 638
 639         /* dma tx */
 640         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
 641         DMA_TX_DIF_APP_ERR, /* 0x41 */
 642         DMA_TX_DIF_RPP_ERR, /* 0x42 */
 643         DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
 644         DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
 645         DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
 646         DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
 647         DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
 648         DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
 649         DMA_TX_RAM_ECC_ERR, /* 0x49 */
 650         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
 651         DMA_TX_MAX_ERR_CODE,
 652
 653         /* sipc rx */
 654         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
 655         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
 656         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
 657         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
 658         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
 659         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
 660         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
 661         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
 662         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
 663         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
 664         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
 665         SIPC_RX_MAX_ERR_CODE,
 666
 667         /* dma rx */
 668         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
 669         DMA_RX_DIF_APP_ERR, /* 0x61 */
 670         DMA_RX_DIF_RPP_ERR, /* 0x62 */
 671         DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
 672         DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
 673         DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
 674         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
 675         DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
 676         RESERVED10, /* 0x68 */
 677         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
 678         DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
 679         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
 680         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
 681         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
 682         DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
 683         DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
 684         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
 685         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
 686         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
 687         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
 688         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
 689         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
 690         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
 691         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
 692         DMA_RX_RAM_ECC_ERR, /* 0x78 */
 693         DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
 694         DMA_RX_MAX_ERR_CODE,
 695 };
 696
 697 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 698 #define HISI_MAX_SATA_SUPPORT_V2_HW     (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
 699
 700 #define DIR_NO_DATA 0
 701 #define DIR_TO_INI 1
 702 #define DIR_TO_DEVICE 2
 703 #define DIR_RESERVED 3
 704
 705 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
 706                 err_phase == 0x4 || err_phase == 0x8 ||\
 707                 err_phase == 0x6 || err_phase == 0xa)
 708 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
 709                 err_phase == 0x20 || err_phase == 0x40)
 710
 711 static void link_timeout_disable_link(unsigned long data);
 712
 713 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 714 {
 715         void __iomem *regs = hisi_hba->regs + off;
 716
 717         return readl(regs);
 718 }
 719
 720 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 721 {
 722         void __iomem *regs = hisi_hba->regs + off;
 723
 724         return readl_relaxed(regs);
 725 }
 726
 727 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 728 {
 729         void __iomem *regs = hisi_hba->regs + off;
 730
 731         writel(val, regs);
 732 }
 733
 734 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 735                                  u32 off, u32 val)
 736 {
 737         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 738
 739         writel(val, regs);
 740 }
 741
 742 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 743                                       int phy_no, u32 off)
 744 {
 745         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 746
 747         return readl(regs);
 748 }
 749
 750 /* This function needs to be protected from pre-emption. */
 751 static int
 752 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
 753                              struct domain_device *device)
 754 {
 755         int sata_dev = dev_is_sata(device);
 756         void *bitmap = hisi_hba->slot_index_tags;
 757         struct hisi_sas_device *sas_dev = device->lldd_dev;
 758         int sata_idx = sas_dev->sata_idx;
 759         int start, end;
 760
 761         if (!sata_dev) {
 762                 /*
 763                  * STP link SoC bug workaround: index starts from 1.
 764                  * additionally, we can only allocate odd IPTT(1~4095)
 765                  * for SAS/SMP device.
 766                  */
 767                 start = 1;
 768                 end = hisi_hba->slot_index_count;
 769         } else {
 770                 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
 771                         return -EINVAL;
 772
 773                 /*
 774                  * For SATA device: allocate even IPTT in this interval
 775                  * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
 776                  * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
 777                  * SoC bug workaround. So we ignore the first 32 even IPTTs.
 778                  */
 779                 start = 64 * (sata_idx + 1);
 780                 end = 64 * (sata_idx + 2);
 781         }
 782
 783         while (1) {
 784                 start = find_next_zero_bit(bitmap,
 785                                         hisi_hba->slot_index_count, start);
 786                 if (start >= end)
 787                         return -SAS_QUEUE_FULL;
 788                 /*
 789                   * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
 790                   */
 791                 if (sata_dev ^ (start & 1))
 792                         break;
 793                 start++;
 794         }
 795
 796         set_bit(start, bitmap);
 797         *slot_idx = start;
 798         return 0;
 799 }
 800
 801 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
 802 {
 803         unsigned int index;
 804         struct device *dev = hisi_hba->dev;
 805         void *bitmap = hisi_hba->sata_dev_bitmap;
 806
 807         index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
 808         if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
 809                 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
 810                 return false;
 811         }
 812
 813         set_bit(index, bitmap);
 814         *idx = index;
 815         return true;
 816 }
 817
 818
 819 static struct
 820 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 821 {
 822         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 823         struct hisi_sas_device *sas_dev = NULL;
 824         int i, sata_dev = dev_is_sata(device);
 825         int sata_idx = -1;
 826         unsigned long flags;
 827
 828         spin_lock_irqsave(&hisi_hba->lock, flags);
 829
 830         if (sata_dev)
 831                 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
 832                         goto out;
 833
 834         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 835                 /*
 836                  * SATA device id bit0 should be 0
 837                  */
 838                 if (sata_dev && (i & 1))
 839                         continue;
 840                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 841                         int queue = i % hisi_hba->queue_count;
 842                         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
 843
 844                         hisi_hba->devices[i].device_id = i;
 845                         sas_dev = &hisi_hba->devices[i];
 846                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 847                         sas_dev->dev_type = device->dev_type;
 848                         sas_dev->hisi_hba = hisi_hba;
 849                         sas_dev->sas_device = device;
 850                         sas_dev->sata_idx = sata_idx;
 851                         sas_dev->dq = dq;
 852                         INIT_LIST_HEAD(&hisi_hba->devices[i].list);
 853                         break;
 854                 }
 855         }
 856
 857 out:
 858         spin_unlock_irqrestore(&hisi_hba->lock, flags);
 859
 860         return sas_dev;
 861 }
 862
 863 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 864 {
 865         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 866
 867         cfg &= ~PHY_CFG_DC_OPT_MSK;
 868         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 869         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 870 }
 871
 872 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 873 {
 874         struct sas_identify_frame identify_frame;
 875         u32 *identify_buffer;
 876
 877         memset(&identify_frame, 0, sizeof(identify_frame));
 878         identify_frame.dev_type = SAS_END_DEVICE;
 879         identify_frame.frame_type = 0;
 880         identify_frame._un1 = 1;
 881         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 882         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 883         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 884         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 885         identify_frame.phy_id = phy_no;
 886         identify_buffer = (u32 *)(&identify_frame);
 887
 888         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 889                         __swab32(identify_buffer[0]));
 890         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 891                         __swab32(identify_buffer[1]));
 892         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 893                         __swab32(identify_buffer[2]));
 894         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 895                         __swab32(identify_buffer[3]));
 896         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 897                         __swab32(identify_buffer[4]));
 898         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 899                         __swab32(identify_buffer[5]));
 900 }
 901
 902 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 903                              struct hisi_sas_device *sas_dev)
 904 {
 905         struct domain_device *device = sas_dev->sas_device;
 906         struct device *dev = hisi_hba->dev;
 907         u64 qw0, device_id = sas_dev->device_id;
 908         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 909         struct domain_device *parent_dev = device->parent;
 910         struct asd_sas_port *sas_port = device->port;
 911         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 912
 913         memset(itct, 0, sizeof(*itct));
 914
 915         /* qw0 */
 916         qw0 = 0;
 917         switch (sas_dev->dev_type) {
 918         case SAS_END_DEVICE:
 919         case SAS_EDGE_EXPANDER_DEVICE:
 920         case SAS_FANOUT_EXPANDER_DEVICE:
 921                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 922                 break;
 923         case SAS_SATA_DEV:
 924         case SAS_SATA_PENDING:
 925                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 926                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 927                 else
 928                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 929                 break;
 930         default:
 931                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 932                          sas_dev->dev_type);
 933         }
 934
 935         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 936                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 937                 (1 << ITCT_HDR_VLN_OFF) |
 938                 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
 939                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 940                 (port->id << ITCT_HDR_PORT_ID_OFF));
 941         itct->qw0 = cpu_to_le64(qw0);
 942
 943         /* qw1 */
 944         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 945         itct->sas_addr = __swab64(itct->sas_addr);
 946
 947         /* qw2 */
 948         if (!dev_is_sata(device))
 949                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 950                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 951                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 952                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 953 }
 954
 955 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
 956                               struct hisi_sas_device *sas_dev)
 957 {
 958         DECLARE_COMPLETION_ONSTACK(completion);
 959         u64 dev_id = sas_dev->device_id;
 960         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 961         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 962         int i;
 963
 964         sas_dev->completion = &completion;
 965
 966         /* SoC bug workaround */
 967         if (dev_is_sata(sas_dev->sas_device))
 968                 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
 969
 970         /* clear the itct interrupt state */
 971         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 972                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 973                                  ENT_INT_SRC3_ITC_INT_MSK);
 974
 975         for (i = 0; i < 2; i++) {
 976                 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 977                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 978                 wait_for_completion(sas_dev->completion);
 979
 980                 memset(itct, 0, sizeof(struct hisi_sas_itct));
 981         }
 982 }
 983
 984 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
 985 {
 986         int i, reset_val;
 987         u32 val;
 988         unsigned long end_time;
 989         struct device *dev = hisi_hba->dev;
 990
 991         /* The mask needs to be set depending on the number of phys */
 992         if (hisi_hba->n_phy == 9)
 993                 reset_val = 0x1fffff;
 994         else
 995                 reset_val = 0x7ffff;
 996
 997         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 998
 999         /* Disable all of the PHYs */
1000         for (i = 0; i < hisi_hba->n_phy; i++) {
1001                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1002
1003                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1004                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1005         }
1006         udelay(50);
1007
1008         /* Ensure DMA tx & rx idle */
1009         for (i = 0; i < hisi_hba->n_phy; i++) {
1010                 u32 dma_tx_status, dma_rx_status;
1011
1012                 end_time = jiffies + msecs_to_jiffies(1000);
1013
1014                 while (1) {
1015                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1016                                                             DMA_TX_STATUS);
1017                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1018                                                             DMA_RX_STATUS);
1019
1020                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1021                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1022                                 break;
1023
1024                         msleep(20);
1025                         if (time_after(jiffies, end_time))
1026                                 return -EIO;
1027                 }
1028         }
1029
1030         /* Ensure axi bus idle */
1031         end_time = jiffies + msecs_to_jiffies(1000);
1032         while (1) {
1033                 u32 axi_status =
1034                         hisi_sas_read32(hisi_hba, AXI_CFG);
1035
1036                 if (axi_status == 0)
1037                         break;
1038
1039                 msleep(20);
1040                 if (time_after(jiffies, end_time))
1041                         return -EIO;
1042         }
1043
1044         if (ACPI_HANDLE(dev)) {
1045                 acpi_status s;
1046
1047                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1048                 if (ACPI_FAILURE(s)) {
1049                         dev_err(dev, "Reset failed\n");
1050                         return -EIO;
1051                 }
1052         } else if (hisi_hba->ctrl) {
1053                 /* reset and disable clock*/
1054                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1055                                 reset_val);
1056                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1057                                 reset_val);
1058                 msleep(1);
1059                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1060                 if (reset_val != (val & reset_val)) {
1061                         dev_err(dev, "SAS reset fail.\n");
1062                         return -EIO;
1063                 }
1064
1065                 /* De-reset and enable clock*/
1066                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1067                                 reset_val);
1068                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1069                                 reset_val);
1070                 msleep(1);
1071                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1072                                 &val);
1073                 if (val & reset_val) {
1074                         dev_err(dev, "SAS de-reset fail.\n");
1075                         return -EIO;
1076                 }
1077         } else
1078                 dev_warn(dev, "no reset method\n");
1079
1080         return 0;
1081 }
1082
1083 /* This function needs to be called after resetting SAS controller. */
1084 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1085 {
1086         u32 cfg;
1087         int phy_no;
1088
1089         hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1090         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1091                 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1092                 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1093                         continue;
1094
1095                 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1096                 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1097         }
1098 }
1099
1100 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1101 {
1102         int phy_no;
1103         u32 dma_tx_dfx1;
1104
1105         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1106                 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1107                         continue;
1108
1109                 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1110                                                 DMA_TX_DFX1);
1111                 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1112                         u32 cfg = hisi_sas_phy_read32(hisi_hba,
1113                                 phy_no, CON_CONTROL);
1114
1115                         cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1116                         hisi_sas_phy_write32(hisi_hba, phy_no,
1117                                 CON_CONTROL, cfg);
1118                         clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1119                 }
1120         }
1121 }
1122
1123 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1124 {
1125         struct device *dev = hisi_hba->dev;
1126         int i;
1127
1128         /* Global registers init */
1129
1130         /* Deal with am-max-transmissions quirk */
1131         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1132                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1133                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1134                                  0x2020);
1135         } /* Else, use defaults -> do nothing */
1136
1137         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1138                          (u32)((1ULL << hisi_hba->queue_count) - 1));
1139         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1140         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1141         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1142         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1143         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1144         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1145         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1146         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1147         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1148         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1149         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1150         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1151         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1152         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1153         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1154         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1155         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1156         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1157         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1158         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1159         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1160         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1161         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1162         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1163         for (i = 0; i < hisi_hba->queue_count; i++)
1164                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1165
1166         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1167         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1168
1169         for (i = 0; i < hisi_hba->n_phy; i++) {
1170                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1171                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1172                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1173                 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1174                 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1175                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1176                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1177                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1178                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1179                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1180                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1181                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
1182                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1183                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1184                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1185                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1186                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1187                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1188                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1189                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1190                 if (hisi_hba->refclk_frequency_mhz == 66)
1191                         hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1192                 /* else, do nothing -> leave it how you found it */
1193         }
1194
1195         for (i = 0; i < hisi_hba->queue_count; i++) {
1196                 /* Delivery queue */
1197                 hisi_sas_write32(hisi_hba,
1198                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1199                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1200
1201                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1202                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1203
1204                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1205                                  HISI_SAS_QUEUE_SLOTS);
1206
1207                 /* Completion queue */
1208                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1209                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1210
1211                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1212                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1213
1214                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1215                                  HISI_SAS_QUEUE_SLOTS);
1216         }
1217
1218         /* itct */
1219         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1220                          lower_32_bits(hisi_hba->itct_dma));
1221
1222         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1223                          upper_32_bits(hisi_hba->itct_dma));
1224
1225         /* iost */
1226         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1227                          lower_32_bits(hisi_hba->iost_dma));
1228
1229         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1230                          upper_32_bits(hisi_hba->iost_dma));
1231
1232         /* breakpoint */
1233         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1234                          lower_32_bits(hisi_hba->breakpoint_dma));
1235
1236         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1237                          upper_32_bits(hisi_hba->breakpoint_dma));
1238
1239         /* SATA broken msg */
1240         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1241                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
1242
1243         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1244                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
1245
1246         /* SATA initial fis */
1247         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1248                          lower_32_bits(hisi_hba->initial_fis_dma));
1249
1250         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1251                          upper_32_bits(hisi_hba->initial_fis_dma));
1252 }
1253
1254 static void link_timeout_enable_link(unsigned long data)
1255 {
1256         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1257         int i, reg_val;
1258
1259         for (i = 0; i < hisi_hba->n_phy; i++) {
1260                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1261                         continue;
1262
1263                 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1264                 if (!(reg_val & BIT(0))) {
1265                         hisi_sas_phy_write32(hisi_hba, i,
1266                                         CON_CONTROL, 0x7);
1267                         break;
1268                 }
1269         }
1270
1271         hisi_hba->timer.function = link_timeout_disable_link;
1272         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1273 }
1274
1275 static void link_timeout_disable_link(unsigned long data)
1276 {
1277         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1278         int i, reg_val;
1279
1280         reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1281         for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1282                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1283                         continue;
1284
1285                 if (reg_val & BIT(i)) {
1286                         hisi_sas_phy_write32(hisi_hba, i,
1287                                         CON_CONTROL, 0x6);
1288                         break;
1289                 }
1290         }
1291
1292         hisi_hba->timer.function = link_timeout_enable_link;
1293         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1294 }
1295
1296 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1297 {
1298         hisi_hba->timer.data = (unsigned long)hisi_hba;
1299         hisi_hba->timer.function = link_timeout_disable_link;
1300         hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1301         add_timer(&hisi_hba->timer);
1302 }
1303
1304 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1305 {
1306         struct device *dev = hisi_hba->dev;
1307         int rc;
1308
1309         rc = reset_hw_v2_hw(hisi_hba);
1310         if (rc) {
1311                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1312                 return rc;
1313         }
1314
1315         msleep(100);
1316         init_reg_v2_hw(hisi_hba);
1317
1318         return 0;
1319 }
1320
1321 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1322 {
1323         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1324
1325         cfg |= PHY_CFG_ENA_MSK;
1326         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1327 }
1328
1329 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1330 {
1331         u32 context;
1332
1333         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1334         if (context & (1 << phy_no))
1335                 return true;
1336
1337         return false;
1338 }
1339
1340 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1341 {
1342         u32 dfx_val;
1343
1344         dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1345
1346         if (dfx_val & BIT(16))
1347                 return false;
1348
1349         return true;
1350 }
1351
1352 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1353 {
1354         int i, max_loop = 1000;
1355         struct device *dev = hisi_hba->dev;
1356         u32 status, axi_status, dfx_val, dfx_tx_val;
1357
1358         for (i = 0; i < max_loop; i++) {
1359                 status = hisi_sas_read32_relaxed(hisi_hba,
1360                         AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1361
1362                 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1363                 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1364                 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1365                         phy_no, DMA_TX_FIFO_DFX0);
1366
1367                 if ((status == 0x3) && (axi_status == 0x0) &&
1368                     (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1369                         return true;
1370                 udelay(10);
1371         }
1372         dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1373                         phy_no, status, axi_status,
1374                         dfx_val, dfx_tx_val);
1375         return false;
1376 }
1377
1378 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1379 {
1380         int i, max_loop = 1000;
1381         struct device *dev = hisi_hba->dev;
1382         u32 status, tx_dfx0;
1383
1384         for (i = 0; i < max_loop; i++) {
1385                 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1386                 status = (status & 0x3fc0) >> 6;
1387
1388                 if (status != 0x1)
1389                         return true;
1390
1391                 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1392                 if ((tx_dfx0 & 0x1ff) == 0x2)
1393                         return true;
1394                 udelay(10);
1395         }
1396         dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1397                         phy_no, status, tx_dfx0);
1398         return false;
1399 }
1400
1401 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1402 {
1403         if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1404                 return true;
1405
1406         if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1407                 return false;
1408
1409         if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1410                 return false;
1411
1412         return true;
1413 }
1414
1415
1416 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1417 {
1418         u32 cfg, axi_val, dfx0_val, txid_auto;
1419         struct device *dev = hisi_hba->dev;
1420
1421         /* Close axi bus. */
1422         axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1423                                 AM_CTRL_GLOBAL);
1424         axi_val |= 0x1;
1425         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1426                 AM_CTRL_GLOBAL, axi_val);
1427
1428         if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1429                 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1430                         goto do_disable;
1431
1432                 /* Reset host controller. */
1433                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1434                 return;
1435         }
1436
1437         dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1438         dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1439         if (dfx0_val != 0x4)
1440                 goto do_disable;
1441
1442         if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1443                 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1444                         phy_no);
1445                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1446                                         TXID_AUTO);
1447                 txid_auto |= TXID_AUTO_CTB_MSK;
1448                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1449                                         txid_auto);
1450         }
1451
1452 do_disable:
1453         cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1454         cfg &= ~PHY_CFG_ENA_MSK;
1455         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1456
1457         /* Open axi bus. */
1458         axi_val &= ~0x1;
1459         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1460                 AM_CTRL_GLOBAL, axi_val);
1461 }
1462
1463 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1464 {
1465         config_id_frame_v2_hw(hisi_hba, phy_no);
1466         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1467         enable_phy_v2_hw(hisi_hba, phy_no);
1468 }
1469
1470 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1471 {
1472         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1473         u32 txid_auto;
1474
1475         disable_phy_v2_hw(hisi_hba, phy_no);
1476         if (phy->identify.device_type == SAS_END_DEVICE) {
1477                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1478                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1479                                         txid_auto | TX_HARDRST_MSK);
1480         }
1481         msleep(100);
1482         start_phy_v2_hw(hisi_hba, phy_no);
1483 }
1484
1485 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1486 {
1487         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1488         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1489         struct sas_phy *sphy = sas_phy->phy;
1490         u32 err4_reg_val, err6_reg_val;
1491
1492         /* loss dword syn, phy reset problem */
1493         err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1494
1495         /* disparity err, invalid dword */
1496         err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1497
1498         sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1499         sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1500         sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1501         sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1502 }
1503
1504 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1505 {
1506         int i;
1507
1508         for (i = 0; i < hisi_hba->n_phy; i++) {
1509                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1510                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1511
1512                 if (!sas_phy->phy->enabled)
1513                         continue;
1514
1515                 start_phy_v2_hw(hisi_hba, i);
1516         }
1517 }
1518
1519 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1520 {
1521         u32 sl_control;
1522
1523         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1524         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1525         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1526         msleep(1);
1527         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1528         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1529         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1530 }
1531
1532 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1533 {
1534         return SAS_LINK_RATE_12_0_GBPS;
1535 }
1536
1537 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1538                 struct sas_phy_linkrates *r)
1539 {
1540         u32 prog_phy_link_rate =
1541                 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1542         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1543         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1544         int i;
1545         enum sas_linkrate min, max;
1546         u32 rate_mask = 0;
1547
1548         if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1549                 max = sas_phy->phy->maximum_linkrate;
1550                 min = r->minimum_linkrate;
1551         } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1552                 max = r->maximum_linkrate;
1553                 min = sas_phy->phy->minimum_linkrate;
1554         } else
1555                 return;
1556
1557         sas_phy->phy->maximum_linkrate = max;
1558         sas_phy->phy->minimum_linkrate = min;
1559
1560         min -= SAS_LINK_RATE_1_5_GBPS;
1561         max -= SAS_LINK_RATE_1_5_GBPS;
1562
1563         for (i = 0; i <= max; i++)
1564                 rate_mask |= 1 << (i * 2);
1565
1566         prog_phy_link_rate &= ~0xff;
1567         prog_phy_link_rate |= rate_mask;
1568
1569         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1570                         prog_phy_link_rate);
1571
1572         phy_hard_reset_v2_hw(hisi_hba, phy_no);
1573 }
1574
1575 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1576 {
1577         int i, bitmap = 0;
1578         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1579         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1580
1581         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1582                 if (phy_state & 1 << i)
1583                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1584                                 bitmap |= 1 << i;
1585
1586         if (hisi_hba->n_phy == 9) {
1587                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1588
1589                 if (phy_state & 1 << 8)
1590                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1591                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1592                                 bitmap |= 1 << 9;
1593         }
1594
1595         return bitmap;
1596 }
1597
1598 /*
1599  * The callpath to this function and upto writing the write
1600  * queue pointer should be safe from interruption.
1601  */
1602 static int
1603 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1604 {
1605         struct device *dev = hisi_hba->dev;
1606         int queue = dq->id;
1607         u32 r, w;
1608
1609         w = dq->wr_point;
1610         r = hisi_sas_read32_relaxed(hisi_hba,
1611                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1612         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1613                 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1614                                 queue, r, w);
1615                 return -EAGAIN;
1616         }
1617
1618         return 0;
1619 }
1620
1621 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1622 {
1623         struct hisi_hba *hisi_hba = dq->hisi_hba;
1624         int dlvry_queue = dq->slot_prep->dlvry_queue;
1625         int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1626
1627         dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1628         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1629                          dq->wr_point);
1630 }
1631
1632 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1633                               struct hisi_sas_slot *slot,
1634                               struct hisi_sas_cmd_hdr *hdr,
1635                               struct scatterlist *scatter,
1636                               int n_elem)
1637 {
1638         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1639         struct device *dev = hisi_hba->dev;
1640         struct scatterlist *sg;
1641         int i;
1642
1643         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1644                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1645                         n_elem);
1646                 return -EINVAL;
1647         }
1648
1649         for_each_sg(scatter, sg, n_elem, i) {
1650                 struct hisi_sas_sge *entry = &sge_page->sge[i];
1651
1652                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1653                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1654                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1655                 entry->data_off = 0;
1656         }
1657
1658         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1659
1660         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1661
1662         return 0;
1663 }
1664
1665 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1666                           struct hisi_sas_slot *slot)
1667 {
1668         struct sas_task *task = slot->task;
1669         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1670         struct domain_device *device = task->dev;
1671         struct device *dev = hisi_hba->dev;
1672         struct hisi_sas_port *port = slot->port;
1673         struct scatterlist *sg_req, *sg_resp;
1674         struct hisi_sas_device *sas_dev = device->lldd_dev;
1675         dma_addr_t req_dma_addr;
1676         unsigned int req_len, resp_len;
1677         int elem, rc;
1678
1679         /*
1680         * DMA-map SMP request, response buffers
1681         */
1682         /* req */
1683         sg_req = &task->smp_task.smp_req;
1684         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1685         if (!elem)
1686                 return -ENOMEM;
1687         req_len = sg_dma_len(sg_req);
1688         req_dma_addr = sg_dma_address(sg_req);
1689
1690         /* resp */
1691         sg_resp = &task->smp_task.smp_resp;
1692         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1693         if (!elem) {
1694                 rc = -ENOMEM;
1695                 goto err_out_req;
1696         }
1697         resp_len = sg_dma_len(sg_resp);
1698         if ((req_len & 0x3) || (resp_len & 0x3)) {
1699                 rc = -EINVAL;
1700                 goto err_out_resp;
1701         }
1702
1703         /* create header */
1704         /* dw0 */
1705         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1706                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1707                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1708
1709         /* map itct entry */
1710         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1711                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1712                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1713
1714         /* dw2 */
1715         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1716                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1717                                CMD_HDR_MRFL_OFF));
1718
1719         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1720
1721         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1722         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1723
1724         return 0;
1725
1726 err_out_resp:
1727         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1728                      DMA_FROM_DEVICE);
1729 err_out_req:
1730         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1731                      DMA_TO_DEVICE);
1732         return rc;
1733 }
1734
1735 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1736                           struct hisi_sas_slot *slot, int is_tmf,
1737                           struct hisi_sas_tmf_task *tmf)
1738 {
1739         struct sas_task *task = slot->task;
1740         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1741         struct domain_device *device = task->dev;
1742         struct hisi_sas_device *sas_dev = device->lldd_dev;
1743         struct hisi_sas_port *port = slot->port;
1744         struct sas_ssp_task *ssp_task = &task->ssp_task;
1745         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1746         int has_data = 0, rc, priority = is_tmf;
1747         u8 *buf_cmd;
1748         u32 dw1 = 0, dw2 = 0;
1749
1750         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1751                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1752                                (port->id << CMD_HDR_PORT_OFF) |
1753                                (priority << CMD_HDR_PRIORITY_OFF) |
1754                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1755
1756         dw1 = 1 << CMD_HDR_VDTL_OFF;
1757         if (is_tmf) {
1758                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1759                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1760         } else {
1761                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1762                 switch (scsi_cmnd->sc_data_direction) {
1763                 case DMA_TO_DEVICE:
1764                         has_data = 1;
1765                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1766                         break;
1767                 case DMA_FROM_DEVICE:
1768                         has_data = 1;
1769                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1770                         break;
1771                 default:
1772                         dw1 &= ~CMD_HDR_DIR_MSK;
1773                 }
1774         }
1775
1776         /* map itct entry */
1777         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1778         hdr->dw1 = cpu_to_le32(dw1);
1779
1780         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1781               + 3) / 4) << CMD_HDR_CFL_OFF) |
1782               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1783               (2 << CMD_HDR_SG_MOD_OFF);
1784         hdr->dw2 = cpu_to_le32(dw2);
1785
1786         hdr->transfer_tags = cpu_to_le32(slot->idx);
1787
1788         if (has_data) {
1789                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1790                                         slot->n_elem);
1791                 if (rc)
1792                         return rc;
1793         }
1794
1795         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1796         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1797         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1798
1799         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1800                 sizeof(struct ssp_frame_hdr);
1801
1802         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1803         if (!is_tmf) {
1804                 buf_cmd[9] = task->ssp_task.task_attr |
1805                                 (task->ssp_task.task_prio << 3);
1806                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1807                                 task->ssp_task.cmd->cmd_len);
1808         } else {
1809                 buf_cmd[10] = tmf->tmf;
1810                 switch (tmf->tmf) {
1811                 case TMF_ABORT_TASK:
1812                 case TMF_QUERY_TASK:
1813                         buf_cmd[12] =
1814                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1815                         buf_cmd[13] =
1816                                 tmf->tag_of_task_to_be_managed & 0xff;
1817                         break;
1818                 default:
1819                         break;
1820                 }
1821         }
1822
1823         return 0;
1824 }
1825
1826 #define TRANS_TX_ERR    0
1827 #define TRANS_RX_ERR    1
1828 #define DMA_TX_ERR              2
1829 #define SIPC_RX_ERR             3
1830 #define DMA_RX_ERR              4
1831
1832 #define DMA_TX_ERR_OFF  0
1833 #define DMA_TX_ERR_MSK  (0xffff << DMA_TX_ERR_OFF)
1834 #define SIPC_RX_ERR_OFF 16
1835 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1836
1837 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1838 {
1839         static const u8 trans_tx_err_code_prio[] = {
1840                 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1841                 TRANS_TX_ERR_PHY_NOT_ENABLE,
1842                 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1843                 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1844                 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1845                 RESERVED0,
1846                 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1847                 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1848                 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1849                 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1850                 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1851                 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1852                 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1853                 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1854                 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1855                 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1856                 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1857                 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1858                 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1859                 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1860                 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1861                 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1862                 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1863                 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1864                 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1865                 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1866                 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1867                 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1868                 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1869                 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1870                 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1871         };
1872         int index, i;
1873
1874         for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1875                 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1876                 if (err_msk & (1 << index))
1877                         return trans_tx_err_code_prio[i];
1878         }
1879         return -1;
1880 }
1881
1882 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1883 {
1884         static const u8 trans_rx_err_code_prio[] = {
1885                 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1886                 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1887                 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1888                 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1889                 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1890                 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1891                 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1892                 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1893                 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1894                 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1895                 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1896                 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1897                 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1898                 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1899                 RESERVED1,
1900                 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1901                 TRANS_RX_ERR_WITH_DATA_LEN0,
1902                 TRANS_RX_ERR_WITH_BAD_HASH,
1903                 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1904                 TRANS_RX_SSP_FRM_LEN_ERR,
1905                 RESERVED2,
1906                 RESERVED3,
1907                 RESERVED4,
1908                 RESERVED5,
1909                 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1910                 TRANS_RX_SMP_FRM_LEN_ERR,
1911                 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1912                 RESERVED6,
1913                 RESERVED7,
1914                 RESERVED8,
1915                 RESERVED9,
1916                 TRANS_RX_R_ERR,
1917         };
1918         int index, i;
1919
1920         for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1921                 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1922                 if (err_msk & (1 << index))
1923                         return trans_rx_err_code_prio[i];
1924         }
1925         return -1;
1926 }
1927
1928 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1929 {
1930         static const u8 dma_tx_err_code_prio[] = {
1931                 DMA_TX_UNEXP_XFER_ERR,
1932                 DMA_TX_UNEXP_RETRANS_ERR,
1933                 DMA_TX_XFER_LEN_OVERFLOW,
1934                 DMA_TX_XFER_OFFSET_ERR,
1935                 DMA_TX_RAM_ECC_ERR,
1936                 DMA_TX_DIF_LEN_ALIGN_ERR,
1937                 DMA_TX_DIF_CRC_ERR,
1938                 DMA_TX_DIF_APP_ERR,
1939                 DMA_TX_DIF_RPP_ERR,
1940                 DMA_TX_DATA_SGL_OVERFLOW,
1941                 DMA_TX_DIF_SGL_OVERFLOW,
1942         };
1943         int index, i;
1944
1945         for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1946                 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1947                 err_msk = err_msk & DMA_TX_ERR_MSK;
1948                 if (err_msk & (1 << index))
1949                         return dma_tx_err_code_prio[i];
1950         }
1951         return -1;
1952 }
1953
1954 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1955 {
1956         static const u8 sipc_rx_err_code_prio[] = {
1957                 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1958                 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1959                 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1960                 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1961                 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1962                 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1963                 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1964                 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1965                 SIPC_RX_SATA_UNEXP_FIS_ERR,
1966                 SIPC_RX_WRSETUP_ESTATUS_ERR,
1967                 SIPC_RX_DATA_UNDERFLOW_ERR,
1968         };
1969         int index, i;
1970
1971         for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1972                 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1973                 err_msk = err_msk & SIPC_RX_ERR_MSK;
1974                 if (err_msk & (1 << (index + 0x10)))
1975                         return sipc_rx_err_code_prio[i];
1976         }
1977         return -1;
1978 }
1979
1980 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1981 {
1982         static const u8 dma_rx_err_code_prio[] = {
1983                 DMA_RX_UNKNOWN_FRM_ERR,
1984                 DMA_RX_DATA_LEN_OVERFLOW,
1985                 DMA_RX_DATA_LEN_UNDERFLOW,
1986                 DMA_RX_DATA_OFFSET_ERR,
1987                 RESERVED10,
1988                 DMA_RX_SATA_FRAME_TYPE_ERR,
1989                 DMA_RX_RESP_BUF_OVERFLOW,
1990                 DMA_RX_UNEXP_RETRANS_RESP_ERR,
1991                 DMA_RX_UNEXP_NORM_RESP_ERR,
1992                 DMA_RX_UNEXP_RDFRAME_ERR,
1993                 DMA_RX_PIO_DATA_LEN_ERR,
1994                 DMA_RX_RDSETUP_STATUS_ERR,
1995                 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
1996                 DMA_RX_RDSETUP_STATUS_BSY_ERR,
1997                 DMA_RX_RDSETUP_LEN_ODD_ERR,
1998                 DMA_RX_RDSETUP_LEN_ZERO_ERR,
1999                 DMA_RX_RDSETUP_LEN_OVER_ERR,
2000                 DMA_RX_RDSETUP_OFFSET_ERR,
2001                 DMA_RX_RDSETUP_ACTIVE_ERR,
2002                 DMA_RX_RDSETUP_ESTATUS_ERR,
2003                 DMA_RX_RAM_ECC_ERR,
2004                 DMA_RX_DIF_CRC_ERR,
2005                 DMA_RX_DIF_APP_ERR,
2006                 DMA_RX_DIF_RPP_ERR,
2007                 DMA_RX_DATA_SGL_OVERFLOW,
2008                 DMA_RX_DIF_SGL_OVERFLOW,
2009         };
2010         int index, i;
2011
2012         for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2013                 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2014                 if (err_msk & (1 << index))
2015                         return dma_rx_err_code_prio[i];
2016         }
2017         return -1;
2018 }
2019
2020 /* by default, task resp is complete */
2021 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2022                            struct sas_task *task,
2023                            struct hisi_sas_slot *slot,
2024                            int err_phase)
2025 {
2026         struct task_status_struct *ts = &task->task_status;
2027         struct hisi_sas_err_record_v2 *err_record =
2028                         hisi_sas_status_buf_addr_mem(slot);
2029         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2030         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2031         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2032         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2033         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2034         int error = -1;
2035
2036         if (err_phase == 1) {
2037                 /* error in TX phase, the priority of error is: DW2 > DW0 */
2038                 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2039                 if (error == -1)
2040                         error = parse_trans_tx_err_code_v2_hw(
2041                                         trans_tx_fail_type);
2042         } else if (err_phase == 2) {
2043                 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2044                 error = parse_trans_rx_err_code_v2_hw(
2045                                         trans_rx_fail_type);
2046                 if (error == -1) {
2047                         error = parse_dma_rx_err_code_v2_hw(
2048                                         dma_rx_err_type);
2049                         if (error == -1)
2050                                 error = parse_sipc_rx_err_code_v2_hw(
2051                                                 sipc_rx_err_type);
2052                 }
2053         }
2054
2055         switch (task->task_proto) {
2056         case SAS_PROTOCOL_SSP:
2057         {
2058                 switch (error) {
2059                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2060                 {
2061                         ts->stat = SAS_OPEN_REJECT;
2062                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2063                         break;
2064                 }
2065                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2066                 {
2067                         ts->stat = SAS_OPEN_REJECT;
2068                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2069                         break;
2070                 }
2071                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2072                 {
2073                         ts->stat = SAS_OPEN_REJECT;
2074                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2075                         break;
2076                 }
2077                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2078                 {
2079                         ts->stat = SAS_OPEN_REJECT;
2080                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2081                         break;
2082                 }
2083                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2084                 {
2085                         ts->stat = SAS_OPEN_REJECT;
2086                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2087                         break;
2088                 }
2089                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2090                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2091                 case DMA_RX_RESP_BUF_OVERFLOW:
2092                 {
2093                         ts->stat = SAS_OPEN_REJECT;
2094                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2095                         break;
2096                 }
2097                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2098                 {
2099                         /* not sure */
2100                         ts->stat = SAS_DEV_NO_RESPONSE;
2101                         break;
2102                 }
2103                 case DMA_RX_DATA_LEN_OVERFLOW:
2104                 {
2105                         ts->stat = SAS_DATA_OVERRUN;
2106                         ts->residual = 0;
2107                         break;
2108                 }
2109                 case DMA_RX_DATA_LEN_UNDERFLOW:
2110                 {
2111                         ts->residual = trans_tx_fail_type;
2112                         ts->stat = SAS_DATA_UNDERRUN;
2113                         break;
2114                 }
2115                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2116                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2117                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2118                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2119                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2120                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2121                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2122                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2123                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2124                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2125                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2126                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2127                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2128                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2129                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2130                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2131                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2132                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2133                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2134                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2135                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2136                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2137                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2138                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2139                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2140                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2141                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2142                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2143                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2144                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2145                 case TRANS_TX_ERR_FRAME_TXED:
2146                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2147                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2148                 case TRANS_RX_ERR_WITH_BAD_HASH:
2149                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2150                 case TRANS_RX_SSP_FRM_LEN_ERR:
2151                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2152                 case DMA_TX_DATA_SGL_OVERFLOW:
2153                 case DMA_TX_UNEXP_XFER_ERR:
2154                 case DMA_TX_UNEXP_RETRANS_ERR:
2155                 case DMA_TX_XFER_LEN_OVERFLOW:
2156                 case DMA_TX_XFER_OFFSET_ERR:
2157                 case SIPC_RX_DATA_UNDERFLOW_ERR:
2158                 case DMA_RX_DATA_SGL_OVERFLOW:
2159                 case DMA_RX_DATA_OFFSET_ERR:
2160                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2161                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2162                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2163                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2164                 case DMA_RX_UNKNOWN_FRM_ERR:
2165                 {
2166                         /* This will request a retry */
2167                         ts->stat = SAS_QUEUE_FULL;
2168                         slot->abort = 1;
2169                         break;
2170                 }
2171                 default:
2172                         break;
2173                 }
2174         }
2175                 break;
2176         case SAS_PROTOCOL_SMP:
2177                 ts->stat = SAM_STAT_CHECK_CONDITION;
2178                 break;
2179
2180         case SAS_PROTOCOL_SATA:
2181         case SAS_PROTOCOL_STP:
2182         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2183         {
2184                 switch (error) {
2185                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2186                 {
2187                         ts->stat = SAS_OPEN_REJECT;
2188                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2189                         break;
2190                 }
2191                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2192                 {
2193                         ts->resp = SAS_TASK_UNDELIVERED;
2194                         ts->stat = SAS_DEV_NO_RESPONSE;
2195                         break;
2196                 }
2197                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2198                 {
2199                         ts->stat = SAS_OPEN_REJECT;
2200                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2201                         break;
2202                 }
2203                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2204                 {
2205                         ts->stat = SAS_OPEN_REJECT;
2206                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2207                         break;
2208                 }
2209                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2210                 {
2211                         ts->stat = SAS_OPEN_REJECT;
2212                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2213                         break;
2214                 }
2215                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2216                 {
2217                         ts->stat = SAS_OPEN_REJECT;
2218                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2219                         break;
2220                 }
2221                 case DMA_RX_RESP_BUF_OVERFLOW:
2222                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2223                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2224                 {
2225                         ts->stat = SAS_OPEN_REJECT;
2226                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2227                         break;
2228                 }
2229                 case DMA_RX_DATA_LEN_OVERFLOW:
2230                 {
2231                         ts->stat = SAS_DATA_OVERRUN;
2232                         ts->residual = 0;
2233                         break;
2234                 }
2235                 case DMA_RX_DATA_LEN_UNDERFLOW:
2236                 {
2237                         ts->residual = trans_tx_fail_type;
2238                         ts->stat = SAS_DATA_UNDERRUN;
2239                         break;
2240                 }
2241                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2242                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2243                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2244                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2245                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2246                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2247                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2248                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2249                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2250                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2251                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2252                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2253                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2254                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2255                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2256                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2257                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2258                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2259                 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2260                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2261                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2262                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2263                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2264                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2265                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2266                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2267                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2268                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2269                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2270                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2271                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2272                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2273                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2274                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2275                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2276                 case TRANS_RX_ERR_WITH_BAD_HASH:
2277                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2278                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2279                 case DMA_TX_DATA_SGL_OVERFLOW:
2280                 case DMA_TX_UNEXP_XFER_ERR:
2281                 case DMA_TX_UNEXP_RETRANS_ERR:
2282                 case DMA_TX_XFER_LEN_OVERFLOW:
2283                 case DMA_TX_XFER_OFFSET_ERR:
2284                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2285                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2286                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2287                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2288                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2289                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2290                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2291                 case DMA_RX_DATA_SGL_OVERFLOW:
2292                 case DMA_RX_DATA_OFFSET_ERR:
2293                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2294                 case DMA_RX_UNEXP_RDFRAME_ERR:
2295                 case DMA_RX_PIO_DATA_LEN_ERR:
2296                 case DMA_RX_RDSETUP_STATUS_ERR:
2297                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2298                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2299                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2300                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2301                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2302                 case DMA_RX_RDSETUP_OFFSET_ERR:
2303                 case DMA_RX_RDSETUP_ACTIVE_ERR:
2304                 case DMA_RX_RDSETUP_ESTATUS_ERR:
2305                 case DMA_RX_UNKNOWN_FRM_ERR:
2306                 case TRANS_RX_SSP_FRM_LEN_ERR:
2307                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2308                 {
2309                         slot->abort = 1;
2310                         ts->stat = SAS_PHY_DOWN;
2311                         break;
2312                 }
2313                 default:
2314                 {
2315                         ts->stat = SAS_PROTO_RESPONSE;
2316                         break;
2317                 }
2318                 }
2319                 hisi_sas_sata_done(task, slot);
2320         }
2321                 break;
2322         default:
2323                 break;
2324         }
2325 }
2326
2327 static int
2328 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2329 {
2330         struct sas_task *task = slot->task;
2331         struct hisi_sas_device *sas_dev;
2332         struct device *dev = hisi_hba->dev;
2333         struct task_status_struct *ts;
2334         struct domain_device *device;
2335         enum exec_status sts;
2336         struct hisi_sas_complete_v2_hdr *complete_queue =
2337                         hisi_hba->complete_hdr[slot->cmplt_queue];
2338         struct hisi_sas_complete_v2_hdr *complete_hdr =
2339                         &complete_queue[slot->cmplt_queue_slot];
2340         unsigned long flags;
2341         int aborted;
2342
2343         if (unlikely(!task || !task->lldd_task || !task->dev))
2344                 return -EINVAL;
2345
2346         ts = &task->task_status;
2347         device = task->dev;
2348         sas_dev = device->lldd_dev;
2349
2350         spin_lock_irqsave(&task->task_state_lock, flags);
2351         aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2352         task->task_state_flags &=
2353                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2354         spin_unlock_irqrestore(&task->task_state_lock, flags);
2355
2356         memset(ts, 0, sizeof(*ts));
2357         ts->resp = SAS_TASK_COMPLETE;
2358
2359         if (unlikely(aborted)) {
2360                 ts->stat = SAS_ABORTED_TASK;
2361                 spin_lock_irqsave(&hisi_hba->lock, flags);
2362                 hisi_sas_slot_task_free(hisi_hba, task, slot);
2363                 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2364                 return -1;
2365         }
2366
2367         if (unlikely(!sas_dev)) {
2368                 dev_dbg(dev, "slot complete: port has no device\n");
2369                 ts->stat = SAS_PHY_DOWN;
2370                 goto out;
2371         }
2372
2373         /* Use SAS+TMF status codes */
2374         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2375                         >> CMPLT_HDR_ABORT_STAT_OFF) {
2376         case STAT_IO_ABORTED:
2377                 /* this io has been aborted by abort command */
2378                 ts->stat = SAS_ABORTED_TASK;
2379                 goto out;
2380         case STAT_IO_COMPLETE:
2381                 /* internal abort command complete */
2382                 ts->stat = TMF_RESP_FUNC_SUCC;
2383                 del_timer(&slot->internal_abort_timer);
2384                 goto out;
2385         case STAT_IO_NO_DEVICE:
2386                 ts->stat = TMF_RESP_FUNC_COMPLETE;
2387                 del_timer(&slot->internal_abort_timer);
2388                 goto out;
2389         case STAT_IO_NOT_VALID:
2390                 /* abort single io, controller don't find
2391                  * the io need to abort
2392                  */
2393                 ts->stat = TMF_RESP_FUNC_FAILED;
2394                 del_timer(&slot->internal_abort_timer);
2395                 goto out;
2396         default:
2397                 break;
2398         }
2399
2400         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2401                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2402                 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2403                                 >> CMPLT_HDR_ERR_PHASE_OFF;
2404
2405                 /* Analyse error happens on which phase TX or RX */
2406                 if (ERR_ON_TX_PHASE(err_phase))
2407                         slot_err_v2_hw(hisi_hba, task, slot, 1);
2408                 else if (ERR_ON_RX_PHASE(err_phase))
2409                         slot_err_v2_hw(hisi_hba, task, slot, 2);
2410
2411                 if (unlikely(slot->abort))
2412                         return ts->stat;
2413                 goto out;
2414         }
2415
2416         switch (task->task_proto) {
2417         case SAS_PROTOCOL_SSP:
2418         {
2419                 struct hisi_sas_status_buffer *status_buffer =
2420                                 hisi_sas_status_buf_addr_mem(slot);
2421                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2422                                 &status_buffer->iu[0];
2423
2424                 sas_ssp_task_response(dev, task, iu);
2425                 break;
2426         }
2427         case SAS_PROTOCOL_SMP:
2428         {
2429                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2430                 void *to;
2431
2432                 ts->stat = SAM_STAT_GOOD;
2433                 to = kmap_atomic(sg_page(sg_resp));
2434
2435                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2436                              DMA_FROM_DEVICE);
2437                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2438                              DMA_TO_DEVICE);
2439                 memcpy(to + sg_resp->offset,
2440                        hisi_sas_status_buf_addr_mem(slot) +
2441                        sizeof(struct hisi_sas_err_record),
2442                        sg_dma_len(sg_resp));
2443                 kunmap_atomic(to);
2444                 break;
2445         }
2446         case SAS_PROTOCOL_SATA:
2447         case SAS_PROTOCOL_STP:
2448         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2449         {
2450                 ts->stat = SAM_STAT_GOOD;
2451                 hisi_sas_sata_done(task, slot);
2452                 break;
2453         }
2454         default:
2455                 ts->stat = SAM_STAT_CHECK_CONDITION;
2456                 break;
2457         }
2458
2459         if (!slot->port->port_attached) {
2460                 dev_err(dev, "slot complete: port %d has removed\n",
2461                         slot->port->sas_port.id);
2462                 ts->stat = SAS_PHY_DOWN;
2463         }
2464
2465 out:
2466         spin_lock_irqsave(&task->task_state_lock, flags);
2467         task->task_state_flags |= SAS_TASK_STATE_DONE;
2468         spin_unlock_irqrestore(&task->task_state_lock, flags);
2469         spin_lock_irqsave(&hisi_hba->lock, flags);
2470         hisi_sas_slot_task_free(hisi_hba, task, slot);
2471         spin_unlock_irqrestore(&hisi_hba->lock, flags);
2472         sts = ts->stat;
2473
2474         if (task->task_done)
2475                 task->task_done(task);
2476
2477         return sts;
2478 }
2479
2480 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2481                           struct hisi_sas_slot *slot)
2482 {
2483         struct sas_task *task = slot->task;
2484         struct domain_device *device = task->dev;
2485         struct domain_device *parent_dev = device->parent;
2486         struct hisi_sas_device *sas_dev = device->lldd_dev;
2487         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2488         struct asd_sas_port *sas_port = device->port;
2489         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2490         u8 *buf_cmd;
2491         int has_data = 0, rc = 0, hdr_tag = 0;
2492         u32 dw1 = 0, dw2 = 0;
2493
2494         /* create header */
2495         /* dw0 */
2496         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2497         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2498                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2499         else
2500                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2501
2502         /* dw1 */
2503         switch (task->data_dir) {
2504         case DMA_TO_DEVICE:
2505                 has_data = 1;
2506                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2507                 break;
2508         case DMA_FROM_DEVICE:
2509                 has_data = 1;
2510                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2511                 break;
2512         default:
2513                 dw1 &= ~CMD_HDR_DIR_MSK;
2514         }
2515
2516         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2517                         (task->ata_task.fis.control & ATA_SRST))
2518                 dw1 |= 1 << CMD_HDR_RESET_OFF;
2519
2520         dw1 |= (hisi_sas_get_ata_protocol(
2521                 task->ata_task.fis.command, task->data_dir))
2522                 << CMD_HDR_FRAME_TYPE_OFF;
2523         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2524         hdr->dw1 = cpu_to_le32(dw1);
2525
2526         /* dw2 */
2527         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2528                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2529                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2530         }
2531
2532         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2533                         2 << CMD_HDR_SG_MOD_OFF;
2534         hdr->dw2 = cpu_to_le32(dw2);
2535
2536         /* dw3 */
2537         hdr->transfer_tags = cpu_to_le32(slot->idx);
2538
2539         if (has_data) {
2540                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2541                                         slot->n_elem);
2542                 if (rc)
2543                         return rc;
2544         }
2545
2546         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2547         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2548         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2549
2550         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2551
2552         if (likely(!task->ata_task.device_control_reg_update))
2553                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2554         /* fill in command FIS */
2555         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2556
2557         return 0;
2558 }
2559
2560 static void hisi_sas_internal_abort_quirk_timeout(unsigned long data)
2561 {
2562         struct hisi_sas_slot *slot = (struct hisi_sas_slot *)data;
2563         struct hisi_sas_port *port = slot->port;
2564         struct asd_sas_port *asd_sas_port;
2565         struct asd_sas_phy *sas_phy;
2566
2567         if (!port)
2568                 return;
2569
2570         asd_sas_port = &port->sas_port;
2571
2572         /* Kick the hardware - send break command */
2573         list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2574                 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2575                 struct hisi_hba *hisi_hba = phy->hisi_hba;
2576                 int phy_no = sas_phy->id;
2577                 u32 link_dfx2;
2578
2579                 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2580                 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2581                     (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2582                         u32 txid_auto;
2583
2584                         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2585                                                         TXID_AUTO);
2586                         txid_auto |= TXID_AUTO_CTB_MSK;
2587                         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2588                                              txid_auto);
2589                         return;
2590                 }
2591         }
2592 }
2593
2594 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2595                 struct hisi_sas_slot *slot,
2596                 int device_id, int abort_flag, int tag_to_abort)
2597 {
2598         struct sas_task *task = slot->task;
2599         struct domain_device *dev = task->dev;
2600         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2601         struct hisi_sas_port *port = slot->port;
2602         struct timer_list *timer = &slot->internal_abort_timer;
2603
2604         /* setup the quirk timer */
2605         setup_timer(timer, hisi_sas_internal_abort_quirk_timeout,
2606                     (unsigned long)slot);
2607         /* Set the timeout to 10ms less than internal abort timeout */
2608         mod_timer(timer, jiffies + msecs_to_jiffies(100));
2609
2610         /* dw0 */
2611         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2612                                (port->id << CMD_HDR_PORT_OFF) |
2613                                ((dev_is_sata(dev) ? 1:0) <<
2614                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2615                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2616
2617         /* dw1 */
2618         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2619
2620         /* dw7 */
2621         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2622         hdr->transfer_tags = cpu_to_le32(slot->idx);
2623
2624         return 0;
2625 }
2626
2627 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2628 {
2629         int i, res = IRQ_HANDLED;
2630         u32 port_id, link_rate, hard_phy_linkrate;
2631         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2632         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2633         struct device *dev = hisi_hba->dev;
2634         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2635         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2636
2637         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2638
2639         if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2640                 goto end;
2641
2642         if (phy_no == 8) {
2643                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2644
2645                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2646                           PORT_STATE_PHY8_PORT_NUM_OFF;
2647                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2648                             PORT_STATE_PHY8_CONN_RATE_OFF;
2649         } else {
2650                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2651                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2652                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2653                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2654         }
2655
2656         if (port_id == 0xf) {
2657                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2658                 res = IRQ_NONE;
2659                 goto end;
2660         }
2661
2662         for (i = 0; i < 6; i++) {
2663                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2664                                                RX_IDAF_DWORD0 + (i * 4));
2665                 frame_rcvd[i] = __swab32(idaf);
2666         }
2667
2668         sas_phy->linkrate = link_rate;
2669         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2670                                                 HARD_PHY_LINKRATE);
2671         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2672         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2673
2674         sas_phy->oob_mode = SAS_OOB_MODE;
2675         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2676         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2677         phy->port_id = port_id;
2678         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2679         phy->phy_type |= PORT_TYPE_SAS;
2680         phy->phy_attached = 1;
2681         phy->identify.device_type = id->dev_type;
2682         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
2683         if (phy->identify.device_type == SAS_END_DEVICE)
2684                 phy->identify.target_port_protocols =
2685                         SAS_PROTOCOL_SSP;
2686         else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2687                 phy->identify.target_port_protocols =
2688                         SAS_PROTOCOL_SMP;
2689                 if (!timer_pending(&hisi_hba->timer))
2690                         set_link_timer_quirk(hisi_hba);
2691         }
2692         queue_work(hisi_hba->wq, &phy->phyup_ws);
2693
2694 end:
2695         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2696                              CHL_INT0_SL_PHY_ENABLE_MSK);
2697         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2698
2699         return res;
2700 }
2701
2702 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2703 {
2704         u32 port_state;
2705
2706         port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2707         if (port_state & 0x1ff)
2708                 return true;
2709
2710         return false;
2711 }
2712
2713 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2714 {
2715         u32 phy_state, sl_ctrl, txid_auto;
2716         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2717         struct hisi_sas_port *port = phy->port;
2718
2719         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2720
2721         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2722         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2723
2724         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2725         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2726                              sl_ctrl & ~SL_CONTROL_CTA_MSK);
2727         if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2728                 if (!check_any_wideports_v2_hw(hisi_hba) &&
2729                                 timer_pending(&hisi_hba->timer))
2730                         del_timer(&hisi_hba->timer);
2731
2732         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2733         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2734                              txid_auto | TXID_AUTO_CT3_MSK);
2735
2736         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2737         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2738
2739         return IRQ_HANDLED;
2740 }
2741
2742 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2743 {
2744         struct hisi_hba *hisi_hba = p;
2745         u32 irq_msk;
2746         int phy_no = 0;
2747         irqreturn_t res = IRQ_NONE;
2748
2749         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2750                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2751         while (irq_msk) {
2752                 if (irq_msk  & 1) {
2753                         u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2754                                             CHL_INT0);
2755
2756                         switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2757                                         CHL_INT0_SL_PHY_ENABLE_MSK)) {
2758
2759                         case CHL_INT0_SL_PHY_ENABLE_MSK:
2760                                 /* phy up */
2761                                 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2762                                     IRQ_HANDLED)
2763                                         res = IRQ_HANDLED;
2764                                 break;
2765
2766                         case CHL_INT0_NOT_RDY_MSK:
2767                                 /* phy down */
2768                                 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2769                                     IRQ_HANDLED)
2770                                         res = IRQ_HANDLED;
2771                                 break;
2772
2773                         case (CHL_INT0_NOT_RDY_MSK |
2774                                         CHL_INT0_SL_PHY_ENABLE_MSK):
2775                                 reg_value = hisi_sas_read32(hisi_hba,
2776                                                 PHY_STATE);
2777                                 if (reg_value & BIT(phy_no)) {
2778                                         /* phy up */
2779                                         if (phy_up_v2_hw(phy_no, hisi_hba) ==
2780                                             IRQ_HANDLED)
2781                                                 res = IRQ_HANDLED;
2782                                 } else {
2783                                         /* phy down */
2784                                         if (phy_down_v2_hw(phy_no, hisi_hba) ==
2785                                             IRQ_HANDLED)
2786                                                 res = IRQ_HANDLED;
2787                                 }
2788                                 break;
2789
2790                         default:
2791                                 break;
2792                         }
2793
2794                 }
2795                 irq_msk >>= 1;
2796                 phy_no++;
2797         }
2798
2799         return res;
2800 }
2801
2802 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2803 {
2804         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2805         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2806         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2807         u32 bcast_status;
2808
2809         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2810         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2811         if (bcast_status & RX_BCAST_CHG_MSK)
2812                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2813         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2814                              CHL_INT0_SL_RX_BCST_ACK_MSK);
2815         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2816 }
2817
2818 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2819 {
2820         struct hisi_hba *hisi_hba = p;
2821         struct device *dev = hisi_hba->dev;
2822         u32 ent_msk, ent_tmp, irq_msk;
2823         int phy_no = 0;
2824
2825         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2826         ent_tmp = ent_msk;
2827         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2828         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2829
2830         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2831                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2832
2833         while (irq_msk) {
2834                 if (irq_msk & (1 << phy_no)) {
2835                         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2836                                                              CHL_INT0);
2837                         u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2838                                                              CHL_INT1);
2839                         u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2840                                                              CHL_INT2);
2841
2842                         if (irq_value1) {
2843                                 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2844                                                   CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2845                                         panic("%s: DMAC RX/TX ecc bad error!\
2846                                                (0x%x)",
2847                                               dev_name(dev), irq_value1);
2848
2849                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2850                                                      CHL_INT1, irq_value1);
2851                         }
2852
2853                         if (irq_value2)
2854                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2855                                                      CHL_INT2, irq_value2);
2856
2857
2858                         if (irq_value0) {
2859                                 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2860                                         phy_bcast_v2_hw(phy_no, hisi_hba);
2861
2862                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2863                                                 CHL_INT0, irq_value0
2864                                                 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2865                                                 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2866                                                 & (~CHL_INT0_NOT_RDY_MSK));
2867                         }
2868                 }
2869                 irq_msk &= ~(1 << phy_no);
2870                 phy_no++;
2871         }
2872
2873         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2874
2875         return IRQ_HANDLED;
2876 }
2877
2878 static void
2879 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2880 {
2881         struct device *dev = hisi_hba->dev;
2882         const struct hisi_sas_hw_error *ecc_error;
2883         u32 val;
2884         int i;
2885
2886         for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2887                 ecc_error = &one_bit_ecc_errors[i];
2888                 if (irq_value & ecc_error->irq_msk) {
2889                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2890                         val &= ecc_error->msk;
2891                         val >>= ecc_error->shift;
2892                         dev_warn(dev, ecc_error->msg, val);
2893                 }
2894         }
2895 }
2896
2897 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2898                 u32 irq_value)
2899 {
2900         struct device *dev = hisi_hba->dev;
2901         const struct hisi_sas_hw_error *ecc_error;
2902         u32 val;
2903         int i;
2904
2905         for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2906                 ecc_error = &multi_bit_ecc_errors[i];
2907                 if (irq_value & ecc_error->irq_msk) {
2908                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2909                         val &= ecc_error->msk;
2910                         val >>= ecc_error->shift;
2911                         dev_warn(dev, ecc_error->msg, irq_value, val);
2912                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2913                 }
2914         }
2915
2916         return;
2917 }
2918
2919 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2920 {
2921         struct hisi_hba *hisi_hba = p;
2922         u32 irq_value, irq_msk;
2923
2924         irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2925         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2926
2927         irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2928         if (irq_value) {
2929                 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2930                 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2931         }
2932
2933         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2934         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2935
2936         return IRQ_HANDLED;
2937 }
2938
2939 static const struct hisi_sas_hw_error axi_error[] = {
2940         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2941         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2942         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2943         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2944         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2945         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2946         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2947         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2948         {},
2949 };
2950
2951 static const struct hisi_sas_hw_error fifo_error[] = {
2952         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
2953         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
2954         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
2955         { .msk = BIT(11), .msg = "CMDP_FIFO" },
2956         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2957         {},
2958 };
2959
2960 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
2961         {
2962                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2963                 .msg = "write pointer and depth",
2964         },
2965         {
2966                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2967                 .msg = "iptt no match slot",
2968         },
2969         {
2970                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2971                 .msg = "read pointer and depth",
2972         },
2973         {
2974                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2975                 .reg = HGC_AXI_FIFO_ERR_INFO,
2976                 .sub = axi_error,
2977         },
2978         {
2979                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2980                 .reg = HGC_AXI_FIFO_ERR_INFO,
2981                 .sub = fifo_error,
2982         },
2983         {
2984                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2985                 .msg = "LM add/fetch list",
2986         },
2987         {
2988                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2989                 .msg = "SAS_HGC_ABT fetch LM list",
2990         },
2991 };
2992
2993 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
2994 {
2995         struct hisi_hba *hisi_hba = p;
2996         u32 irq_value, irq_msk, err_value;
2997         struct device *dev = hisi_hba->dev;
2998         const struct hisi_sas_hw_error *axi_error;
2999         int i;
3000
3001         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3002         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3003
3004         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3005
3006         for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3007                 axi_error = &fatal_axi_errors[i];
3008                 if (!(irq_value & axi_error->irq_msk))
3009                         continue;
3010
3011                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3012                                  1 << axi_error->shift);
3013                 if (axi_error->sub) {
3014                         const struct hisi_sas_hw_error *sub = axi_error->sub;
3015
3016                         err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3017                         for (; sub->msk || sub->msg; sub++) {
3018                                 if (!(err_value & sub->msk))
3019                                         continue;
3020                                 dev_warn(dev, "%s (0x%x) found!\n",
3021                                          sub->msg, irq_value);
3022                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3023                         }
3024                 } else {
3025                         dev_warn(dev, "%s (0x%x) found!\n",
3026                                  axi_error->msg, irq_value);
3027                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3028                 }
3029         }
3030
3031         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3032                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3033                 u32 dev_id = reg_val & ITCT_DEV_MSK;
3034                 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3035
3036                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3037                 dev_dbg(dev, "clear ITCT ok\n");
3038                 complete(sas_dev->completion);
3039         }
3040
3041         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3042         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3043
3044         return IRQ_HANDLED;
3045 }
3046
3047 static void cq_tasklet_v2_hw(unsigned long val)
3048 {
3049         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3050         struct hisi_hba *hisi_hba = cq->hisi_hba;
3051         struct hisi_sas_slot *slot;
3052         struct hisi_sas_itct *itct;
3053         struct hisi_sas_complete_v2_hdr *complete_queue;
3054         u32 rd_point = cq->rd_point, wr_point, dev_id;
3055         int queue = cq->id;
3056         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3057
3058         if (unlikely(hisi_hba->reject_stp_links_msk))
3059                 phys_try_accept_stp_links_v2_hw(hisi_hba);
3060
3061         complete_queue = hisi_hba->complete_hdr[queue];
3062
3063         spin_lock(&dq->lock);
3064         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3065                                    (0x14 * queue));
3066
3067         while (rd_point != wr_point) {
3068                 struct hisi_sas_complete_v2_hdr *complete_hdr;
3069                 int iptt;
3070
3071                 complete_hdr = &complete_queue[rd_point];
3072
3073                 /* Check for NCQ completion */
3074                 if (complete_hdr->act) {
3075                         u32 act_tmp = complete_hdr->act;
3076                         int ncq_tag_count = ffs(act_tmp);
3077
3078                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3079                                  CMPLT_HDR_DEV_ID_OFF;
3080                         itct = &hisi_hba->itct[dev_id];
3081
3082                         /* The NCQ tags are held in the itct header */
3083                         while (ncq_tag_count) {
3084                                 __le64 *ncq_tag = &itct->qw4_15[0];
3085
3086                                 ncq_tag_count -= 1;
3087                                 iptt = (ncq_tag[ncq_tag_count / 5]
3088                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
3089
3090                                 slot = &hisi_hba->slot_info[iptt];
3091                                 slot->cmplt_queue_slot = rd_point;
3092                                 slot->cmplt_queue = queue;
3093                                 slot_complete_v2_hw(hisi_hba, slot);
3094
3095                                 act_tmp &= ~(1 << ncq_tag_count);
3096                                 ncq_tag_count = ffs(act_tmp);
3097                         }
3098                 } else {