Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[muen/linux.git] / drivers / soc / rockchip / pm_domains.c
1 /*
2  * Rockchip Generic power domain support.
3  *
4  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/err.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_platform.h>
19 #include <linux/clk.h>
20 #include <linux/regmap.h>
21 #include <linux/mfd/syscon.h>
22 #include <dt-bindings/power/px30-power.h>
23 #include <dt-bindings/power/rk3036-power.h>
24 #include <dt-bindings/power/rk3128-power.h>
25 #include <dt-bindings/power/rk3228-power.h>
26 #include <dt-bindings/power/rk3288-power.h>
27 #include <dt-bindings/power/rk3328-power.h>
28 #include <dt-bindings/power/rk3366-power.h>
29 #include <dt-bindings/power/rk3368-power.h>
30 #include <dt-bindings/power/rk3399-power.h>
31
32 struct rockchip_domain_info {
33         int pwr_mask;
34         int status_mask;
35         int req_mask;
36         int idle_mask;
37         int ack_mask;
38         bool active_wakeup;
39         int pwr_w_mask;
40         int req_w_mask;
41 };
42
43 struct rockchip_pmu_info {
44         u32 pwr_offset;
45         u32 status_offset;
46         u32 req_offset;
47         u32 idle_offset;
48         u32 ack_offset;
49
50         u32 core_pwrcnt_offset;
51         u32 gpu_pwrcnt_offset;
52
53         unsigned int core_power_transition_time;
54         unsigned int gpu_power_transition_time;
55
56         int num_domains;
57         const struct rockchip_domain_info *domain_info;
58 };
59
60 #define MAX_QOS_REGS_NUM        5
61 #define QOS_PRIORITY            0x08
62 #define QOS_MODE                0x0c
63 #define QOS_BANDWIDTH           0x10
64 #define QOS_SATURATION          0x14
65 #define QOS_EXTCONTROL          0x18
66
67 struct rockchip_pm_domain {
68         struct generic_pm_domain genpd;
69         const struct rockchip_domain_info *info;
70         struct rockchip_pmu *pmu;
71         int num_qos;
72         struct regmap **qos_regmap;
73         u32 *qos_save_regs[MAX_QOS_REGS_NUM];
74         int num_clks;
75         struct clk_bulk_data *clks;
76 };
77
78 struct rockchip_pmu {
79         struct device *dev;
80         struct regmap *regmap;
81         const struct rockchip_pmu_info *info;
82         struct mutex mutex; /* mutex lock for pmu */
83         struct genpd_onecell_data genpd_data;
84         struct generic_pm_domain *domains[];
85 };
86
87 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
88
89 #define DOMAIN(pwr, status, req, idle, ack, wakeup)     \
90 {                                               \
91         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
92         .status_mask = (status >= 0) ? BIT(status) : 0, \
93         .req_mask = (req >= 0) ? BIT(req) : 0,          \
94         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
95         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
96         .active_wakeup = wakeup,                        \
97 }
98
99 #define DOMAIN_M(pwr, status, req, idle, ack, wakeup)   \
100 {                                                       \
101         .pwr_w_mask = (pwr >= 0) ? BIT(pwr + 16) : 0,   \
102         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
103         .status_mask = (status >= 0) ? BIT(status) : 0, \
104         .req_w_mask = (req >= 0) ?  BIT(req + 16) : 0,  \
105         .req_mask = (req >= 0) ?  BIT(req) : 0,         \
106         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
107         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
108         .active_wakeup = wakeup,                        \
109 }
110
111 #define DOMAIN_RK3036(req, ack, idle, wakeup)           \
112 {                                                       \
113         .req_mask = (req >= 0) ? BIT(req) : 0,          \
114         .req_w_mask = (req >= 0) ?  BIT(req + 16) : 0,  \
115         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
116         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
117         .active_wakeup = wakeup,                        \
118 }
119
120 #define DOMAIN_PX30(pwr, status, req, wakeup)           \
121         DOMAIN_M(pwr, status, req, (req) + 16, req, wakeup)
122
123 #define DOMAIN_RK3288(pwr, status, req, wakeup)         \
124         DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
125
126 #define DOMAIN_RK3328(pwr, status, req, wakeup)         \
127         DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup)
128
129 #define DOMAIN_RK3368(pwr, status, req, wakeup)         \
130         DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
131
132 #define DOMAIN_RK3399(pwr, status, req, wakeup)         \
133         DOMAIN(pwr, status, req, req, req, wakeup)
134
135 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
136 {
137         struct rockchip_pmu *pmu = pd->pmu;
138         const struct rockchip_domain_info *pd_info = pd->info;
139         unsigned int val;
140
141         regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
142         return (val & pd_info->idle_mask) == pd_info->idle_mask;
143 }
144
145 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
146 {
147         unsigned int val;
148
149         regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
150         return val;
151 }
152
153 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
154                                          bool idle)
155 {
156         const struct rockchip_domain_info *pd_info = pd->info;
157         struct generic_pm_domain *genpd = &pd->genpd;
158         struct rockchip_pmu *pmu = pd->pmu;
159         unsigned int target_ack;
160         unsigned int val;
161         bool is_idle;
162         int ret;
163
164         if (pd_info->req_mask == 0)
165                 return 0;
166         else if (pd_info->req_w_mask)
167                 regmap_write(pmu->regmap, pmu->info->req_offset,
168                              idle ? (pd_info->req_mask | pd_info->req_w_mask) :
169                              pd_info->req_w_mask);
170         else
171                 regmap_update_bits(pmu->regmap, pmu->info->req_offset,
172                                    pd_info->req_mask, idle ? -1U : 0);
173
174         dsb(sy);
175
176         /* Wait util idle_ack = 1 */
177         target_ack = idle ? pd_info->ack_mask : 0;
178         ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
179                                         (val & pd_info->ack_mask) == target_ack,
180                                         0, 10000);
181         if (ret) {
182                 dev_err(pmu->dev,
183                         "failed to get ack on domain '%s', val=0x%x\n",
184                         genpd->name, val);
185                 return ret;
186         }
187
188         ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
189                                         is_idle, is_idle == idle, 0, 10000);
190         if (ret) {
191                 dev_err(pmu->dev,
192                         "failed to set idle on domain '%s', val=%d\n",
193                         genpd->name, is_idle);
194                 return ret;
195         }
196
197         return 0;
198 }
199
200 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
201 {
202         int i;
203
204         for (i = 0; i < pd->num_qos; i++) {
205                 regmap_read(pd->qos_regmap[i],
206                             QOS_PRIORITY,
207                             &pd->qos_save_regs[0][i]);
208                 regmap_read(pd->qos_regmap[i],
209                             QOS_MODE,
210                             &pd->qos_save_regs[1][i]);
211                 regmap_read(pd->qos_regmap[i],
212                             QOS_BANDWIDTH,
213                             &pd->qos_save_regs[2][i]);
214                 regmap_read(pd->qos_regmap[i],
215                             QOS_SATURATION,
216                             &pd->qos_save_regs[3][i]);
217                 regmap_read(pd->qos_regmap[i],
218                             QOS_EXTCONTROL,
219                             &pd->qos_save_regs[4][i]);
220         }
221         return 0;
222 }
223
224 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
225 {
226         int i;
227
228         for (i = 0; i < pd->num_qos; i++) {
229                 regmap_write(pd->qos_regmap[i],
230                              QOS_PRIORITY,
231                              pd->qos_save_regs[0][i]);
232                 regmap_write(pd->qos_regmap[i],
233                              QOS_MODE,
234                              pd->qos_save_regs[1][i]);
235                 regmap_write(pd->qos_regmap[i],
236                              QOS_BANDWIDTH,
237                              pd->qos_save_regs[2][i]);
238                 regmap_write(pd->qos_regmap[i],
239                              QOS_SATURATION,
240                              pd->qos_save_regs[3][i]);
241                 regmap_write(pd->qos_regmap[i],
242                              QOS_EXTCONTROL,
243                              pd->qos_save_regs[4][i]);
244         }
245
246         return 0;
247 }
248
249 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
250 {
251         struct rockchip_pmu *pmu = pd->pmu;
252         unsigned int val;
253
254         /* check idle status for idle-only domains */
255         if (pd->info->status_mask == 0)
256                 return !rockchip_pmu_domain_is_idle(pd);
257
258         regmap_read(pmu->regmap, pmu->info->status_offset, &val);
259
260         /* 1'b0: power on, 1'b1: power off */
261         return !(val & pd->info->status_mask);
262 }
263
264 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
265                                              bool on)
266 {
267         struct rockchip_pmu *pmu = pd->pmu;
268         struct generic_pm_domain *genpd = &pd->genpd;
269         bool is_on;
270
271         if (pd->info->pwr_mask == 0)
272                 return;
273         else if (pd->info->pwr_w_mask)
274                 regmap_write(pmu->regmap, pmu->info->pwr_offset,
275                              on ? pd->info->pwr_w_mask :
276                              (pd->info->pwr_mask | pd->info->pwr_w_mask));
277         else
278                 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
279                                    pd->info->pwr_mask, on ? 0 : -1U);
280
281         dsb(sy);
282
283         if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
284                                       is_on == on, 0, 10000)) {
285                 dev_err(pmu->dev,
286                         "failed to set domain '%s', val=%d\n",
287                         genpd->name, is_on);
288                 return;
289         }
290 }
291
292 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
293 {
294         struct rockchip_pmu *pmu = pd->pmu;
295         int ret;
296
297         mutex_lock(&pmu->mutex);
298
299         if (rockchip_pmu_domain_is_on(pd) != power_on) {
300                 ret = clk_bulk_enable(pd->num_clks, pd->clks);
301                 if (ret < 0) {
302                         dev_err(pmu->dev, "failed to enable clocks\n");
303                         mutex_unlock(&pmu->mutex);
304                         return ret;
305                 }
306
307                 if (!power_on) {
308                         rockchip_pmu_save_qos(pd);
309
310                         /* if powering down, idle request to NIU first */
311                         rockchip_pmu_set_idle_request(pd, true);
312                 }
313
314                 rockchip_do_pmu_set_power_domain(pd, power_on);
315
316                 if (power_on) {
317                         /* if powering up, leave idle mode */
318                         rockchip_pmu_set_idle_request(pd, false);
319
320                         rockchip_pmu_restore_qos(pd);
321                 }
322
323                 clk_bulk_disable(pd->num_clks, pd->clks);
324         }
325
326         mutex_unlock(&pmu->mutex);
327         return 0;
328 }
329
330 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
331 {
332         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
333
334         return rockchip_pd_power(pd, true);
335 }
336
337 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
338 {
339         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
340
341         return rockchip_pd_power(pd, false);
342 }
343
344 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
345                                   struct device *dev)
346 {
347         struct clk *clk;
348         int i;
349         int error;
350
351         dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
352
353         error = pm_clk_create(dev);
354         if (error) {
355                 dev_err(dev, "pm_clk_create failed %d\n", error);
356                 return error;
357         }
358
359         i = 0;
360         while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
361                 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
362                 error = pm_clk_add_clk(dev, clk);
363                 if (error) {
364                         dev_err(dev, "pm_clk_add_clk failed %d\n", error);
365                         clk_put(clk);
366                         pm_clk_destroy(dev);
367                         return error;
368                 }
369         }
370
371         return 0;
372 }
373
374 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
375                                    struct device *dev)
376 {
377         dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
378
379         pm_clk_destroy(dev);
380 }
381
382 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
383                                       struct device_node *node)
384 {
385         const struct rockchip_domain_info *pd_info;
386         struct rockchip_pm_domain *pd;
387         struct device_node *qos_node;
388         int i, j;
389         u32 id;
390         int error;
391
392         error = of_property_read_u32(node, "reg", &id);
393         if (error) {
394                 dev_err(pmu->dev,
395                         "%s: failed to retrieve domain id (reg): %d\n",
396                         node->name, error);
397                 return -EINVAL;
398         }
399
400         if (id >= pmu->info->num_domains) {
401                 dev_err(pmu->dev, "%s: invalid domain id %d\n",
402                         node->name, id);
403                 return -EINVAL;
404         }
405
406         pd_info = &pmu->info->domain_info[id];
407         if (!pd_info) {
408                 dev_err(pmu->dev, "%s: undefined domain id %d\n",
409                         node->name, id);
410                 return -EINVAL;
411         }
412
413         pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
414         if (!pd)
415                 return -ENOMEM;
416
417         pd->info = pd_info;
418         pd->pmu = pmu;
419
420         pd->num_clks = of_clk_get_parent_count(node);
421         if (pd->num_clks > 0) {
422                 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
423                                         sizeof(*pd->clks), GFP_KERNEL);
424                 if (!pd->clks)
425                         return -ENOMEM;
426         } else {
427                 dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n",
428                         node->name, pd->num_clks);
429                 pd->num_clks = 0;
430         }
431
432         for (i = 0; i < pd->num_clks; i++) {
433                 pd->clks[i].clk = of_clk_get(node, i);
434                 if (IS_ERR(pd->clks[i].clk)) {
435                         error = PTR_ERR(pd->clks[i].clk);
436                         dev_err(pmu->dev,
437                                 "%s: failed to get clk at index %d: %d\n",
438                                 node->name, i, error);
439                         return error;
440                 }
441         }
442
443         error = clk_bulk_prepare(pd->num_clks, pd->clks);
444         if (error)
445                 goto err_put_clocks;
446
447         pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
448                                                  NULL);
449
450         if (pd->num_qos > 0) {
451                 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
452                                               sizeof(*pd->qos_regmap),
453                                               GFP_KERNEL);
454                 if (!pd->qos_regmap) {
455                         error = -ENOMEM;
456                         goto err_unprepare_clocks;
457                 }
458
459                 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
460                         pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
461                                                             pd->num_qos,
462                                                             sizeof(u32),
463                                                             GFP_KERNEL);
464                         if (!pd->qos_save_regs[j]) {
465                                 error = -ENOMEM;
466                                 goto err_unprepare_clocks;
467                         }
468                 }
469
470                 for (j = 0; j < pd->num_qos; j++) {
471                         qos_node = of_parse_phandle(node, "pm_qos", j);
472                         if (!qos_node) {
473                                 error = -ENODEV;
474                                 goto err_unprepare_clocks;
475                         }
476                         pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
477                         if (IS_ERR(pd->qos_regmap[j])) {
478                                 error = -ENODEV;
479                                 of_node_put(qos_node);
480                                 goto err_unprepare_clocks;
481                         }
482                         of_node_put(qos_node);
483                 }
484         }
485
486         error = rockchip_pd_power(pd, true);
487         if (error) {
488                 dev_err(pmu->dev,
489                         "failed to power on domain '%s': %d\n",
490                         node->name, error);
491                 goto err_unprepare_clocks;
492         }
493
494         pd->genpd.name = node->name;
495         pd->genpd.power_off = rockchip_pd_power_off;
496         pd->genpd.power_on = rockchip_pd_power_on;
497         pd->genpd.attach_dev = rockchip_pd_attach_dev;
498         pd->genpd.detach_dev = rockchip_pd_detach_dev;
499         pd->genpd.flags = GENPD_FLAG_PM_CLK;
500         if (pd_info->active_wakeup)
501                 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
502         pm_genpd_init(&pd->genpd, NULL, false);
503
504         pmu->genpd_data.domains[id] = &pd->genpd;
505         return 0;
506
507 err_unprepare_clocks:
508         clk_bulk_unprepare(pd->num_clks, pd->clks);
509 err_put_clocks:
510         clk_bulk_put(pd->num_clks, pd->clks);
511         return error;
512 }
513
514 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
515 {
516         int ret;
517
518         /*
519          * We're in the error cleanup already, so we only complain,
520          * but won't emit another error on top of the original one.
521          */
522         ret = pm_genpd_remove(&pd->genpd);
523         if (ret < 0)
524                 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
525                         pd->genpd.name, ret);
526
527         clk_bulk_unprepare(pd->num_clks, pd->clks);
528         clk_bulk_put(pd->num_clks, pd->clks);
529
530         /* protect the zeroing of pm->num_clks */
531         mutex_lock(&pd->pmu->mutex);
532         pd->num_clks = 0;
533         mutex_unlock(&pd->pmu->mutex);
534
535         /* devm will free our memory */
536 }
537
538 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
539 {
540         struct generic_pm_domain *genpd;
541         struct rockchip_pm_domain *pd;
542         int i;
543
544         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
545                 genpd = pmu->genpd_data.domains[i];
546                 if (genpd) {
547                         pd = to_rockchip_pd(genpd);
548                         rockchip_pm_remove_one_domain(pd);
549                 }
550         }
551
552         /* devm will free our memory */
553 }
554
555 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
556                                       u32 domain_reg_offset,
557                                       unsigned int count)
558 {
559         /* First configure domain power down transition count ... */
560         regmap_write(pmu->regmap, domain_reg_offset, count);
561         /* ... and then power up count. */
562         regmap_write(pmu->regmap, domain_reg_offset + 4, count);
563 }
564
565 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
566                                      struct device_node *parent)
567 {
568         struct device_node *np;
569         struct generic_pm_domain *child_domain, *parent_domain;
570         int error;
571
572         for_each_child_of_node(parent, np) {
573                 u32 idx;
574
575                 error = of_property_read_u32(parent, "reg", &idx);
576                 if (error) {
577                         dev_err(pmu->dev,
578                                 "%s: failed to retrieve domain id (reg): %d\n",
579                                 parent->name, error);
580                         goto err_out;
581                 }
582                 parent_domain = pmu->genpd_data.domains[idx];
583
584                 error = rockchip_pm_add_one_domain(pmu, np);
585                 if (error) {
586                         dev_err(pmu->dev, "failed to handle node %s: %d\n",
587                                 np->name, error);
588                         goto err_out;
589                 }
590
591                 error = of_property_read_u32(np, "reg", &idx);
592                 if (error) {
593                         dev_err(pmu->dev,
594                                 "%s: failed to retrieve domain id (reg): %d\n",
595                                 np->name, error);
596                         goto err_out;
597                 }
598                 child_domain = pmu->genpd_data.domains[idx];
599
600                 error = pm_genpd_add_subdomain(parent_domain, child_domain);
601                 if (error) {
602                         dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
603                                 parent_domain->name, child_domain->name, error);
604                         goto err_out;
605                 } else {
606                         dev_dbg(pmu->dev, "%s add subdomain: %s\n",
607                                 parent_domain->name, child_domain->name);
608                 }
609
610                 rockchip_pm_add_subdomain(pmu, np);
611         }
612
613         return 0;
614
615 err_out:
616         of_node_put(np);
617         return error;
618 }
619
620 static int rockchip_pm_domain_probe(struct platform_device *pdev)
621 {
622         struct device *dev = &pdev->dev;
623         struct device_node *np = dev->of_node;
624         struct device_node *node;
625         struct device *parent;
626         struct rockchip_pmu *pmu;
627         const struct of_device_id *match;
628         const struct rockchip_pmu_info *pmu_info;
629         int error;
630
631         if (!np) {
632                 dev_err(dev, "device tree node not found\n");
633                 return -ENODEV;
634         }
635
636         match = of_match_device(dev->driver->of_match_table, dev);
637         if (!match || !match->data) {
638                 dev_err(dev, "missing pmu data\n");
639                 return -EINVAL;
640         }
641
642         pmu_info = match->data;
643
644         pmu = devm_kzalloc(dev,
645                            struct_size(pmu, domains, pmu_info->num_domains),
646                            GFP_KERNEL);
647         if (!pmu)
648                 return -ENOMEM;
649
650         pmu->dev = &pdev->dev;
651         mutex_init(&pmu->mutex);
652
653         pmu->info = pmu_info;
654
655         pmu->genpd_data.domains = pmu->domains;
656         pmu->genpd_data.num_domains = pmu_info->num_domains;
657
658         parent = dev->parent;
659         if (!parent) {
660                 dev_err(dev, "no parent for syscon devices\n");
661                 return -ENODEV;
662         }
663
664         pmu->regmap = syscon_node_to_regmap(parent->of_node);
665         if (IS_ERR(pmu->regmap)) {
666                 dev_err(dev, "no regmap available\n");
667                 return PTR_ERR(pmu->regmap);
668         }
669
670         /*
671          * Configure power up and down transition delays for CORE
672          * and GPU domains.
673          */
674         if (pmu_info->core_power_transition_time)
675                 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
676                                         pmu_info->core_power_transition_time);
677         if (pmu_info->gpu_pwrcnt_offset)
678                 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
679                                         pmu_info->gpu_power_transition_time);
680
681         error = -ENODEV;
682
683         for_each_available_child_of_node(np, node) {
684                 error = rockchip_pm_add_one_domain(pmu, node);
685                 if (error) {
686                         dev_err(dev, "failed to handle node %s: %d\n",
687                                 node->name, error);
688                         of_node_put(node);
689                         goto err_out;
690                 }
691
692                 error = rockchip_pm_add_subdomain(pmu, node);
693                 if (error < 0) {
694                         dev_err(dev, "failed to handle subdomain node %s: %d\n",
695                                 node->name, error);
696                         of_node_put(node);
697                         goto err_out;
698                 }
699         }
700
701         if (error) {
702                 dev_dbg(dev, "no power domains defined\n");
703                 goto err_out;
704         }
705
706         error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
707         if (error) {
708                 dev_err(dev, "failed to add provider: %d\n", error);
709                 goto err_out;
710         }
711
712         return 0;
713
714 err_out:
715         rockchip_pm_domain_cleanup(pmu);
716         return error;
717 }
718
719 static const struct rockchip_domain_info px30_pm_domains[] = {
720         [PX30_PD_USB]           = DOMAIN_PX30(5, 5, 10, false),
721         [PX30_PD_SDCARD]        = DOMAIN_PX30(8, 8, 9, false),
722         [PX30_PD_GMAC]          = DOMAIN_PX30(10, 10, 6, false),
723         [PX30_PD_MMC_NAND]      = DOMAIN_PX30(11, 11, 5, false),
724         [PX30_PD_VPU]           = DOMAIN_PX30(12, 12, 14, false),
725         [PX30_PD_VO]            = DOMAIN_PX30(13, 13, 7, false),
726         [PX30_PD_VI]            = DOMAIN_PX30(14, 14, 8, false),
727         [PX30_PD_GPU]           = DOMAIN_PX30(15, 15, 2, false),
728 };
729
730 static const struct rockchip_domain_info rk3036_pm_domains[] = {
731         [RK3036_PD_MSCH]        = DOMAIN_RK3036(14, 23, 30, true),
732         [RK3036_PD_CORE]        = DOMAIN_RK3036(13, 17, 24, false),
733         [RK3036_PD_PERI]        = DOMAIN_RK3036(12, 18, 25, false),
734         [RK3036_PD_VIO]         = DOMAIN_RK3036(11, 19, 26, false),
735         [RK3036_PD_VPU]         = DOMAIN_RK3036(10, 20, 27, false),
736         [RK3036_PD_GPU]         = DOMAIN_RK3036(9, 21, 28, false),
737         [RK3036_PD_SYS]         = DOMAIN_RK3036(8, 22, 29, false),
738 };
739
740 static const struct rockchip_domain_info rk3128_pm_domains[] = {
741         [RK3128_PD_CORE]        = DOMAIN_RK3288(0, 0, 4, false),
742         [RK3128_PD_MSCH]        = DOMAIN_RK3288(-1, -1, 6, true),
743         [RK3128_PD_VIO]         = DOMAIN_RK3288(3, 3, 2, false),
744         [RK3128_PD_VIDEO]       = DOMAIN_RK3288(2, 2, 1, false),
745         [RK3128_PD_GPU]         = DOMAIN_RK3288(1, 1, 3, false),
746 };
747
748 static const struct rockchip_domain_info rk3228_pm_domains[] = {
749         [RK3228_PD_CORE]        = DOMAIN_RK3036(0, 0, 16, true),
750         [RK3228_PD_MSCH]        = DOMAIN_RK3036(1, 1, 17, true),
751         [RK3228_PD_BUS]         = DOMAIN_RK3036(2, 2, 18, true),
752         [RK3228_PD_SYS]         = DOMAIN_RK3036(3, 3, 19, true),
753         [RK3228_PD_VIO]         = DOMAIN_RK3036(4, 4, 20, false),
754         [RK3228_PD_VOP]         = DOMAIN_RK3036(5, 5, 21, false),
755         [RK3228_PD_VPU]         = DOMAIN_RK3036(6, 6, 22, false),
756         [RK3228_PD_RKVDEC]      = DOMAIN_RK3036(7, 7, 23, false),
757         [RK3228_PD_GPU]         = DOMAIN_RK3036(8, 8, 24, false),
758         [RK3228_PD_PERI]        = DOMAIN_RK3036(9, 9, 25, true),
759         [RK3228_PD_GMAC]        = DOMAIN_RK3036(10, 10, 26, false),
760 };
761
762 static const struct rockchip_domain_info rk3288_pm_domains[] = {
763         [RK3288_PD_VIO]         = DOMAIN_RK3288(7, 7, 4, false),
764         [RK3288_PD_HEVC]        = DOMAIN_RK3288(14, 10, 9, false),
765         [RK3288_PD_VIDEO]       = DOMAIN_RK3288(8, 8, 3, false),
766         [RK3288_PD_GPU]         = DOMAIN_RK3288(9, 9, 2, false),
767 };
768
769 static const struct rockchip_domain_info rk3328_pm_domains[] = {
770         [RK3328_PD_CORE]        = DOMAIN_RK3328(-1, 0, 0, false),
771         [RK3328_PD_GPU]         = DOMAIN_RK3328(-1, 1, 1, false),
772         [RK3328_PD_BUS]         = DOMAIN_RK3328(-1, 2, 2, true),
773         [RK3328_PD_MSCH]        = DOMAIN_RK3328(-1, 3, 3, true),
774         [RK3328_PD_PERI]        = DOMAIN_RK3328(-1, 4, 4, true),
775         [RK3328_PD_VIDEO]       = DOMAIN_RK3328(-1, 5, 5, false),
776         [RK3328_PD_HEVC]        = DOMAIN_RK3328(-1, 6, 6, false),
777         [RK3328_PD_VIO]         = DOMAIN_RK3328(-1, 8, 8, false),
778         [RK3328_PD_VPU]         = DOMAIN_RK3328(-1, 9, 9, false),
779 };
780
781 static const struct rockchip_domain_info rk3366_pm_domains[] = {
782         [RK3366_PD_PERI]        = DOMAIN_RK3368(10, 10, 6, true),
783         [RK3366_PD_VIO]         = DOMAIN_RK3368(14, 14, 8, false),
784         [RK3366_PD_VIDEO]       = DOMAIN_RK3368(13, 13, 7, false),
785         [RK3366_PD_RKVDEC]      = DOMAIN_RK3368(11, 11, 7, false),
786         [RK3366_PD_WIFIBT]      = DOMAIN_RK3368(8, 8, 9, false),
787         [RK3366_PD_VPU]         = DOMAIN_RK3368(12, 12, 7, false),
788         [RK3366_PD_GPU]         = DOMAIN_RK3368(15, 15, 2, false),
789 };
790
791 static const struct rockchip_domain_info rk3368_pm_domains[] = {
792         [RK3368_PD_PERI]        = DOMAIN_RK3368(13, 12, 6, true),
793         [RK3368_PD_VIO]         = DOMAIN_RK3368(15, 14, 8, false),
794         [RK3368_PD_VIDEO]       = DOMAIN_RK3368(14, 13, 7, false),
795         [RK3368_PD_GPU_0]       = DOMAIN_RK3368(16, 15, 2, false),
796         [RK3368_PD_GPU_1]       = DOMAIN_RK3368(17, 16, 2, false),
797 };
798
799 static const struct rockchip_domain_info rk3399_pm_domains[] = {
800         [RK3399_PD_TCPD0]       = DOMAIN_RK3399(8, 8, -1, false),
801         [RK3399_PD_TCPD1]       = DOMAIN_RK3399(9, 9, -1, false),
802         [RK3399_PD_CCI]         = DOMAIN_RK3399(10, 10, -1, true),
803         [RK3399_PD_CCI0]        = DOMAIN_RK3399(-1, -1, 15, true),
804         [RK3399_PD_CCI1]        = DOMAIN_RK3399(-1, -1, 16, true),
805         [RK3399_PD_PERILP]      = DOMAIN_RK3399(11, 11, 1, true),
806         [RK3399_PD_PERIHP]      = DOMAIN_RK3399(12, 12, 2, true),
807         [RK3399_PD_CENTER]      = DOMAIN_RK3399(13, 13, 14, true),
808         [RK3399_PD_VIO]         = DOMAIN_RK3399(14, 14, 17, false),
809         [RK3399_PD_GPU]         = DOMAIN_RK3399(15, 15, 0, false),
810         [RK3399_PD_VCODEC]      = DOMAIN_RK3399(16, 16, 3, false),
811         [RK3399_PD_VDU]         = DOMAIN_RK3399(17, 17, 4, false),
812         [RK3399_PD_RGA]         = DOMAIN_RK3399(18, 18, 5, false),
813         [RK3399_PD_IEP]         = DOMAIN_RK3399(19, 19, 6, false),
814         [RK3399_PD_VO]          = DOMAIN_RK3399(20, 20, -1, false),
815         [RK3399_PD_VOPB]        = DOMAIN_RK3399(-1, -1, 7, false),
816         [RK3399_PD_VOPL]        = DOMAIN_RK3399(-1, -1, 8, false),
817         [RK3399_PD_ISP0]        = DOMAIN_RK3399(22, 22, 9, false),
818         [RK3399_PD_ISP1]        = DOMAIN_RK3399(23, 23, 10, false),
819         [RK3399_PD_HDCP]        = DOMAIN_RK3399(24, 24, 11, false),
820         [RK3399_PD_GMAC]        = DOMAIN_RK3399(25, 25, 23, true),
821         [RK3399_PD_EMMC]        = DOMAIN_RK3399(26, 26, 24, true),
822         [RK3399_PD_USB3]        = DOMAIN_RK3399(27, 27, 12, true),
823         [RK3399_PD_EDP]         = DOMAIN_RK3399(28, 28, 22, false),
824         [RK3399_PD_GIC]         = DOMAIN_RK3399(29, 29, 27, true),
825         [RK3399_PD_SD]          = DOMAIN_RK3399(30, 30, 28, true),
826         [RK3399_PD_SDIOAUDIO]   = DOMAIN_RK3399(31, 31, 29, true),
827 };
828
829 static const struct rockchip_pmu_info px30_pmu = {
830         .pwr_offset = 0x18,
831         .status_offset = 0x20,
832         .req_offset = 0x64,
833         .idle_offset = 0x6c,
834         .ack_offset = 0x6c,
835
836         .num_domains = ARRAY_SIZE(px30_pm_domains),
837         .domain_info = px30_pm_domains,
838 };
839
840 static const struct rockchip_pmu_info rk3036_pmu = {
841         .req_offset = 0x148,
842         .idle_offset = 0x14c,
843         .ack_offset = 0x14c,
844
845         .num_domains = ARRAY_SIZE(rk3036_pm_domains),
846         .domain_info = rk3036_pm_domains,
847 };
848
849 static const struct rockchip_pmu_info rk3128_pmu = {
850         .pwr_offset = 0x04,
851         .status_offset = 0x08,
852         .req_offset = 0x0c,
853         .idle_offset = 0x10,
854         .ack_offset = 0x10,
855
856         .num_domains = ARRAY_SIZE(rk3128_pm_domains),
857         .domain_info = rk3128_pm_domains,
858 };
859
860 static const struct rockchip_pmu_info rk3228_pmu = {
861         .req_offset = 0x40c,
862         .idle_offset = 0x488,
863         .ack_offset = 0x488,
864
865         .num_domains = ARRAY_SIZE(rk3228_pm_domains),
866         .domain_info = rk3228_pm_domains,
867 };
868
869 static const struct rockchip_pmu_info rk3288_pmu = {
870         .pwr_offset = 0x08,
871         .status_offset = 0x0c,
872         .req_offset = 0x10,
873         .idle_offset = 0x14,
874         .ack_offset = 0x14,
875
876         .core_pwrcnt_offset = 0x34,
877         .gpu_pwrcnt_offset = 0x3c,
878
879         .core_power_transition_time = 24, /* 1us */
880         .gpu_power_transition_time = 24, /* 1us */
881
882         .num_domains = ARRAY_SIZE(rk3288_pm_domains),
883         .domain_info = rk3288_pm_domains,
884 };
885
886 static const struct rockchip_pmu_info rk3328_pmu = {
887         .req_offset = 0x414,
888         .idle_offset = 0x484,
889         .ack_offset = 0x484,
890
891         .num_domains = ARRAY_SIZE(rk3328_pm_domains),
892         .domain_info = rk3328_pm_domains,
893 };
894
895 static const struct rockchip_pmu_info rk3366_pmu = {
896         .pwr_offset = 0x0c,
897         .status_offset = 0x10,
898         .req_offset = 0x3c,
899         .idle_offset = 0x40,
900         .ack_offset = 0x40,
901
902         .core_pwrcnt_offset = 0x48,
903         .gpu_pwrcnt_offset = 0x50,
904
905         .core_power_transition_time = 24,
906         .gpu_power_transition_time = 24,
907
908         .num_domains = ARRAY_SIZE(rk3366_pm_domains),
909         .domain_info = rk3366_pm_domains,
910 };
911
912 static const struct rockchip_pmu_info rk3368_pmu = {
913         .pwr_offset = 0x0c,
914         .status_offset = 0x10,
915         .req_offset = 0x3c,
916         .idle_offset = 0x40,
917         .ack_offset = 0x40,
918
919         .core_pwrcnt_offset = 0x48,
920         .gpu_pwrcnt_offset = 0x50,
921
922         .core_power_transition_time = 24,
923         .gpu_power_transition_time = 24,
924
925         .num_domains = ARRAY_SIZE(rk3368_pm_domains),
926         .domain_info = rk3368_pm_domains,
927 };
928
929 static const struct rockchip_pmu_info rk3399_pmu = {
930         .pwr_offset = 0x14,
931         .status_offset = 0x18,
932         .req_offset = 0x60,
933         .idle_offset = 0x64,
934         .ack_offset = 0x68,
935
936         /* ARM Trusted Firmware manages power transition times */
937
938         .num_domains = ARRAY_SIZE(rk3399_pm_domains),
939         .domain_info = rk3399_pm_domains,
940 };
941
942 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
943         {
944                 .compatible = "rockchip,px30-power-controller",
945                 .data = (void *)&px30_pmu,
946         },
947         {
948                 .compatible = "rockchip,rk3036-power-controller",
949                 .data = (void *)&rk3036_pmu,
950         },
951         {
952                 .compatible = "rockchip,rk3128-power-controller",
953                 .data = (void *)&rk3128_pmu,
954         },
955         {
956                 .compatible = "rockchip,rk3228-power-controller",
957                 .data = (void *)&rk3228_pmu,
958         },
959         {
960                 .compatible = "rockchip,rk3288-power-controller",
961                 .data = (void *)&rk3288_pmu,
962         },
963         {
964                 .compatible = "rockchip,rk3328-power-controller",
965                 .data = (void *)&rk3328_pmu,
966         },
967         {
968                 .compatible = "rockchip,rk3366-power-controller",
969                 .data = (void *)&rk3366_pmu,
970         },
971         {
972                 .compatible = "rockchip,rk3368-power-controller",
973                 .data = (void *)&rk3368_pmu,
974         },
975         {
976                 .compatible = "rockchip,rk3399-power-controller",
977                 .data = (void *)&rk3399_pmu,
978         },
979         { /* sentinel */ },
980 };
981
982 static struct platform_driver rockchip_pm_domain_driver = {
983         .probe = rockchip_pm_domain_probe,
984         .driver = {
985                 .name   = "rockchip-pm-domain",
986                 .of_match_table = rockchip_pm_domain_dt_match,
987                 /*
988                  * We can't forcibly eject devices form power domain,
989                  * so we can't really remove power domains once they
990                  * were added.
991                  */
992                 .suppress_bind_attrs = true,
993         },
994 };
995
996 static int __init rockchip_pm_domain_drv_register(void)
997 {
998         return platform_driver_register(&rockchip_pm_domain_driver);
999 }
1000 postcore_initcall(rockchip_pm_domain_drv_register);