ARM: OMAP1: DMA: Moving OMAP1 DMA channel definitions to mach-omap1
[muen/linux.git] / drivers / usb / gadget / omap_udc.c
1 /*
2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3  *
4  * Copyright (C) 2004 Texas Instruments, Inc.
5  * Copyright (C) 2004-2005 David Brownell
6  *
7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  */
14
15 #undef  DEBUG
16 #undef  VERBOSE
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/timer.h>
27 #include <linux/list.h>
28 #include <linux/interrupt.h>
29 #include <linux/proc_fs.h>
30 #include <linux/mm.h>
31 #include <linux/moduleparam.h>
32 #include <linux/platform_device.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/otg.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/prefetch.h>
40 #include <linux/io.h>
41
42 #include <asm/byteorder.h>
43 #include <asm/irq.h>
44 #include <asm/unaligned.h>
45 #include <asm/mach-types.h>
46
47 #include <plat/dma.h>
48
49 #include <mach/usb.h>
50
51 #include "omap_udc.h"
52
53 #undef  USB_TRACE
54
55 /* bulk DMA seems to be behaving for both IN and OUT */
56 #define USE_DMA
57
58 /* ISO too */
59 #define USE_ISO
60
61 #define DRIVER_DESC     "OMAP UDC driver"
62 #define DRIVER_VERSION  "4 October 2004"
63
64 #define OMAP_DMA_USB_W2FC_TX0           29
65
66 /*
67  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
68  * D+ pullup to allow enumeration.  That's too early for the gadget
69  * framework to use from usb_endpoint_enable(), which happens after
70  * enumeration as part of activating an interface.  (But if we add an
71  * optional new "UDC not yet running" state to the gadget driver model,
72  * even just during driver binding, the endpoint autoconfig logic is the
73  * natural spot to manufacture new endpoints.)
74  *
75  * So instead of using endpoint enable calls to control the hardware setup,
76  * this driver defines a "fifo mode" parameter.  It's used during driver
77  * initialization to choose among a set of pre-defined endpoint configs.
78  * See omap_udc_setup() for available modes, or to add others.  That code
79  * lives in an init section, so use this driver as a module if you need
80  * to change the fifo mode after the kernel boots.
81  *
82  * Gadget drivers normally ignore endpoints they don't care about, and
83  * won't include them in configuration descriptors.  That means only
84  * misbehaving hosts would even notice they exist.
85  */
86 #ifdef  USE_ISO
87 static unsigned fifo_mode = 3;
88 #else
89 static unsigned fifo_mode;
90 #endif
91
92 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
93  * boot parameter "omap_udc:fifo_mode=42"
94  */
95 module_param(fifo_mode, uint, 0);
96 MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
97
98 #ifdef  USE_DMA
99 static bool use_dma = 1;
100
101 /* "modprobe omap_udc use_dma=y", or else as a kernel
102  * boot parameter "omap_udc:use_dma=y"
103  */
104 module_param(use_dma, bool, 0);
105 MODULE_PARM_DESC(use_dma, "enable/disable DMA");
106 #else   /* !USE_DMA */
107
108 /* save a bit of code */
109 #define use_dma         0
110 #endif  /* !USE_DMA */
111
112
113 static const char driver_name[] = "omap_udc";
114 static const char driver_desc[] = DRIVER_DESC;
115
116 /*-------------------------------------------------------------------------*/
117
118 /* there's a notion of "current endpoint" for modifying endpoint
119  * state, and PIO access to its FIFO.
120  */
121
122 static void use_ep(struct omap_ep *ep, u16 select)
123 {
124         u16     num = ep->bEndpointAddress & 0x0f;
125
126         if (ep->bEndpointAddress & USB_DIR_IN)
127                 num |= UDC_EP_DIR;
128         omap_writew(num | select, UDC_EP_NUM);
129         /* when select, MUST deselect later !! */
130 }
131
132 static inline void deselect_ep(void)
133 {
134         u16 w;
135
136         w = omap_readw(UDC_EP_NUM);
137         w &= ~UDC_EP_SEL;
138         omap_writew(w, UDC_EP_NUM);
139         /* 6 wait states before TX will happen */
140 }
141
142 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
143
144 /*-------------------------------------------------------------------------*/
145
146 static int omap_ep_enable(struct usb_ep *_ep,
147                 const struct usb_endpoint_descriptor *desc)
148 {
149         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
150         struct omap_udc *udc;
151         unsigned long   flags;
152         u16             maxp;
153
154         /* catch various bogus parameters */
155         if (!_ep || !desc
156                         || desc->bDescriptorType != USB_DT_ENDPOINT
157                         || ep->bEndpointAddress != desc->bEndpointAddress
158                         || ep->maxpacket < usb_endpoint_maxp(desc)) {
159                 DBG("%s, bad ep or descriptor\n", __func__);
160                 return -EINVAL;
161         }
162         maxp = usb_endpoint_maxp(desc);
163         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
164                                 && maxp != ep->maxpacket)
165                         || usb_endpoint_maxp(desc) > ep->maxpacket
166                         || !desc->wMaxPacketSize) {
167                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
168                 return -ERANGE;
169         }
170
171 #ifdef  USE_ISO
172         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
173                                 && desc->bInterval != 1)) {
174                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
175                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
176                                 1 << (desc->bInterval - 1));
177                 return -EDOM;
178         }
179 #else
180         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
181                 DBG("%s, ISO nyet\n", _ep->name);
182                 return -EDOM;
183         }
184 #endif
185
186         /* xfer types must match, except that interrupt ~= bulk */
187         if (ep->bmAttributes != desc->bmAttributes
188                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
189                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
190                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
191                 return -EINVAL;
192         }
193
194         udc = ep->udc;
195         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
196                 DBG("%s, bogus device state\n", __func__);
197                 return -ESHUTDOWN;
198         }
199
200         spin_lock_irqsave(&udc->lock, flags);
201
202         ep->ep.desc = desc;
203         ep->irqs = 0;
204         ep->stopped = 0;
205         ep->ep.maxpacket = maxp;
206
207         /* set endpoint to initial state */
208         ep->dma_channel = 0;
209         ep->has_dma = 0;
210         ep->lch = -1;
211         use_ep(ep, UDC_EP_SEL);
212         omap_writew(udc->clr_halt, UDC_CTRL);
213         ep->ackwait = 0;
214         deselect_ep();
215
216         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
217                 list_add(&ep->iso, &udc->iso);
218
219         /* maybe assign a DMA channel to this endpoint */
220         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
221                 /* FIXME ISO can dma, but prefers first channel */
222                 dma_channel_claim(ep, 0);
223
224         /* PIO OUT may RX packets */
225         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
226                         && !ep->has_dma
227                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
228                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
229                 ep->ackwait = 1 + ep->double_buf;
230         }
231
232         spin_unlock_irqrestore(&udc->lock, flags);
233         VDBG("%s enabled\n", _ep->name);
234         return 0;
235 }
236
237 static void nuke(struct omap_ep *, int status);
238
239 static int omap_ep_disable(struct usb_ep *_ep)
240 {
241         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
242         unsigned long   flags;
243
244         if (!_ep || !ep->ep.desc) {
245                 DBG("%s, %s not enabled\n", __func__,
246                         _ep ? ep->ep.name : NULL);
247                 return -EINVAL;
248         }
249
250         spin_lock_irqsave(&ep->udc->lock, flags);
251         ep->ep.desc = NULL;
252         nuke(ep, -ESHUTDOWN);
253         ep->ep.maxpacket = ep->maxpacket;
254         ep->has_dma = 0;
255         omap_writew(UDC_SET_HALT, UDC_CTRL);
256         list_del_init(&ep->iso);
257         del_timer(&ep->timer);
258
259         spin_unlock_irqrestore(&ep->udc->lock, flags);
260
261         VDBG("%s disabled\n", _ep->name);
262         return 0;
263 }
264
265 /*-------------------------------------------------------------------------*/
266
267 static struct usb_request *
268 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
269 {
270         struct omap_req *req;
271
272         req = kzalloc(sizeof(*req), gfp_flags);
273         if (!req)
274                 return NULL;
275
276         INIT_LIST_HEAD(&req->queue);
277
278         return &req->req;
279 }
280
281 static void
282 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
283 {
284         struct omap_req *req = container_of(_req, struct omap_req, req);
285
286         kfree(req);
287 }
288
289 /*-------------------------------------------------------------------------*/
290
291 static void
292 done(struct omap_ep *ep, struct omap_req *req, int status)
293 {
294         struct omap_udc         *udc = ep->udc;
295         unsigned                stopped = ep->stopped;
296
297         list_del_init(&req->queue);
298
299         if (req->req.status == -EINPROGRESS)
300                 req->req.status = status;
301         else
302                 status = req->req.status;
303
304         if (use_dma && ep->has_dma)
305                 usb_gadget_unmap_request(&udc->gadget, &req->req,
306                                 (ep->bEndpointAddress & USB_DIR_IN));
307
308 #ifndef USB_TRACE
309         if (status && status != -ESHUTDOWN)
310 #endif
311                 VDBG("complete %s req %p stat %d len %u/%u\n",
312                         ep->ep.name, &req->req, status,
313                         req->req.actual, req->req.length);
314
315         /* don't modify queue heads during completion callback */
316         ep->stopped = 1;
317         spin_unlock(&ep->udc->lock);
318         req->req.complete(&ep->ep, &req->req);
319         spin_lock(&ep->udc->lock);
320         ep->stopped = stopped;
321 }
322
323 /*-------------------------------------------------------------------------*/
324
325 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
326 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
327
328 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
329 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
330
331 static inline int
332 write_packet(u8 *buf, struct omap_req *req, unsigned max)
333 {
334         unsigned        len;
335         u16             *wp;
336
337         len = min(req->req.length - req->req.actual, max);
338         req->req.actual += len;
339
340         max = len;
341         if (likely((((int)buf) & 1) == 0)) {
342                 wp = (u16 *)buf;
343                 while (max >= 2) {
344                         omap_writew(*wp++, UDC_DATA);
345                         max -= 2;
346                 }
347                 buf = (u8 *)wp;
348         }
349         while (max--)
350                 omap_writeb(*buf++, UDC_DATA);
351         return len;
352 }
353
354 /* FIXME change r/w fifo calling convention */
355
356
357 /* return:  0 = still running, 1 = completed, negative = errno */
358 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
359 {
360         u8              *buf;
361         unsigned        count;
362         int             is_last;
363         u16             ep_stat;
364
365         buf = req->req.buf + req->req.actual;
366         prefetch(buf);
367
368         /* PIO-IN isn't double buffered except for iso */
369         ep_stat = omap_readw(UDC_STAT_FLG);
370         if (ep_stat & UDC_FIFO_UNWRITABLE)
371                 return 0;
372
373         count = ep->ep.maxpacket;
374         count = write_packet(buf, req, count);
375         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
376         ep->ackwait = 1;
377
378         /* last packet is often short (sometimes a zlp) */
379         if (count != ep->ep.maxpacket)
380                 is_last = 1;
381         else if (req->req.length == req->req.actual
382                         && !req->req.zero)
383                 is_last = 1;
384         else
385                 is_last = 0;
386
387         /* NOTE:  requests complete when all IN data is in a
388          * FIFO (or sometimes later, if a zlp was needed).
389          * Use usb_ep_fifo_status() where needed.
390          */
391         if (is_last)
392                 done(ep, req, 0);
393         return is_last;
394 }
395
396 static inline int
397 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
398 {
399         unsigned        len;
400         u16             *wp;
401
402         len = min(req->req.length - req->req.actual, avail);
403         req->req.actual += len;
404         avail = len;
405
406         if (likely((((int)buf) & 1) == 0)) {
407                 wp = (u16 *)buf;
408                 while (avail >= 2) {
409                         *wp++ = omap_readw(UDC_DATA);
410                         avail -= 2;
411                 }
412                 buf = (u8 *)wp;
413         }
414         while (avail--)
415                 *buf++ = omap_readb(UDC_DATA);
416         return len;
417 }
418
419 /* return:  0 = still running, 1 = queue empty, negative = errno */
420 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
421 {
422         u8              *buf;
423         unsigned        count, avail;
424         int             is_last;
425
426         buf = req->req.buf + req->req.actual;
427         prefetchw(buf);
428
429         for (;;) {
430                 u16     ep_stat = omap_readw(UDC_STAT_FLG);
431
432                 is_last = 0;
433                 if (ep_stat & FIFO_EMPTY) {
434                         if (!ep->double_buf)
435                                 break;
436                         ep->fnf = 1;
437                 }
438                 if (ep_stat & UDC_EP_HALTED)
439                         break;
440
441                 if (ep_stat & UDC_FIFO_FULL)
442                         avail = ep->ep.maxpacket;
443                 else  {
444                         avail = omap_readw(UDC_RXFSTAT);
445                         ep->fnf = ep->double_buf;
446                 }
447                 count = read_packet(buf, req, avail);
448
449                 /* partial packet reads may not be errors */
450                 if (count < ep->ep.maxpacket) {
451                         is_last = 1;
452                         /* overflowed this request?  flush extra data */
453                         if (count != avail) {
454                                 req->req.status = -EOVERFLOW;
455                                 avail -= count;
456                                 while (avail--)
457                                         omap_readw(UDC_DATA);
458                         }
459                 } else if (req->req.length == req->req.actual)
460                         is_last = 1;
461                 else
462                         is_last = 0;
463
464                 if (!ep->bEndpointAddress)
465                         break;
466                 if (is_last)
467                         done(ep, req, 0);
468                 break;
469         }
470         return is_last;
471 }
472
473 /*-------------------------------------------------------------------------*/
474
475 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
476 {
477         dma_addr_t      end;
478
479         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
480          * the last transfer's bytecount by more than a FIFO's worth.
481          */
482         if (cpu_is_omap15xx())
483                 return 0;
484
485         end = omap_get_dma_src_pos(ep->lch);
486         if (end == ep->dma_counter)
487                 return 0;
488
489         end |= start & (0xffff << 16);
490         if (end < start)
491                 end += 0x10000;
492         return end - start;
493 }
494
495 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
496 {
497         dma_addr_t      end;
498
499         end = omap_get_dma_dst_pos(ep->lch);
500         if (end == ep->dma_counter)
501                 return 0;
502
503         end |= start & (0xffff << 16);
504         if (cpu_is_omap15xx())
505                 end++;
506         if (end < start)
507                 end += 0x10000;
508         return end - start;
509 }
510
511
512 /* Each USB transfer request using DMA maps to one or more DMA transfers.
513  * When DMA completion isn't request completion, the UDC continues with
514  * the next DMA transfer for that USB transfer.
515  */
516
517 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
518 {
519         u16             txdma_ctrl, w;
520         unsigned        length = req->req.length - req->req.actual;
521         const int       sync_mode = cpu_is_omap15xx()
522                                 ? OMAP_DMA_SYNC_FRAME
523                                 : OMAP_DMA_SYNC_ELEMENT;
524         int             dma_trigger = 0;
525
526         /* measure length in either bytes or packets */
527         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
528                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
529                 txdma_ctrl = UDC_TXN_EOT | length;
530                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
531                                 length, 1, sync_mode, dma_trigger, 0);
532         } else {
533                 length = min(length / ep->maxpacket,
534                                 (unsigned) UDC_TXN_TSC + 1);
535                 txdma_ctrl = length;
536                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
537                                 ep->ep.maxpacket >> 1, length, sync_mode,
538                                 dma_trigger, 0);
539                 length *= ep->maxpacket;
540         }
541         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
542                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
543                 0, 0);
544
545         omap_start_dma(ep->lch);
546         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
547         w = omap_readw(UDC_DMA_IRQ_EN);
548         w |= UDC_TX_DONE_IE(ep->dma_channel);
549         omap_writew(w, UDC_DMA_IRQ_EN);
550         omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
551         req->dma_bytes = length;
552 }
553
554 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
555 {
556         u16 w;
557
558         if (status == 0) {
559                 req->req.actual += req->dma_bytes;
560
561                 /* return if this request needs to send data or zlp */
562                 if (req->req.actual < req->req.length)
563                         return;
564                 if (req->req.zero
565                                 && req->dma_bytes != 0
566                                 && (req->req.actual % ep->maxpacket) == 0)
567                         return;
568         } else
569                 req->req.actual += dma_src_len(ep, req->req.dma
570                                                         + req->req.actual);
571
572         /* tx completion */
573         omap_stop_dma(ep->lch);
574         w = omap_readw(UDC_DMA_IRQ_EN);
575         w &= ~UDC_TX_DONE_IE(ep->dma_channel);
576         omap_writew(w, UDC_DMA_IRQ_EN);
577         done(ep, req, status);
578 }
579
580 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
581 {
582         unsigned packets = req->req.length - req->req.actual;
583         int dma_trigger = 0;
584         u16 w;
585
586         /* set up this DMA transfer, enable the fifo, start */
587         packets /= ep->ep.maxpacket;
588         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
589         req->dma_bytes = packets * ep->ep.maxpacket;
590         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
591                         ep->ep.maxpacket >> 1, packets,
592                         OMAP_DMA_SYNC_ELEMENT,
593                         dma_trigger, 0);
594         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
595                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
596                 0, 0);
597         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
598
599         omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
600         w = omap_readw(UDC_DMA_IRQ_EN);
601         w |= UDC_RX_EOT_IE(ep->dma_channel);
602         omap_writew(w, UDC_DMA_IRQ_EN);
603         omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
604         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
605
606         omap_start_dma(ep->lch);
607 }
608
609 static void
610 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
611 {
612         u16     count, w;
613
614         if (status == 0)
615                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
616         count = dma_dest_len(ep, req->req.dma + req->req.actual);
617         count += req->req.actual;
618         if (one)
619                 count--;
620         if (count <= req->req.length)
621                 req->req.actual = count;
622
623         if (count != req->dma_bytes || status)
624                 omap_stop_dma(ep->lch);
625
626         /* if this wasn't short, request may need another transfer */
627         else if (req->req.actual < req->req.length)
628                 return;
629
630         /* rx completion */
631         w = omap_readw(UDC_DMA_IRQ_EN);
632         w &= ~UDC_RX_EOT_IE(ep->dma_channel);
633         omap_writew(w, UDC_DMA_IRQ_EN);
634         done(ep, req, status);
635 }
636
637 static void dma_irq(struct omap_udc *udc, u16 irq_src)
638 {
639         u16             dman_stat = omap_readw(UDC_DMAN_STAT);
640         struct omap_ep  *ep;
641         struct omap_req *req;
642
643         /* IN dma: tx to host */
644         if (irq_src & UDC_TXN_DONE) {
645                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
646                 ep->irqs++;
647                 /* can see TXN_DONE after dma abort */
648                 if (!list_empty(&ep->queue)) {
649                         req = container_of(ep->queue.next,
650                                                 struct omap_req, queue);
651                         finish_in_dma(ep, req, 0);
652                 }
653                 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
654
655                 if (!list_empty(&ep->queue)) {
656                         req = container_of(ep->queue.next,
657                                         struct omap_req, queue);
658                         next_in_dma(ep, req);
659                 }
660         }
661
662         /* OUT dma: rx from host */
663         if (irq_src & UDC_RXN_EOT) {
664                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
665                 ep->irqs++;
666                 /* can see RXN_EOT after dma abort */
667                 if (!list_empty(&ep->queue)) {
668                         req = container_of(ep->queue.next,
669                                         struct omap_req, queue);
670                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
671                 }
672                 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
673
674                 if (!list_empty(&ep->queue)) {
675                         req = container_of(ep->queue.next,
676                                         struct omap_req, queue);
677                         next_out_dma(ep, req);
678                 }
679         }
680
681         if (irq_src & UDC_RXN_CNT) {
682                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
683                 ep->irqs++;
684                 /* omap15xx does this unasked... */
685                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
686                 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
687         }
688 }
689
690 static void dma_error(int lch, u16 ch_status, void *data)
691 {
692         struct omap_ep  *ep = data;
693
694         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
695         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
696         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
697
698         /* complete current transfer ... */
699 }
700
701 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
702 {
703         u16     reg;
704         int     status, restart, is_in;
705         int     dma_channel;
706
707         is_in = ep->bEndpointAddress & USB_DIR_IN;
708         if (is_in)
709                 reg = omap_readw(UDC_TXDMA_CFG);
710         else
711                 reg = omap_readw(UDC_RXDMA_CFG);
712         reg |= UDC_DMA_REQ;             /* "pulse" activated */
713
714         ep->dma_channel = 0;
715         ep->lch = -1;
716         if (channel == 0 || channel > 3) {
717                 if ((reg & 0x0f00) == 0)
718                         channel = 3;
719                 else if ((reg & 0x00f0) == 0)
720                         channel = 2;
721                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
722                         channel = 1;
723                 else {
724                         status = -EMLINK;
725                         goto just_restart;
726                 }
727         }
728         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
729         ep->dma_channel = channel;
730
731         if (is_in) {
732                 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
733                 status = omap_request_dma(dma_channel,
734                         ep->ep.name, dma_error, ep, &ep->lch);
735                 if (status == 0) {
736                         omap_writew(reg, UDC_TXDMA_CFG);
737                         /* EMIFF or SDRC */
738                         omap_set_dma_src_burst_mode(ep->lch,
739                                                 OMAP_DMA_DATA_BURST_4);
740                         omap_set_dma_src_data_pack(ep->lch, 1);
741                         /* TIPB */
742                         omap_set_dma_dest_params(ep->lch,
743                                 OMAP_DMA_PORT_TIPB,
744                                 OMAP_DMA_AMODE_CONSTANT,
745                                 UDC_DATA_DMA,
746                                 0, 0);
747                 }
748         } else {
749                 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
750                 status = omap_request_dma(dma_channel,
751                         ep->ep.name, dma_error, ep, &ep->lch);
752                 if (status == 0) {
753                         omap_writew(reg, UDC_RXDMA_CFG);
754                         /* TIPB */
755                         omap_set_dma_src_params(ep->lch,
756                                 OMAP_DMA_PORT_TIPB,
757                                 OMAP_DMA_AMODE_CONSTANT,
758                                 UDC_DATA_DMA,
759                                 0, 0);
760                         /* EMIFF or SDRC */
761                         omap_set_dma_dest_burst_mode(ep->lch,
762                                                 OMAP_DMA_DATA_BURST_4);
763                         omap_set_dma_dest_data_pack(ep->lch, 1);
764                 }
765         }
766         if (status)
767                 ep->dma_channel = 0;
768         else {
769                 ep->has_dma = 1;
770                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
771
772                 /* channel type P: hw synch (fifo) */
773                 if (!cpu_is_omap15xx())
774                         omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
775         }
776
777 just_restart:
778         /* restart any queue, even if the claim failed  */
779         restart = !ep->stopped && !list_empty(&ep->queue);
780
781         if (status)
782                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
783                         restart ? " (restart)" : "");
784         else
785                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
786                         is_in ? 't' : 'r',
787                         ep->dma_channel - 1, ep->lch,
788                         restart ? " (restart)" : "");
789
790         if (restart) {
791                 struct omap_req *req;
792                 req = container_of(ep->queue.next, struct omap_req, queue);
793                 if (ep->has_dma)
794                         (is_in ? next_in_dma : next_out_dma)(ep, req);
795                 else {
796                         use_ep(ep, UDC_EP_SEL);
797                         (is_in ? write_fifo : read_fifo)(ep, req);
798                         deselect_ep();
799                         if (!is_in) {
800                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
801                                 ep->ackwait = 1 + ep->double_buf;
802                         }
803                         /* IN: 6 wait states before it'll tx */
804                 }
805         }
806 }
807
808 static void dma_channel_release(struct omap_ep *ep)
809 {
810         int             shift = 4 * (ep->dma_channel - 1);
811         u16             mask = 0x0f << shift;
812         struct omap_req *req;
813         int             active;
814
815         /* abort any active usb transfer request */
816         if (!list_empty(&ep->queue))
817                 req = container_of(ep->queue.next, struct omap_req, queue);
818         else
819                 req = NULL;
820
821         active = omap_get_dma_active_status(ep->lch);
822
823         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
824                         active ? "active" : "idle",
825                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
826                         ep->dma_channel - 1, req);
827
828         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
829          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
830          */
831
832         /* wait till current packet DMA finishes, and fifo empties */
833         if (ep->bEndpointAddress & USB_DIR_IN) {
834                 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
835                                         UDC_TXDMA_CFG);
836
837                 if (req) {
838                         finish_in_dma(ep, req, -ECONNRESET);
839
840                         /* clear FIFO; hosts probably won't empty it */
841                         use_ep(ep, UDC_EP_SEL);
842                         omap_writew(UDC_CLR_EP, UDC_CTRL);
843                         deselect_ep();
844                 }
845                 while (omap_readw(UDC_TXDMA_CFG) & mask)
846                         udelay(10);
847         } else {
848                 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
849                                         UDC_RXDMA_CFG);
850
851                 /* dma empties the fifo */
852                 while (omap_readw(UDC_RXDMA_CFG) & mask)
853                         udelay(10);
854                 if (req)
855                         finish_out_dma(ep, req, -ECONNRESET, 0);
856         }
857         omap_free_dma(ep->lch);
858         ep->dma_channel = 0;
859         ep->lch = -1;
860         /* has_dma still set, till endpoint is fully quiesced */
861 }
862
863
864 /*-------------------------------------------------------------------------*/
865
866 static int
867 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
868 {
869         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
870         struct omap_req *req = container_of(_req, struct omap_req, req);
871         struct omap_udc *udc;
872         unsigned long   flags;
873         int             is_iso = 0;
874
875         /* catch various bogus parameters */
876         if (!_req || !req->req.complete || !req->req.buf
877                         || !list_empty(&req->queue)) {
878                 DBG("%s, bad params\n", __func__);
879                 return -EINVAL;
880         }
881         if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
882                 DBG("%s, bad ep\n", __func__);
883                 return -EINVAL;
884         }
885         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
886                 if (req->req.length > ep->ep.maxpacket)
887                         return -EMSGSIZE;
888                 is_iso = 1;
889         }
890
891         /* this isn't bogus, but OMAP DMA isn't the only hardware to
892          * have a hard time with partial packet reads...  reject it.
893          */
894         if (use_dma
895                         && ep->has_dma
896                         && ep->bEndpointAddress != 0
897                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
898                         && (req->req.length % ep->ep.maxpacket) != 0) {
899                 DBG("%s, no partial packet OUT reads\n", __func__);
900                 return -EMSGSIZE;
901         }
902
903         udc = ep->udc;
904         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
905                 return -ESHUTDOWN;
906
907         if (use_dma && ep->has_dma)
908                 usb_gadget_map_request(&udc->gadget, &req->req,
909                                 (ep->bEndpointAddress & USB_DIR_IN));
910
911         VDBG("%s queue req %p, len %d buf %p\n",
912                 ep->ep.name, _req, _req->length, _req->buf);
913
914         spin_lock_irqsave(&udc->lock, flags);
915
916         req->req.status = -EINPROGRESS;
917         req->req.actual = 0;
918
919         /* maybe kickstart non-iso i/o queues */
920         if (is_iso) {
921                 u16 w;
922
923                 w = omap_readw(UDC_IRQ_EN);
924                 w |= UDC_SOF_IE;
925                 omap_writew(w, UDC_IRQ_EN);
926         } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
927                 int     is_in;
928
929                 if (ep->bEndpointAddress == 0) {
930                         if (!udc->ep0_pending || !list_empty(&ep->queue)) {
931                                 spin_unlock_irqrestore(&udc->lock, flags);
932                                 return -EL2HLT;
933                         }
934
935                         /* empty DATA stage? */
936                         is_in = udc->ep0_in;
937                         if (!req->req.length) {
938
939                                 /* chip became CONFIGURED or ADDRESSED
940                                  * earlier; drivers may already have queued
941                                  * requests to non-control endpoints
942                                  */
943                                 if (udc->ep0_set_config) {
944                                         u16     irq_en = omap_readw(UDC_IRQ_EN);
945
946                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
947                                         if (!udc->ep0_reset_config)
948                                                 irq_en |= UDC_EPN_RX_IE
949                                                         | UDC_EPN_TX_IE;
950                                         omap_writew(irq_en, UDC_IRQ_EN);
951                                 }
952
953                                 /* STATUS for zero length DATA stages is
954                                  * always an IN ... even for IN transfers,
955                                  * a weird case which seem to stall OMAP.
956                                  */
957                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
958                                                 UDC_EP_NUM);
959                                 omap_writew(UDC_CLR_EP, UDC_CTRL);
960                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
961                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
962
963                                 /* cleanup */
964                                 udc->ep0_pending = 0;
965                                 done(ep, req, 0);
966                                 req = NULL;
967
968                         /* non-empty DATA stage */
969                         } else if (is_in) {
970                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
971                                                 UDC_EP_NUM);
972                         } else {
973                                 if (udc->ep0_setup)
974                                         goto irq_wait;
975                                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
976                         }
977                 } else {
978                         is_in = ep->bEndpointAddress & USB_DIR_IN;
979                         if (!ep->has_dma)
980                                 use_ep(ep, UDC_EP_SEL);
981                         /* if ISO: SOF IRQs must be enabled/disabled! */
982                 }
983
984                 if (ep->has_dma)
985                         (is_in ? next_in_dma : next_out_dma)(ep, req);
986                 else if (req) {
987                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
988                                 req = NULL;
989                         deselect_ep();
990                         if (!is_in) {
991                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
992                                 ep->ackwait = 1 + ep->double_buf;
993                         }
994                         /* IN: 6 wait states before it'll tx */
995                 }
996         }
997
998 irq_wait:
999         /* irq handler advances the queue */
1000         if (req != NULL)
1001                 list_add_tail(&req->queue, &ep->queue);
1002         spin_unlock_irqrestore(&udc->lock, flags);
1003
1004         return 0;
1005 }
1006
1007 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1008 {
1009         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1010         struct omap_req *req;
1011         unsigned long   flags;
1012
1013         if (!_ep || !_req)
1014                 return -EINVAL;
1015
1016         spin_lock_irqsave(&ep->udc->lock, flags);
1017
1018         /* make sure it's actually queued on this endpoint */
1019         list_for_each_entry(req, &ep->queue, queue) {
1020                 if (&req->req == _req)
1021                         break;
1022         }
1023         if (&req->req != _req) {
1024                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1025                 return -EINVAL;
1026         }
1027
1028         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1029                 int channel = ep->dma_channel;
1030
1031                 /* releasing the channel cancels the request,
1032                  * reclaiming the channel restarts the queue
1033                  */
1034                 dma_channel_release(ep);
1035                 dma_channel_claim(ep, channel);
1036         } else
1037                 done(ep, req, -ECONNRESET);
1038         spin_unlock_irqrestore(&ep->udc->lock, flags);
1039         return 0;
1040 }
1041
1042 /*-------------------------------------------------------------------------*/
1043
1044 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1045 {
1046         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1047         unsigned long   flags;
1048         int             status = -EOPNOTSUPP;
1049
1050         spin_lock_irqsave(&ep->udc->lock, flags);
1051
1052         /* just use protocol stalls for ep0; real halts are annoying */
1053         if (ep->bEndpointAddress == 0) {
1054                 if (!ep->udc->ep0_pending)
1055                         status = -EINVAL;
1056                 else if (value) {
1057                         if (ep->udc->ep0_set_config) {
1058                                 WARNING("error changing config?\n");
1059                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1060                         }
1061                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1062                         ep->udc->ep0_pending = 0;
1063                         status = 0;
1064                 } else /* NOP */
1065                         status = 0;
1066
1067         /* otherwise, all active non-ISO endpoints can halt */
1068         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1069
1070                 /* IN endpoints must already be idle */
1071                 if ((ep->bEndpointAddress & USB_DIR_IN)
1072                                 && !list_empty(&ep->queue)) {
1073                         status = -EAGAIN;
1074                         goto done;
1075                 }
1076
1077                 if (value) {
1078                         int     channel;
1079
1080                         if (use_dma && ep->dma_channel
1081                                         && !list_empty(&ep->queue)) {
1082                                 channel = ep->dma_channel;
1083                                 dma_channel_release(ep);
1084                         } else
1085                                 channel = 0;
1086
1087                         use_ep(ep, UDC_EP_SEL);
1088                         if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1089                                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1090                                 status = 0;
1091                         } else
1092                                 status = -EAGAIN;
1093                         deselect_ep();
1094
1095                         if (channel)
1096                                 dma_channel_claim(ep, channel);
1097                 } else {
1098                         use_ep(ep, 0);
1099                         omap_writew(ep->udc->clr_halt, UDC_CTRL);
1100                         ep->ackwait = 0;
1101                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1102                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1103                                 ep->ackwait = 1 + ep->double_buf;
1104                         }
1105                 }
1106         }
1107 done:
1108         VDBG("%s %s halt stat %d\n", ep->ep.name,
1109                 value ? "set" : "clear", status);
1110
1111         spin_unlock_irqrestore(&ep->udc->lock, flags);
1112         return status;
1113 }
1114
1115 static struct usb_ep_ops omap_ep_ops = {
1116         .enable         = omap_ep_enable,
1117         .disable        = omap_ep_disable,
1118
1119         .alloc_request  = omap_alloc_request,
1120         .free_request   = omap_free_request,
1121
1122         .queue          = omap_ep_queue,
1123         .dequeue        = omap_ep_dequeue,
1124
1125         .set_halt       = omap_ep_set_halt,
1126         /* fifo_status ... report bytes in fifo */
1127         /* fifo_flush ... flush fifo */
1128 };
1129
1130 /*-------------------------------------------------------------------------*/
1131
1132 static int omap_get_frame(struct usb_gadget *gadget)
1133 {
1134         u16     sof = omap_readw(UDC_SOF);
1135         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1136 }
1137
1138 static int omap_wakeup(struct usb_gadget *gadget)
1139 {
1140         struct omap_udc *udc;
1141         unsigned long   flags;
1142         int             retval = -EHOSTUNREACH;
1143
1144         udc = container_of(gadget, struct omap_udc, gadget);
1145
1146         spin_lock_irqsave(&udc->lock, flags);
1147         if (udc->devstat & UDC_SUS) {
1148                 /* NOTE:  OTG spec erratum says that OTG devices may
1149                  * issue wakeups without host enable.
1150                  */
1151                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1152                         DBG("remote wakeup...\n");
1153                         omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1154                         retval = 0;
1155                 }
1156
1157         /* NOTE:  non-OTG systems may use SRP TOO... */
1158         } else if (!(udc->devstat & UDC_ATT)) {
1159                 if (!IS_ERR_OR_NULL(udc->transceiver))
1160                         retval = otg_start_srp(udc->transceiver->otg);
1161         }
1162         spin_unlock_irqrestore(&udc->lock, flags);
1163
1164         return retval;
1165 }
1166
1167 static int
1168 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1169 {
1170         struct omap_udc *udc;
1171         unsigned long   flags;
1172         u16             syscon1;
1173
1174         udc = container_of(gadget, struct omap_udc, gadget);
1175         spin_lock_irqsave(&udc->lock, flags);
1176         syscon1 = omap_readw(UDC_SYSCON1);
1177         if (is_selfpowered)
1178                 syscon1 |= UDC_SELF_PWR;
1179         else
1180                 syscon1 &= ~UDC_SELF_PWR;
1181         omap_writew(syscon1, UDC_SYSCON1);
1182         spin_unlock_irqrestore(&udc->lock, flags);
1183
1184         return 0;
1185 }
1186
1187 static int can_pullup(struct omap_udc *udc)
1188 {
1189         return udc->driver && udc->softconnect && udc->vbus_active;
1190 }
1191
1192 static void pullup_enable(struct omap_udc *udc)
1193 {
1194         u16 w;
1195
1196         w = omap_readw(UDC_SYSCON1);
1197         w |= UDC_PULLUP_EN;
1198         omap_writew(w, UDC_SYSCON1);
1199         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1200                 u32 l;
1201
1202                 l = omap_readl(OTG_CTRL);
1203                 l |= OTG_BSESSVLD;
1204                 omap_writel(l, OTG_CTRL);
1205         }
1206         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1207 }
1208
1209 static void pullup_disable(struct omap_udc *udc)
1210 {
1211         u16 w;
1212
1213         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1214                 u32 l;
1215
1216                 l = omap_readl(OTG_CTRL);
1217                 l &= ~OTG_BSESSVLD;
1218                 omap_writel(l, OTG_CTRL);
1219         }
1220         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1221         w = omap_readw(UDC_SYSCON1);
1222         w &= ~UDC_PULLUP_EN;
1223         omap_writew(w, UDC_SYSCON1);
1224 }
1225
1226 static struct omap_udc *udc;
1227
1228 static void omap_udc_enable_clock(int enable)
1229 {
1230         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1231                 return;
1232
1233         if (enable) {
1234                 clk_enable(udc->dc_clk);
1235                 clk_enable(udc->hhc_clk);
1236                 udelay(100);
1237         } else {
1238                 clk_disable(udc->hhc_clk);
1239                 clk_disable(udc->dc_clk);
1240         }
1241 }
1242
1243 /*
1244  * Called by whatever detects VBUS sessions:  external transceiver
1245  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1246  */
1247 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1248 {
1249         struct omap_udc *udc;
1250         unsigned long   flags;
1251         u32 l;
1252
1253         udc = container_of(gadget, struct omap_udc, gadget);
1254         spin_lock_irqsave(&udc->lock, flags);
1255         VDBG("VBUS %s\n", is_active ? "on" : "off");
1256         udc->vbus_active = (is_active != 0);
1257         if (cpu_is_omap15xx()) {
1258                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1259                 l = omap_readl(FUNC_MUX_CTRL_0);
1260                 if (is_active)
1261                         l |= VBUS_CTRL_1510;
1262                 else
1263                         l &= ~VBUS_CTRL_1510;
1264                 omap_writel(l, FUNC_MUX_CTRL_0);
1265         }
1266         if (udc->dc_clk != NULL && is_active) {
1267                 if (!udc->clk_requested) {
1268                         omap_udc_enable_clock(1);
1269                         udc->clk_requested = 1;
1270                 }
1271         }
1272         if (can_pullup(udc))
1273                 pullup_enable(udc);
1274         else
1275                 pullup_disable(udc);
1276         if (udc->dc_clk != NULL && !is_active) {
1277                 if (udc->clk_requested) {
1278                         omap_udc_enable_clock(0);
1279                         udc->clk_requested = 0;
1280                 }
1281         }
1282         spin_unlock_irqrestore(&udc->lock, flags);
1283         return 0;
1284 }
1285
1286 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1287 {
1288         struct omap_udc *udc;
1289
1290         udc = container_of(gadget, struct omap_udc, gadget);
1291         if (!IS_ERR_OR_NULL(udc->transceiver))
1292                 return usb_phy_set_power(udc->transceiver, mA);
1293         return -EOPNOTSUPP;
1294 }
1295
1296 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1297 {
1298         struct omap_udc *udc;
1299         unsigned long   flags;
1300
1301         udc = container_of(gadget, struct omap_udc, gadget);
1302         spin_lock_irqsave(&udc->lock, flags);
1303         udc->softconnect = (is_on != 0);
1304         if (can_pullup(udc))
1305                 pullup_enable(udc);
1306         else
1307                 pullup_disable(udc);
1308         spin_unlock_irqrestore(&udc->lock, flags);
1309         return 0;
1310 }
1311
1312 static int omap_udc_start(struct usb_gadget_driver *driver,
1313                 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *));
1314 static int omap_udc_stop(struct usb_gadget_driver *driver);
1315
1316 static struct usb_gadget_ops omap_gadget_ops = {
1317         .get_frame              = omap_get_frame,
1318         .wakeup                 = omap_wakeup,
1319         .set_selfpowered        = omap_set_selfpowered,
1320         .vbus_session           = omap_vbus_session,
1321         .vbus_draw              = omap_vbus_draw,
1322         .pullup                 = omap_pullup,
1323         .start                  = omap_udc_start,
1324         .stop                   = omap_udc_stop,
1325 };
1326
1327 /*-------------------------------------------------------------------------*/
1328
1329 /* dequeue ALL requests; caller holds udc->lock */
1330 static void nuke(struct omap_ep *ep, int status)
1331 {
1332         struct omap_req *req;
1333
1334         ep->stopped = 1;
1335
1336         if (use_dma && ep->dma_channel)
1337                 dma_channel_release(ep);
1338
1339         use_ep(ep, 0);
1340         omap_writew(UDC_CLR_EP, UDC_CTRL);
1341         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1342                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1343
1344         while (!list_empty(&ep->queue)) {
1345                 req = list_entry(ep->queue.next, struct omap_req, queue);
1346                 done(ep, req, status);
1347         }
1348 }
1349
1350 /* caller holds udc->lock */
1351 static void udc_quiesce(struct omap_udc *udc)
1352 {
1353         struct omap_ep  *ep;
1354
1355         udc->gadget.speed = USB_SPEED_UNKNOWN;
1356         nuke(&udc->ep[0], -ESHUTDOWN);
1357         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1358                 nuke(ep, -ESHUTDOWN);
1359 }
1360
1361 /*-------------------------------------------------------------------------*/
1362
1363 static void update_otg(struct omap_udc *udc)
1364 {
1365         u16     devstat;
1366
1367         if (!gadget_is_otg(&udc->gadget))
1368                 return;
1369
1370         if (omap_readl(OTG_CTRL) & OTG_ID)
1371                 devstat = omap_readw(UDC_DEVSTAT);
1372         else
1373                 devstat = 0;
1374
1375         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1376         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1377         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1378
1379         /* Enable HNP early, avoiding races on suspend irq path.
1380          * ASSUMES OTG state machine B_BUS_REQ input is true.
1381          */
1382         if (udc->gadget.b_hnp_enable) {
1383                 u32 l;
1384
1385                 l = omap_readl(OTG_CTRL);
1386                 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1387                 l &= ~OTG_PULLUP;
1388                 omap_writel(l, OTG_CTRL);
1389         }
1390 }
1391
1392 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1393 {
1394         struct omap_ep  *ep0 = &udc->ep[0];
1395         struct omap_req *req = NULL;
1396
1397         ep0->irqs++;
1398
1399         /* Clear any pending requests and then scrub any rx/tx state
1400          * before starting to handle the SETUP request.
1401          */
1402         if (irq_src & UDC_SETUP) {
1403                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1404
1405                 nuke(ep0, 0);
1406                 if (ack) {
1407                         omap_writew(ack, UDC_IRQ_SRC);
1408                         irq_src = UDC_SETUP;
1409                 }
1410         }
1411
1412         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1413          * This driver uses only uses protocol stalls (ep0 never halts),
1414          * and if we got this far the gadget driver already had a
1415          * chance to stall.  Tries to be forgiving of host oddities.
1416          *
1417          * NOTE:  the last chance gadget drivers have to stall control
1418          * requests is during their request completion callback.
1419          */
1420         if (!list_empty(&ep0->queue))
1421                 req = container_of(ep0->queue.next, struct omap_req, queue);
1422
1423         /* IN == TX to host */
1424         if (irq_src & UDC_EP0_TX) {
1425                 int     stat;
1426
1427                 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1428                 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1429                 stat = omap_readw(UDC_STAT_FLG);
1430                 if (stat & UDC_ACK) {
1431                         if (udc->ep0_in) {
1432                                 /* write next IN packet from response,
1433                                  * or set up the status stage.
1434                                  */
1435                                 if (req)
1436                                         stat = write_fifo(ep0, req);
1437                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1438                                 if (!req && udc->ep0_pending) {
1439                                         omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1440                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1441                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1442                                         omap_writew(0, UDC_EP_NUM);
1443                                         udc->ep0_pending = 0;
1444                                 } /* else:  6 wait states before it'll tx */
1445                         } else {
1446                                 /* ack status stage of OUT transfer */
1447                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1448                                 if (req)
1449                                         done(ep0, req, 0);
1450                         }
1451                         req = NULL;
1452                 } else if (stat & UDC_STALL) {
1453                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1454                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1455                 } else {
1456                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1457                 }
1458         }
1459
1460         /* OUT == RX from host */
1461         if (irq_src & UDC_EP0_RX) {
1462                 int     stat;
1463
1464                 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1465                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1466                 stat = omap_readw(UDC_STAT_FLG);
1467                 if (stat & UDC_ACK) {
1468                         if (!udc->ep0_in) {
1469                                 stat = 0;
1470                                 /* read next OUT packet of request, maybe
1471                                  * reactiviting the fifo; stall on errors.
1472                                  */
1473                                 stat = read_fifo(ep0, req);
1474                                 if (!req || stat < 0) {
1475                                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1476                                         udc->ep0_pending = 0;
1477                                         stat = 0;
1478                                 } else if (stat == 0)
1479                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1480                                 omap_writew(0, UDC_EP_NUM);
1481
1482                                 /* activate status stage */
1483                                 if (stat == 1) {
1484                                         done(ep0, req, 0);
1485                                         /* that may have STALLed ep0... */
1486                                         omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1487                                                         UDC_EP_NUM);
1488                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1489                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1490                                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1491                                         udc->ep0_pending = 0;
1492                                 }
1493                         } else {
1494                                 /* ack status stage of IN transfer */
1495                                 omap_writew(0, UDC_EP_NUM);
1496                                 if (req)
1497                                         done(ep0, req, 0);
1498                         }
1499                 } else if (stat & UDC_STALL) {
1500                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1501                         omap_writew(0, UDC_EP_NUM);
1502                 } else {
1503                         omap_writew(0, UDC_EP_NUM);
1504                 }
1505         }
1506
1507         /* SETUP starts all control transfers */
1508         if (irq_src & UDC_SETUP) {
1509                 union u {
1510                         u16                     word[4];
1511                         struct usb_ctrlrequest  r;
1512                 } u;
1513                 int                     status = -EINVAL;
1514                 struct omap_ep          *ep;
1515
1516                 /* read the (latest) SETUP message */
1517                 do {
1518                         omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1519                         /* two bytes at a time */
1520                         u.word[0] = omap_readw(UDC_DATA);
1521                         u.word[1] = omap_readw(UDC_DATA);
1522                         u.word[2] = omap_readw(UDC_DATA);
1523                         u.word[3] = omap_readw(UDC_DATA);
1524                         omap_writew(0, UDC_EP_NUM);
1525                 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1526
1527 #define w_value         le16_to_cpu(u.r.wValue)
1528 #define w_index         le16_to_cpu(u.r.wIndex)
1529 #define w_length        le16_to_cpu(u.r.wLength)
1530
1531                 /* Delegate almost all control requests to the gadget driver,
1532                  * except for a handful of ch9 status/feature requests that
1533                  * hardware doesn't autodecode _and_ the gadget API hides.
1534                  */
1535                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1536                 udc->ep0_set_config = 0;
1537                 udc->ep0_pending = 1;
1538                 ep0->stopped = 0;
1539                 ep0->ackwait = 0;
1540                 switch (u.r.bRequest) {
1541                 case USB_REQ_SET_CONFIGURATION:
1542                         /* udc needs to know when ep != 0 is valid */
1543                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1544                                 goto delegate;
1545                         if (w_length != 0)
1546                                 goto do_stall;
1547                         udc->ep0_set_config = 1;
1548                         udc->ep0_reset_config = (w_value == 0);
1549                         VDBG("set config %d\n", w_value);
1550
1551                         /* update udc NOW since gadget driver may start
1552                          * queueing requests immediately; clear config
1553                          * later if it fails the request.
1554                          */
1555                         if (udc->ep0_reset_config)
1556                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1557                         else
1558                                 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1559                         update_otg(udc);
1560                         goto delegate;
1561                 case USB_REQ_CLEAR_FEATURE:
1562                         /* clear endpoint halt */
1563                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1564                                 goto delegate;
1565                         if (w_value != USB_ENDPOINT_HALT
1566                                         || w_length != 0)
1567                                 goto do_stall;
1568                         ep = &udc->ep[w_index & 0xf];
1569                         if (ep != ep0) {
1570                                 if (w_index & USB_DIR_IN)
1571                                         ep += 16;
1572                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1573                                                 || !ep->ep.desc)
1574                                         goto do_stall;
1575                                 use_ep(ep, 0);
1576                                 omap_writew(udc->clr_halt, UDC_CTRL);
1577                                 ep->ackwait = 0;
1578                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1579                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1580                                         ep->ackwait = 1 + ep->double_buf;
1581                                 }
1582                                 /* NOTE:  assumes the host behaves sanely,
1583                                  * only clearing real halts.  Else we may
1584                                  * need to kill pending transfers and then
1585                                  * restart the queue... very messy for DMA!
1586                                  */
1587                         }
1588                         VDBG("%s halt cleared by host\n", ep->name);
1589                         goto ep0out_status_stage;
1590                 case USB_REQ_SET_FEATURE:
1591                         /* set endpoint halt */
1592                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1593                                 goto delegate;
1594                         if (w_value != USB_ENDPOINT_HALT
1595                                         || w_length != 0)
1596                                 goto do_stall;
1597                         ep = &udc->ep[w_index & 0xf];
1598                         if (w_index & USB_DIR_IN)
1599                                 ep += 16;
1600                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1601                                         || ep == ep0 || !ep->ep.desc)
1602                                 goto do_stall;
1603                         if (use_dma && ep->has_dma) {
1604                                 /* this has rude side-effects (aborts) and
1605                                  * can't really work if DMA-IN is active
1606                                  */
1607                                 DBG("%s host set_halt, NYET\n", ep->name);
1608                                 goto do_stall;
1609                         }
1610                         use_ep(ep, 0);
1611                         /* can't halt if fifo isn't empty... */
1612                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1613                         omap_writew(UDC_SET_HALT, UDC_CTRL);
1614                         VDBG("%s halted by host\n", ep->name);
1615 ep0out_status_stage:
1616                         status = 0;
1617                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1618                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1619                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1620                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1621                         udc->ep0_pending = 0;
1622                         break;
1623                 case USB_REQ_GET_STATUS:
1624                         /* USB_ENDPOINT_HALT status? */
1625                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1626                                 goto intf_status;
1627
1628                         /* ep0 never stalls */
1629                         if (!(w_index & 0xf))
1630                                 goto zero_status;
1631
1632                         /* only active endpoints count */
1633                         ep = &udc->ep[w_index & 0xf];
1634                         if (w_index & USB_DIR_IN)
1635                                 ep += 16;
1636                         if (!ep->ep.desc)
1637                                 goto do_stall;
1638
1639                         /* iso never stalls */
1640                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1641                                 goto zero_status;
1642
1643                         /* FIXME don't assume non-halted endpoints!! */
1644                         ERR("%s status, can't report\n", ep->ep.name);
1645                         goto do_stall;
1646
1647 intf_status:
1648                         /* return interface status.  if we were pedantic,
1649                          * we'd detect non-existent interfaces, and stall.
1650                          */
1651                         if (u.r.bRequestType
1652                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1653                                 goto delegate;
1654
1655 zero_status:
1656                         /* return two zero bytes */
1657                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1658                         omap_writew(0, UDC_DATA);
1659                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1660                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1661                         status = 0;
1662                         VDBG("GET_STATUS, interface %d\n", w_index);
1663                         /* next, status stage */
1664                         break;
1665                 default:
1666 delegate:
1667                         /* activate the ep0out fifo right away */
1668                         if (!udc->ep0_in && w_length) {
1669                                 omap_writew(0, UDC_EP_NUM);
1670                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1671                         }
1672
1673                         /* gadget drivers see class/vendor specific requests,
1674                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1675                          * and more
1676                          */
1677                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1678                                 u.r.bRequestType, u.r.bRequest,
1679                                 w_value, w_index, w_length);
1680
1681 #undef  w_value
1682 #undef  w_index
1683 #undef  w_length
1684
1685                         /* The gadget driver may return an error here,
1686                          * causing an immediate protocol stall.
1687                          *
1688                          * Else it must issue a response, either queueing a
1689                          * response buffer for the DATA stage, or halting ep0
1690                          * (causing a protocol stall, not a real halt).  A
1691                          * zero length buffer means no DATA stage.
1692                          *
1693                          * It's fine to issue that response after the setup()
1694                          * call returns, and this IRQ was handled.
1695                          */
1696                         udc->ep0_setup = 1;
1697                         spin_unlock(&udc->lock);
1698                         status = udc->driver->setup(&udc->gadget, &u.r);
1699                         spin_lock(&udc->lock);
1700                         udc->ep0_setup = 0;
1701                 }
1702
1703                 if (status < 0) {
1704 do_stall:
1705                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1706                                         u.r.bRequestType, u.r.bRequest, status);
1707                         if (udc->ep0_set_config) {
1708                                 if (udc->ep0_reset_config)
1709                                         WARNING("error resetting config?\n");
1710                                 else
1711                                         omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1712                         }
1713                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1714                         udc->ep0_pending = 0;
1715                 }
1716         }
1717 }
1718
1719 /*-------------------------------------------------------------------------*/
1720
1721 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1722
1723 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1724 {
1725         u16     devstat, change;
1726
1727         devstat = omap_readw(UDC_DEVSTAT);
1728         change = devstat ^ udc->devstat;
1729         udc->devstat = devstat;
1730
1731         if (change & (UDC_USB_RESET|UDC_ATT)) {
1732                 udc_quiesce(udc);
1733
1734                 if (change & UDC_ATT) {
1735                         /* driver for any external transceiver will
1736                          * have called omap_vbus_session() already
1737                          */
1738                         if (devstat & UDC_ATT) {
1739                                 udc->gadget.speed = USB_SPEED_FULL;
1740                                 VDBG("connect\n");
1741                                 if (IS_ERR_OR_NULL(udc->transceiver))
1742                                         pullup_enable(udc);
1743                                 /* if (driver->connect) call it */
1744                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1745                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1746                                 if (IS_ERR_OR_NULL(udc->transceiver))
1747                                         pullup_disable(udc);
1748                                 DBG("disconnect, gadget %s\n",
1749                                         udc->driver->driver.name);
1750                                 if (udc->driver->disconnect) {
1751                                         spin_unlock(&udc->lock);
1752                                         udc->driver->disconnect(&udc->gadget);
1753                                         spin_lock(&udc->lock);
1754                                 }
1755                         }
1756                         change &= ~UDC_ATT;
1757                 }
1758
1759                 if (change & UDC_USB_RESET) {
1760                         if (devstat & UDC_USB_RESET) {
1761                                 VDBG("RESET=1\n");
1762                         } else {
1763                                 udc->gadget.speed = USB_SPEED_FULL;
1764                                 INFO("USB reset done, gadget %s\n",
1765                                         udc->driver->driver.name);
1766                                 /* ep0 traffic is legal from now on */
1767                                 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1768                                                 UDC_IRQ_EN);
1769                         }
1770                         change &= ~UDC_USB_RESET;
1771                 }
1772         }
1773         if (change & UDC_SUS) {
1774                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1775                         /* FIXME tell isp1301 to suspend/resume (?) */
1776                         if (devstat & UDC_SUS) {
1777                                 VDBG("suspend\n");
1778                                 update_otg(udc);
1779                                 /* HNP could be under way already */
1780                                 if (udc->gadget.speed == USB_SPEED_FULL
1781                                                 && udc->driver->suspend) {
1782                                         spin_unlock(&udc->lock);
1783                                         udc->driver->suspend(&udc->gadget);
1784                                         spin_lock(&udc->lock);
1785                                 }
1786                                 if (!IS_ERR_OR_NULL(udc->transceiver))
1787                                         usb_phy_set_suspend(
1788                                                         udc->transceiver, 1);
1789                         } else {
1790                                 VDBG("resume\n");
1791                                 if (!IS_ERR_OR_NULL(udc->transceiver))
1792                                         usb_phy_set_suspend(
1793                                                         udc->transceiver, 0);
1794                                 if (udc->gadget.speed == USB_SPEED_FULL
1795                                                 && udc->driver->resume) {
1796                                         spin_unlock(&udc->lock);
1797                                         udc->driver->resume(&udc->gadget);
1798                                         spin_lock(&udc->lock);
1799                                 }
1800                         }
1801                 }
1802                 change &= ~UDC_SUS;
1803         }
1804         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1805                 update_otg(udc);
1806                 change &= ~OTG_FLAGS;
1807         }
1808
1809         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1810         if (change)
1811                 VDBG("devstat %03x, ignore change %03x\n",
1812                         devstat,  change);
1813
1814         omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1815 }
1816
1817 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1818 {
1819         struct omap_udc *udc = _udc;
1820         u16             irq_src;
1821         irqreturn_t     status = IRQ_NONE;
1822         unsigned long   flags;
1823
1824         spin_lock_irqsave(&udc->lock, flags);
1825         irq_src = omap_readw(UDC_IRQ_SRC);
1826
1827         /* Device state change (usb ch9 stuff) */
1828         if (irq_src & UDC_DS_CHG) {
1829                 devstate_irq(_udc, irq_src);
1830                 status = IRQ_HANDLED;
1831                 irq_src &= ~UDC_DS_CHG;
1832         }
1833
1834         /* EP0 control transfers */
1835         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1836                 ep0_irq(_udc, irq_src);
1837                 status = IRQ_HANDLED;
1838                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1839         }
1840
1841         /* DMA transfer completion */
1842         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1843                 dma_irq(_udc, irq_src);
1844                 status = IRQ_HANDLED;
1845                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1846         }
1847
1848         irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1849         if (irq_src)
1850                 DBG("udc_irq, unhandled %03x\n", irq_src);
1851         spin_unlock_irqrestore(&udc->lock, flags);
1852
1853         return status;
1854 }
1855
1856 /* workaround for seemingly-lost IRQs for RX ACKs... */
1857 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1858 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1859
1860 static void pio_out_timer(unsigned long _ep)
1861 {
1862         struct omap_ep  *ep = (void *) _ep;
1863         unsigned long   flags;
1864         u16             stat_flg;
1865
1866         spin_lock_irqsave(&ep->udc->lock, flags);
1867         if (!list_empty(&ep->queue) && ep->ackwait) {
1868                 use_ep(ep, UDC_EP_SEL);
1869                 stat_flg = omap_readw(UDC_STAT_FLG);
1870
1871                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1872                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1873                         struct omap_req *req;
1874
1875                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1876                         req = container_of(ep->queue.next,
1877                                         struct omap_req, queue);
1878                         (void) read_fifo(ep, req);
1879                         omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1880                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1881                         ep->ackwait = 1 + ep->double_buf;
1882                 } else
1883                         deselect_ep();
1884         }
1885         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1886         spin_unlock_irqrestore(&ep->udc->lock, flags);
1887 }
1888
1889 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1890 {
1891         u16             epn_stat, irq_src;
1892         irqreturn_t     status = IRQ_NONE;
1893         struct omap_ep  *ep;
1894         int             epnum;
1895         struct omap_udc *udc = _dev;
1896         struct omap_req *req;
1897         unsigned long   flags;
1898
1899         spin_lock_irqsave(&udc->lock, flags);
1900         epn_stat = omap_readw(UDC_EPN_STAT);
1901         irq_src = omap_readw(UDC_IRQ_SRC);
1902
1903         /* handle OUT first, to avoid some wasteful NAKs */
1904         if (irq_src & UDC_EPN_RX) {
1905                 epnum = (epn_stat >> 8) & 0x0f;
1906                 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1907                 status = IRQ_HANDLED;
1908                 ep = &udc->ep[epnum];
1909                 ep->irqs++;
1910
1911                 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1912                 ep->fnf = 0;
1913                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1914                         ep->ackwait--;
1915                         if (!list_empty(&ep->queue)) {
1916                                 int stat;
1917                                 req = container_of(ep->queue.next,
1918                                                 struct omap_req, queue);
1919                                 stat = read_fifo(ep, req);
1920                                 if (!ep->double_buf)
1921                                         ep->fnf = 1;
1922                         }
1923                 }
1924                 /* min 6 clock delay before clearing EP_SEL ... */
1925                 epn_stat = omap_readw(UDC_EPN_STAT);
1926                 epn_stat = omap_readw(UDC_EPN_STAT);
1927                 omap_writew(epnum, UDC_EP_NUM);
1928
1929                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1930                  * reduces lossage; timer still needed though (sigh).
1931                  */
1932                 if (ep->fnf) {
1933                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1934                         ep->ackwait = 1 + ep->double_buf;
1935                 }
1936                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1937         }
1938
1939         /* then IN transfers */
1940         else if (irq_src & UDC_EPN_TX) {
1941                 epnum = epn_stat & 0x0f;
1942                 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1943                 status = IRQ_HANDLED;
1944                 ep = &udc->ep[16 + epnum];
1945                 ep->irqs++;
1946
1947                 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1948                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1949                         ep->ackwait = 0;
1950                         if (!list_empty(&ep->queue)) {
1951                                 req = container_of(ep->queue.next,
1952                                                 struct omap_req, queue);
1953                                 (void) write_fifo(ep, req);
1954                         }
1955                 }
1956                 /* min 6 clock delay before clearing EP_SEL ... */
1957                 epn_stat = omap_readw(UDC_EPN_STAT);
1958                 epn_stat = omap_readw(UDC_EPN_STAT);
1959                 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1960                 /* then 6 clocks before it'd tx */
1961         }
1962
1963         spin_unlock_irqrestore(&udc->lock, flags);
1964         return status;
1965 }
1966
1967 #ifdef  USE_ISO
1968 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1969 {
1970         struct omap_udc *udc = _dev;
1971         struct omap_ep  *ep;
1972         int             pending = 0;
1973         unsigned long   flags;
1974
1975         spin_lock_irqsave(&udc->lock, flags);
1976
1977         /* handle all non-DMA ISO transfers */
1978         list_for_each_entry(ep, &udc->iso, iso) {
1979                 u16             stat;
1980                 struct omap_req *req;
1981
1982                 if (ep->has_dma || list_empty(&ep->queue))
1983                         continue;
1984                 req = list_entry(ep->queue.next, struct omap_req, queue);
1985
1986                 use_ep(ep, UDC_EP_SEL);
1987                 stat = omap_readw(UDC_STAT_FLG);
1988
1989                 /* NOTE: like the other controller drivers, this isn't
1990                  * currently reporting lost or damaged frames.
1991                  */
1992                 if (ep->bEndpointAddress & USB_DIR_IN) {
1993                         if (stat & UDC_MISS_IN)
1994                                 /* done(ep, req, -EPROTO) */;
1995                         else
1996                                 write_fifo(ep, req);
1997                 } else {
1998                         int     status = 0;
1999
2000                         if (stat & UDC_NO_RXPACKET)
2001                                 status = -EREMOTEIO;
2002                         else if (stat & UDC_ISO_ERR)
2003                                 status = -EILSEQ;
2004                         else if (stat & UDC_DATA_FLUSH)
2005                                 status = -ENOSR;
2006
2007                         if (status)
2008                                 /* done(ep, req, status) */;
2009                         else
2010                                 read_fifo(ep, req);
2011                 }
2012                 deselect_ep();
2013                 /* 6 wait states before next EP */
2014
2015                 ep->irqs++;
2016                 if (!list_empty(&ep->queue))
2017                         pending = 1;
2018         }
2019         if (!pending) {
2020                 u16 w;
2021
2022                 w = omap_readw(UDC_IRQ_EN);
2023                 w &= ~UDC_SOF_IE;
2024                 omap_writew(w, UDC_IRQ_EN);
2025         }
2026         omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2027
2028         spin_unlock_irqrestore(&udc->lock, flags);
2029         return IRQ_HANDLED;
2030 }
2031 #endif
2032
2033 /*-------------------------------------------------------------------------*/
2034
2035 static inline int machine_without_vbus_sense(void)
2036 {
2037         return machine_is_omap_innovator()
2038                 || machine_is_omap_osk()
2039                 || machine_is_sx1()
2040                 /* No known omap7xx boards with vbus sense */
2041                 || cpu_is_omap7xx();
2042 }
2043
2044 static int omap_udc_start(struct usb_gadget_driver *driver,
2045                 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *))
2046 {
2047         int             status = -ENODEV;
2048         struct omap_ep  *ep;
2049         unsigned long   flags;
2050
2051         /* basic sanity tests */
2052         if (!udc)
2053                 return -ENODEV;
2054         if (!driver
2055                         /* FIXME if otg, check:  driver->is_otg */
2056                         || driver->max_speed < USB_SPEED_FULL
2057                         || !bind || !driver->setup)
2058                 return -EINVAL;
2059
2060         spin_lock_irqsave(&udc->lock, flags);
2061         if (udc->driver) {
2062                 spin_unlock_irqrestore(&udc->lock, flags);
2063                 return -EBUSY;
2064         }
2065
2066         /* reset state */
2067         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2068                 ep->irqs = 0;
2069                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2070                         continue;
2071                 use_ep(ep, 0);
2072                 omap_writew(UDC_SET_HALT, UDC_CTRL);
2073         }
2074         udc->ep0_pending = 0;
2075         udc->ep[0].irqs = 0;
2076         udc->softconnect = 1;
2077
2078         /* hook up the driver */
2079         driver->driver.bus = NULL;
2080         udc->driver = driver;
2081         udc->gadget.dev.driver = &driver->driver;
2082         spin_unlock_irqrestore(&udc->lock, flags);
2083
2084         if (udc->dc_clk != NULL)
2085                 omap_udc_enable_clock(1);
2086
2087         status = bind(&udc->gadget, driver);
2088         if (status) {
2089                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2090                 udc->gadget.dev.driver = NULL;
2091                 udc->driver = NULL;
2092                 goto done;
2093         }
2094         DBG("bound to driver %s\n", driver->driver.name);
2095
2096         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2097
2098         /* connect to bus through transceiver */
2099         if (!IS_ERR_OR_NULL(udc->transceiver)) {
2100                 status = otg_set_peripheral(udc->transceiver->otg,
2101                                                 &udc->gadget);
2102                 if (status < 0) {
2103                         ERR("can't bind to transceiver\n");
2104                         if (driver->unbind) {
2105                                 driver->unbind(&udc->gadget);
2106                                 udc->gadget.dev.driver = NULL;
2107                                 udc->driver = NULL;
2108                         }
2109                         goto done;
2110                 }
2111         } else {
2112                 if (can_pullup(udc))
2113                         pullup_enable(udc);
2114                 else
2115                         pullup_disable(udc);
2116         }
2117
2118         /* boards that don't have VBUS sensing can't autogate 48MHz;
2119          * can't enter deep sleep while a gadget driver is active.
2120          */
2121         if (machine_without_vbus_sense())
2122                 omap_vbus_session(&udc->gadget, 1);
2123
2124 done:
2125         if (udc->dc_clk != NULL)
2126                 omap_udc_enable_clock(0);
2127         return status;
2128 }
2129
2130 static int omap_udc_stop(struct usb_gadget_driver *driver)
2131 {
2132         unsigned long   flags;
2133         int             status = -ENODEV;
2134
2135         if (!udc)
2136                 return -ENODEV;
2137         if (!driver || driver != udc->driver || !driver->unbind)
2138                 return -EINVAL;
2139
2140         if (udc->dc_clk != NULL)
2141                 omap_udc_enable_clock(1);
2142
2143         if (machine_without_vbus_sense())
2144                 omap_vbus_session(&udc->gadget, 0);
2145
2146         if (!IS_ERR_OR_NULL(udc->transceiver))
2147                 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2148         else
2149                 pullup_disable(udc);
2150
2151         spin_lock_irqsave(&udc->lock, flags);
2152         udc_quiesce(udc);
2153         spin_unlock_irqrestore(&udc->lock, flags);
2154
2155         driver->unbind(&udc->gadget);
2156         udc->gadget.dev.driver = NULL;
2157         udc->driver = NULL;
2158
2159         if (udc->dc_clk != NULL)
2160                 omap_udc_enable_clock(0);
2161         DBG("unregistered driver '%s'\n", driver->driver.name);
2162         return status;
2163 }
2164
2165 /*-------------------------------------------------------------------------*/
2166
2167 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2168
2169 #include <linux/seq_file.h>
2170
2171 static const char proc_filename[] = "driver/udc";
2172
2173 #define FOURBITS "%s%s%s%s"
2174 #define EIGHTBITS "%s%s%s%s%s%s%s%s"
2175
2176 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2177 {
2178         u16             stat_flg;
2179         struct omap_req *req;
2180         char            buf[20];
2181
2182         use_ep(ep, 0);
2183
2184         if (use_dma && ep->has_dma)
2185                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2186                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2187                         ep->dma_channel - 1, ep->lch);
2188         else
2189                 buf[0] = 0;
2190
2191         stat_flg = omap_readw(UDC_STAT_FLG);
2192         seq_printf(s,
2193                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2194                 ep->name, buf,
2195                 ep->double_buf ? "dbuf " : "",
2196                 ({ char *s;
2197                 switch (ep->ackwait) {
2198                 case 0:
2199                         s = "";
2200                         break;
2201                 case 1:
2202                         s = "(ackw) ";
2203                         break;
2204                 case 2:
2205                         s = "(ackw2) ";
2206                         break;
2207                 default:
2208                         s = "(?) ";
2209                         break;
2210                 } s; }),
2211                 ep->irqs, stat_flg,
2212                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2213                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2214                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2215                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2216                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2217                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2218                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2219                 (stat_flg & UDC_STALL) ? "STALL " : "",
2220                 (stat_flg & UDC_NAK) ? "NAK " : "",
2221                 (stat_flg & UDC_ACK) ? "ACK " : "",
2222                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2223                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2224                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2225
2226         if (list_empty(&ep->queue))
2227                 seq_printf(s, "\t(queue empty)\n");
2228         else
2229                 list_for_each_entry(req, &ep->queue, queue) {
2230                         unsigned        length = req->req.actual;
2231
2232                         if (use_dma && buf[0]) {
2233                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2234                                                 ? dma_src_len : dma_dest_len)
2235                                         (ep, req->req.dma + length);
2236                                 buf[0] = 0;
2237                         }
2238                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2239                                         &req->req, length,
2240                                         req->req.length, req->req.buf);
2241                 }
2242 }
2243
2244 static char *trx_mode(unsigned m, int enabled)
2245 {
2246         switch (m) {
2247         case 0:
2248                 return enabled ? "*6wire" : "unused";
2249         case 1:
2250                 return "4wire";
2251         case 2:
2252                 return "3wire";
2253         case 3:
2254                 return "6wire";
2255         default:
2256                 return "unknown";
2257         }
2258 }
2259
2260 static int proc_otg_show(struct seq_file *s)
2261 {
2262         u32             tmp;
2263         u32             trans = 0;
2264         char            *ctrl_name = "(UNKNOWN)";
2265
2266         tmp = omap_readl(OTG_REV);
2267         ctrl_name = "tranceiver_ctrl";
2268         trans = omap_readw(USB_TRANSCEIVER_CTRL);
2269         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2270                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2271         tmp = omap_readw(OTG_SYSCON_1);
2272         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2273                         FOURBITS "\n", tmp,
2274                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2275                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2276                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2277                         ? "internal"
2278                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2279                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2280                 (tmp & HST_IDLE_EN) ? " !host" : "",
2281                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2282                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2283         tmp = omap_readl(OTG_SYSCON_2);
2284         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2285                         " b_ase_brst=%d hmc=%d\n", tmp,
2286                 (tmp & OTG_EN) ? " otg_en" : "",
2287                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2288                 /* much more SRP stuff */
2289                 (tmp & SRP_DATA) ? " srp_data" : "",
2290                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2291                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2292                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2293                 (tmp & UHOST_EN) ? " uhost_en" : "",
2294                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2295                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2296                 B_ASE_BRST(tmp),
2297                 OTG_HMC(tmp));
2298         tmp = omap_readl(OTG_CTRL);
2299         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2300                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2301                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2302                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2303                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2304                 (tmp & OTG_ID) ? " id" : "",
2305                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2306                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2307                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2308                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2309                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2310                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2311                 (tmp & OTG_PULLDOWN) ? " down" : "",
2312                 (tmp & OTG_PULLUP) ? " up" : "",
2313                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2314                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2315                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2316                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2317                 );
2318         tmp = omap_readw(OTG_IRQ_EN);
2319         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2320         tmp = omap_readw(OTG_IRQ_SRC);
2321         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2322         tmp = omap_readw(OTG_OUTCTRL);
2323         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2324         tmp = omap_readw(OTG_TEST);
2325         seq_printf(s, "otg_test    %04x" "\n", tmp);
2326         return 0;
2327 }
2328
2329 static int proc_udc_show(struct seq_file *s, void *_)
2330 {
2331         u32             tmp;
2332         struct omap_ep  *ep;
2333         unsigned long   flags;
2334
2335         spin_lock_irqsave(&udc->lock, flags);
2336
2337         seq_printf(s, "%s, version: " DRIVER_VERSION
2338 #ifdef  USE_ISO
2339                 " (iso)"
2340 #endif
2341                 "%s\n",
2342                 driver_desc,
2343                 use_dma ?  " (dma)" : "");
2344
2345         tmp = omap_readw(UDC_REV) & 0xff;
2346         seq_printf(s,
2347                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2348                 "hmc %d, transceiver %s\n",
2349                 tmp >> 4, tmp & 0xf,
2350                 fifo_mode,
2351                 udc->driver ? udc->driver->driver.name : "(none)",
2352                 HMC,
2353                 udc->transceiver
2354                         ? udc->transceiver->label
2355                         : (cpu_is_omap1710()
2356                                 ? "external" : "(none)"));
2357         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2358                 omap_readw(ULPD_CLOCK_CTRL),
2359                 omap_readw(ULPD_SOFT_REQ),
2360                 omap_readw(ULPD_STATUS_REQ));
2361
2362         /* OTG controller registers */
2363         if (!cpu_is_omap15xx())
2364                 proc_otg_show(s);
2365
2366         tmp = omap_readw(UDC_SYSCON1);
2367         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2368                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2369                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2370                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2371                 (tmp & UDC_NAK_EN) ? " nak" : "",
2372                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2373                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2374                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2375                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2376         /* syscon2 is write-only */
2377
2378         /* UDC controller registers */
2379         if (!(tmp & UDC_PULLUP_EN)) {
2380                 seq_printf(s, "(suspended)\n");
2381                 spin_unlock_irqrestore(&udc->lock, flags);
2382                 return 0;
2383         }
2384
2385         tmp = omap_readw(UDC_DEVSTAT);
2386         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2387                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2388                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2389                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2390                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2391                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2392                 (tmp & UDC_SUS) ? " SUS" : "",
2393                 (tmp & UDC_CFG) ? " CFG" : "",
2394                 (tmp & UDC_ADD) ? " ADD" : "",
2395                 (tmp & UDC_DEF) ? " DEF" : "",
2396                 (tmp & UDC_ATT) ? " ATT" : "");
2397         seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2398         tmp = omap_readw(UDC_IRQ_EN);
2399         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2400                 (tmp & UDC_SOF_IE) ? " sof" : "",
2401                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2402                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2403                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2404                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2405         tmp = omap_readw(UDC_IRQ_SRC);
2406         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2407                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2408                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2409                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2410                 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2411                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2412                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2413                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2414                 (tmp & UDC_SETUP) ? " setup" : "",
2415                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2416                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2417         if (use_dma) {
2418                 unsigned i;
2419
2420                 tmp = omap_readw(UDC_DMA_IRQ_EN);
2421                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2422                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2423                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2424                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2425
2426                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2427                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2428                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2429
2430                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2431                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2432                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2433
2434                 tmp = omap_readw(UDC_RXDMA_CFG);
2435                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2436                 if (tmp) {
2437                         for (i = 0; i < 3; i++) {
2438                                 if ((tmp & (0x0f << (i * 4))) == 0)
2439                                         continue;
2440                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2441                                                 omap_readw(UDC_RXDMA(i + 1)));
2442                         }
2443                 }
2444                 tmp = omap_readw(UDC_TXDMA_CFG);
2445                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2446                 if (tmp) {
2447                         for (i = 0; i < 3; i++) {
2448                                 if (!(tmp & (0x0f << (i * 4))))
2449                                         continue;
2450                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2451                                                 omap_readw(UDC_TXDMA(i + 1)));
2452                         }
2453                 }
2454         }
2455
2456         tmp = omap_readw(UDC_DEVSTAT);
2457         if (tmp & UDC_ATT) {
2458                 proc_ep_show(s, &udc->ep[0]);
2459                 if (tmp & UDC_ADD) {
2460                         list_for_each_entry(ep, &udc->gadget.ep_list,
2461                                         ep.ep_list) {
2462                                 if (ep->ep.desc)
2463                                         proc_ep_show(s, ep);
2464                         }
2465                 }
2466         }
2467         spin_unlock_irqrestore(&udc->lock, flags);
2468         return 0;
2469 }
2470
2471 static int proc_udc_open(struct inode *inode, struct file *file)
2472 {
2473         return single_open(file, proc_udc_show, NULL);
2474 }
2475
2476 static const struct file_operations proc_ops = {
2477         .owner          = THIS_MODULE,
2478         .open           = proc_udc_open,
2479         .read           = seq_read,
2480         .llseek         = seq_lseek,
2481         .release        = single_release,
2482 };
2483
2484 static void create_proc_file(void)
2485 {
2486         proc_create(proc_filename, 0, NULL, &proc_ops);
2487 }
2488
2489 static void remove_proc_file(void)
2490 {
2491         remove_proc_entry(proc_filename, NULL);
2492 }
2493
2494 #else
2495
2496 static inline void create_proc_file(void) {}
2497 static inline void remove_proc_file(void) {}
2498
2499 #endif
2500
2501 /*-------------------------------------------------------------------------*/
2502
2503 /* Before this controller can enumerate, we need to pick an endpoint
2504  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2505  * buffer space among the endpoints we'll be operating.
2506  *
2507  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2508  * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2509  * capability yet though.
2510  */
2511 static unsigned __devinit
2512 omap_ep_setup(char *name, u8 addr, u8 type,
2513                 unsigned buf, unsigned maxp, int dbuf)
2514 {
2515         struct omap_ep  *ep;
2516         u16             epn_rxtx = 0;
2517
2518         /* OUT endpoints first, then IN */
2519         ep = &udc->ep[addr & 0xf];
2520         if (addr & USB_DIR_IN)
2521                 ep += 16;
2522
2523         /* in case of ep init table bugs */
2524         BUG_ON(ep->name[0]);
2525
2526         /* chip setup ... bit values are same for IN, OUT */
2527         if (type == USB_ENDPOINT_XFER_ISOC) {
2528                 switch (maxp) {
2529                 case 8:
2530                         epn_rxtx = 0 << 12;
2531                         break;
2532                 case 16:
2533                         epn_rxtx = 1 << 12;
2534                         break;
2535                 case 32:
2536                         epn_rxtx = 2 << 12;
2537                         break;
2538                 case 64:
2539                         epn_rxtx = 3 << 12;
2540                         break;
2541                 case 128:
2542                         epn_rxtx = 4 << 12;
2543                         break;
2544                 case 256:
2545                         epn_rxtx = 5 << 12;
2546                         break;
2547                 case 512:
2548                         epn_rxtx = 6 << 12;
2549                         break;
2550                 default:
2551                         BUG();
2552                 }
2553                 epn_rxtx |= UDC_EPN_RX_ISO;
2554                 dbuf = 1;
2555         } else {
2556                 /* double-buffering "not supported" on 15xx,
2557                  * and ignored for PIO-IN on newer chips
2558                  * (for more reliable behavior)
2559                  */
2560                 if (!use_dma || cpu_is_omap15xx())
2561                         dbuf = 0;
2562
2563                 switch (maxp) {
2564                 case 8:
2565                         epn_rxtx = 0 << 12;
2566                         break;
2567                 case 16:
2568                         epn_rxtx = 1 << 12;
2569                         break;
2570                 case 32:
2571                         epn_rxtx = 2 << 12;
2572                         break;
2573                 case 64:
2574                         epn_rxtx = 3 << 12;
2575                         break;
2576                 default:
2577                         BUG();
2578                 }
2579                 if (dbuf && addr)
2580                         epn_rxtx |= UDC_EPN_RX_DB;
2581                 init_timer(&ep->timer);
2582                 ep->timer.function = pio_out_timer;
2583                 ep->timer.data = (unsigned long) ep;
2584         }
2585         if (addr)
2586                 epn_rxtx |= UDC_EPN_RX_VALID;
2587         BUG_ON(buf & 0x07);
2588         epn_rxtx |= buf >> 3;
2589
2590         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2591                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2592
2593         if (addr & USB_DIR_IN)
2594                 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2595         else
2596                 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2597
2598         /* next endpoint's buffer starts after this one's */
2599         buf += maxp;
2600         if (dbuf)
2601                 buf += maxp;
2602         BUG_ON(buf > 2048);
2603
2604         /* set up driver data structures */
2605         BUG_ON(strlen(name) >= sizeof ep->name);
2606         strlcpy(ep->name, name, sizeof ep->name);
2607         INIT_LIST_HEAD(&ep->queue);
2608         INIT_LIST_HEAD(&ep->iso);
2609         ep->bEndpointAddress = addr;
2610         ep->bmAttributes = type;
2611         ep->double_buf = dbuf;
2612         ep->udc = udc;
2613
2614         ep->ep.name = ep->name;
2615         ep->ep.ops = &omap_ep_ops;
2616         ep->ep.maxpacket = ep->maxpacket = maxp;
2617         list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2618
2619         return buf;
2620 }
2621
2622 static void omap_udc_release(struct device *dev)
2623 {
2624         complete(udc->done);
2625         kfree(udc);
2626         udc = NULL;
2627 }
2628
2629 static int __devinit
2630 omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2631 {
2632         unsigned        tmp, buf;
2633
2634         /* abolish any previous hardware state */
2635         omap_writew(0, UDC_SYSCON1);
2636         omap_writew(0, UDC_IRQ_EN);
2637         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2638         omap_writew(0, UDC_DMA_IRQ_EN);
2639         omap_writew(0, UDC_RXDMA_CFG);
2640         omap_writew(0, UDC_TXDMA_CFG);
2641
2642         /* UDC_PULLUP_EN gates the chip clock */
2643         /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2644
2645         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2646         if (!udc)
2647                 return -ENOMEM;
2648
2649         spin_lock_init(&udc->lock);
2650
2651         udc->gadget.ops = &omap_gadget_ops;
2652         udc->gadget.ep0 = &udc->ep[0].ep;
2653         INIT_LIST_HEAD(&udc->gadget.ep_list);
2654         INIT_LIST_HEAD(&udc->iso);
2655         udc->gadget.speed = USB_SPEED_UNKNOWN;
2656         udc->gadget.max_speed = USB_SPEED_FULL;
2657         udc->gadget.name = driver_name;
2658
2659         device_initialize(&udc->gadget.dev);
2660         dev_set_name(&udc->gadget.dev, "gadget");
2661         udc->gadget.dev.release = omap_udc_release;
2662         udc->gadget.dev.parent = &odev->dev;
2663         if (use_dma)
2664                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2665
2666         udc->transceiver = xceiv;
2667
2668         /* ep0 is special; put it right after the SETUP buffer */
2669         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2670                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2671         list_del_init(&udc->ep[0].ep.ep_list);
2672
2673         /* initially disable all non-ep0 endpoints */
2674         for (tmp = 1; tmp < 15; tmp++) {
2675                 omap_writew(0, UDC_EP_RX(tmp));
2676                 omap_writew(0, UDC_EP_TX(tmp));
2677         }
2678
2679 #define OMAP_BULK_EP(name, addr) \
2680         buf = omap_ep_setup(name "-bulk", addr, \
2681                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2682 #define OMAP_INT_EP(name, addr, maxp) \
2683         buf = omap_ep_setup(name "-int", addr, \
2684                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2685 #define OMAP_ISO_EP(name, addr, maxp) \
2686         buf = omap_ep_setup(name "-iso", addr, \
2687                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2688
2689         switch (fifo_mode) {
2690         case 0:
2691                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2692                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2693                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2694                 break;
2695         case 1:
2696                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2697                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2698                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2699
2700                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2701                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2702                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2703
2704                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2705                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2706                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2707
2708                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2709                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2710                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2711
2712                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2713                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2714                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2715                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2716
2717                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2718                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2719                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2720                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2721
2722                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2723                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2724
2725                 break;
2726
2727 #ifdef  USE_ISO
2728         case 2:                 /* mixed iso/bulk */
2729                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2730                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2731                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2732                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2733
2734                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2735
2736                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2737                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2738                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2739                 break;
2740         case 3:                 /* mixed bulk/iso */
2741                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2742                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2743                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2744
2745                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2746                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2747                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2748
2749                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2750                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2751                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2752                 break;
2753 #endif
2754
2755         /* add more modes as needed */
2756
2757         default:
2758                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2759                 return -ENODEV;
2760         }
2761         omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2762         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2763         return 0;
2764 }
2765
2766 static int __devinit omap_udc_probe(struct platform_device *pdev)
2767 {
2768         int                     status = -ENODEV;
2769         int                     hmc;
2770         struct usb_phy          *xceiv = NULL;
2771         const char              *type = NULL;
2772         struct omap_usb_config  *config = pdev->dev.platform_data;
2773         struct clk              *dc_clk = NULL;
2774         struct clk              *hhc_clk = NULL;
2775
2776         if (cpu_is_omap7xx())
2777                 use_dma = 0;
2778
2779         /* NOTE:  "knows" the order of the resources! */
2780         if (!request_mem_region(pdev->resource[0].start,
2781                         pdev->resource[0].end - pdev->resource[0].start + 1,
2782                         driver_name)) {
2783                 DBG("request_mem_region failed\n");
2784                 return -EBUSY;
2785         }
2786
2787         if (cpu_is_omap16xx()) {
2788                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2789                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2790                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2791                 /* can't use omap_udc_enable_clock yet */
2792                 clk_enable(dc_clk);
2793                 clk_enable(hhc_clk);
2794                 udelay(100);
2795         }
2796
2797         if (cpu_is_omap7xx()) {
2798                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2799                 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2800                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2801                 /* can't use omap_udc_enable_clock yet */
2802                 clk_enable(dc_clk);
2803                 clk_enable(hhc_clk);
2804                 udelay(100);
2805         }
2806
2807         INFO("OMAP UDC rev %d.%d%s\n",
2808                 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2809                 config->otg ? ", Mini-AB" : "");
2810
2811         /* use the mode given to us by board init code */
2812         if (cpu_is_omap15xx()) {
2813                 hmc = HMC_1510;
2814                 type = "(unknown)";
2815
2816                 if (machine_without_vbus_sense()) {
2817                         /* just set up software VBUS detect, and then
2818                          * later rig it so we always report VBUS.
2819                          * FIXME without really sensing VBUS, we can't
2820                          * know when to turn PULLUP_EN on/off; and that
2821                          * means we always "need" the 48MHz clock.
2822                          */
2823                         u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2824                         tmp &= ~VBUS_CTRL_1510;
2825                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2826                         tmp |= VBUS_MODE_1510;
2827                         tmp &= ~VBUS_CTRL_1510;
2828                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2829                 }
2830         } else {
2831                 /* The transceiver may package some GPIO logic or handle
2832                  * loopback and/or transceiverless setup; if we find one,
2833                  * use it.  Except for OTG, we don't _need_ to talk to one;
2834                  * but not having one probably means no VBUS detection.
2835                  */
2836                 xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2837                 if (!IS_ERR_OR_NULL(xceiv))
2838                         type = xceiv->label;
2839                 else if (config->otg) {
2840                         DBG("OTG requires external transceiver!\n");
2841                         goto cleanup0;
2842                 }
2843
2844                 hmc = HMC_1610;
2845
2846                 switch (hmc) {
2847                 case 0:                 /* POWERUP DEFAULT == 0 */
2848                 case 4:
2849                 case 12:
2850                 case 20:
2851                         if (!cpu_is_omap1710()) {
2852                                 type = "integrated";
2853                                 break;
2854                         }
2855                         /* FALL THROUGH */
2856                 case 3:
2857                 case 11:
2858                 case 16:
2859                 case 19:
2860                 case 25:
2861                         if (IS_ERR_OR_NULL(xceiv)) {
2862                                 DBG("external transceiver not registered!\n");
2863                                 type = "unknown";
2864                         }
2865                         break;
2866                 case 21:                        /* internal loopback */
2867                         type = "loopback";
2868                         break;
2869                 case 14:                        /* transceiverless */
2870                         if (cpu_is_omap1710())
2871                                 goto bad_on_1710;
2872                         /* FALL THROUGH */
2873                 case 13:
2874                 case 15:
2875                         type = "no";
2876                         break;
2877
2878                 default:
2879 bad_on_1710:
2880                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2881                         goto cleanup0;
2882                 }
2883         }
2884
2885         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2886
2887         /* a "gadget" abstracts/virtualizes the controller */
2888         status = omap_udc_setup(pdev, xceiv);
2889         if (status)
2890                 goto cleanup0;
2891
2892         xceiv = NULL;
2893         /* "udc" is now valid */
2894         pullup_disable(udc);
2895 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2896         udc->gadget.is_otg = (config->otg != 0);
2897 #endif
2898
2899         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2900         if (omap_readw(UDC_REV) >= 0x61)
2901                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2902         else
2903                 udc->clr_halt = UDC_RESET_EP;
2904
2905         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2906         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2907                         0, driver_name, udc);
2908         if (status != 0) {
2909                 ERR("can't get irq %d, err %d\n",
2910                         (int) pdev->resource[1].start, status);
2911                 goto cleanup1;
2912         }
2913
2914         /* USB "non-iso" IRQ (PIO for all but ep0) */
2915         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2916                         0, "omap_udc pio", udc);
2917         if (status != 0) {
2918                 ERR("can't get irq %d, err %d\n",
2919                         (int) pdev->resource[2].start, status);
2920                 goto cleanup2;
2921         }
2922 #ifdef  USE_ISO
2923         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2924                         0, "omap_udc iso", udc);
2925         if (status != 0) {
2926                 ERR("can't get irq %d, err %d\n",
2927                         (int) pdev->resource[3].start, status);
2928                 goto cleanup3;
2929         }
2930 #endif
2931         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2932                 udc->dc_clk = dc_clk;
2933                 udc->hhc_clk = hhc_clk;
2934                 clk_disable(hhc_clk);
2935                 clk_disable(dc_clk);
2936         }
2937
2938         create_proc_file();
2939         status = device_add(&udc->gadget.dev);
2940         if (status)
2941                 goto cleanup4;
2942
2943         status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2944         if (!status)
2945                 return status;
2946         /* If fail, fall through */
2947 cleanup4:
2948         remove_proc_file();
2949
2950 #ifdef  USE_ISO
2951 cleanup3:
2952         free_irq(pdev->resource[2].start, udc);
2953 #endif
2954
2955 cleanup2:
2956         free_irq(pdev->resource[1].start, udc);
2957
2958 cleanup1:
2959         kfree(udc);
2960         udc = NULL;
2961
2962 cleanup0:
2963         if (!IS_ERR_OR_NULL(xceiv))
2964                 usb_put_phy(xceiv);
2965
2966         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2967                 clk_disable(hhc_clk);
2968                 clk_disable(dc_clk);
2969                 clk_put(hhc_clk);
2970                 clk_put(dc_clk);
2971         }
2972
2973         release_mem_region(pdev->resource[0].start,
2974                         pdev->resource[0].end - pdev->resource[0].start + 1);
2975
2976         return status;
2977 }
2978
2979 static int __devexit omap_udc_remove(struct platform_device *pdev)
2980 {
2981         DECLARE_COMPLETION_ONSTACK(done);
2982
2983         if (!udc)
2984                 return -ENODEV;
2985
2986         usb_del_gadget_udc(&udc->gadget);
2987         if (udc->driver)
2988                 return -EBUSY;
2989
2990         udc->done = &done;
2991
2992         pullup_disable(udc);
2993         if (!IS_ERR_OR_NULL(udc->transceiver)) {
2994                 usb_put_phy(udc->transceiver);
2995                 udc->transceiver = NULL;
2996         }
2997         omap_writew(0, UDC_SYSCON1);
2998
2999         remove_proc_file();
3000
3001 #ifdef  USE_ISO
3002         free_irq(pdev->resource[3].start, udc);
3003 #endif
3004         free_irq(pdev->resource[2].start, udc);
3005         free_irq(pdev->resource[1].start, udc);
3006
3007         if (udc->dc_clk) {
3008                 if (udc->clk_requested)
3009                         omap_udc_enable_clock(0);
3010                 clk_put(udc->hhc_clk);
3011                 clk_put(udc->dc_clk);
3012         }
3013
3014         release_mem_region(pdev->resource[0].start,
3015                         pdev->resource[0].end - pdev->resource[0].start + 1);
3016
3017         device_unregister(&udc->gadget.dev);
3018         wait_for_completion(&done);
3019
3020         return 0;
3021 }
3022
3023 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3024  * system is forced into deep sleep
3025  *
3026  * REVISIT we should probably reject suspend requests when there's a host
3027  * session active, rather than disconnecting, at least on boards that can
3028  * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
3029  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3030  * may involve talking to an external transceiver (e.g. isp1301).
3031  */
3032
3033 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3034 {
3035         u32     devstat;
3036
3037         devstat = omap_readw(UDC_DEVSTAT);
3038
3039         /* we're requesting 48 MHz clock if the pullup is enabled
3040          * (== we're attached to the host) and we're not suspended,
3041          * which would prevent entry to deep sleep...
3042          */
3043         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3044                 WARNING("session active; suspend requires disconnect\n");
3045                 omap_pullup(&udc->gadget, 0);
3046         }
3047
3048         return 0;
3049 }
3050
3051 static int omap_udc_resume(struct platform_device *dev)
3052 {
3053         DBG("resume + wakeup/SRP\n");
3054         omap_pullup(&udc->gadget, 1);
3055
3056         /* maybe the host would enumerate us if we nudged it */
3057         msleep(100);
3058         return omap_wakeup(&udc->gadget);
3059 }
3060
3061 /*-------------------------------------------------------------------------*/
3062
3063 static struct platform_driver udc_driver = {
3064         .probe          = omap_udc_probe,
3065         .remove         = __devexit_p(omap_udc_remove),
3066         .suspend        = omap_udc_suspend,
3067         .resume         = omap_udc_resume,
3068         .driver         = {
3069                 .owner  = THIS_MODULE,
3070                 .name   = (char *) driver_name,
3071         },
3072 };
3073
3074 module_platform_driver(udc_driver);
3075
3076 MODULE_DESCRIPTION(DRIVER_DESC);
3077 MODULE_LICENSE("GPL");
3078 MODULE_ALIAS("platform:omap_udc");