2a4749c3eb3f7bd7679f768ca5cdab27de0db72f
[muen/linux.git] / drivers / usb / gadget / omap_udc.c
1 /*
2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3  *
4  * Copyright (C) 2004 Texas Instruments, Inc.
5  * Copyright (C) 2004-2005 David Brownell
6  *
7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  */
14
15 #undef  DEBUG
16 #undef  VERBOSE
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/timer.h>
27 #include <linux/list.h>
28 #include <linux/interrupt.h>
29 #include <linux/proc_fs.h>
30 #include <linux/mm.h>
31 #include <linux/moduleparam.h>
32 #include <linux/platform_device.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/otg.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/prefetch.h>
40 #include <linux/io.h>
41
42 #include <asm/byteorder.h>
43 #include <asm/irq.h>
44 #include <asm/unaligned.h>
45 #include <asm/mach-types.h>
46
47 #include <plat/dma.h>
48
49 #include <mach/usb.h>
50
51 #include "omap_udc.h"
52
53 #undef  USB_TRACE
54
55 /* bulk DMA seems to be behaving for both IN and OUT */
56 #define USE_DMA
57
58 /* ISO too */
59 #define USE_ISO
60
61 #define DRIVER_DESC     "OMAP UDC driver"
62 #define DRIVER_VERSION  "4 October 2004"
63
64 /*
65  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
66  * D+ pullup to allow enumeration.  That's too early for the gadget
67  * framework to use from usb_endpoint_enable(), which happens after
68  * enumeration as part of activating an interface.  (But if we add an
69  * optional new "UDC not yet running" state to the gadget driver model,
70  * even just during driver binding, the endpoint autoconfig logic is the
71  * natural spot to manufacture new endpoints.)
72  *
73  * So instead of using endpoint enable calls to control the hardware setup,
74  * this driver defines a "fifo mode" parameter.  It's used during driver
75  * initialization to choose among a set of pre-defined endpoint configs.
76  * See omap_udc_setup() for available modes, or to add others.  That code
77  * lives in an init section, so use this driver as a module if you need
78  * to change the fifo mode after the kernel boots.
79  *
80  * Gadget drivers normally ignore endpoints they don't care about, and
81  * won't include them in configuration descriptors.  That means only
82  * misbehaving hosts would even notice they exist.
83  */
84 #ifdef  USE_ISO
85 static unsigned fifo_mode = 3;
86 #else
87 static unsigned fifo_mode;
88 #endif
89
90 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
91  * boot parameter "omap_udc:fifo_mode=42"
92  */
93 module_param(fifo_mode, uint, 0);
94 MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
95
96 #ifdef  USE_DMA
97 static bool use_dma = 1;
98
99 /* "modprobe omap_udc use_dma=y", or else as a kernel
100  * boot parameter "omap_udc:use_dma=y"
101  */
102 module_param(use_dma, bool, 0);
103 MODULE_PARM_DESC(use_dma, "enable/disable DMA");
104 #else   /* !USE_DMA */
105
106 /* save a bit of code */
107 #define use_dma         0
108 #endif  /* !USE_DMA */
109
110
111 static const char driver_name[] = "omap_udc";
112 static const char driver_desc[] = DRIVER_DESC;
113
114 /*-------------------------------------------------------------------------*/
115
116 /* there's a notion of "current endpoint" for modifying endpoint
117  * state, and PIO access to its FIFO.
118  */
119
120 static void use_ep(struct omap_ep *ep, u16 select)
121 {
122         u16     num = ep->bEndpointAddress & 0x0f;
123
124         if (ep->bEndpointAddress & USB_DIR_IN)
125                 num |= UDC_EP_DIR;
126         omap_writew(num | select, UDC_EP_NUM);
127         /* when select, MUST deselect later !! */
128 }
129
130 static inline void deselect_ep(void)
131 {
132         u16 w;
133
134         w = omap_readw(UDC_EP_NUM);
135         w &= ~UDC_EP_SEL;
136         omap_writew(w, UDC_EP_NUM);
137         /* 6 wait states before TX will happen */
138 }
139
140 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
141
142 /*-------------------------------------------------------------------------*/
143
144 static int omap_ep_enable(struct usb_ep *_ep,
145                 const struct usb_endpoint_descriptor *desc)
146 {
147         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
148         struct omap_udc *udc;
149         unsigned long   flags;
150         u16             maxp;
151
152         /* catch various bogus parameters */
153         if (!_ep || !desc
154                         || desc->bDescriptorType != USB_DT_ENDPOINT
155                         || ep->bEndpointAddress != desc->bEndpointAddress
156                         || ep->maxpacket < usb_endpoint_maxp(desc)) {
157                 DBG("%s, bad ep or descriptor\n", __func__);
158                 return -EINVAL;
159         }
160         maxp = usb_endpoint_maxp(desc);
161         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
162                                 && maxp != ep->maxpacket)
163                         || usb_endpoint_maxp(desc) > ep->maxpacket
164                         || !desc->wMaxPacketSize) {
165                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
166                 return -ERANGE;
167         }
168
169 #ifdef  USE_ISO
170         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
171                                 && desc->bInterval != 1)) {
172                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
173                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
174                                 1 << (desc->bInterval - 1));
175                 return -EDOM;
176         }
177 #else
178         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
179                 DBG("%s, ISO nyet\n", _ep->name);
180                 return -EDOM;
181         }
182 #endif
183
184         /* xfer types must match, except that interrupt ~= bulk */
185         if (ep->bmAttributes != desc->bmAttributes
186                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
187                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
188                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
189                 return -EINVAL;
190         }
191
192         udc = ep->udc;
193         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
194                 DBG("%s, bogus device state\n", __func__);
195                 return -ESHUTDOWN;
196         }
197
198         spin_lock_irqsave(&udc->lock, flags);
199
200         ep->ep.desc = desc;
201         ep->irqs = 0;
202         ep->stopped = 0;
203         ep->ep.maxpacket = maxp;
204
205         /* set endpoint to initial state */
206         ep->dma_channel = 0;
207         ep->has_dma = 0;
208         ep->lch = -1;
209         use_ep(ep, UDC_EP_SEL);
210         omap_writew(udc->clr_halt, UDC_CTRL);
211         ep->ackwait = 0;
212         deselect_ep();
213
214         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
215                 list_add(&ep->iso, &udc->iso);
216
217         /* maybe assign a DMA channel to this endpoint */
218         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
219                 /* FIXME ISO can dma, but prefers first channel */
220                 dma_channel_claim(ep, 0);
221
222         /* PIO OUT may RX packets */
223         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
224                         && !ep->has_dma
225                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
226                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
227                 ep->ackwait = 1 + ep->double_buf;
228         }
229
230         spin_unlock_irqrestore(&udc->lock, flags);
231         VDBG("%s enabled\n", _ep->name);
232         return 0;
233 }
234
235 static void nuke(struct omap_ep *, int status);
236
237 static int omap_ep_disable(struct usb_ep *_ep)
238 {
239         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
240         unsigned long   flags;
241
242         if (!_ep || !ep->ep.desc) {
243                 DBG("%s, %s not enabled\n", __func__,
244                         _ep ? ep->ep.name : NULL);
245                 return -EINVAL;
246         }
247
248         spin_lock_irqsave(&ep->udc->lock, flags);
249         ep->ep.desc = NULL;
250         nuke(ep, -ESHUTDOWN);
251         ep->ep.maxpacket = ep->maxpacket;
252         ep->has_dma = 0;
253         omap_writew(UDC_SET_HALT, UDC_CTRL);
254         list_del_init(&ep->iso);
255         del_timer(&ep->timer);
256
257         spin_unlock_irqrestore(&ep->udc->lock, flags);
258
259         VDBG("%s disabled\n", _ep->name);
260         return 0;
261 }
262
263 /*-------------------------------------------------------------------------*/
264
265 static struct usb_request *
266 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
267 {
268         struct omap_req *req;
269
270         req = kzalloc(sizeof(*req), gfp_flags);
271         if (!req)
272                 return NULL;
273
274         INIT_LIST_HEAD(&req->queue);
275
276         return &req->req;
277 }
278
279 static void
280 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
281 {
282         struct omap_req *req = container_of(_req, struct omap_req, req);
283
284         kfree(req);
285 }
286
287 /*-------------------------------------------------------------------------*/
288
289 static void
290 done(struct omap_ep *ep, struct omap_req *req, int status)
291 {
292         struct omap_udc         *udc = ep->udc;
293         unsigned                stopped = ep->stopped;
294
295         list_del_init(&req->queue);
296
297         if (req->req.status == -EINPROGRESS)
298                 req->req.status = status;
299         else
300                 status = req->req.status;
301
302         if (use_dma && ep->has_dma)
303                 usb_gadget_unmap_request(&udc->gadget, &req->req,
304                                 (ep->bEndpointAddress & USB_DIR_IN));
305
306 #ifndef USB_TRACE
307         if (status && status != -ESHUTDOWN)
308 #endif
309                 VDBG("complete %s req %p stat %d len %u/%u\n",
310                         ep->ep.name, &req->req, status,
311                         req->req.actual, req->req.length);
312
313         /* don't modify queue heads during completion callback */
314         ep->stopped = 1;
315         spin_unlock(&ep->udc->lock);
316         req->req.complete(&ep->ep, &req->req);
317         spin_lock(&ep->udc->lock);
318         ep->stopped = stopped;
319 }
320
321 /*-------------------------------------------------------------------------*/
322
323 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
324 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
325
326 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
327 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
328
329 static inline int
330 write_packet(u8 *buf, struct omap_req *req, unsigned max)
331 {
332         unsigned        len;
333         u16             *wp;
334
335         len = min(req->req.length - req->req.actual, max);
336         req->req.actual += len;
337
338         max = len;
339         if (likely((((int)buf) & 1) == 0)) {
340                 wp = (u16 *)buf;
341                 while (max >= 2) {
342                         omap_writew(*wp++, UDC_DATA);
343                         max -= 2;
344                 }
345                 buf = (u8 *)wp;
346         }
347         while (max--)
348                 omap_writeb(*buf++, UDC_DATA);
349         return len;
350 }
351
352 /* FIXME change r/w fifo calling convention */
353
354
355 /* return:  0 = still running, 1 = completed, negative = errno */
356 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
357 {
358         u8              *buf;
359         unsigned        count;
360         int             is_last;
361         u16             ep_stat;
362
363         buf = req->req.buf + req->req.actual;
364         prefetch(buf);
365
366         /* PIO-IN isn't double buffered except for iso */
367         ep_stat = omap_readw(UDC_STAT_FLG);
368         if (ep_stat & UDC_FIFO_UNWRITABLE)
369                 return 0;
370
371         count = ep->ep.maxpacket;
372         count = write_packet(buf, req, count);
373         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
374         ep->ackwait = 1;
375
376         /* last packet is often short (sometimes a zlp) */
377         if (count != ep->ep.maxpacket)
378                 is_last = 1;
379         else if (req->req.length == req->req.actual
380                         && !req->req.zero)
381                 is_last = 1;
382         else
383                 is_last = 0;
384
385         /* NOTE:  requests complete when all IN data is in a
386          * FIFO (or sometimes later, if a zlp was needed).
387          * Use usb_ep_fifo_status() where needed.
388          */
389         if (is_last)
390                 done(ep, req, 0);
391         return is_last;
392 }
393
394 static inline int
395 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
396 {
397         unsigned        len;
398         u16             *wp;
399
400         len = min(req->req.length - req->req.actual, avail);
401         req->req.actual += len;
402         avail = len;
403
404         if (likely((((int)buf) & 1) == 0)) {
405                 wp = (u16 *)buf;
406                 while (avail >= 2) {
407                         *wp++ = omap_readw(UDC_DATA);
408                         avail -= 2;
409                 }
410                 buf = (u8 *)wp;
411         }
412         while (avail--)
413                 *buf++ = omap_readb(UDC_DATA);
414         return len;
415 }
416
417 /* return:  0 = still running, 1 = queue empty, negative = errno */
418 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
419 {
420         u8              *buf;
421         unsigned        count, avail;
422         int             is_last;
423
424         buf = req->req.buf + req->req.actual;
425         prefetchw(buf);
426
427         for (;;) {
428                 u16     ep_stat = omap_readw(UDC_STAT_FLG);
429
430                 is_last = 0;
431                 if (ep_stat & FIFO_EMPTY) {
432                         if (!ep->double_buf)
433                                 break;
434                         ep->fnf = 1;
435                 }
436                 if (ep_stat & UDC_EP_HALTED)
437                         break;
438
439                 if (ep_stat & UDC_FIFO_FULL)
440                         avail = ep->ep.maxpacket;
441                 else  {
442                         avail = omap_readw(UDC_RXFSTAT);
443                         ep->fnf = ep->double_buf;
444                 }
445                 count = read_packet(buf, req, avail);
446
447                 /* partial packet reads may not be errors */
448                 if (count < ep->ep.maxpacket) {
449                         is_last = 1;
450                         /* overflowed this request?  flush extra data */
451                         if (count != avail) {
452                                 req->req.status = -EOVERFLOW;
453                                 avail -= count;
454                                 while (avail--)
455                                         omap_readw(UDC_DATA);
456                         }
457                 } else if (req->req.length == req->req.actual)
458                         is_last = 1;
459                 else
460                         is_last = 0;
461
462                 if (!ep->bEndpointAddress)
463                         break;
464                 if (is_last)
465                         done(ep, req, 0);
466                 break;
467         }
468         return is_last;
469 }
470
471 /*-------------------------------------------------------------------------*/
472
473 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
474 {
475         dma_addr_t      end;
476
477         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
478          * the last transfer's bytecount by more than a FIFO's worth.
479          */
480         if (cpu_is_omap15xx())
481                 return 0;
482
483         end = omap_get_dma_src_pos(ep->lch);
484         if (end == ep->dma_counter)
485                 return 0;
486
487         end |= start & (0xffff << 16);
488         if (end < start)
489                 end += 0x10000;
490         return end - start;
491 }
492
493 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
494 {
495         dma_addr_t      end;
496
497         end = omap_get_dma_dst_pos(ep->lch);
498         if (end == ep->dma_counter)
499                 return 0;
500
501         end |= start & (0xffff << 16);
502         if (cpu_is_omap15xx())
503                 end++;
504         if (end < start)
505                 end += 0x10000;
506         return end - start;
507 }
508
509
510 /* Each USB transfer request using DMA maps to one or more DMA transfers.
511  * When DMA completion isn't request completion, the UDC continues with
512  * the next DMA transfer for that USB transfer.
513  */
514
515 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
516 {
517         u16             txdma_ctrl, w;
518         unsigned        length = req->req.length - req->req.actual;
519         const int       sync_mode = cpu_is_omap15xx()
520                                 ? OMAP_DMA_SYNC_FRAME
521                                 : OMAP_DMA_SYNC_ELEMENT;
522         int             dma_trigger = 0;
523
524         /* measure length in either bytes or packets */
525         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
526                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
527                 txdma_ctrl = UDC_TXN_EOT | length;
528                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
529                                 length, 1, sync_mode, dma_trigger, 0);
530         } else {
531                 length = min(length / ep->maxpacket,
532                                 (unsigned) UDC_TXN_TSC + 1);
533                 txdma_ctrl = length;
534                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
535                                 ep->ep.maxpacket >> 1, length, sync_mode,
536                                 dma_trigger, 0);
537                 length *= ep->maxpacket;
538         }
539         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
540                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
541                 0, 0);
542
543         omap_start_dma(ep->lch);
544         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
545         w = omap_readw(UDC_DMA_IRQ_EN);
546         w |= UDC_TX_DONE_IE(ep->dma_channel);
547         omap_writew(w, UDC_DMA_IRQ_EN);
548         omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
549         req->dma_bytes = length;
550 }
551
552 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
553 {
554         u16 w;
555
556         if (status == 0) {
557                 req->req.actual += req->dma_bytes;
558
559                 /* return if this request needs to send data or zlp */
560                 if (req->req.actual < req->req.length)
561                         return;
562                 if (req->req.zero
563                                 && req->dma_bytes != 0
564                                 && (req->req.actual % ep->maxpacket) == 0)
565                         return;
566         } else
567                 req->req.actual += dma_src_len(ep, req->req.dma
568                                                         + req->req.actual);
569
570         /* tx completion */
571         omap_stop_dma(ep->lch);
572         w = omap_readw(UDC_DMA_IRQ_EN);
573         w &= ~UDC_TX_DONE_IE(ep->dma_channel);
574         omap_writew(w, UDC_DMA_IRQ_EN);
575         done(ep, req, status);
576 }
577
578 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
579 {
580         unsigned packets = req->req.length - req->req.actual;
581         int dma_trigger = 0;
582         u16 w;
583
584         /* set up this DMA transfer, enable the fifo, start */
585         packets /= ep->ep.maxpacket;
586         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
587         req->dma_bytes = packets * ep->ep.maxpacket;
588         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
589                         ep->ep.maxpacket >> 1, packets,
590                         OMAP_DMA_SYNC_ELEMENT,
591                         dma_trigger, 0);
592         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
593                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
594                 0, 0);
595         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
596
597         omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
598         w = omap_readw(UDC_DMA_IRQ_EN);
599         w |= UDC_RX_EOT_IE(ep->dma_channel);
600         omap_writew(w, UDC_DMA_IRQ_EN);
601         omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
602         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
603
604         omap_start_dma(ep->lch);
605 }
606
607 static void
608 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
609 {
610         u16     count, w;
611
612         if (status == 0)
613                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
614         count = dma_dest_len(ep, req->req.dma + req->req.actual);
615         count += req->req.actual;
616         if (one)
617                 count--;
618         if (count <= req->req.length)
619                 req->req.actual = count;
620
621         if (count != req->dma_bytes || status)
622                 omap_stop_dma(ep->lch);
623
624         /* if this wasn't short, request may need another transfer */
625         else if (req->req.actual < req->req.length)
626                 return;
627
628         /* rx completion */
629         w = omap_readw(UDC_DMA_IRQ_EN);
630         w &= ~UDC_RX_EOT_IE(ep->dma_channel);
631         omap_writew(w, UDC_DMA_IRQ_EN);
632         done(ep, req, status);
633 }
634
635 static void dma_irq(struct omap_udc *udc, u16 irq_src)
636 {
637         u16             dman_stat = omap_readw(UDC_DMAN_STAT);
638         struct omap_ep  *ep;
639         struct omap_req *req;
640
641         /* IN dma: tx to host */
642         if (irq_src & UDC_TXN_DONE) {
643                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
644                 ep->irqs++;
645                 /* can see TXN_DONE after dma abort */
646                 if (!list_empty(&ep->queue)) {
647                         req = container_of(ep->queue.next,
648                                                 struct omap_req, queue);
649                         finish_in_dma(ep, req, 0);
650                 }
651                 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
652
653                 if (!list_empty(&ep->queue)) {
654                         req = container_of(ep->queue.next,
655                                         struct omap_req, queue);
656                         next_in_dma(ep, req);
657                 }
658         }
659
660         /* OUT dma: rx from host */
661         if (irq_src & UDC_RXN_EOT) {
662                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
663                 ep->irqs++;
664                 /* can see RXN_EOT after dma abort */
665                 if (!list_empty(&ep->queue)) {
666                         req = container_of(ep->queue.next,
667                                         struct omap_req, queue);
668                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
669                 }
670                 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
671
672                 if (!list_empty(&ep->queue)) {
673                         req = container_of(ep->queue.next,
674                                         struct omap_req, queue);
675                         next_out_dma(ep, req);
676                 }
677         }
678
679         if (irq_src & UDC_RXN_CNT) {
680                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
681                 ep->irqs++;
682                 /* omap15xx does this unasked... */
683                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
684                 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
685         }
686 }
687
688 static void dma_error(int lch, u16 ch_status, void *data)
689 {
690         struct omap_ep  *ep = data;
691
692         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
693         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
694         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
695
696         /* complete current transfer ... */
697 }
698
699 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
700 {
701         u16     reg;
702         int     status, restart, is_in;
703         int     dma_channel;
704
705         is_in = ep->bEndpointAddress & USB_DIR_IN;
706         if (is_in)
707                 reg = omap_readw(UDC_TXDMA_CFG);
708         else
709                 reg = omap_readw(UDC_RXDMA_CFG);
710         reg |= UDC_DMA_REQ;             /* "pulse" activated */
711
712         ep->dma_channel = 0;
713         ep->lch = -1;
714         if (channel == 0 || channel > 3) {
715                 if ((reg & 0x0f00) == 0)
716                         channel = 3;
717                 else if ((reg & 0x00f0) == 0)
718                         channel = 2;
719                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
720                         channel = 1;
721                 else {
722                         status = -EMLINK;
723                         goto just_restart;
724                 }
725         }
726         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
727         ep->dma_channel = channel;
728
729         if (is_in) {
730                 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
731                 status = omap_request_dma(dma_channel,
732                         ep->ep.name, dma_error, ep, &ep->lch);
733                 if (status == 0) {
734                         omap_writew(reg, UDC_TXDMA_CFG);
735                         /* EMIFF or SDRC */
736                         omap_set_dma_src_burst_mode(ep->lch,
737                                                 OMAP_DMA_DATA_BURST_4);
738                         omap_set_dma_src_data_pack(ep->lch, 1);
739                         /* TIPB */
740                         omap_set_dma_dest_params(ep->lch,
741                                 OMAP_DMA_PORT_TIPB,
742                                 OMAP_DMA_AMODE_CONSTANT,
743                                 UDC_DATA_DMA,
744                                 0, 0);
745                 }
746         } else {
747                 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
748                 status = omap_request_dma(dma_channel,
749                         ep->ep.name, dma_error, ep, &ep->lch);
750                 if (status == 0) {
751                         omap_writew(reg, UDC_RXDMA_CFG);
752                         /* TIPB */
753                         omap_set_dma_src_params(ep->lch,
754                                 OMAP_DMA_PORT_TIPB,
755                                 OMAP_DMA_AMODE_CONSTANT,
756                                 UDC_DATA_DMA,
757                                 0, 0);
758                         /* EMIFF or SDRC */
759                         omap_set_dma_dest_burst_mode(ep->lch,
760                                                 OMAP_DMA_DATA_BURST_4);
761                         omap_set_dma_dest_data_pack(ep->lch, 1);
762                 }
763         }
764         if (status)
765                 ep->dma_channel = 0;
766         else {
767                 ep->has_dma = 1;
768                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
769
770                 /* channel type P: hw synch (fifo) */
771                 if (!cpu_is_omap15xx())
772                         omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
773         }
774
775 just_restart:
776         /* restart any queue, even if the claim failed  */
777         restart = !ep->stopped && !list_empty(&ep->queue);
778
779         if (status)
780                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
781                         restart ? " (restart)" : "");
782         else
783                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
784                         is_in ? 't' : 'r',
785                         ep->dma_channel - 1, ep->lch,
786                         restart ? " (restart)" : "");
787
788         if (restart) {
789                 struct omap_req *req;
790                 req = container_of(ep->queue.next, struct omap_req, queue);
791                 if (ep->has_dma)
792                         (is_in ? next_in_dma : next_out_dma)(ep, req);
793                 else {
794                         use_ep(ep, UDC_EP_SEL);
795                         (is_in ? write_fifo : read_fifo)(ep, req);
796                         deselect_ep();
797                         if (!is_in) {
798                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
799                                 ep->ackwait = 1 + ep->double_buf;
800                         }
801                         /* IN: 6 wait states before it'll tx */
802                 }
803         }
804 }
805
806 static void dma_channel_release(struct omap_ep *ep)
807 {
808         int             shift = 4 * (ep->dma_channel - 1);
809         u16             mask = 0x0f << shift;
810         struct omap_req *req;
811         int             active;
812
813         /* abort any active usb transfer request */
814         if (!list_empty(&ep->queue))
815                 req = container_of(ep->queue.next, struct omap_req, queue);
816         else
817                 req = NULL;
818
819         active = omap_get_dma_active_status(ep->lch);
820
821         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
822                         active ? "active" : "idle",
823                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
824                         ep->dma_channel - 1, req);
825
826         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
827          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
828          */
829
830         /* wait till current packet DMA finishes, and fifo empties */
831         if (ep->bEndpointAddress & USB_DIR_IN) {
832                 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
833                                         UDC_TXDMA_CFG);
834
835                 if (req) {
836                         finish_in_dma(ep, req, -ECONNRESET);
837
838                         /* clear FIFO; hosts probably won't empty it */
839                         use_ep(ep, UDC_EP_SEL);
840                         omap_writew(UDC_CLR_EP, UDC_CTRL);
841                         deselect_ep();
842                 }
843                 while (omap_readw(UDC_TXDMA_CFG) & mask)
844                         udelay(10);
845         } else {
846                 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
847                                         UDC_RXDMA_CFG);
848
849                 /* dma empties the fifo */
850                 while (omap_readw(UDC_RXDMA_CFG) & mask)
851                         udelay(10);
852                 if (req)
853                         finish_out_dma(ep, req, -ECONNRESET, 0);
854         }
855         omap_free_dma(ep->lch);
856         ep->dma_channel = 0;
857         ep->lch = -1;
858         /* has_dma still set, till endpoint is fully quiesced */
859 }
860
861
862 /*-------------------------------------------------------------------------*/
863
864 static int
865 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
866 {
867         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
868         struct omap_req *req = container_of(_req, struct omap_req, req);
869         struct omap_udc *udc;
870         unsigned long   flags;
871         int             is_iso = 0;
872
873         /* catch various bogus parameters */
874         if (!_req || !req->req.complete || !req->req.buf
875                         || !list_empty(&req->queue)) {
876                 DBG("%s, bad params\n", __func__);
877                 return -EINVAL;
878         }
879         if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
880                 DBG("%s, bad ep\n", __func__);
881                 return -EINVAL;
882         }
883         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
884                 if (req->req.length > ep->ep.maxpacket)
885                         return -EMSGSIZE;
886                 is_iso = 1;
887         }
888
889         /* this isn't bogus, but OMAP DMA isn't the only hardware to
890          * have a hard time with partial packet reads...  reject it.
891          */
892         if (use_dma
893                         && ep->has_dma
894                         && ep->bEndpointAddress != 0
895                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
896                         && (req->req.length % ep->ep.maxpacket) != 0) {
897                 DBG("%s, no partial packet OUT reads\n", __func__);
898                 return -EMSGSIZE;
899         }
900
901         udc = ep->udc;
902         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
903                 return -ESHUTDOWN;
904
905         if (use_dma && ep->has_dma)
906                 usb_gadget_map_request(&udc->gadget, &req->req,
907                                 (ep->bEndpointAddress & USB_DIR_IN));
908
909         VDBG("%s queue req %p, len %d buf %p\n",
910                 ep->ep.name, _req, _req->length, _req->buf);
911
912         spin_lock_irqsave(&udc->lock, flags);
913
914         req->req.status = -EINPROGRESS;
915         req->req.actual = 0;
916
917         /* maybe kickstart non-iso i/o queues */
918         if (is_iso) {
919                 u16 w;
920
921                 w = omap_readw(UDC_IRQ_EN);
922                 w |= UDC_SOF_IE;
923                 omap_writew(w, UDC_IRQ_EN);
924         } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
925                 int     is_in;
926
927                 if (ep->bEndpointAddress == 0) {
928                         if (!udc->ep0_pending || !list_empty(&ep->queue)) {
929                                 spin_unlock_irqrestore(&udc->lock, flags);
930                                 return -EL2HLT;
931                         }
932
933                         /* empty DATA stage? */
934                         is_in = udc->ep0_in;
935                         if (!req->req.length) {
936
937                                 /* chip became CONFIGURED or ADDRESSED
938                                  * earlier; drivers may already have queued
939                                  * requests to non-control endpoints
940                                  */
941                                 if (udc->ep0_set_config) {
942                                         u16     irq_en = omap_readw(UDC_IRQ_EN);
943
944                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
945                                         if (!udc->ep0_reset_config)
946                                                 irq_en |= UDC_EPN_RX_IE
947                                                         | UDC_EPN_TX_IE;
948                                         omap_writew(irq_en, UDC_IRQ_EN);
949                                 }
950
951                                 /* STATUS for zero length DATA stages is
952                                  * always an IN ... even for IN transfers,
953                                  * a weird case which seem to stall OMAP.
954                                  */
955                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
956                                                 UDC_EP_NUM);
957                                 omap_writew(UDC_CLR_EP, UDC_CTRL);
958                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
959                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
960
961                                 /* cleanup */
962                                 udc->ep0_pending = 0;
963                                 done(ep, req, 0);
964                                 req = NULL;
965
966                         /* non-empty DATA stage */
967                         } else if (is_in) {
968                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
969                                                 UDC_EP_NUM);
970                         } else {
971                                 if (udc->ep0_setup)
972                                         goto irq_wait;
973                                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
974                         }
975                 } else {
976                         is_in = ep->bEndpointAddress & USB_DIR_IN;
977                         if (!ep->has_dma)
978                                 use_ep(ep, UDC_EP_SEL);
979                         /* if ISO: SOF IRQs must be enabled/disabled! */
980                 }
981
982                 if (ep->has_dma)
983                         (is_in ? next_in_dma : next_out_dma)(ep, req);
984                 else if (req) {
985                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
986                                 req = NULL;
987                         deselect_ep();
988                         if (!is_in) {
989                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
990                                 ep->ackwait = 1 + ep->double_buf;
991                         }
992                         /* IN: 6 wait states before it'll tx */
993                 }
994         }
995
996 irq_wait:
997         /* irq handler advances the queue */
998         if (req != NULL)
999                 list_add_tail(&req->queue, &ep->queue);
1000         spin_unlock_irqrestore(&udc->lock, flags);
1001
1002         return 0;
1003 }
1004
1005 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1006 {
1007         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1008         struct omap_req *req;
1009         unsigned long   flags;
1010
1011         if (!_ep || !_req)
1012                 return -EINVAL;
1013
1014         spin_lock_irqsave(&ep->udc->lock, flags);
1015
1016         /* make sure it's actually queued on this endpoint */
1017         list_for_each_entry(req, &ep->queue, queue) {
1018                 if (&req->req == _req)
1019                         break;
1020         }
1021         if (&req->req != _req) {
1022                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1023                 return -EINVAL;
1024         }
1025
1026         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1027                 int channel = ep->dma_channel;
1028
1029                 /* releasing the channel cancels the request,
1030                  * reclaiming the channel restarts the queue
1031                  */
1032                 dma_channel_release(ep);
1033                 dma_channel_claim(ep, channel);
1034         } else
1035                 done(ep, req, -ECONNRESET);
1036         spin_unlock_irqrestore(&ep->udc->lock, flags);
1037         return 0;
1038 }
1039
1040 /*-------------------------------------------------------------------------*/
1041
1042 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1043 {
1044         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1045         unsigned long   flags;
1046         int             status = -EOPNOTSUPP;
1047
1048         spin_lock_irqsave(&ep->udc->lock, flags);
1049
1050         /* just use protocol stalls for ep0; real halts are annoying */
1051         if (ep->bEndpointAddress == 0) {
1052                 if (!ep->udc->ep0_pending)
1053                         status = -EINVAL;
1054                 else if (value) {
1055                         if (ep->udc->ep0_set_config) {
1056                                 WARNING("error changing config?\n");
1057                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1058                         }
1059                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1060                         ep->udc->ep0_pending = 0;
1061                         status = 0;
1062                 } else /* NOP */
1063                         status = 0;
1064
1065         /* otherwise, all active non-ISO endpoints can halt */
1066         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1067
1068                 /* IN endpoints must already be idle */
1069                 if ((ep->bEndpointAddress & USB_DIR_IN)
1070                                 && !list_empty(&ep->queue)) {
1071                         status = -EAGAIN;
1072                         goto done;
1073                 }
1074
1075                 if (value) {
1076                         int     channel;
1077
1078                         if (use_dma && ep->dma_channel
1079                                         && !list_empty(&ep->queue)) {
1080                                 channel = ep->dma_channel;
1081                                 dma_channel_release(ep);
1082                         } else
1083                                 channel = 0;
1084
1085                         use_ep(ep, UDC_EP_SEL);
1086                         if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1087                                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1088                                 status = 0;
1089                         } else
1090                                 status = -EAGAIN;
1091                         deselect_ep();
1092
1093                         if (channel)
1094                                 dma_channel_claim(ep, channel);
1095                 } else {
1096                         use_ep(ep, 0);
1097                         omap_writew(ep->udc->clr_halt, UDC_CTRL);
1098                         ep->ackwait = 0;
1099                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1100                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1101                                 ep->ackwait = 1 + ep->double_buf;
1102                         }
1103                 }
1104         }
1105 done:
1106         VDBG("%s %s halt stat %d\n", ep->ep.name,
1107                 value ? "set" : "clear", status);
1108
1109         spin_unlock_irqrestore(&ep->udc->lock, flags);
1110         return status;
1111 }
1112
1113 static struct usb_ep_ops omap_ep_ops = {
1114         .enable         = omap_ep_enable,
1115         .disable        = omap_ep_disable,
1116
1117         .alloc_request  = omap_alloc_request,
1118         .free_request   = omap_free_request,
1119
1120         .queue          = omap_ep_queue,
1121         .dequeue        = omap_ep_dequeue,
1122
1123         .set_halt       = omap_ep_set_halt,
1124         /* fifo_status ... report bytes in fifo */
1125         /* fifo_flush ... flush fifo */
1126 };
1127
1128 /*-------------------------------------------------------------------------*/
1129
1130 static int omap_get_frame(struct usb_gadget *gadget)
1131 {
1132         u16     sof = omap_readw(UDC_SOF);
1133         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1134 }
1135
1136 static int omap_wakeup(struct usb_gadget *gadget)
1137 {
1138         struct omap_udc *udc;
1139         unsigned long   flags;
1140         int             retval = -EHOSTUNREACH;
1141
1142         udc = container_of(gadget, struct omap_udc, gadget);
1143
1144         spin_lock_irqsave(&udc->lock, flags);
1145         if (udc->devstat & UDC_SUS) {
1146                 /* NOTE:  OTG spec erratum says that OTG devices may
1147                  * issue wakeups without host enable.
1148                  */
1149                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1150                         DBG("remote wakeup...\n");
1151                         omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1152                         retval = 0;
1153                 }
1154
1155         /* NOTE:  non-OTG systems may use SRP TOO... */
1156         } else if (!(udc->devstat & UDC_ATT)) {
1157                 if (!IS_ERR_OR_NULL(udc->transceiver))
1158                         retval = otg_start_srp(udc->transceiver->otg);
1159         }
1160         spin_unlock_irqrestore(&udc->lock, flags);
1161
1162         return retval;
1163 }
1164
1165 static int
1166 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1167 {
1168         struct omap_udc *udc;
1169         unsigned long   flags;
1170         u16             syscon1;
1171
1172         udc = container_of(gadget, struct omap_udc, gadget);
1173         spin_lock_irqsave(&udc->lock, flags);
1174         syscon1 = omap_readw(UDC_SYSCON1);
1175         if (is_selfpowered)
1176                 syscon1 |= UDC_SELF_PWR;
1177         else
1178                 syscon1 &= ~UDC_SELF_PWR;
1179         omap_writew(syscon1, UDC_SYSCON1);
1180         spin_unlock_irqrestore(&udc->lock, flags);
1181
1182         return 0;
1183 }
1184
1185 static int can_pullup(struct omap_udc *udc)
1186 {
1187         return udc->driver && udc->softconnect && udc->vbus_active;
1188 }
1189
1190 static void pullup_enable(struct omap_udc *udc)
1191 {
1192         u16 w;
1193
1194         w = omap_readw(UDC_SYSCON1);
1195         w |= UDC_PULLUP_EN;
1196         omap_writew(w, UDC_SYSCON1);
1197         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1198                 u32 l;
1199
1200                 l = omap_readl(OTG_CTRL);
1201                 l |= OTG_BSESSVLD;
1202                 omap_writel(l, OTG_CTRL);
1203         }
1204         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1205 }
1206
1207 static void pullup_disable(struct omap_udc *udc)
1208 {
1209         u16 w;
1210
1211         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1212                 u32 l;
1213
1214                 l = omap_readl(OTG_CTRL);
1215                 l &= ~OTG_BSESSVLD;
1216                 omap_writel(l, OTG_CTRL);
1217         }
1218         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1219         w = omap_readw(UDC_SYSCON1);
1220         w &= ~UDC_PULLUP_EN;
1221         omap_writew(w, UDC_SYSCON1);
1222 }
1223
1224 static struct omap_udc *udc;
1225
1226 static void omap_udc_enable_clock(int enable)
1227 {
1228         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1229                 return;
1230
1231         if (enable) {
1232                 clk_enable(udc->dc_clk);
1233                 clk_enable(udc->hhc_clk);
1234                 udelay(100);
1235         } else {
1236                 clk_disable(udc->hhc_clk);
1237                 clk_disable(udc->dc_clk);
1238         }
1239 }
1240
1241 /*
1242  * Called by whatever detects VBUS sessions:  external transceiver
1243  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1244  */
1245 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1246 {
1247         struct omap_udc *udc;
1248         unsigned long   flags;
1249         u32 l;
1250
1251         udc = container_of(gadget, struct omap_udc, gadget);
1252         spin_lock_irqsave(&udc->lock, flags);
1253         VDBG("VBUS %s\n", is_active ? "on" : "off");
1254         udc->vbus_active = (is_active != 0);
1255         if (cpu_is_omap15xx()) {
1256                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1257                 l = omap_readl(FUNC_MUX_CTRL_0);
1258                 if (is_active)
1259                         l |= VBUS_CTRL_1510;
1260                 else
1261                         l &= ~VBUS_CTRL_1510;
1262                 omap_writel(l, FUNC_MUX_CTRL_0);
1263         }
1264         if (udc->dc_clk != NULL && is_active) {
1265                 if (!udc->clk_requested) {
1266                         omap_udc_enable_clock(1);
1267                         udc->clk_requested = 1;
1268                 }
1269         }
1270         if (can_pullup(udc))
1271                 pullup_enable(udc);
1272         else
1273                 pullup_disable(udc);
1274         if (udc->dc_clk != NULL && !is_active) {
1275                 if (udc->clk_requested) {
1276                         omap_udc_enable_clock(0);
1277                         udc->clk_requested = 0;
1278                 }
1279         }
1280         spin_unlock_irqrestore(&udc->lock, flags);
1281         return 0;
1282 }
1283
1284 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1285 {
1286         struct omap_udc *udc;
1287
1288         udc = container_of(gadget, struct omap_udc, gadget);
1289         if (!IS_ERR_OR_NULL(udc->transceiver))
1290                 return usb_phy_set_power(udc->transceiver, mA);
1291         return -EOPNOTSUPP;
1292 }
1293
1294 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1295 {
1296         struct omap_udc *udc;
1297         unsigned long   flags;
1298
1299         udc = container_of(gadget, struct omap_udc, gadget);
1300         spin_lock_irqsave(&udc->lock, flags);
1301         udc->softconnect = (is_on != 0);
1302         if (can_pullup(udc))
1303                 pullup_enable(udc);
1304         else
1305                 pullup_disable(udc);
1306         spin_unlock_irqrestore(&udc->lock, flags);
1307         return 0;
1308 }
1309
1310 static int omap_udc_start(struct usb_gadget_driver *driver,
1311                 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *));
1312 static int omap_udc_stop(struct usb_gadget_driver *driver);
1313
1314 static struct usb_gadget_ops omap_gadget_ops = {
1315         .get_frame              = omap_get_frame,
1316         .wakeup                 = omap_wakeup,
1317         .set_selfpowered        = omap_set_selfpowered,
1318         .vbus_session           = omap_vbus_session,
1319         .vbus_draw              = omap_vbus_draw,
1320         .pullup                 = omap_pullup,
1321         .start                  = omap_udc_start,
1322         .stop                   = omap_udc_stop,
1323 };
1324
1325 /*-------------------------------------------------------------------------*/
1326
1327 /* dequeue ALL requests; caller holds udc->lock */
1328 static void nuke(struct omap_ep *ep, int status)
1329 {
1330         struct omap_req *req;
1331
1332         ep->stopped = 1;
1333
1334         if (use_dma && ep->dma_channel)
1335                 dma_channel_release(ep);
1336
1337         use_ep(ep, 0);
1338         omap_writew(UDC_CLR_EP, UDC_CTRL);
1339         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1340                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1341
1342         while (!list_empty(&ep->queue)) {
1343                 req = list_entry(ep->queue.next, struct omap_req, queue);
1344                 done(ep, req, status);
1345         }
1346 }
1347
1348 /* caller holds udc->lock */
1349 static void udc_quiesce(struct omap_udc *udc)
1350 {
1351         struct omap_ep  *ep;
1352
1353         udc->gadget.speed = USB_SPEED_UNKNOWN;
1354         nuke(&udc->ep[0], -ESHUTDOWN);
1355         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1356                 nuke(ep, -ESHUTDOWN);
1357 }
1358
1359 /*-------------------------------------------------------------------------*/
1360
1361 static void update_otg(struct omap_udc *udc)
1362 {
1363         u16     devstat;
1364
1365         if (!gadget_is_otg(&udc->gadget))
1366                 return;
1367
1368         if (omap_readl(OTG_CTRL) & OTG_ID)
1369                 devstat = omap_readw(UDC_DEVSTAT);
1370         else
1371                 devstat = 0;
1372
1373         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1374         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1375         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1376
1377         /* Enable HNP early, avoiding races on suspend irq path.
1378          * ASSUMES OTG state machine B_BUS_REQ input is true.
1379          */
1380         if (udc->gadget.b_hnp_enable) {
1381                 u32 l;
1382
1383                 l = omap_readl(OTG_CTRL);
1384                 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1385                 l &= ~OTG_PULLUP;
1386                 omap_writel(l, OTG_CTRL);
1387         }
1388 }
1389
1390 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1391 {
1392         struct omap_ep  *ep0 = &udc->ep[0];
1393         struct omap_req *req = NULL;
1394
1395         ep0->irqs++;
1396
1397         /* Clear any pending requests and then scrub any rx/tx state
1398          * before starting to handle the SETUP request.
1399          */
1400         if (irq_src & UDC_SETUP) {
1401                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1402
1403                 nuke(ep0, 0);
1404                 if (ack) {
1405                         omap_writew(ack, UDC_IRQ_SRC);
1406                         irq_src = UDC_SETUP;
1407                 }
1408         }
1409
1410         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1411          * This driver uses only uses protocol stalls (ep0 never halts),
1412          * and if we got this far the gadget driver already had a
1413          * chance to stall.  Tries to be forgiving of host oddities.
1414          *
1415          * NOTE:  the last chance gadget drivers have to stall control
1416          * requests is during their request completion callback.
1417          */
1418         if (!list_empty(&ep0->queue))
1419                 req = container_of(ep0->queue.next, struct omap_req, queue);
1420
1421         /* IN == TX to host */
1422         if (irq_src & UDC_EP0_TX) {
1423                 int     stat;
1424
1425                 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1426                 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1427                 stat = omap_readw(UDC_STAT_FLG);
1428                 if (stat & UDC_ACK) {
1429                         if (udc->ep0_in) {
1430                                 /* write next IN packet from response,
1431                                  * or set up the status stage.
1432                                  */
1433                                 if (req)
1434                                         stat = write_fifo(ep0, req);
1435                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1436                                 if (!req && udc->ep0_pending) {
1437                                         omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1438                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1439                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1440                                         omap_writew(0, UDC_EP_NUM);
1441                                         udc->ep0_pending = 0;
1442                                 } /* else:  6 wait states before it'll tx */
1443                         } else {
1444                                 /* ack status stage of OUT transfer */
1445                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1446                                 if (req)
1447                                         done(ep0, req, 0);
1448                         }
1449                         req = NULL;
1450                 } else if (stat & UDC_STALL) {
1451                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1452                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1453                 } else {
1454                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1455                 }
1456         }
1457
1458         /* OUT == RX from host */
1459         if (irq_src & UDC_EP0_RX) {
1460                 int     stat;
1461
1462                 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1463                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1464                 stat = omap_readw(UDC_STAT_FLG);
1465                 if (stat & UDC_ACK) {
1466                         if (!udc->ep0_in) {
1467                                 stat = 0;
1468                                 /* read next OUT packet of request, maybe
1469                                  * reactiviting the fifo; stall on errors.
1470                                  */
1471                                 stat = read_fifo(ep0, req);
1472                                 if (!req || stat < 0) {
1473                                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1474                                         udc->ep0_pending = 0;
1475                                         stat = 0;
1476                                 } else if (stat == 0)
1477                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1478                                 omap_writew(0, UDC_EP_NUM);
1479
1480                                 /* activate status stage */
1481                                 if (stat == 1) {
1482                                         done(ep0, req, 0);
1483                                         /* that may have STALLed ep0... */
1484                                         omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1485                                                         UDC_EP_NUM);
1486                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1487                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1488                                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1489                                         udc->ep0_pending = 0;
1490                                 }
1491                         } else {
1492                                 /* ack status stage of IN transfer */
1493                                 omap_writew(0, UDC_EP_NUM);
1494                                 if (req)
1495                                         done(ep0, req, 0);
1496                         }
1497                 } else if (stat & UDC_STALL) {
1498                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1499                         omap_writew(0, UDC_EP_NUM);
1500                 } else {
1501                         omap_writew(0, UDC_EP_NUM);
1502                 }
1503         }
1504
1505         /* SETUP starts all control transfers */
1506         if (irq_src & UDC_SETUP) {
1507                 union u {
1508                         u16                     word[4];
1509                         struct usb_ctrlrequest  r;
1510                 } u;
1511                 int                     status = -EINVAL;
1512                 struct omap_ep          *ep;
1513
1514                 /* read the (latest) SETUP message */
1515                 do {
1516                         omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1517                         /* two bytes at a time */
1518                         u.word[0] = omap_readw(UDC_DATA);
1519                         u.word[1] = omap_readw(UDC_DATA);
1520                         u.word[2] = omap_readw(UDC_DATA);
1521                         u.word[3] = omap_readw(UDC_DATA);
1522                         omap_writew(0, UDC_EP_NUM);
1523                 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1524
1525 #define w_value         le16_to_cpu(u.r.wValue)
1526 #define w_index         le16_to_cpu(u.r.wIndex)
1527 #define w_length        le16_to_cpu(u.r.wLength)
1528
1529                 /* Delegate almost all control requests to the gadget driver,
1530                  * except for a handful of ch9 status/feature requests that
1531                  * hardware doesn't autodecode _and_ the gadget API hides.
1532                  */
1533                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1534                 udc->ep0_set_config = 0;
1535                 udc->ep0_pending = 1;
1536                 ep0->stopped = 0;
1537                 ep0->ackwait = 0;
1538                 switch (u.r.bRequest) {
1539                 case USB_REQ_SET_CONFIGURATION:
1540                         /* udc needs to know when ep != 0 is valid */
1541                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1542                                 goto delegate;
1543                         if (w_length != 0)
1544                                 goto do_stall;
1545                         udc->ep0_set_config = 1;
1546                         udc->ep0_reset_config = (w_value == 0);
1547                         VDBG("set config %d\n", w_value);
1548
1549                         /* update udc NOW since gadget driver may start
1550                          * queueing requests immediately; clear config
1551                          * later if it fails the request.
1552                          */
1553                         if (udc->ep0_reset_config)
1554                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1555                         else
1556                                 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1557                         update_otg(udc);
1558                         goto delegate;
1559                 case USB_REQ_CLEAR_FEATURE:
1560                         /* clear endpoint halt */
1561                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1562                                 goto delegate;
1563                         if (w_value != USB_ENDPOINT_HALT
1564                                         || w_length != 0)
1565                                 goto do_stall;
1566                         ep = &udc->ep[w_index & 0xf];
1567                         if (ep != ep0) {
1568                                 if (w_index & USB_DIR_IN)
1569                                         ep += 16;
1570                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1571                                                 || !ep->ep.desc)
1572                                         goto do_stall;
1573                                 use_ep(ep, 0);
1574                                 omap_writew(udc->clr_halt, UDC_CTRL);
1575                                 ep->ackwait = 0;
1576                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1577                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1578                                         ep->ackwait = 1 + ep->double_buf;
1579                                 }
1580                                 /* NOTE:  assumes the host behaves sanely,
1581                                  * only clearing real halts.  Else we may
1582                                  * need to kill pending transfers and then
1583                                  * restart the queue... very messy for DMA!
1584                                  */
1585                         }
1586                         VDBG("%s halt cleared by host\n", ep->name);
1587                         goto ep0out_status_stage;
1588                 case USB_REQ_SET_FEATURE:
1589                         /* set endpoint halt */
1590                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1591                                 goto delegate;
1592                         if (w_value != USB_ENDPOINT_HALT
1593                                         || w_length != 0)
1594                                 goto do_stall;
1595                         ep = &udc->ep[w_index & 0xf];
1596                         if (w_index & USB_DIR_IN)
1597                                 ep += 16;
1598                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1599                                         || ep == ep0 || !ep->ep.desc)
1600                                 goto do_stall;
1601                         if (use_dma && ep->has_dma) {
1602                                 /* this has rude side-effects (aborts) and
1603                                  * can't really work if DMA-IN is active
1604                                  */
1605                                 DBG("%s host set_halt, NYET\n", ep->name);
1606                                 goto do_stall;
1607                         }
1608                         use_ep(ep, 0);
1609                         /* can't halt if fifo isn't empty... */
1610                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1611                         omap_writew(UDC_SET_HALT, UDC_CTRL);
1612                         VDBG("%s halted by host\n", ep->name);
1613 ep0out_status_stage:
1614                         status = 0;
1615                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1616                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1617                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1618                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1619                         udc->ep0_pending = 0;
1620                         break;
1621                 case USB_REQ_GET_STATUS:
1622                         /* USB_ENDPOINT_HALT status? */
1623                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1624                                 goto intf_status;
1625
1626                         /* ep0 never stalls */
1627                         if (!(w_index & 0xf))
1628                                 goto zero_status;
1629
1630                         /* only active endpoints count */
1631                         ep = &udc->ep[w_index & 0xf];
1632                         if (w_index & USB_DIR_IN)
1633                                 ep += 16;
1634                         if (!ep->ep.desc)
1635                                 goto do_stall;
1636
1637                         /* iso never stalls */
1638                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1639                                 goto zero_status;
1640
1641                         /* FIXME don't assume non-halted endpoints!! */
1642                         ERR("%s status, can't report\n", ep->ep.name);
1643                         goto do_stall;
1644
1645 intf_status:
1646                         /* return interface status.  if we were pedantic,
1647                          * we'd detect non-existent interfaces, and stall.
1648                          */
1649                         if (u.r.bRequestType
1650                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1651                                 goto delegate;
1652
1653 zero_status:
1654                         /* return two zero bytes */
1655                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1656                         omap_writew(0, UDC_DATA);
1657                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1658                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1659                         status = 0;
1660                         VDBG("GET_STATUS, interface %d\n", w_index);
1661                         /* next, status stage */
1662                         break;
1663                 default:
1664 delegate:
1665                         /* activate the ep0out fifo right away */
1666                         if (!udc->ep0_in && w_length) {
1667                                 omap_writew(0, UDC_EP_NUM);
1668                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1669                         }
1670
1671                         /* gadget drivers see class/vendor specific requests,
1672                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1673                          * and more
1674                          */
1675                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1676                                 u.r.bRequestType, u.r.bRequest,
1677                                 w_value, w_index, w_length);
1678
1679 #undef  w_value
1680 #undef  w_index
1681 #undef  w_length
1682
1683                         /* The gadget driver may return an error here,
1684                          * causing an immediate protocol stall.
1685                          *
1686                          * Else it must issue a response, either queueing a
1687                          * response buffer for the DATA stage, or halting ep0
1688                          * (causing a protocol stall, not a real halt).  A
1689                          * zero length buffer means no DATA stage.
1690                          *
1691                          * It's fine to issue that response after the setup()
1692                          * call returns, and this IRQ was handled.
1693                          */
1694                         udc->ep0_setup = 1;
1695                         spin_unlock(&udc->lock);
1696                         status = udc->driver->setup(&udc->gadget, &u.r);
1697                         spin_lock(&udc->lock);
1698                         udc->ep0_setup = 0;
1699                 }
1700
1701                 if (status < 0) {
1702 do_stall:
1703                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1704                                         u.r.bRequestType, u.r.bRequest, status);
1705                         if (udc->ep0_set_config) {
1706                                 if (udc->ep0_reset_config)
1707                                         WARNING("error resetting config?\n");
1708                                 else
1709                                         omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1710                         }
1711                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1712                         udc->ep0_pending = 0;
1713                 }
1714         }
1715 }
1716
1717 /*-------------------------------------------------------------------------*/
1718
1719 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1720
1721 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1722 {
1723         u16     devstat, change;
1724
1725         devstat = omap_readw(UDC_DEVSTAT);
1726         change = devstat ^ udc->devstat;
1727         udc->devstat = devstat;
1728
1729         if (change & (UDC_USB_RESET|UDC_ATT)) {
1730                 udc_quiesce(udc);
1731
1732                 if (change & UDC_ATT) {
1733                         /* driver for any external transceiver will
1734                          * have called omap_vbus_session() already
1735                          */
1736                         if (devstat & UDC_ATT) {
1737                                 udc->gadget.speed = USB_SPEED_FULL;
1738                                 VDBG("connect\n");
1739                                 if (IS_ERR_OR_NULL(udc->transceiver))
1740                                         pullup_enable(udc);
1741                                 /* if (driver->connect) call it */
1742                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1743                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1744                                 if (IS_ERR_OR_NULL(udc->transceiver))
1745                                         pullup_disable(udc);
1746                                 DBG("disconnect, gadget %s\n",
1747                                         udc->driver->driver.name);
1748                                 if (udc->driver->disconnect) {
1749                                         spin_unlock(&udc->lock);
1750                                         udc->driver->disconnect(&udc->gadget);
1751                                         spin_lock(&udc->lock);
1752                                 }
1753                         }
1754                         change &= ~UDC_ATT;
1755                 }
1756
1757                 if (change & UDC_USB_RESET) {
1758                         if (devstat & UDC_USB_RESET) {
1759                                 VDBG("RESET=1\n");
1760                         } else {
1761                                 udc->gadget.speed = USB_SPEED_FULL;
1762                                 INFO("USB reset done, gadget %s\n",
1763                                         udc->driver->driver.name);
1764                                 /* ep0 traffic is legal from now on */
1765                                 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1766                                                 UDC_IRQ_EN);
1767                         }
1768                         change &= ~UDC_USB_RESET;
1769                 }
1770         }
1771         if (change & UDC_SUS) {
1772                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1773                         /* FIXME tell isp1301 to suspend/resume (?) */
1774                         if (devstat & UDC_SUS) {
1775                                 VDBG("suspend\n");
1776                                 update_otg(udc);
1777                                 /* HNP could be under way already */
1778                                 if (udc->gadget.speed == USB_SPEED_FULL
1779                                                 && udc->driver->suspend) {
1780                                         spin_unlock(&udc->lock);
1781                                         udc->driver->suspend(&udc->gadget);
1782                                         spin_lock(&udc->lock);
1783                                 }
1784                                 if (!IS_ERR_OR_NULL(udc->transceiver))
1785                                         usb_phy_set_suspend(
1786                                                         udc->transceiver, 1);
1787                         } else {
1788                                 VDBG("resume\n");
1789                                 if (!IS_ERR_OR_NULL(udc->transceiver))
1790                                         usb_phy_set_suspend(
1791                                                         udc->transceiver, 0);
1792                                 if (udc->gadget.speed == USB_SPEED_FULL
1793                                                 && udc->driver->resume) {
1794                                         spin_unlock(&udc->lock);
1795                                         udc->driver->resume(&udc->gadget);
1796                                         spin_lock(&udc->lock);
1797                                 }
1798                         }
1799                 }
1800                 change &= ~UDC_SUS;
1801         }
1802         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1803                 update_otg(udc);
1804                 change &= ~OTG_FLAGS;
1805         }
1806
1807         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1808         if (change)
1809                 VDBG("devstat %03x, ignore change %03x\n",
1810                         devstat,  change);
1811
1812         omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1813 }
1814
1815 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1816 {
1817         struct omap_udc *udc = _udc;
1818         u16             irq_src;
1819         irqreturn_t     status = IRQ_NONE;
1820         unsigned long   flags;
1821
1822         spin_lock_irqsave(&udc->lock, flags);
1823         irq_src = omap_readw(UDC_IRQ_SRC);
1824
1825         /* Device state change (usb ch9 stuff) */
1826         if (irq_src & UDC_DS_CHG) {
1827                 devstate_irq(_udc, irq_src);
1828                 status = IRQ_HANDLED;
1829                 irq_src &= ~UDC_DS_CHG;
1830         }
1831
1832         /* EP0 control transfers */
1833         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1834                 ep0_irq(_udc, irq_src);
1835                 status = IRQ_HANDLED;
1836                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1837         }
1838
1839         /* DMA transfer completion */
1840         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1841                 dma_irq(_udc, irq_src);
1842                 status = IRQ_HANDLED;
1843                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1844         }
1845
1846         irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1847         if (irq_src)
1848                 DBG("udc_irq, unhandled %03x\n", irq_src);
1849         spin_unlock_irqrestore(&udc->lock, flags);
1850
1851         return status;
1852 }
1853
1854 /* workaround for seemingly-lost IRQs for RX ACKs... */
1855 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1856 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1857
1858 static void pio_out_timer(unsigned long _ep)
1859 {
1860         struct omap_ep  *ep = (void *) _ep;
1861         unsigned long   flags;
1862         u16             stat_flg;
1863
1864         spin_lock_irqsave(&ep->udc->lock, flags);
1865         if (!list_empty(&ep->queue) && ep->ackwait) {
1866                 use_ep(ep, UDC_EP_SEL);
1867                 stat_flg = omap_readw(UDC_STAT_FLG);
1868
1869                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1870                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1871                         struct omap_req *req;
1872
1873                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1874                         req = container_of(ep->queue.next,
1875                                         struct omap_req, queue);
1876                         (void) read_fifo(ep, req);
1877                         omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1878                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1879                         ep->ackwait = 1 + ep->double_buf;
1880                 } else
1881                         deselect_ep();
1882         }
1883         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1884         spin_unlock_irqrestore(&ep->udc->lock, flags);
1885 }
1886
1887 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1888 {
1889         u16             epn_stat, irq_src;
1890         irqreturn_t     status = IRQ_NONE;
1891         struct omap_ep  *ep;
1892         int             epnum;
1893         struct omap_udc *udc = _dev;
1894         struct omap_req *req;
1895         unsigned long   flags;
1896
1897         spin_lock_irqsave(&udc->lock, flags);
1898         epn_stat = omap_readw(UDC_EPN_STAT);
1899         irq_src = omap_readw(UDC_IRQ_SRC);
1900
1901         /* handle OUT first, to avoid some wasteful NAKs */
1902         if (irq_src & UDC_EPN_RX) {
1903                 epnum = (epn_stat >> 8) & 0x0f;
1904                 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1905                 status = IRQ_HANDLED;
1906                 ep = &udc->ep[epnum];
1907                 ep->irqs++;
1908
1909                 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1910                 ep->fnf = 0;
1911                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1912                         ep->ackwait--;
1913                         if (!list_empty(&ep->queue)) {
1914                                 int stat;
1915                                 req = container_of(ep->queue.next,
1916                                                 struct omap_req, queue);
1917                                 stat = read_fifo(ep, req);
1918                                 if (!ep->double_buf)
1919                                         ep->fnf = 1;
1920                         }
1921                 }
1922                 /* min 6 clock delay before clearing EP_SEL ... */
1923                 epn_stat = omap_readw(UDC_EPN_STAT);
1924                 epn_stat = omap_readw(UDC_EPN_STAT);
1925                 omap_writew(epnum, UDC_EP_NUM);
1926
1927                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1928                  * reduces lossage; timer still needed though (sigh).
1929                  */
1930                 if (ep->fnf) {
1931                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1932                         ep->ackwait = 1 + ep->double_buf;
1933                 }
1934                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1935         }
1936
1937         /* then IN transfers */
1938         else if (irq_src & UDC_EPN_TX) {
1939                 epnum = epn_stat & 0x0f;
1940                 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1941                 status = IRQ_HANDLED;
1942                 ep = &udc->ep[16 + epnum];
1943                 ep->irqs++;
1944
1945                 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1946                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1947                         ep->ackwait = 0;
1948                         if (!list_empty(&ep->queue)) {
1949                                 req = container_of(ep->queue.next,
1950                                                 struct omap_req, queue);
1951                                 (void) write_fifo(ep, req);
1952                         }
1953                 }
1954                 /* min 6 clock delay before clearing EP_SEL ... */
1955                 epn_stat = omap_readw(UDC_EPN_STAT);
1956                 epn_stat = omap_readw(UDC_EPN_STAT);
1957                 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1958                 /* then 6 clocks before it'd tx */
1959         }
1960
1961         spin_unlock_irqrestore(&udc->lock, flags);
1962         return status;
1963 }
1964
1965 #ifdef  USE_ISO
1966 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1967 {
1968         struct omap_udc *udc = _dev;
1969         struct omap_ep  *ep;
1970         int             pending = 0;
1971         unsigned long   flags;
1972
1973         spin_lock_irqsave(&udc->lock, flags);
1974
1975         /* handle all non-DMA ISO transfers */
1976         list_for_each_entry(ep, &udc->iso, iso) {
1977                 u16             stat;
1978                 struct omap_req *req;
1979
1980                 if (ep->has_dma || list_empty(&ep->queue))
1981                         continue;
1982                 req = list_entry(ep->queue.next, struct omap_req, queue);
1983
1984                 use_ep(ep, UDC_EP_SEL);
1985                 stat = omap_readw(UDC_STAT_FLG);
1986
1987                 /* NOTE: like the other controller drivers, this isn't
1988                  * currently reporting lost or damaged frames.
1989                  */
1990                 if (ep->bEndpointAddress & USB_DIR_IN) {
1991                         if (stat & UDC_MISS_IN)
1992                                 /* done(ep, req, -EPROTO) */;
1993                         else
1994                                 write_fifo(ep, req);
1995                 } else {
1996                         int     status = 0;
1997
1998                         if (stat & UDC_NO_RXPACKET)
1999                                 status = -EREMOTEIO;
2000                         else if (stat & UDC_ISO_ERR)
2001                                 status = -EILSEQ;
2002                         else if (stat & UDC_DATA_FLUSH)
2003                                 status = -ENOSR;
2004
2005                         if (status)
2006                                 /* done(ep, req, status) */;
2007                         else
2008                                 read_fifo(ep, req);
2009                 }
2010                 deselect_ep();
2011                 /* 6 wait states before next EP */
2012
2013                 ep->irqs++;
2014                 if (!list_empty(&ep->queue))
2015                         pending = 1;
2016         }
2017         if (!pending) {
2018                 u16 w;
2019
2020                 w = omap_readw(UDC_IRQ_EN);
2021                 w &= ~UDC_SOF_IE;
2022                 omap_writew(w, UDC_IRQ_EN);
2023         }
2024         omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2025
2026         spin_unlock_irqrestore(&udc->lock, flags);
2027         return IRQ_HANDLED;
2028 }
2029 #endif
2030
2031 /*-------------------------------------------------------------------------*/
2032
2033 static inline int machine_without_vbus_sense(void)
2034 {
2035         return machine_is_omap_innovator()
2036                 || machine_is_omap_osk()
2037                 || machine_is_sx1()
2038                 /* No known omap7xx boards with vbus sense */
2039                 || cpu_is_omap7xx();
2040 }
2041
2042 static int omap_udc_start(struct usb_gadget_driver *driver,
2043                 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *))
2044 {
2045         int             status = -ENODEV;
2046         struct omap_ep  *ep;
2047         unsigned long   flags;
2048
2049         /* basic sanity tests */
2050         if (!udc)
2051                 return -ENODEV;
2052         if (!driver
2053                         /* FIXME if otg, check:  driver->is_otg */
2054                         || driver->max_speed < USB_SPEED_FULL
2055                         || !bind || !driver->setup)
2056                 return -EINVAL;
2057
2058         spin_lock_irqsave(&udc->lock, flags);
2059         if (udc->driver) {
2060                 spin_unlock_irqrestore(&udc->lock, flags);
2061                 return -EBUSY;
2062         }
2063
2064         /* reset state */
2065         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2066                 ep->irqs = 0;
2067                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2068                         continue;
2069                 use_ep(ep, 0);
2070                 omap_writew(UDC_SET_HALT, UDC_CTRL);
2071         }
2072         udc->ep0_pending = 0;
2073         udc->ep[0].irqs = 0;
2074         udc->softconnect = 1;
2075
2076         /* hook up the driver */
2077         driver->driver.bus = NULL;
2078         udc->driver = driver;
2079         udc->gadget.dev.driver = &driver->driver;
2080         spin_unlock_irqrestore(&udc->lock, flags);
2081
2082         if (udc->dc_clk != NULL)
2083                 omap_udc_enable_clock(1);
2084
2085         status = bind(&udc->gadget, driver);
2086         if (status) {
2087                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2088                 udc->gadget.dev.driver = NULL;
2089                 udc->driver = NULL;
2090                 goto done;
2091         }
2092         DBG("bound to driver %s\n", driver->driver.name);
2093
2094         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2095
2096         /* connect to bus through transceiver */
2097         if (!IS_ERR_OR_NULL(udc->transceiver)) {
2098                 status = otg_set_peripheral(udc->transceiver->otg,
2099                                                 &udc->gadget);
2100                 if (status < 0) {
2101                         ERR("can't bind to transceiver\n");
2102                         if (driver->unbind) {
2103                                 driver->unbind(&udc->gadget);
2104                                 udc->gadget.dev.driver = NULL;
2105                                 udc->driver = NULL;
2106                         }
2107                         goto done;
2108                 }
2109         } else {
2110                 if (can_pullup(udc))
2111                         pullup_enable(udc);
2112                 else
2113                         pullup_disable(udc);
2114         }
2115
2116         /* boards that don't have VBUS sensing can't autogate 48MHz;
2117          * can't enter deep sleep while a gadget driver is active.
2118          */
2119         if (machine_without_vbus_sense())
2120                 omap_vbus_session(&udc->gadget, 1);
2121
2122 done:
2123         if (udc->dc_clk != NULL)
2124                 omap_udc_enable_clock(0);
2125         return status;
2126 }
2127
2128 static int omap_udc_stop(struct usb_gadget_driver *driver)
2129 {
2130         unsigned long   flags;
2131         int             status = -ENODEV;
2132
2133         if (!udc)
2134                 return -ENODEV;
2135         if (!driver || driver != udc->driver || !driver->unbind)
2136                 return -EINVAL;
2137
2138         if (udc->dc_clk != NULL)
2139                 omap_udc_enable_clock(1);
2140
2141         if (machine_without_vbus_sense())
2142                 omap_vbus_session(&udc->gadget, 0);
2143
2144         if (!IS_ERR_OR_NULL(udc->transceiver))
2145                 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2146         else
2147                 pullup_disable(udc);
2148
2149         spin_lock_irqsave(&udc->lock, flags);
2150         udc_quiesce(udc);
2151         spin_unlock_irqrestore(&udc->lock, flags);
2152
2153         driver->unbind(&udc->gadget);
2154         udc->gadget.dev.driver = NULL;
2155         udc->driver = NULL;
2156
2157         if (udc->dc_clk != NULL)
2158                 omap_udc_enable_clock(0);
2159         DBG("unregistered driver '%s'\n", driver->driver.name);
2160         return status;
2161 }
2162
2163 /*-------------------------------------------------------------------------*/
2164
2165 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2166
2167 #include <linux/seq_file.h>
2168
2169 static const char proc_filename[] = "driver/udc";
2170
2171 #define FOURBITS "%s%s%s%s"
2172 #define EIGHTBITS "%s%s%s%s%s%s%s%s"
2173
2174 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2175 {
2176         u16             stat_flg;
2177         struct omap_req *req;
2178         char            buf[20];
2179
2180         use_ep(ep, 0);
2181
2182         if (use_dma && ep->has_dma)
2183                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2184                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2185                         ep->dma_channel - 1, ep->lch);
2186         else
2187                 buf[0] = 0;
2188
2189         stat_flg = omap_readw(UDC_STAT_FLG);
2190         seq_printf(s,
2191                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2192                 ep->name, buf,
2193                 ep->double_buf ? "dbuf " : "",
2194                 ({ char *s;
2195                 switch (ep->ackwait) {
2196                 case 0:
2197                         s = "";
2198                         break;
2199                 case 1:
2200                         s = "(ackw) ";
2201                         break;
2202                 case 2:
2203                         s = "(ackw2) ";
2204                         break;
2205                 default:
2206                         s = "(?) ";
2207                         break;
2208                 } s; }),
2209                 ep->irqs, stat_flg,
2210                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2211                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2212                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2213                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2214                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2215                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2216                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2217                 (stat_flg & UDC_STALL) ? "STALL " : "",
2218                 (stat_flg & UDC_NAK) ? "NAK " : "",
2219                 (stat_flg & UDC_ACK) ? "ACK " : "",
2220                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2221                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2222                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2223
2224         if (list_empty(&ep->queue))
2225                 seq_printf(s, "\t(queue empty)\n");
2226         else
2227                 list_for_each_entry(req, &ep->queue, queue) {
2228                         unsigned        length = req->req.actual;
2229
2230                         if (use_dma && buf[0]) {
2231                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2232                                                 ? dma_src_len : dma_dest_len)
2233                                         (ep, req->req.dma + length);
2234                                 buf[0] = 0;
2235                         }
2236                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2237                                         &req->req, length,
2238                                         req->req.length, req->req.buf);
2239                 }
2240 }
2241
2242 static char *trx_mode(unsigned m, int enabled)
2243 {
2244         switch (m) {
2245         case 0:
2246                 return enabled ? "*6wire" : "unused";
2247         case 1:
2248                 return "4wire";
2249         case 2:
2250                 return "3wire";
2251         case 3:
2252                 return "6wire";
2253         default:
2254                 return "unknown";
2255         }
2256 }
2257
2258 static int proc_otg_show(struct seq_file *s)
2259 {
2260         u32             tmp;
2261         u32             trans = 0;
2262         char            *ctrl_name = "(UNKNOWN)";
2263
2264         tmp = omap_readl(OTG_REV);
2265         ctrl_name = "tranceiver_ctrl";
2266         trans = omap_readw(USB_TRANSCEIVER_CTRL);
2267         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2268                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2269         tmp = omap_readw(OTG_SYSCON_1);
2270         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2271                         FOURBITS "\n", tmp,
2272                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2273                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2274                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2275                         ? "internal"
2276                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2277                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2278                 (tmp & HST_IDLE_EN) ? " !host" : "",
2279                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2280                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2281         tmp = omap_readl(OTG_SYSCON_2);
2282         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2283                         " b_ase_brst=%d hmc=%d\n", tmp,
2284                 (tmp & OTG_EN) ? " otg_en" : "",
2285                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2286                 /* much more SRP stuff */
2287                 (tmp & SRP_DATA) ? " srp_data" : "",
2288                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2289                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2290                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2291                 (tmp & UHOST_EN) ? " uhost_en" : "",
2292                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2293                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2294                 B_ASE_BRST(tmp),
2295                 OTG_HMC(tmp));
2296         tmp = omap_readl(OTG_CTRL);
2297         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2298                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2299                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2300                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2301                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2302                 (tmp & OTG_ID) ? " id" : "",
2303                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2304                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2305                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2306                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2307                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2308                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2309                 (tmp & OTG_PULLDOWN) ? " down" : "",
2310                 (tmp & OTG_PULLUP) ? " up" : "",
2311                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2312                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2313                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2314                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2315                 );
2316         tmp = omap_readw(OTG_IRQ_EN);
2317         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2318         tmp = omap_readw(OTG_IRQ_SRC);
2319         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2320         tmp = omap_readw(OTG_OUTCTRL);
2321         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2322         tmp = omap_readw(OTG_TEST);
2323         seq_printf(s, "otg_test    %04x" "\n", tmp);
2324         return 0;
2325 }
2326
2327 static int proc_udc_show(struct seq_file *s, void *_)
2328 {
2329         u32             tmp;
2330         struct omap_ep  *ep;
2331         unsigned long   flags;
2332
2333         spin_lock_irqsave(&udc->lock, flags);
2334
2335         seq_printf(s, "%s, version: " DRIVER_VERSION
2336 #ifdef  USE_ISO
2337                 " (iso)"
2338 #endif
2339                 "%s\n",
2340                 driver_desc,
2341                 use_dma ?  " (dma)" : "");
2342
2343         tmp = omap_readw(UDC_REV) & 0xff;
2344         seq_printf(s,
2345                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2346                 "hmc %d, transceiver %s\n",
2347                 tmp >> 4, tmp & 0xf,
2348                 fifo_mode,
2349                 udc->driver ? udc->driver->driver.name : "(none)",
2350                 HMC,
2351                 udc->transceiver
2352                         ? udc->transceiver->label
2353                         : (cpu_is_omap1710()
2354                                 ? "external" : "(none)"));
2355         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2356                 omap_readw(ULPD_CLOCK_CTRL),
2357                 omap_readw(ULPD_SOFT_REQ),
2358                 omap_readw(ULPD_STATUS_REQ));
2359
2360         /* OTG controller registers */
2361         if (!cpu_is_omap15xx())
2362                 proc_otg_show(s);
2363
2364         tmp = omap_readw(UDC_SYSCON1);
2365         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2366                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2367                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2368                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2369                 (tmp & UDC_NAK_EN) ? " nak" : "",
2370                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2371                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2372                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2373                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2374         /* syscon2 is write-only */
2375
2376         /* UDC controller registers */
2377         if (!(tmp & UDC_PULLUP_EN)) {
2378                 seq_printf(s, "(suspended)\n");
2379                 spin_unlock_irqrestore(&udc->lock, flags);
2380                 return 0;
2381         }
2382
2383         tmp = omap_readw(UDC_DEVSTAT);
2384         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2385                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2386                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2387                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2388                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2389                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2390                 (tmp & UDC_SUS) ? " SUS" : "",
2391                 (tmp & UDC_CFG) ? " CFG" : "",
2392                 (tmp & UDC_ADD) ? " ADD" : "",
2393                 (tmp & UDC_DEF) ? " DEF" : "",
2394                 (tmp & UDC_ATT) ? " ATT" : "");
2395         seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2396         tmp = omap_readw(UDC_IRQ_EN);
2397         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2398                 (tmp & UDC_SOF_IE) ? " sof" : "",
2399                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2400                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2401                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2402                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2403         tmp = omap_readw(UDC_IRQ_SRC);
2404         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2405                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2406                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2407                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2408                 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2409                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2410                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2411                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2412                 (tmp & UDC_SETUP) ? " setup" : "",
2413                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2414                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2415         if (use_dma) {
2416                 unsigned i;
2417
2418                 tmp = omap_readw(UDC_DMA_IRQ_EN);
2419                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2420                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2421                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2422                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2423
2424                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2425                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2426                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2427
2428                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2429                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2430                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2431
2432                 tmp = omap_readw(UDC_RXDMA_CFG);
2433                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2434                 if (tmp) {
2435                         for (i = 0; i < 3; i++) {
2436                                 if ((tmp & (0x0f << (i * 4))) == 0)
2437                                         continue;
2438                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2439                                                 omap_readw(UDC_RXDMA(i + 1)));
2440                         }
2441                 }
2442                 tmp = omap_readw(UDC_TXDMA_CFG);
2443                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2444                 if (tmp) {
2445                         for (i = 0; i < 3; i++) {
2446                                 if (!(tmp & (0x0f << (i * 4))))
2447                                         continue;
2448                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2449                                                 omap_readw(UDC_TXDMA(i + 1)));
2450                         }
2451                 }
2452         }
2453
2454         tmp = omap_readw(UDC_DEVSTAT);
2455         if (tmp & UDC_ATT) {
2456                 proc_ep_show(s, &udc->ep[0]);
2457                 if (tmp & UDC_ADD) {
2458                         list_for_each_entry(ep, &udc->gadget.ep_list,
2459                                         ep.ep_list) {
2460                                 if (ep->ep.desc)
2461                                         proc_ep_show(s, ep);
2462                         }
2463                 }
2464         }
2465         spin_unlock_irqrestore(&udc->lock, flags);
2466         return 0;
2467 }
2468
2469 static int proc_udc_open(struct inode *inode, struct file *file)
2470 {
2471         return single_open(file, proc_udc_show, NULL);
2472 }
2473
2474 static const struct file_operations proc_ops = {
2475         .owner          = THIS_MODULE,
2476         .open           = proc_udc_open,
2477         .read           = seq_read,
2478         .llseek         = seq_lseek,
2479         .release        = single_release,
2480 };
2481
2482 static void create_proc_file(void)
2483 {
2484         proc_create(proc_filename, 0, NULL, &proc_ops);
2485 }
2486
2487 static void remove_proc_file(void)
2488 {
2489         remove_proc_entry(proc_filename, NULL);
2490 }
2491
2492 #else
2493
2494 static inline void create_proc_file(void) {}
2495 static inline void remove_proc_file(void) {}
2496
2497 #endif
2498
2499 /*-------------------------------------------------------------------------*/
2500
2501 /* Before this controller can enumerate, we need to pick an endpoint
2502  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2503  * buffer space among the endpoints we'll be operating.
2504  *
2505  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2506  * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2507  * capability yet though.
2508  */
2509 static unsigned __devinit
2510 omap_ep_setup(char *name, u8 addr, u8 type,
2511                 unsigned buf, unsigned maxp, int dbuf)
2512 {
2513         struct omap_ep  *ep;
2514         u16             epn_rxtx = 0;
2515
2516         /* OUT endpoints first, then IN */
2517         ep = &udc->ep[addr & 0xf];
2518         if (addr & USB_DIR_IN)
2519                 ep += 16;
2520
2521         /* in case of ep init table bugs */
2522         BUG_ON(ep->name[0]);
2523
2524         /* chip setup ... bit values are same for IN, OUT */
2525         if (type == USB_ENDPOINT_XFER_ISOC) {
2526                 switch (maxp) {
2527                 case 8:
2528                         epn_rxtx = 0 << 12;
2529                         break;
2530                 case 16:
2531                         epn_rxtx = 1 << 12;
2532                         break;
2533                 case 32:
2534                         epn_rxtx = 2 << 12;
2535                         break;
2536                 case 64:
2537                         epn_rxtx = 3 << 12;
2538                         break;
2539                 case 128:
2540                         epn_rxtx = 4 << 12;
2541                         break;
2542                 case 256:
2543                         epn_rxtx = 5 << 12;
2544                         break;
2545                 case 512:
2546                         epn_rxtx = 6 << 12;
2547                         break;
2548                 default:
2549                         BUG();
2550                 }
2551                 epn_rxtx |= UDC_EPN_RX_ISO;
2552                 dbuf = 1;
2553         } else {
2554                 /* double-buffering "not supported" on 15xx,
2555                  * and ignored for PIO-IN on newer chips
2556                  * (for more reliable behavior)
2557                  */
2558                 if (!use_dma || cpu_is_omap15xx())
2559                         dbuf = 0;
2560
2561                 switch (maxp) {
2562                 case 8:
2563                         epn_rxtx = 0 << 12;
2564                         break;
2565                 case 16:
2566                         epn_rxtx = 1 << 12;
2567                         break;
2568                 case 32:
2569                         epn_rxtx = 2 << 12;
2570                         break;
2571                 case 64:
2572                         epn_rxtx = 3 << 12;
2573                         break;
2574                 default:
2575                         BUG();
2576                 }
2577                 if (dbuf && addr)
2578                         epn_rxtx |= UDC_EPN_RX_DB;
2579                 init_timer(&ep->timer);
2580                 ep->timer.function = pio_out_timer;
2581                 ep->timer.data = (unsigned long) ep;
2582         }
2583         if (addr)
2584                 epn_rxtx |= UDC_EPN_RX_VALID;
2585         BUG_ON(buf & 0x07);
2586         epn_rxtx |= buf >> 3;
2587
2588         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2589                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2590
2591         if (addr & USB_DIR_IN)
2592                 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2593         else
2594                 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2595
2596         /* next endpoint's buffer starts after this one's */
2597         buf += maxp;
2598         if (dbuf)
2599                 buf += maxp;
2600         BUG_ON(buf > 2048);
2601
2602         /* set up driver data structures */
2603         BUG_ON(strlen(name) >= sizeof ep->name);
2604         strlcpy(ep->name, name, sizeof ep->name);
2605         INIT_LIST_HEAD(&ep->queue);
2606         INIT_LIST_HEAD(&ep->iso);
2607         ep->bEndpointAddress = addr;
2608         ep->bmAttributes = type;
2609         ep->double_buf = dbuf;
2610         ep->udc = udc;
2611
2612         ep->ep.name = ep->name;
2613         ep->ep.ops = &omap_ep_ops;
2614         ep->ep.maxpacket = ep->maxpacket = maxp;
2615         list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2616
2617         return buf;
2618 }
2619
2620 static void omap_udc_release(struct device *dev)
2621 {
2622         complete(udc->done);
2623         kfree(udc);
2624         udc = NULL;
2625 }
2626
2627 static int __devinit
2628 omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2629 {
2630         unsigned        tmp, buf;
2631
2632         /* abolish any previous hardware state */
2633         omap_writew(0, UDC_SYSCON1);
2634         omap_writew(0, UDC_IRQ_EN);
2635         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2636         omap_writew(0, UDC_DMA_IRQ_EN);
2637         omap_writew(0, UDC_RXDMA_CFG);
2638         omap_writew(0, UDC_TXDMA_CFG);
2639
2640         /* UDC_PULLUP_EN gates the chip clock */
2641         /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2642
2643         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2644         if (!udc)
2645                 return -ENOMEM;
2646
2647         spin_lock_init(&udc->lock);
2648
2649         udc->gadget.ops = &omap_gadget_ops;
2650         udc->gadget.ep0 = &udc->ep[0].ep;
2651         INIT_LIST_HEAD(&udc->gadget.ep_list);
2652         INIT_LIST_HEAD(&udc->iso);
2653         udc->gadget.speed = USB_SPEED_UNKNOWN;
2654         udc->gadget.max_speed = USB_SPEED_FULL;
2655         udc->gadget.name = driver_name;
2656
2657         device_initialize(&udc->gadget.dev);
2658         dev_set_name(&udc->gadget.dev, "gadget");
2659         udc->gadget.dev.release = omap_udc_release;
2660         udc->gadget.dev.parent = &odev->dev;
2661         if (use_dma)
2662                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2663
2664         udc->transceiver = xceiv;
2665
2666         /* ep0 is special; put it right after the SETUP buffer */
2667         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2668                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2669         list_del_init(&udc->ep[0].ep.ep_list);
2670
2671         /* initially disable all non-ep0 endpoints */
2672         for (tmp = 1; tmp < 15; tmp++) {
2673                 omap_writew(0, UDC_EP_RX(tmp));
2674                 omap_writew(0, UDC_EP_TX(tmp));
2675         }
2676
2677 #define OMAP_BULK_EP(name, addr) \
2678         buf = omap_ep_setup(name "-bulk", addr, \
2679                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2680 #define OMAP_INT_EP(name, addr, maxp) \
2681         buf = omap_ep_setup(name "-int", addr, \
2682                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2683 #define OMAP_ISO_EP(name, addr, maxp) \
2684         buf = omap_ep_setup(name "-iso", addr, \
2685                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2686
2687         switch (fifo_mode) {
2688         case 0:
2689                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2690                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2691                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2692                 break;
2693         case 1:
2694                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2695                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2696                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2697
2698                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2699                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2700                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2701
2702                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2703                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2704                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2705
2706                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2707                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2708                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2709
2710                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2711                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2712                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2713                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2714
2715                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2716                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2717                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2718                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2719
2720                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2721                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2722
2723                 break;
2724
2725 #ifdef  USE_ISO
2726         case 2:                 /* mixed iso/bulk */
2727                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2728                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2729                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2730                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2731
2732                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2733
2734                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2735                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2736                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2737                 break;
2738         case 3:                 /* mixed bulk/iso */
2739                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2740                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2741                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2742
2743                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2744                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2745                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2746
2747                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2748                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2749                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2750                 break;
2751 #endif
2752
2753         /* add more modes as needed */
2754
2755         default:
2756                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2757                 return -ENODEV;
2758         }
2759         omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2760         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2761         return 0;
2762 }
2763
2764 static int __devinit omap_udc_probe(struct platform_device *pdev)
2765 {
2766         int                     status = -ENODEV;
2767         int                     hmc;
2768         struct usb_phy          *xceiv = NULL;
2769         const char              *type = NULL;
2770         struct omap_usb_config  *config = pdev->dev.platform_data;
2771         struct clk              *dc_clk = NULL;
2772         struct clk              *hhc_clk = NULL;
2773
2774         if (cpu_is_omap7xx())
2775                 use_dma = 0;
2776
2777         /* NOTE:  "knows" the order of the resources! */
2778         if (!request_mem_region(pdev->resource[0].start,
2779                         pdev->resource[0].end - pdev->resource[0].start + 1,
2780                         driver_name)) {
2781                 DBG("request_mem_region failed\n");
2782                 return -EBUSY;
2783         }
2784
2785         if (cpu_is_omap16xx()) {
2786                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2787                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2788                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2789                 /* can't use omap_udc_enable_clock yet */
2790                 clk_enable(dc_clk);
2791                 clk_enable(hhc_clk);
2792                 udelay(100);
2793         }
2794
2795         if (cpu_is_omap7xx()) {
2796                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2797                 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2798                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2799                 /* can't use omap_udc_enable_clock yet */
2800                 clk_enable(dc_clk);
2801                 clk_enable(hhc_clk);
2802                 udelay(100);
2803         }
2804
2805         INFO("OMAP UDC rev %d.%d%s\n",
2806                 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2807                 config->otg ? ", Mini-AB" : "");
2808
2809         /* use the mode given to us by board init code */
2810         if (cpu_is_omap15xx()) {
2811                 hmc = HMC_1510;
2812                 type = "(unknown)";
2813
2814                 if (machine_without_vbus_sense()) {
2815                         /* just set up software VBUS detect, and then
2816                          * later rig it so we always report VBUS.
2817                          * FIXME without really sensing VBUS, we can't
2818                          * know when to turn PULLUP_EN on/off; and that
2819                          * means we always "need" the 48MHz clock.
2820                          */
2821                         u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2822                         tmp &= ~VBUS_CTRL_1510;
2823                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2824                         tmp |= VBUS_MODE_1510;
2825                         tmp &= ~VBUS_CTRL_1510;
2826                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2827                 }
2828         } else {
2829                 /* The transceiver may package some GPIO logic or handle
2830                  * loopback and/or transceiverless setup; if we find one,
2831                  * use it.  Except for OTG, we don't _need_ to talk to one;
2832                  * but not having one probably means no VBUS detection.
2833                  */
2834                 xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2835                 if (!IS_ERR_OR_NULL(xceiv))
2836                         type = xceiv->label;
2837                 else if (config->otg) {
2838                         DBG("OTG requires external transceiver!\n");
2839                         goto cleanup0;
2840                 }
2841
2842                 hmc = HMC_1610;
2843
2844                 switch (hmc) {
2845                 case 0:                 /* POWERUP DEFAULT == 0 */
2846                 case 4:
2847                 case 12:
2848                 case 20:
2849                         if (!cpu_is_omap1710()) {
2850                                 type = "integrated";
2851                                 break;
2852                         }
2853                         /* FALL THROUGH */
2854                 case 3:
2855                 case 11:
2856                 case 16:
2857                 case 19:
2858                 case 25:
2859                         if (IS_ERR_OR_NULL(xceiv)) {
2860                                 DBG("external transceiver not registered!\n");
2861                                 type = "unknown";
2862                         }
2863                         break;
2864                 case 21:                        /* internal loopback */
2865                         type = "loopback";
2866                         break;
2867                 case 14:                        /* transceiverless */
2868                         if (cpu_is_omap1710())
2869                                 goto bad_on_1710;
2870                         /* FALL THROUGH */
2871                 case 13:
2872                 case 15:
2873                         type = "no";
2874                         break;
2875
2876                 default:
2877 bad_on_1710:
2878                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2879                         goto cleanup0;
2880                 }
2881         }
2882
2883         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2884
2885         /* a "gadget" abstracts/virtualizes the controller */
2886         status = omap_udc_setup(pdev, xceiv);
2887         if (status)
2888                 goto cleanup0;
2889
2890         xceiv = NULL;
2891         /* "udc" is now valid */
2892         pullup_disable(udc);
2893 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2894         udc->gadget.is_otg = (config->otg != 0);
2895 #endif
2896
2897         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2898         if (omap_readw(UDC_REV) >= 0x61)
2899                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2900         else
2901                 udc->clr_halt = UDC_RESET_EP;
2902
2903         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2904         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2905                         0, driver_name, udc);
2906         if (status != 0) {
2907                 ERR("can't get irq %d, err %d\n",
2908                         (int) pdev->resource[1].start, status);
2909                 goto cleanup1;
2910         }
2911
2912         /* USB "non-iso" IRQ (PIO for all but ep0) */
2913         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2914                         0, "omap_udc pio", udc);
2915         if (status != 0) {
2916                 ERR("can't get irq %d, err %d\n",
2917                         (int) pdev->resource[2].start, status);
2918                 goto cleanup2;
2919         }
2920 #ifdef  USE_ISO
2921         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2922                         0, "omap_udc iso", udc);
2923         if (status != 0) {
2924                 ERR("can't get irq %d, err %d\n",
2925                         (int) pdev->resource[3].start, status);
2926                 goto cleanup3;
2927         }
2928 #endif
2929         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2930                 udc->dc_clk = dc_clk;
2931                 udc->hhc_clk = hhc_clk;
2932                 clk_disable(hhc_clk);
2933                 clk_disable(dc_clk);
2934         }
2935
2936         create_proc_file();
2937         status = device_add(&udc->gadget.dev);
2938         if (status)
2939                 goto cleanup4;
2940
2941         status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2942         if (!status)
2943                 return status;
2944         /* If fail, fall through */
2945 cleanup4:
2946         remove_proc_file();
2947
2948 #ifdef  USE_ISO
2949 cleanup3:
2950         free_irq(pdev->resource[2].start, udc);
2951 #endif
2952
2953 cleanup2:
2954         free_irq(pdev->resource[1].start, udc);
2955
2956 cleanup1:
2957         kfree(udc);
2958         udc = NULL;
2959
2960 cleanup0:
2961         if (!IS_ERR_OR_NULL(xceiv))
2962                 usb_put_phy(xceiv);
2963
2964         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2965                 clk_disable(hhc_clk);
2966                 clk_disable(dc_clk);
2967                 clk_put(hhc_clk);
2968                 clk_put(dc_clk);
2969         }
2970
2971         release_mem_region(pdev->resource[0].start,
2972                         pdev->resource[0].end - pdev->resource[0].start + 1);
2973
2974         return status;
2975 }
2976
2977 static int __devexit omap_udc_remove(struct platform_device *pdev)
2978 {
2979         DECLARE_COMPLETION_ONSTACK(done);
2980
2981         if (!udc)
2982                 return -ENODEV;
2983
2984         usb_del_gadget_udc(&udc->gadget);
2985         if (udc->driver)
2986                 return -EBUSY;
2987
2988         udc->done = &done;
2989
2990         pullup_disable(udc);
2991         if (!IS_ERR_OR_NULL(udc->transceiver)) {
2992                 usb_put_phy(udc->transceiver);
2993                 udc->transceiver = NULL;
2994         }
2995         omap_writew(0, UDC_SYSCON1);
2996
2997         remove_proc_file();
2998
2999 #ifdef  USE_ISO
3000         free_irq(pdev->resource[3].start, udc);
3001 #endif
3002         free_irq(pdev->resource[2].start, udc);
3003         free_irq(pdev->resource[1].start, udc);
3004
3005         if (udc->dc_clk) {
3006                 if (udc->clk_requested)
3007                         omap_udc_enable_clock(0);
3008                 clk_put(udc->hhc_clk);
3009                 clk_put(udc->dc_clk);
3010         }
3011
3012         release_mem_region(pdev->resource[0].start,
3013                         pdev->resource[0].end - pdev->resource[0].start + 1);
3014
3015         device_unregister(&udc->gadget.dev);
3016         wait_for_completion(&done);
3017
3018         return 0;
3019 }
3020
3021 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3022  * system is forced into deep sleep
3023  *
3024  * REVISIT we should probably reject suspend requests when there's a host
3025  * session active, rather than disconnecting, at least on boards that can
3026  * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
3027  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3028  * may involve talking to an external transceiver (e.g. isp1301).
3029  */
3030
3031 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3032 {
3033         u32     devstat;
3034
3035         devstat = omap_readw(UDC_DEVSTAT);
3036
3037         /* we're requesting 48 MHz clock if the pullup is enabled
3038          * (== we're attached to the host) and we're not suspended,
3039          * which would prevent entry to deep sleep...
3040          */
3041         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3042                 WARNING("session active; suspend requires disconnect\n");
3043                 omap_pullup(&udc->gadget, 0);
3044         }
3045
3046         return 0;
3047 }
3048
3049 static int omap_udc_resume(struct platform_device *dev)
3050 {
3051         DBG("resume + wakeup/SRP\n");
3052         omap_pullup(&udc->gadget, 1);
3053
3054         /* maybe the host would enumerate us if we nudged it */
3055         msleep(100);
3056         return omap_wakeup(&udc->gadget);
3057 }
3058
3059 /*-------------------------------------------------------------------------*/
3060
3061 static struct platform_driver udc_driver = {
3062         .probe          = omap_udc_probe,
3063         .remove         = __devexit_p(omap_udc_remove),
3064         .suspend        = omap_udc_suspend,
3065         .resume         = omap_udc_resume,
3066         .driver         = {
3067                 .owner  = THIS_MODULE,
3068                 .name   = (char *) driver_name,
3069         },
3070 };
3071
3072 module_platform_driver(udc_driver);
3073
3074 MODULE_DESCRIPTION(DRIVER_DESC);
3075 MODULE_LICENSE("GPL");
3076 MODULE_ALIAS("platform:omap_udc");