Merge tag 'acpi-5.1-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[muen/linux.git] / drivers / usb / host / xhci-hub.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * xHCI host controller driver
4  *
5  * Copyright (C) 2008 Intel Corp.
6  *
7  * Author: Sarah Sharp
8  * Some code borrowed from the Linux EHCI driver.
9  */
10
11
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
14
15 #include "xhci.h"
16 #include "xhci-trace.h"
17
18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
20                          PORT_RC | PORT_PLC | PORT_PE)
21
22 /* USB 3 BOS descriptor and a capability descriptors, combined.
23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
24  */
25 static u8 usb_bos_descriptor [] = {
26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
29         0x1,                            /*  __u8 bNumDeviceCaps */
30         /* First device capability, SuperSpeed */
31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
34         0x00,                           /* bmAttributes, LTM off by default */
35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
36         0x03,                           /* bFunctionalitySupport,
37                                            USB 3.0 speed only */
38         0x00,                           /* bU1DevExitLat, set later. */
39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
40         /* Second device capability, SuperSpeedPlus */
41         0x1c,                           /* bLength 28, will be adjusted later */
42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
44         0x00,                           /* bReserved 0 */
45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
46         0x01, 0x00,                     /* wFunctionalitySupport */
47         0x00, 0x00,                     /* wReserved 0 */
48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
53 };
54
55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
56                                      u16 wLength)
57 {
58         int i, ssa_count;
59         u32 temp;
60         u16 desc_size, ssp_cap_size, ssa_size = 0;
61         bool usb3_1 = false;
62
63         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
64         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
65
66         /* does xhci support USB 3.1 Enhanced SuperSpeed */
67         if (xhci->usb3_rhub.min_rev >= 0x01) {
68                 /* does xhci provide a PSI table for SSA speed attributes? */
69                 if (xhci->usb3_rhub.psi_count) {
70                         /* two SSA entries for each unique PSI ID, RX and TX */
71                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
72                         ssa_size = ssa_count * sizeof(u32);
73                         ssp_cap_size -= 16; /* skip copying the default SSA */
74                 }
75                 desc_size += ssp_cap_size;
76                 usb3_1 = true;
77         }
78         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
79
80         if (usb3_1) {
81                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
82                 buf[4] += 1;
83                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
84         }
85
86         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
87                 return wLength;
88
89         /* Indicate whether the host has LTM support. */
90         temp = readl(&xhci->cap_regs->hcc_params);
91         if (HCC_LTC(temp))
92                 buf[8] |= USB_LTM_SUPPORT;
93
94         /* Set the U1 and U2 exit latencies. */
95         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
96                 temp = readl(&xhci->cap_regs->hcs_params3);
97                 buf[12] = HCS_U1_LATENCY(temp);
98                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
99         }
100
101         /* If PSI table exists, add the custom speed attributes from it */
102         if (usb3_1 && xhci->usb3_rhub.psi_count) {
103                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
104                 int offset;
105
106                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
107
108                 if (wLength < desc_size)
109                         return wLength;
110                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
111
112                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
113                 bm_attrib = (ssa_count - 1) & 0x1f;
114                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
115                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
116
117                 if (wLength < desc_size + ssa_size)
118                         return wLength;
119                 /*
120                  * Create the Sublink Speed Attributes (SSA) array.
121                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
122                  * but link type bits 7:6 differ for values 01b and 10b.
123                  * xhci has also only one PSI entry for a symmetric link when
124                  * USB 3.1 requires two SSA entries (RX and TX) for every link
125                  */
126                 offset = desc_size;
127                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
128                         psi = xhci->usb3_rhub.psi[i];
129                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
130                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
131                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
132
133                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
134                         for (; psi_exp < 3; psi_exp++)
135                                 psi_mant /= 1000;
136                         if (psi_mant >= 10)
137                                 psi |= BIT(14);
138
139                         if ((psi & PLT_MASK) == PLT_SYM) {
140                         /* Symmetric, create SSA RX and TX from one PSI entry */
141                                 put_unaligned_le32(psi, &buf[offset]);
142                                 psi |= 1 << 7;  /* turn entry to TX */
143                                 offset += 4;
144                                 if (offset >= desc_size + ssa_size)
145                                         return desc_size + ssa_size;
146                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
147                                 /* Asymetric RX, flip bits 7:6 for SSA */
148                                 psi ^= PLT_MASK;
149                         }
150                         put_unaligned_le32(psi, &buf[offset]);
151                         offset += 4;
152                         if (offset >= desc_size + ssa_size)
153                                 return desc_size + ssa_size;
154                 }
155         }
156         /* ssa_size is 0 for other than usb 3.1 hosts */
157         return desc_size + ssa_size;
158 }
159
160 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
161                 struct usb_hub_descriptor *desc, int ports)
162 {
163         u16 temp;
164
165         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
166         desc->bHubContrCurrent = 0;
167
168         desc->bNbrPorts = ports;
169         temp = 0;
170         /* Bits 1:0 - support per-port power switching, or power always on */
171         if (HCC_PPC(xhci->hcc_params))
172                 temp |= HUB_CHAR_INDV_PORT_LPSM;
173         else
174                 temp |= HUB_CHAR_NO_LPSM;
175         /* Bit  2 - root hubs are not part of a compound device */
176         /* Bits 4:3 - individual port over current protection */
177         temp |= HUB_CHAR_INDV_PORT_OCPM;
178         /* Bits 6:5 - no TTs in root ports */
179         /* Bit  7 - no port indicators */
180         desc->wHubCharacteristics = cpu_to_le16(temp);
181 }
182
183 /* Fill in the USB 2.0 roothub descriptor */
184 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
185                 struct usb_hub_descriptor *desc)
186 {
187         int ports;
188         u16 temp;
189         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
190         u32 portsc;
191         unsigned int i;
192         struct xhci_hub *rhub;
193
194         rhub = &xhci->usb2_rhub;
195         ports = rhub->num_ports;
196         xhci_common_hub_descriptor(xhci, desc, ports);
197         desc->bDescriptorType = USB_DT_HUB;
198         temp = 1 + (ports / 8);
199         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
200
201         /* The Device Removable bits are reported on a byte granularity.
202          * If the port doesn't exist within that byte, the bit is set to 0.
203          */
204         memset(port_removable, 0, sizeof(port_removable));
205         for (i = 0; i < ports; i++) {
206                 portsc = readl(rhub->ports[i]->addr);
207                 /* If a device is removable, PORTSC reports a 0, same as in the
208                  * hub descriptor DeviceRemovable bits.
209                  */
210                 if (portsc & PORT_DEV_REMOVE)
211                         /* This math is hairy because bit 0 of DeviceRemovable
212                          * is reserved, and bit 1 is for port 1, etc.
213                          */
214                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
215         }
216
217         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
218          * ports on it.  The USB 2.0 specification says that there are two
219          * variable length fields at the end of the hub descriptor:
220          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
221          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
222          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
223          * 0xFF, so we initialize the both arrays (DeviceRemovable and
224          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
225          * set of ports that actually exist.
226          */
227         memset(desc->u.hs.DeviceRemovable, 0xff,
228                         sizeof(desc->u.hs.DeviceRemovable));
229         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
230                         sizeof(desc->u.hs.PortPwrCtrlMask));
231
232         for (i = 0; i < (ports + 1 + 7) / 8; i++)
233                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
234                                 sizeof(__u8));
235 }
236
237 /* Fill in the USB 3.0 roothub descriptor */
238 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
239                 struct usb_hub_descriptor *desc)
240 {
241         int ports;
242         u16 port_removable;
243         u32 portsc;
244         unsigned int i;
245         struct xhci_hub *rhub;
246
247         rhub = &xhci->usb3_rhub;
248         ports = rhub->num_ports;
249         xhci_common_hub_descriptor(xhci, desc, ports);
250         desc->bDescriptorType = USB_DT_SS_HUB;
251         desc->bDescLength = USB_DT_SS_HUB_SIZE;
252
253         /* header decode latency should be zero for roothubs,
254          * see section 4.23.5.2.
255          */
256         desc->u.ss.bHubHdrDecLat = 0;
257         desc->u.ss.wHubDelay = 0;
258
259         port_removable = 0;
260         /* bit 0 is reserved, bit 1 is for port 1, etc. */
261         for (i = 0; i < ports; i++) {
262                 portsc = readl(rhub->ports[i]->addr);
263                 if (portsc & PORT_DEV_REMOVE)
264                         port_removable |= 1 << (i + 1);
265         }
266
267         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
268 }
269
270 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
271                 struct usb_hub_descriptor *desc)
272 {
273
274         if (hcd->speed >= HCD_USB3)
275                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
276         else
277                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
278
279 }
280
281 static unsigned int xhci_port_speed(unsigned int port_status)
282 {
283         if (DEV_LOWSPEED(port_status))
284                 return USB_PORT_STAT_LOW_SPEED;
285         if (DEV_HIGHSPEED(port_status))
286                 return USB_PORT_STAT_HIGH_SPEED;
287         /*
288          * FIXME: Yes, we should check for full speed, but the core uses that as
289          * a default in portspeed() in usb/core/hub.c (which is the only place
290          * USB_PORT_STAT_*_SPEED is used).
291          */
292         return 0;
293 }
294
295 /*
296  * These bits are Read Only (RO) and should be saved and written to the
297  * registers: 0, 3, 10:13, 30
298  * connect status, over-current status, port speed, and device removable.
299  * connect status and port speed are also sticky - meaning they're in
300  * the AUX well and they aren't changed by a hot, warm, or cold reset.
301  */
302 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
303 /*
304  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
305  * bits 5:8, 9, 14:15, 25:27
306  * link state, port power, port indicator state, "wake on" enable state
307  */
308 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
309 /*
310  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
311  * bit 4 (port reset)
312  */
313 #define XHCI_PORT_RW1S  ((1<<4))
314 /*
315  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
316  * bits 1, 17, 18, 19, 20, 21, 22, 23
317  * port enable/disable, and
318  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
319  * over-current, reset, link state, and L1 change
320  */
321 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
322 /*
323  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
324  * latched in
325  */
326 #define XHCI_PORT_RW    ((1<<16))
327 /*
328  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
329  * bits 2, 24, 28:31
330  */
331 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
332
333 /*
334  * Given a port state, this function returns a value that would result in the
335  * port being in the same state, if the value was written to the port status
336  * control register.
337  * Save Read Only (RO) bits and save read/write bits where
338  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
339  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
340  */
341 u32 xhci_port_state_to_neutral(u32 state)
342 {
343         /* Save read-only status and port state */
344         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
345 }
346
347 /*
348  * find slot id based on port number.
349  * @port: The one-based port number from one of the two split roothubs.
350  */
351 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
352                 u16 port)
353 {
354         int slot_id;
355         int i;
356         enum usb_device_speed speed;
357
358         slot_id = 0;
359         for (i = 0; i < MAX_HC_SLOTS; i++) {
360                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
361                         continue;
362                 speed = xhci->devs[i]->udev->speed;
363                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
364                                 && xhci->devs[i]->fake_port == port) {
365                         slot_id = i;
366                         break;
367                 }
368         }
369
370         return slot_id;
371 }
372
373 /*
374  * Stop device
375  * It issues stop endpoint command for EP 0 to 30. And wait the last command
376  * to complete.
377  * suspend will set to 1, if suspend bit need to set in command.
378  */
379 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
380 {
381         struct xhci_virt_device *virt_dev;
382         struct xhci_command *cmd;
383         unsigned long flags;
384         int ret;
385         int i;
386
387         ret = 0;
388         virt_dev = xhci->devs[slot_id];
389         if (!virt_dev)
390                 return -ENODEV;
391
392         trace_xhci_stop_device(virt_dev);
393
394         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
395         if (!cmd)
396                 return -ENOMEM;
397
398         spin_lock_irqsave(&xhci->lock, flags);
399         for (i = LAST_EP_INDEX; i > 0; i--) {
400                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
401                         struct xhci_ep_ctx *ep_ctx;
402                         struct xhci_command *command;
403
404                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
405
406                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
407                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
408                                 continue;
409
410                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
411                         if (!command) {
412                                 spin_unlock_irqrestore(&xhci->lock, flags);
413                                 ret = -ENOMEM;
414                                 goto cmd_cleanup;
415                         }
416
417                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
418                                                        i, suspend);
419                         if (ret) {
420                                 spin_unlock_irqrestore(&xhci->lock, flags);
421                                 xhci_free_command(xhci, command);
422                                 goto cmd_cleanup;
423                         }
424                 }
425         }
426         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
427         if (ret) {
428                 spin_unlock_irqrestore(&xhci->lock, flags);
429                 goto cmd_cleanup;
430         }
431
432         xhci_ring_cmd_db(xhci);
433         spin_unlock_irqrestore(&xhci->lock, flags);
434
435         /* Wait for last stop endpoint command to finish */
436         wait_for_completion(cmd->completion);
437
438         if (cmd->status == COMP_COMMAND_ABORTED ||
439             cmd->status == COMP_COMMAND_RING_STOPPED) {
440                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
441                 ret = -ETIME;
442         }
443
444 cmd_cleanup:
445         xhci_free_command(xhci, cmd);
446         return ret;
447 }
448
449 /*
450  * Ring device, it rings the all doorbells unconditionally.
451  */
452 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
453 {
454         int i, s;
455         struct xhci_virt_ep *ep;
456
457         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
458                 ep = &xhci->devs[slot_id]->eps[i];
459
460                 if (ep->ep_state & EP_HAS_STREAMS) {
461                         for (s = 1; s < ep->stream_info->num_streams; s++)
462                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
463                 } else if (ep->ring && ep->ring->dequeue) {
464                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
465                 }
466         }
467
468         return;
469 }
470
471 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
472                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
473 {
474         /* Don't allow the USB core to disable SuperSpeed ports. */
475         if (hcd->speed >= HCD_USB3) {
476                 xhci_dbg(xhci, "Ignoring request to disable "
477                                 "SuperSpeed port.\n");
478                 return;
479         }
480
481         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
482                 xhci_dbg(xhci,
483                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
484                 return;
485         }
486
487         /* Write 1 to disable the port */
488         writel(port_status | PORT_PE, addr);
489         port_status = readl(addr);
490         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
491                         wIndex, port_status);
492 }
493
494 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
495                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
496 {
497         char *port_change_bit;
498         u32 status;
499
500         switch (wValue) {
501         case USB_PORT_FEAT_C_RESET:
502                 status = PORT_RC;
503                 port_change_bit = "reset";
504                 break;
505         case USB_PORT_FEAT_C_BH_PORT_RESET:
506                 status = PORT_WRC;
507                 port_change_bit = "warm(BH) reset";
508                 break;
509         case USB_PORT_FEAT_C_CONNECTION:
510                 status = PORT_CSC;
511                 port_change_bit = "connect";
512                 break;
513         case USB_PORT_FEAT_C_OVER_CURRENT:
514                 status = PORT_OCC;
515                 port_change_bit = "over-current";
516                 break;
517         case USB_PORT_FEAT_C_ENABLE:
518                 status = PORT_PEC;
519                 port_change_bit = "enable/disable";
520                 break;
521         case USB_PORT_FEAT_C_SUSPEND:
522                 status = PORT_PLC;
523                 port_change_bit = "suspend/resume";
524                 break;
525         case USB_PORT_FEAT_C_PORT_LINK_STATE:
526                 status = PORT_PLC;
527                 port_change_bit = "link state";
528                 break;
529         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
530                 status = PORT_CEC;
531                 port_change_bit = "config error";
532                 break;
533         default:
534                 /* Should never happen */
535                 return;
536         }
537         /* Change bits are all write 1 to clear */
538         writel(port_status | status, addr);
539         port_status = readl(addr);
540         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
541                         port_change_bit, wIndex, port_status);
542 }
543
544 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
545 {
546         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
547
548         if (hcd->speed >= HCD_USB3)
549                 return &xhci->usb3_rhub;
550         return &xhci->usb2_rhub;
551 }
552
553 /*
554  * xhci_set_port_power() must be called with xhci->lock held.
555  * It will release and re-aquire the lock while calling ACPI
556  * method.
557  */
558 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
559                                 u16 index, bool on, unsigned long *flags)
560 {
561         struct xhci_hub *rhub;
562         struct xhci_port *port;
563         u32 temp;
564
565         rhub = xhci_get_rhub(hcd);
566         port = rhub->ports[index];
567         temp = readl(port->addr);
568         temp = xhci_port_state_to_neutral(temp);
569         if (on) {
570                 /* Power on */
571                 writel(temp | PORT_POWER, port->addr);
572                 temp = readl(port->addr);
573                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
574                                                 index, temp);
575         } else {
576                 /* Power off */
577                 writel(temp & ~PORT_POWER, port->addr);
578         }
579
580         spin_unlock_irqrestore(&xhci->lock, *flags);
581         temp = usb_acpi_power_manageable(hcd->self.root_hub,
582                                         index);
583         if (temp)
584                 usb_acpi_set_power_state(hcd->self.root_hub,
585                         index, on);
586         spin_lock_irqsave(&xhci->lock, *flags);
587 }
588
589 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
590         u16 test_mode, u16 wIndex)
591 {
592         u32 temp;
593         struct xhci_port *port;
594
595         /* xhci only supports test mode for usb2 ports */
596         port = xhci->usb2_rhub.ports[wIndex];
597         temp = readl(port->addr + PORTPMSC);
598         temp |= test_mode << PORT_TEST_MODE_SHIFT;
599         writel(temp, port->addr + PORTPMSC);
600         xhci->test_mode = test_mode;
601         if (test_mode == TEST_FORCE_EN)
602                 xhci_start(xhci);
603 }
604
605 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
606                                 u16 test_mode, u16 wIndex, unsigned long *flags)
607 {
608         int i, retval;
609
610         /* Disable all Device Slots */
611         xhci_dbg(xhci, "Disable all slots\n");
612         spin_unlock_irqrestore(&xhci->lock, *flags);
613         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
614                 if (!xhci->devs[i])
615                         continue;
616
617                 retval = xhci_disable_slot(xhci, i);
618                 if (retval)
619                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
620                                  i, retval);
621         }
622         spin_lock_irqsave(&xhci->lock, *flags);
623         /* Put all ports to the Disable state by clear PP */
624         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
625         /* Power off USB3 ports*/
626         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
627                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
628         /* Power off USB2 ports*/
629         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
630                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
631         /* Stop the controller */
632         xhci_dbg(xhci, "Stop controller\n");
633         retval = xhci_halt(xhci);
634         if (retval)
635                 return retval;
636         /* Disable runtime PM for test mode */
637         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
638         /* Set PORTPMSC.PTC field to enter selected test mode */
639         /* Port is selected by wIndex. port_id = wIndex + 1 */
640         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
641                                         test_mode, wIndex + 1);
642         xhci_port_set_test_mode(xhci, test_mode, wIndex);
643         return retval;
644 }
645
646 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
647 {
648         int retval;
649
650         if (!xhci->test_mode) {
651                 xhci_err(xhci, "Not in test mode, do nothing.\n");
652                 return 0;
653         }
654         if (xhci->test_mode == TEST_FORCE_EN &&
655                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
656                 retval = xhci_halt(xhci);
657                 if (retval)
658                         return retval;
659         }
660         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
661         xhci->test_mode = 0;
662         return xhci_reset(xhci);
663 }
664
665 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
666                          u32 link_state)
667 {
668         u32 temp;
669
670         temp = readl(port->addr);
671         temp = xhci_port_state_to_neutral(temp);
672         temp &= ~PORT_PLS_MASK;
673         temp |= PORT_LINK_STROBE | link_state;
674         writel(temp, port->addr);
675 }
676
677 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
678                                       struct xhci_port *port, u16 wake_mask)
679 {
680         u32 temp;
681
682         temp = readl(port->addr);
683         temp = xhci_port_state_to_neutral(temp);
684
685         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
686                 temp |= PORT_WKCONN_E;
687         else
688                 temp &= ~PORT_WKCONN_E;
689
690         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
691                 temp |= PORT_WKDISC_E;
692         else
693                 temp &= ~PORT_WKDISC_E;
694
695         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
696                 temp |= PORT_WKOC_E;
697         else
698                 temp &= ~PORT_WKOC_E;
699
700         writel(temp, port->addr);
701 }
702
703 /* Test and clear port RWC bit */
704 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
705                              u32 port_bit)
706 {
707         u32 temp;
708
709         temp = readl(port->addr);
710         if (temp & port_bit) {
711                 temp = xhci_port_state_to_neutral(temp);
712                 temp |= port_bit;
713                 writel(temp, port->addr);
714         }
715 }
716
717 /* Updates Link Status for super Speed port */
718 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
719                 u32 *status, u32 status_reg)
720 {
721         u32 pls = status_reg & PORT_PLS_MASK;
722
723         /* resume state is a xHCI internal state.
724          * Do not report it to usb core, instead, pretend to be U3,
725          * thus usb core knows it's not ready for transfer
726          */
727         if (pls == XDEV_RESUME) {
728                 *status |= USB_SS_PORT_LS_U3;
729                 return;
730         }
731
732         /* When the CAS bit is set then warm reset
733          * should be performed on port
734          */
735         if (status_reg & PORT_CAS) {
736                 /* The CAS bit can be set while the port is
737                  * in any link state.
738                  * Only roothubs have CAS bit, so we
739                  * pretend to be in compliance mode
740                  * unless we're already in compliance
741                  * or the inactive state.
742                  */
743                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
744                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
745                         pls = USB_SS_PORT_LS_COMP_MOD;
746                 }
747                 /* Return also connection bit -
748                  * hub state machine resets port
749                  * when this bit is set.
750                  */
751                 pls |= USB_PORT_STAT_CONNECTION;
752         } else {
753                 /*
754                  * If CAS bit isn't set but the Port is already at
755                  * Compliance Mode, fake a connection so the USB core
756                  * notices the Compliance state and resets the port.
757                  * This resolves an issue generated by the SN65LVPE502CP
758                  * in which sometimes the port enters compliance mode
759                  * caused by a delay on the host-device negotiation.
760                  */
761                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
762                                 (pls == USB_SS_PORT_LS_COMP_MOD))
763                         pls |= USB_PORT_STAT_CONNECTION;
764         }
765
766         /* update status field */
767         *status |= pls;
768 }
769
770 /*
771  * Function for Compliance Mode Quirk.
772  *
773  * This Function verifies if all xhc USB3 ports have entered U0, if so,
774  * the compliance mode timer is deleted. A port won't enter
775  * compliance mode if it has previously entered U0.
776  */
777 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
778                                     u16 wIndex)
779 {
780         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
781         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
782
783         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
784                 return;
785
786         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
787                 xhci->port_status_u0 |= 1 << wIndex;
788                 if (xhci->port_status_u0 == all_ports_seen_u0) {
789                         del_timer_sync(&xhci->comp_mode_recovery_timer);
790                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
791                                 "All USB3 ports have entered U0 already!");
792                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
793                                 "Compliance Mode Recovery Timer Deleted.");
794                 }
795         }
796 }
797
798 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
799                                              u32 *status, u32 portsc,
800                                              unsigned long flags)
801 {
802         struct xhci_bus_state *bus_state;
803         struct xhci_hcd *xhci;
804         struct usb_hcd *hcd;
805         int slot_id;
806         u32 wIndex;
807
808         hcd = port->rhub->hcd;
809         bus_state = &port->rhub->bus_state;
810         xhci = hcd_to_xhci(hcd);
811         wIndex = port->hcd_portnum;
812
813         if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
814                 *status = 0xffffffff;
815                 return -EINVAL;
816         }
817         /* did port event handler already start resume timing? */
818         if (!bus_state->resume_done[wIndex]) {
819                 /* If not, maybe we are in a host initated resume? */
820                 if (test_bit(wIndex, &bus_state->resuming_ports)) {
821                         /* Host initated resume doesn't time the resume
822                          * signalling using resume_done[].
823                          * It manually sets RESUME state, sleeps 20ms
824                          * and sets U0 state. This should probably be
825                          * changed, but not right now.
826                          */
827                 } else {
828                         /* port resume was discovered now and here,
829                          * start resume timing
830                          */
831                         unsigned long timeout = jiffies +
832                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
833
834                         set_bit(wIndex, &bus_state->resuming_ports);
835                         bus_state->resume_done[wIndex] = timeout;
836                         mod_timer(&hcd->rh_timer, timeout);
837                         usb_hcd_start_port_resume(&hcd->self, wIndex);
838                 }
839         /* Has resume been signalled for USB_RESUME_TIME yet? */
840         } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
841                 int time_left;
842
843                 xhci_dbg(xhci, "Resume USB2 port %d\n", wIndex + 1);
844                 bus_state->resume_done[wIndex] = 0;
845                 clear_bit(wIndex, &bus_state->resuming_ports);
846
847                 set_bit(wIndex, &bus_state->rexit_ports);
848
849                 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
850                 xhci_set_link_state(xhci, port, XDEV_U0);
851
852                 spin_unlock_irqrestore(&xhci->lock, flags);
853                 time_left = wait_for_completion_timeout(
854                         &bus_state->rexit_done[wIndex],
855                         msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
856                 spin_lock_irqsave(&xhci->lock, flags);
857
858                 if (time_left) {
859                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
860                                                             wIndex + 1);
861                         if (!slot_id) {
862                                 xhci_dbg(xhci, "slot_id is zero\n");
863                                 *status = 0xffffffff;
864                                 return -ENODEV;
865                         }
866                         xhci_ring_device(xhci, slot_id);
867                 } else {
868                         int port_status = readl(port->addr);
869
870                         xhci_warn(xhci, "Port resume %i msec timed out, portsc = 0x%x\n",
871                                   XHCI_MAX_REXIT_TIMEOUT_MS,
872                                   port_status);
873                         *status |= USB_PORT_STAT_SUSPEND;
874                         clear_bit(wIndex, &bus_state->rexit_ports);
875                 }
876
877                 usb_hcd_end_port_resume(&hcd->self, wIndex);
878                 bus_state->port_c_suspend |= 1 << wIndex;
879                 bus_state->suspended_ports &= ~(1 << wIndex);
880         } else {
881                 /*
882                  * The resume has been signaling for less than
883                  * USB_RESUME_TIME. Report the port status as SUSPEND,
884                  * let the usbcore check port status again and clear
885                  * resume signaling later.
886                  */
887                 *status |= USB_PORT_STAT_SUSPEND;
888         }
889         return 0;
890 }
891
892 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
893 {
894         u32 ext_stat = 0;
895         int speed_id;
896
897         /* only support rx and tx lane counts of 1 in usb3.1 spec */
898         speed_id = DEV_PORT_SPEED(raw_port_status);
899         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
900         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
901
902         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
903         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
904
905         return ext_stat;
906 }
907
908 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
909                                       u32 portsc)
910 {
911         struct xhci_bus_state *bus_state;
912         struct xhci_hcd *xhci;
913         u32 link_state;
914         u32 portnum;
915
916         bus_state = &port->rhub->bus_state;
917         xhci = hcd_to_xhci(port->rhub->hcd);
918         link_state = portsc & PORT_PLS_MASK;
919         portnum = port->hcd_portnum;
920
921         /* USB3 specific wPortChange bits
922          *
923          * Port link change with port in resume state should not be
924          * reported to usbcore, as this is an internal state to be
925          * handled by xhci driver. Reporting PLC to usbcore may
926          * cause usbcore clearing PLC first and port change event
927          * irq won't be generated.
928          */
929
930         if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
931                 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
932         if (portsc & PORT_WRC)
933                 *status |= USB_PORT_STAT_C_BH_RESET << 16;
934         if (portsc & PORT_CEC)
935                 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
936
937         /* USB3 specific wPortStatus bits */
938         if (portsc & PORT_POWER) {
939                 *status |= USB_SS_PORT_STAT_POWER;
940                 /* link state handling */
941                 if (link_state == XDEV_U0)
942                         bus_state->suspended_ports &= ~(1 << portnum);
943         }
944
945         xhci_hub_report_usb3_link_state(xhci, status, portsc);
946         xhci_del_comp_mod_timer(xhci, portsc, portnum);
947 }
948
949 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
950                                       u32 portsc, unsigned long flags)
951 {
952         struct xhci_bus_state *bus_state;
953         u32 link_state;
954         u32 portnum;
955         int ret;
956
957         bus_state = &port->rhub->bus_state;
958         link_state = portsc & PORT_PLS_MASK;
959         portnum = port->hcd_portnum;
960
961         /* USB2 wPortStatus bits */
962         if (portsc & PORT_POWER) {
963                 *status |= USB_PORT_STAT_POWER;
964
965                 /* link state is only valid if port is powered */
966                 if (link_state == XDEV_U3)
967                         *status |= USB_PORT_STAT_SUSPEND;
968                 if (link_state == XDEV_U2)
969                         *status |= USB_PORT_STAT_L1;
970                 if (link_state == XDEV_U0) {
971                         bus_state->resume_done[portnum] = 0;
972                         clear_bit(portnum, &bus_state->resuming_ports);
973                         if (bus_state->suspended_ports & (1 << portnum)) {
974                                 bus_state->suspended_ports &= ~(1 << portnum);
975                                 bus_state->port_c_suspend |= 1 << portnum;
976                         }
977                 }
978                 if (link_state == XDEV_RESUME) {
979                         ret = xhci_handle_usb2_port_link_resume(port, status,
980                                                                 portsc, flags);
981                         if (ret)
982                                 return;
983                 }
984         }
985 }
986
987 /*
988  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
989  * 3.0 hubs use.
990  *
991  * Possible side effects:
992  *  - Mark a port as being done with device resume,
993  *    and ring the endpoint doorbells.
994  *  - Stop the Synopsys redriver Compliance Mode polling.
995  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
996  */
997 static u32 xhci_get_port_status(struct usb_hcd *hcd,
998                 struct xhci_bus_state *bus_state,
999         u16 wIndex, u32 raw_port_status,
1000                 unsigned long flags)
1001         __releases(&xhci->lock)
1002         __acquires(&xhci->lock)
1003 {
1004         u32 status = 0;
1005         struct xhci_hub *rhub;
1006         struct xhci_port *port;
1007
1008         rhub = xhci_get_rhub(hcd);
1009         port = rhub->ports[wIndex];
1010
1011         /* common wPortChange bits */
1012         if (raw_port_status & PORT_CSC)
1013                 status |= USB_PORT_STAT_C_CONNECTION << 16;
1014         if (raw_port_status & PORT_PEC)
1015                 status |= USB_PORT_STAT_C_ENABLE << 16;
1016         if ((raw_port_status & PORT_OCC))
1017                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1018         if ((raw_port_status & PORT_RC))
1019                 status |= USB_PORT_STAT_C_RESET << 16;
1020
1021         /* common wPortStatus bits */
1022         if (raw_port_status & PORT_CONNECT) {
1023                 status |= USB_PORT_STAT_CONNECTION;
1024                 status |= xhci_port_speed(raw_port_status);
1025         }
1026         if (raw_port_status & PORT_PE)
1027                 status |= USB_PORT_STAT_ENABLE;
1028         if (raw_port_status & PORT_OC)
1029                 status |= USB_PORT_STAT_OVERCURRENT;
1030         if (raw_port_status & PORT_RESET)
1031                 status |= USB_PORT_STAT_RESET;
1032
1033         /* USB2 and USB3 specific bits, including Port Link State */
1034         if (hcd->speed >= HCD_USB3)
1035                 xhci_get_usb3_port_status(port, &status, raw_port_status);
1036         else
1037                 xhci_get_usb2_port_status(port, &status, raw_port_status,
1038                                           flags);
1039         /*
1040          * Clear stale usb2 resume signalling variables in case port changed
1041          * state during resume signalling. For example on error
1042          */
1043         if ((bus_state->resume_done[wIndex] ||
1044              test_bit(wIndex, &bus_state->resuming_ports)) &&
1045             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1046             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1047                 bus_state->resume_done[wIndex] = 0;
1048                 clear_bit(wIndex, &bus_state->resuming_ports);
1049                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1050         }
1051
1052         if (bus_state->port_c_suspend & (1 << wIndex))
1053                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1054
1055         return status;
1056 }
1057
1058 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1059                 u16 wIndex, char *buf, u16 wLength)
1060 {
1061         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1062         int max_ports;
1063         unsigned long flags;
1064         u32 temp, status;
1065         int retval = 0;
1066         int slot_id;
1067         struct xhci_bus_state *bus_state;
1068         u16 link_state = 0;
1069         u16 wake_mask = 0;
1070         u16 timeout = 0;
1071         u16 test_mode = 0;
1072         struct xhci_hub *rhub;
1073         struct xhci_port **ports;
1074
1075         rhub = xhci_get_rhub(hcd);
1076         ports = rhub->ports;
1077         max_ports = rhub->num_ports;
1078         bus_state = &rhub->bus_state;
1079
1080         spin_lock_irqsave(&xhci->lock, flags);
1081         switch (typeReq) {
1082         case GetHubStatus:
1083                 /* No power source, over-current reported per port */
1084                 memset(buf, 0, 4);
1085                 break;
1086         case GetHubDescriptor:
1087                 /* Check to make sure userspace is asking for the USB 3.0 hub
1088                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1089                  * endpoint, like external hubs do.
1090                  */
1091                 if (hcd->speed >= HCD_USB3 &&
1092                                 (wLength < USB_DT_SS_HUB_SIZE ||
1093                                  wValue != (USB_DT_SS_HUB << 8))) {
1094                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1095                                         "USB 3.0 roothub.\n");
1096                         goto error;
1097                 }
1098                 xhci_hub_descriptor(hcd, xhci,
1099                                 (struct usb_hub_descriptor *) buf);
1100                 break;
1101         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1102                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1103                         goto error;
1104
1105                 if (hcd->speed < HCD_USB3)
1106                         goto error;
1107
1108                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1109                 spin_unlock_irqrestore(&xhci->lock, flags);
1110                 return retval;
1111         case GetPortStatus:
1112                 if (!wIndex || wIndex > max_ports)
1113                         goto error;
1114                 wIndex--;
1115                 temp = readl(ports[wIndex]->addr);
1116                 if (temp == ~(u32)0) {
1117                         xhci_hc_died(xhci);
1118                         retval = -ENODEV;
1119                         break;
1120                 }
1121                 trace_xhci_get_port_status(wIndex, temp);
1122                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1123                                               flags);
1124                 if (status == 0xffffffff)
1125                         goto error;
1126
1127                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1128                                 wIndex, temp);
1129                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1130
1131                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1132                 /* if USB 3.1 extended port status return additional 4 bytes */
1133                 if (wValue == 0x02) {
1134                         u32 port_li;
1135
1136                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1137                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1138                                 retval = -EINVAL;
1139                                 break;
1140                         }
1141                         port_li = readl(ports[wIndex]->addr + PORTLI);
1142                         status = xhci_get_ext_port_status(temp, port_li);
1143                         put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1144                 }
1145                 break;
1146         case SetPortFeature:
1147                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1148                         link_state = (wIndex & 0xff00) >> 3;
1149                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1150                         wake_mask = wIndex & 0xff00;
1151                 if (wValue == USB_PORT_FEAT_TEST)
1152                         test_mode = (wIndex & 0xff00) >> 8;
1153                 /* The MSB of wIndex is the U1/U2 timeout */
1154                 timeout = (wIndex & 0xff00) >> 8;
1155                 wIndex &= 0xff;
1156                 if (!wIndex || wIndex > max_ports)
1157                         goto error;
1158                 wIndex--;
1159                 temp = readl(ports[wIndex]->addr);
1160                 if (temp == ~(u32)0) {
1161                         xhci_hc_died(xhci);
1162                         retval = -ENODEV;
1163                         break;
1164                 }
1165                 temp = xhci_port_state_to_neutral(temp);
1166                 /* FIXME: What new port features do we need to support? */
1167                 switch (wValue) {
1168                 case USB_PORT_FEAT_SUSPEND:
1169                         temp = readl(ports[wIndex]->addr);
1170                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1171                                 /* Resume the port to U0 first */
1172                                 xhci_set_link_state(xhci, ports[wIndex],
1173                                                         XDEV_U0);
1174                                 spin_unlock_irqrestore(&xhci->lock, flags);
1175                                 msleep(10);
1176                                 spin_lock_irqsave(&xhci->lock, flags);
1177                         }
1178                         /* In spec software should not attempt to suspend
1179                          * a port unless the port reports that it is in the
1180                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1181                          */
1182                         temp = readl(ports[wIndex]->addr);
1183                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1184                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1185                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1186                                 goto error;
1187                         }
1188
1189                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1190                                         wIndex + 1);
1191                         if (!slot_id) {
1192                                 xhci_warn(xhci, "slot_id is zero\n");
1193                                 goto error;
1194                         }
1195                         /* unlock to execute stop endpoint commands */
1196                         spin_unlock_irqrestore(&xhci->lock, flags);
1197                         xhci_stop_device(xhci, slot_id, 1);
1198                         spin_lock_irqsave(&xhci->lock, flags);
1199
1200                         xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1201
1202                         spin_unlock_irqrestore(&xhci->lock, flags);
1203                         msleep(10); /* wait device to enter */
1204                         spin_lock_irqsave(&xhci->lock, flags);
1205
1206                         temp = readl(ports[wIndex]->addr);
1207                         bus_state->suspended_ports |= 1 << wIndex;
1208                         break;
1209                 case USB_PORT_FEAT_LINK_STATE:
1210                         temp = readl(ports[wIndex]->addr);
1211                         /* Disable port */
1212                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1213                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1214                                 temp = xhci_port_state_to_neutral(temp);
1215                                 /*
1216                                  * Clear all change bits, so that we get a new
1217                                  * connection event.
1218                                  */
1219                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1220                                         PORT_OCC | PORT_RC | PORT_PLC |
1221                                         PORT_CEC;
1222                                 writel(temp | PORT_PE, ports[wIndex]->addr);
1223                                 temp = readl(ports[wIndex]->addr);
1224                                 break;
1225                         }
1226
1227                         /* Put link in RxDetect (enable port) */
1228                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1229                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1230                                 xhci_set_link_state(xhci, ports[wIndex],
1231                                                         link_state);
1232                                 temp = readl(ports[wIndex]->addr);
1233                                 break;
1234                         }
1235
1236                         /*
1237                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1238                          * root hub port's transition to compliance mode upon
1239                          * detecting LFPS timeout may be controlled by an
1240                          * Compliance Transition Enabled (CTE) flag (not
1241                          * software visible). This flag is set by writing 0xA
1242                          * to PORTSC PLS field which will allow transition to
1243                          * compliance mode the next time LFPS timeout is
1244                          * encountered. A warm reset will clear it.
1245                          *
1246                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1247                          * flag is set, otherwise, the compliance substate is
1248                          * automatically entered as on 1.0 and prior.
1249                          */
1250                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1251                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1252                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1253                                         break;
1254                                 }
1255
1256                                 if ((temp & PORT_CONNECT)) {
1257                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1258                                         goto error;
1259                                 }
1260
1261                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1262                                                 wIndex);
1263                                 xhci_set_link_state(xhci, ports[wIndex],
1264                                                 link_state);
1265
1266                                 temp = readl(ports[wIndex]->addr);
1267                                 break;
1268                         }
1269                         /* Port must be enabled */
1270                         if (!(temp & PORT_PE)) {
1271                                 retval = -ENODEV;
1272                                 break;
1273                         }
1274                         /* Can't set port link state above '3' (U3) */
1275                         if (link_state > USB_SS_PORT_LS_U3) {
1276                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1277                                          wIndex, link_state);
1278                                 goto error;
1279                         }
1280                         if (link_state == USB_SS_PORT_LS_U3) {
1281                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1282                                                 wIndex + 1);
1283                                 if (slot_id) {
1284                                         /* unlock to execute stop endpoint
1285                                          * commands */
1286                                         spin_unlock_irqrestore(&xhci->lock,
1287                                                                 flags);
1288                                         xhci_stop_device(xhci, slot_id, 1);
1289                                         spin_lock_irqsave(&xhci->lock, flags);
1290                                 }
1291                         }
1292
1293                         xhci_set_link_state(xhci, ports[wIndex], link_state);
1294
1295                         spin_unlock_irqrestore(&xhci->lock, flags);
1296                         msleep(20); /* wait device to enter */
1297                         spin_lock_irqsave(&xhci->lock, flags);
1298
1299                         temp = readl(ports[wIndex]->addr);
1300                         if (link_state == USB_SS_PORT_LS_U3)
1301                                 bus_state->suspended_ports |= 1 << wIndex;
1302                         break;
1303                 case USB_PORT_FEAT_POWER:
1304                         /*
1305                          * Turn on ports, even if there isn't per-port switching.
1306                          * HC will report connect events even before this is set.
1307                          * However, hub_wq will ignore the roothub events until
1308                          * the roothub is registered.
1309                          */
1310                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1311                         break;
1312                 case USB_PORT_FEAT_RESET:
1313                         temp = (temp | PORT_RESET);
1314                         writel(temp, ports[wIndex]->addr);
1315
1316                         temp = readl(ports[wIndex]->addr);
1317                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1318                         break;
1319                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1320                         xhci_set_remote_wake_mask(xhci, ports[wIndex],
1321                                                   wake_mask);
1322                         temp = readl(ports[wIndex]->addr);
1323                         xhci_dbg(xhci, "set port remote wake mask, "
1324                                         "actual port %d status  = 0x%x\n",
1325                                         wIndex, temp);
1326                         break;
1327                 case USB_PORT_FEAT_BH_PORT_RESET:
1328                         temp |= PORT_WR;
1329                         writel(temp, ports[wIndex]->addr);
1330                         temp = readl(ports[wIndex]->addr);
1331                         break;
1332                 case USB_PORT_FEAT_U1_TIMEOUT:
1333                         if (hcd->speed < HCD_USB3)
1334                                 goto error;
1335                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1336                         temp &= ~PORT_U1_TIMEOUT_MASK;
1337                         temp |= PORT_U1_TIMEOUT(timeout);
1338                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1339                         break;
1340                 case USB_PORT_FEAT_U2_TIMEOUT:
1341                         if (hcd->speed < HCD_USB3)
1342                                 goto error;
1343                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1344                         temp &= ~PORT_U2_TIMEOUT_MASK;
1345                         temp |= PORT_U2_TIMEOUT(timeout);
1346                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1347                         break;
1348                 case USB_PORT_FEAT_TEST:
1349                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1350                         if (hcd->speed != HCD_USB2)
1351                                 goto error;
1352                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1353                                 goto error;
1354                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1355                                                       &flags);
1356                         break;
1357                 default:
1358                         goto error;
1359                 }
1360                 /* unblock any posted writes */
1361                 temp = readl(ports[wIndex]->addr);
1362                 break;
1363         case ClearPortFeature:
1364                 if (!wIndex || wIndex > max_ports)
1365                         goto error;
1366                 wIndex--;
1367                 temp = readl(ports[wIndex]->addr);
1368                 if (temp == ~(u32)0) {
1369                         xhci_hc_died(xhci);
1370                         retval = -ENODEV;
1371                         break;
1372                 }
1373                 /* FIXME: What new port features do we need to support? */
1374                 temp = xhci_port_state_to_neutral(temp);
1375                 switch (wValue) {
1376                 case USB_PORT_FEAT_SUSPEND:
1377                         temp = readl(ports[wIndex]->addr);
1378                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1379                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1380                         if (temp & PORT_RESET)
1381                                 goto error;
1382                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1383                                 if ((temp & PORT_PE) == 0)
1384                                         goto error;
1385
1386                                 set_bit(wIndex, &bus_state->resuming_ports);
1387                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1388                                 xhci_set_link_state(xhci, ports[wIndex],
1389                                                     XDEV_RESUME);
1390                                 spin_unlock_irqrestore(&xhci->lock, flags);
1391                                 msleep(USB_RESUME_TIMEOUT);
1392                                 spin_lock_irqsave(&xhci->lock, flags);
1393                                 xhci_set_link_state(xhci, ports[wIndex],
1394                                                         XDEV_U0);
1395                                 clear_bit(wIndex, &bus_state->resuming_ports);
1396                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1397                         }
1398                         bus_state->port_c_suspend |= 1 << wIndex;
1399
1400                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1401                                         wIndex + 1);
1402                         if (!slot_id) {
1403                                 xhci_dbg(xhci, "slot_id is zero\n");
1404                                 goto error;
1405                         }
1406                         xhci_ring_device(xhci, slot_id);
1407                         break;
1408                 case USB_PORT_FEAT_C_SUSPEND:
1409                         bus_state->port_c_suspend &= ~(1 << wIndex);
1410                         /* fall through */
1411                 case USB_PORT_FEAT_C_RESET:
1412                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1413                 case USB_PORT_FEAT_C_CONNECTION:
1414                 case USB_PORT_FEAT_C_OVER_CURRENT:
1415                 case USB_PORT_FEAT_C_ENABLE:
1416                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1417                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1418                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1419                                         ports[wIndex]->addr, temp);
1420                         break;
1421                 case USB_PORT_FEAT_ENABLE:
1422                         xhci_disable_port(hcd, xhci, wIndex,
1423                                         ports[wIndex]->addr, temp);
1424                         break;
1425                 case USB_PORT_FEAT_POWER:
1426                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1427                         break;
1428                 case USB_PORT_FEAT_TEST:
1429                         retval = xhci_exit_test_mode(xhci);
1430                         break;
1431                 default:
1432                         goto error;
1433                 }
1434                 break;
1435         default:
1436 error:
1437                 /* "stall" on error */
1438                 retval = -EPIPE;
1439         }
1440         spin_unlock_irqrestore(&xhci->lock, flags);
1441         return retval;
1442 }
1443
1444 /*
1445  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1446  * Ports are 0-indexed from the HCD point of view,
1447  * and 1-indexed from the USB core pointer of view.
1448  *
1449  * Note that the status change bits will be cleared as soon as a port status
1450  * change event is generated, so we use the saved status from that event.
1451  */
1452 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1453 {
1454         unsigned long flags;
1455         u32 temp, status;
1456         u32 mask;
1457         int i, retval;
1458         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1459         int max_ports;
1460         struct xhci_bus_state *bus_state;
1461         bool reset_change = false;
1462         struct xhci_hub *rhub;
1463         struct xhci_port **ports;
1464
1465         rhub = xhci_get_rhub(hcd);
1466         ports = rhub->ports;
1467         max_ports = rhub->num_ports;
1468         bus_state = &rhub->bus_state;
1469
1470         /* Initial status is no changes */
1471         retval = (max_ports + 8) / 8;
1472         memset(buf, 0, retval);
1473
1474         /*
1475          * Inform the usbcore about resume-in-progress by returning
1476          * a non-zero value even if there are no status changes.
1477          */
1478         status = bus_state->resuming_ports;
1479
1480         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1481
1482         spin_lock_irqsave(&xhci->lock, flags);
1483         /* For each port, did anything change?  If so, set that bit in buf. */
1484         for (i = 0; i < max_ports; i++) {
1485                 temp = readl(ports[i]->addr);
1486                 if (temp == ~(u32)0) {
1487                         xhci_hc_died(xhci);
1488                         retval = -ENODEV;
1489                         break;
1490                 }
1491                 trace_xhci_hub_status_data(i, temp);
1492
1493                 if ((temp & mask) != 0 ||
1494                         (bus_state->port_c_suspend & 1 << i) ||
1495                         (bus_state->resume_done[i] && time_after_eq(
1496                             jiffies, bus_state->resume_done[i]))) {
1497                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1498                         status = 1;
1499                 }
1500                 if ((temp & PORT_RC))
1501                         reset_change = true;
1502         }
1503         if (!status && !reset_change) {
1504                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1505                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1506         }
1507         spin_unlock_irqrestore(&xhci->lock, flags);
1508         return status ? retval : 0;
1509 }
1510
1511 #ifdef CONFIG_PM
1512
1513 int xhci_bus_suspend(struct usb_hcd *hcd)
1514 {
1515         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1516         int max_ports, port_index;
1517         struct xhci_bus_state *bus_state;
1518         unsigned long flags;
1519         struct xhci_hub *rhub;
1520         struct xhci_port **ports;
1521         u32 portsc_buf[USB_MAXCHILDREN];
1522         bool wake_enabled;
1523
1524         rhub = xhci_get_rhub(hcd);
1525         ports = rhub->ports;
1526         max_ports = rhub->num_ports;
1527         bus_state = &rhub->bus_state;
1528         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1529
1530         spin_lock_irqsave(&xhci->lock, flags);
1531
1532         if (wake_enabled) {
1533                 if (bus_state->resuming_ports ||        /* USB2 */
1534                     bus_state->port_remote_wakeup) {    /* USB3 */
1535                         spin_unlock_irqrestore(&xhci->lock, flags);
1536                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1537                         return -EBUSY;
1538                 }
1539         }
1540         /*
1541          * Prepare ports for suspend, but don't write anything before all ports
1542          * are checked and we know bus suspend can proceed
1543          */
1544         bus_state->bus_suspended = 0;
1545         port_index = max_ports;
1546         while (port_index--) {
1547                 u32 t1, t2;
1548
1549                 t1 = readl(ports[port_index]->addr);
1550                 t2 = xhci_port_state_to_neutral(t1);
1551                 portsc_buf[port_index] = 0;
1552
1553                 /* Bail out if a USB3 port has a new device in link training */
1554                 if ((hcd->speed >= HCD_USB3) &&
1555                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1556                         bus_state->bus_suspended = 0;
1557                         spin_unlock_irqrestore(&xhci->lock, flags);
1558                         xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1559                         return -EBUSY;
1560                 }
1561
1562                 /* suspend ports in U0, or bail out for new connect changes */
1563                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1564                         if ((t1 & PORT_CSC) && wake_enabled) {
1565                                 bus_state->bus_suspended = 0;
1566                                 spin_unlock_irqrestore(&xhci->lock, flags);
1567                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1568                                 return -EBUSY;
1569                         }
1570                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1571                         t2 &= ~PORT_PLS_MASK;
1572                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1573                         set_bit(port_index, &bus_state->bus_suspended);
1574                 }
1575                 /* USB core sets remote wake mask for USB 3.0 hubs,
1576                  * including the USB 3.0 roothub, but only if CONFIG_PM
1577                  * is enabled, so also enable remote wake here.
1578                  */
1579                 if (wake_enabled) {
1580                         if (t1 & PORT_CONNECT) {
1581                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1582                                 t2 &= ~PORT_WKCONN_E;
1583                         } else {
1584                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1585                                 t2 &= ~PORT_WKDISC_E;
1586                         }
1587
1588                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1589                             (hcd->speed < HCD_USB3)) {
1590                                 if (usb_amd_pt_check_port(hcd->self.controller,
1591                                                           port_index))
1592                                         t2 &= ~PORT_WAKE_BITS;
1593                         }
1594                 } else
1595                         t2 &= ~PORT_WAKE_BITS;
1596
1597                 t1 = xhci_port_state_to_neutral(t1);
1598                 if (t1 != t2)
1599                         portsc_buf[port_index] = t2;
1600         }
1601
1602         /* write port settings, stopping and suspending ports if needed */
1603         port_index = max_ports;
1604         while (port_index--) {
1605                 if (!portsc_buf[port_index])
1606                         continue;
1607                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1608                         int slot_id;
1609
1610                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1611                                                             port_index + 1);
1612                         if (slot_id) {
1613                                 spin_unlock_irqrestore(&xhci->lock, flags);
1614                                 xhci_stop_device(xhci, slot_id, 1);
1615                                 spin_lock_irqsave(&xhci->lock, flags);
1616                         }
1617                 }
1618                 writel(portsc_buf[port_index], ports[port_index]->addr);
1619         }
1620         hcd->state = HC_STATE_SUSPENDED;
1621         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1622         spin_unlock_irqrestore(&xhci->lock, flags);
1623         return 0;
1624 }
1625
1626 /*
1627  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1628  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1629  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1630  */
1631 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1632 {
1633         u32 portsc;
1634
1635         portsc = readl(port->addr);
1636
1637         /* if any of these are set we are not stuck */
1638         if (portsc & (PORT_CONNECT | PORT_CAS))
1639                 return false;
1640
1641         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1642             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1643                 return false;
1644
1645         /* clear wakeup/change bits, and do a warm port reset */
1646         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1647         portsc |= PORT_WR;
1648         writel(portsc, port->addr);
1649         /* flush write */
1650         readl(port->addr);
1651         return true;
1652 }
1653
1654 int xhci_bus_resume(struct usb_hcd *hcd)
1655 {
1656         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1657         struct xhci_bus_state *bus_state;
1658         unsigned long flags;
1659         int max_ports, port_index;
1660         int slot_id;
1661         int sret;
1662         u32 next_state;
1663         u32 temp, portsc;
1664         struct xhci_hub *rhub;
1665         struct xhci_port **ports;
1666
1667         rhub = xhci_get_rhub(hcd);
1668         ports = rhub->ports;
1669         max_ports = rhub->num_ports;
1670         bus_state = &rhub->bus_state;
1671
1672         if (time_before(jiffies, bus_state->next_statechange))
1673                 msleep(5);
1674
1675         spin_lock_irqsave(&xhci->lock, flags);
1676         if (!HCD_HW_ACCESSIBLE(hcd)) {
1677                 spin_unlock_irqrestore(&xhci->lock, flags);
1678                 return -ESHUTDOWN;
1679         }
1680
1681         /* delay the irqs */
1682         temp = readl(&xhci->op_regs->command);
1683         temp &= ~CMD_EIE;
1684         writel(temp, &xhci->op_regs->command);
1685
1686         /* bus specific resume for ports we suspended at bus_suspend */
1687         if (hcd->speed >= HCD_USB3)
1688                 next_state = XDEV_U0;
1689         else
1690                 next_state = XDEV_RESUME;
1691
1692         port_index = max_ports;
1693         while (port_index--) {
1694                 portsc = readl(ports[port_index]->addr);
1695
1696                 /* warm reset CAS limited ports stuck in polling/compliance */
1697                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1698                     (hcd->speed >= HCD_USB3) &&
1699                     xhci_port_missing_cas_quirk(ports[port_index])) {
1700                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1701                         clear_bit(port_index, &bus_state->bus_suspended);
1702                         continue;
1703                 }
1704                 /* resume if we suspended the link, and it is still suspended */
1705                 if (test_bit(port_index, &bus_state->bus_suspended))
1706                         switch (portsc & PORT_PLS_MASK) {
1707                         case XDEV_U3:
1708                                 portsc = xhci_port_state_to_neutral(portsc);
1709                                 portsc &= ~PORT_PLS_MASK;
1710                                 portsc |= PORT_LINK_STROBE | next_state;
1711                                 break;
1712                         case XDEV_RESUME:
1713                                 /* resume already initiated */
1714                                 break;
1715                         default:
1716                                 /* not in a resumeable state, ignore it */
1717                                 clear_bit(port_index,
1718                                           &bus_state->bus_suspended);
1719                                 break;
1720                         }
1721                 /* disable wake for all ports, write new link state if needed */
1722                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1723                 writel(portsc, ports[port_index]->addr);
1724         }
1725
1726         /* USB2 specific resume signaling delay and U0 link state transition */
1727         if (hcd->speed < HCD_USB3) {
1728                 if (bus_state->bus_suspended) {
1729                         spin_unlock_irqrestore(&xhci->lock, flags);
1730                         msleep(USB_RESUME_TIMEOUT);
1731                         spin_lock_irqsave(&xhci->lock, flags);
1732                 }
1733                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1734                                  BITS_PER_LONG) {
1735                         /* Clear PLC to poll it later for U0 transition */
1736                         xhci_test_and_clear_bit(xhci, ports[port_index],
1737                                                 PORT_PLC);
1738                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1739                 }
1740         }
1741
1742         /* poll for U0 link state complete, both USB2 and USB3 */
1743         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1744                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1745                                       PORT_PLC, 10 * 1000);
1746                 if (sret) {
1747                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1748                                   port_index);
1749                         continue;
1750                 }
1751                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1752                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1753                 if (slot_id)
1754                         xhci_ring_device(xhci, slot_id);
1755         }
1756         (void) readl(&xhci->op_regs->command);
1757
1758         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1759         /* re-enable irqs */
1760         temp = readl(&xhci->op_regs->command);
1761         temp |= CMD_EIE;
1762         writel(temp, &xhci->op_regs->command);
1763         temp = readl(&xhci->op_regs->command);
1764
1765         spin_unlock_irqrestore(&xhci->lock, flags);
1766         return 0;
1767 }
1768
1769 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1770 {
1771         struct xhci_hub *rhub = xhci_get_rhub(hcd);
1772
1773         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1774         return rhub->bus_state.resuming_ports;  /* USB2 ports only */
1775 }
1776
1777 #endif  /* CONFIG_PM */