dt-bindings: cpu: Fix JSON schema
[muen/linux.git] / include / dt-bindings / reset / amlogic,meson-g12a-reset.h
1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2 /*
3  * Copyright (c) 2019 BayLibre, SAS.
4  * Author: Jerome Brunet <jbrunet@baylibre.com>
5  *
6  */
7
8 #ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
9 #define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
10
11 /*      RESET0                                  */
12 #define RESET_HIU                       0
13 /*                                      1       */
14 #define RESET_DOS                       2
15 /*                                      3-4     */
16 #define RESET_VIU                       5
17 #define RESET_AFIFO                     6
18 #define RESET_VID_PLL_DIV               7
19 /*                                      8-9     */
20 #define RESET_VENC                      10
21 #define RESET_ASSIST                    11
22 #define RESET_PCIE_CTRL_A               12
23 #define RESET_VCBUS                     13
24 #define RESET_PCIE_PHY                  14
25 #define RESET_PCIE_APB                  15
26 #define RESET_GIC                       16
27 #define RESET_CAPB3_DECODE              17
28 /*                                      18      */
29 #define RESET_HDMITX_CAPB3              19
30 #define RESET_DVALIN_CAPB3              20
31 #define RESET_DOS_CAPB3                 21
32 /*                                      22      */
33 #define RESET_CBUS_CAPB3                23
34 #define RESET_AHB_CNTL                  24
35 #define RESET_AHB_DATA                  25
36 #define RESET_VCBUS_CLK81               26
37 /*                                      27-31   */
38 /*      RESET1                                  */
39 /*                                      32      */
40 #define RESET_DEMUX                     33
41 #define RESET_USB                       34
42 #define RESET_DDR                       35
43 /*                                      36      */
44 #define RESET_BT656                     37
45 #define RESET_AHB_SRAM                  38
46 /*                                      39      */
47 #define RESET_PARSER                    40
48 /*                                      41      */
49 #define RESET_ISA                       42
50 #define RESET_ETHERNET                  43
51 #define RESET_SD_EMMC_A                 44
52 #define RESET_SD_EMMC_B                 45
53 #define RESET_SD_EMMC_C                 46
54 /*                                      47-60 */
55 #define RESET_AUDIO_CODEC               61
56 /*                                      62-63   */
57 /*      RESET2                                  */
58 /*                                      64      */
59 #define RESET_AUDIO                     65
60 #define RESET_HDMITX_PHY                66
61 /*                                      67      */
62 #define RESET_MIPI_DSI_HOST             68
63 #define RESET_ALOCKER                   69
64 #define RESET_GE2D                      70
65 #define RESET_PARSER_REG                71
66 #define RESET_PARSER_FETCH              72
67 #define RESET_CTL                       73
68 #define RESET_PARSER_TOP                74
69 /*                                      75-77   */
70 #define RESET_DVALIN                    78
71 #define RESET_HDMITX                    79
72 /*                                      80-95   */
73 /*      RESET3                                  */
74 /*                                      96-95   */
75 #define RESET_DEMUX_TOP                 105
76 #define RESET_DEMUX_DES_PL              106
77 #define RESET_DEMUX_S2P_0               107
78 #define RESET_DEMUX_S2P_1               108
79 #define RESET_DEMUX_0                   109
80 #define RESET_DEMUX_1                   110
81 #define RESET_DEMUX_2                   111
82 /*                                      112-127 */
83 /*      RESET4                                  */
84 /*                                      128-129 */
85 #define RESET_MIPI_DSI_PHY              130
86 /*                                      131-132 */
87 #define RESET_RDMA                      133
88 #define RESET_VENCI                     134
89 #define RESET_VENCP                     135
90 /*                                      136     */
91 #define RESET_VDAC                      137
92 /*                                      138-139 */
93 #define RESET_VDI6                      140
94 #define RESET_VENCL                     141
95 #define RESET_I2C_M1                    142
96 #define RESET_I2C_M2                    143
97 /*                                      144-159 */
98 /*      RESET5                                  */
99 /*                                      160-191 */
100 /*      RESET6                                  */
101 #define RESET_GEN                       192
102 #define RESET_SPICC0                    193
103 #define RESET_SC                        194
104 #define RESET_SANA_3                    195
105 #define RESET_I2C_M0                    196
106 #define RESET_TS_PLL                    197
107 #define RESET_SPICC1                    198
108 #define RESET_STREAM                    199
109 #define RESET_TS_CPU                    200
110 #define RESET_UART0                     201
111 #define RESET_UART1_2                   202
112 #define RESET_ASYNC0                    203
113 #define RESET_ASYNC1                    204
114 #define RESET_SPIFC0                    205
115 #define RESET_I2C_M3                    206
116 /*                                      207-223 */
117 /*      RESET7                                  */
118 #define RESET_USB_DDR_0                 224
119 #define RESET_USB_DDR_1                 225
120 #define RESET_USB_DDR_2                 226
121 #define RESET_USB_DDR_3                 227
122 #define RESET_TS_GPU                    228
123 #define RESET_DEVICE_MMC_ARB            229
124 #define RESET_DVALIN_DMC_PIPL           230
125 #define RESET_VID_LOCK                  231
126 #define RESET_NIC_DMC_PIPL              232
127 #define RESET_DMC_VPU_PIPL              233
128 #define RESET_GE2D_DMC_PIPL             234
129 #define RESET_HCODEC_DMC_PIPL           235
130 #define RESET_WAVE420_DMC_PIPL          236
131 #define RESET_HEVCF_DMC_PIPL            237
132 /*                                      238-255 */
133
134 #endif