Merge tag 'for-linus-unmerged' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma...
[muen/linux.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 };
64
65 enum {
66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
70 };
71
72 enum {
73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
75 };
76
77 enum {
78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
95         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
96         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
97         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
98         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
99         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
100         MLX5_CMD_OP_GEN_EQE                       = 0x304,
101         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
102         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
103         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
104         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
105         MLX5_CMD_OP_CREATE_QP                     = 0x500,
106         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
107         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
108         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
109         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
110         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
111         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
112         MLX5_CMD_OP_2ERR_QP                       = 0x507,
113         MLX5_CMD_OP_2RST_QP                       = 0x50a,
114         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
115         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
116         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
117         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
118         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
119         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
120         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
121         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
122         MLX5_CMD_OP_ARM_RQ                        = 0x703,
123         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
124         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
125         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
126         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
127         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
128         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
129         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
130         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
131         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
132         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
133         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
134         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
135         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
136         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
137         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
138         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
139         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
140         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
141         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
142         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
143         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
144         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
145         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
146         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
147         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
148         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
149         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
150         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
151         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
152         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
153         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
154         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
155         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
156         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
157         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
158         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
159         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
160         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
161         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
162         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
163         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
164         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
165         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
166         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
167         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
168         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
169         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
170         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
171         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
172         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
173         MLX5_CMD_OP_NOP                           = 0x80d,
174         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
175         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
176         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
177         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
178         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
179         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
180         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
181         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
182         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
183         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
184         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
185         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
186         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
187         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
188         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
189         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
190         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
191         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
192         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
193         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
194         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
195         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
196         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
197         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
198         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
199         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
200         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
201         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
202         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
203         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
204         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
205         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
206         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
207         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
208         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
209         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
210         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
211         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
212         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
213         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
214         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
215         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
216         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
217         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
218         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
219         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
220         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
221         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
222         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
223         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
224         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
225         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
226         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
227         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
228         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
229         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
230         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
231         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
232         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
233         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
234         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
235         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
236         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
237         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
238         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
239         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
240         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
241         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
242         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
243         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
244         MLX5_CMD_OP_MAX
245 };
246
247 struct mlx5_ifc_flow_table_fields_supported_bits {
248         u8         outer_dmac[0x1];
249         u8         outer_smac[0x1];
250         u8         outer_ether_type[0x1];
251         u8         outer_ip_version[0x1];
252         u8         outer_first_prio[0x1];
253         u8         outer_first_cfi[0x1];
254         u8         outer_first_vid[0x1];
255         u8         outer_ipv4_ttl[0x1];
256         u8         outer_second_prio[0x1];
257         u8         outer_second_cfi[0x1];
258         u8         outer_second_vid[0x1];
259         u8         reserved_at_b[0x1];
260         u8         outer_sip[0x1];
261         u8         outer_dip[0x1];
262         u8         outer_frag[0x1];
263         u8         outer_ip_protocol[0x1];
264         u8         outer_ip_ecn[0x1];
265         u8         outer_ip_dscp[0x1];
266         u8         outer_udp_sport[0x1];
267         u8         outer_udp_dport[0x1];
268         u8         outer_tcp_sport[0x1];
269         u8         outer_tcp_dport[0x1];
270         u8         outer_tcp_flags[0x1];
271         u8         outer_gre_protocol[0x1];
272         u8         outer_gre_key[0x1];
273         u8         outer_vxlan_vni[0x1];
274         u8         reserved_at_1a[0x5];
275         u8         source_eswitch_port[0x1];
276
277         u8         inner_dmac[0x1];
278         u8         inner_smac[0x1];
279         u8         inner_ether_type[0x1];
280         u8         inner_ip_version[0x1];
281         u8         inner_first_prio[0x1];
282         u8         inner_first_cfi[0x1];
283         u8         inner_first_vid[0x1];
284         u8         reserved_at_27[0x1];
285         u8         inner_second_prio[0x1];
286         u8         inner_second_cfi[0x1];
287         u8         inner_second_vid[0x1];
288         u8         reserved_at_2b[0x1];
289         u8         inner_sip[0x1];
290         u8         inner_dip[0x1];
291         u8         inner_frag[0x1];
292         u8         inner_ip_protocol[0x1];
293         u8         inner_ip_ecn[0x1];
294         u8         inner_ip_dscp[0x1];
295         u8         inner_udp_sport[0x1];
296         u8         inner_udp_dport[0x1];
297         u8         inner_tcp_sport[0x1];
298         u8         inner_tcp_dport[0x1];
299         u8         inner_tcp_flags[0x1];
300         u8         reserved_at_37[0x9];
301         u8         reserved_at_40[0x17];
302         u8         outer_esp_spi[0x1];
303         u8         reserved_at_58[0x2];
304         u8         bth_dst_qp[0x1];
305
306         u8         reserved_at_5b[0x25];
307 };
308
309 struct mlx5_ifc_flow_table_prop_layout_bits {
310         u8         ft_support[0x1];
311         u8         reserved_at_1[0x1];
312         u8         flow_counter[0x1];
313         u8         flow_modify_en[0x1];
314         u8         modify_root[0x1];
315         u8         identified_miss_table_mode[0x1];
316         u8         flow_table_modify[0x1];
317         u8         encap[0x1];
318         u8         decap[0x1];
319         u8         reserved_at_9[0x1];
320         u8         pop_vlan[0x1];
321         u8         push_vlan[0x1];
322         u8         reserved_at_c[0x14];
323
324         u8         reserved_at_20[0x2];
325         u8         log_max_ft_size[0x6];
326         u8         log_max_modify_header_context[0x8];
327         u8         max_modify_header_actions[0x8];
328         u8         max_ft_level[0x8];
329
330         u8         reserved_at_40[0x20];
331
332         u8         reserved_at_60[0x18];
333         u8         log_max_ft_num[0x8];
334
335         u8         reserved_at_80[0x18];
336         u8         log_max_destination[0x8];
337
338         u8         log_max_flow_counter[0x8];
339         u8         reserved_at_a8[0x10];
340         u8         log_max_flow[0x8];
341
342         u8         reserved_at_c0[0x40];
343
344         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
345
346         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
347 };
348
349 struct mlx5_ifc_odp_per_transport_service_cap_bits {
350         u8         send[0x1];
351         u8         receive[0x1];
352         u8         write[0x1];
353         u8         read[0x1];
354         u8         atomic[0x1];
355         u8         srq_receive[0x1];
356         u8         reserved_at_6[0x1a];
357 };
358
359 struct mlx5_ifc_ipv4_layout_bits {
360         u8         reserved_at_0[0x60];
361
362         u8         ipv4[0x20];
363 };
364
365 struct mlx5_ifc_ipv6_layout_bits {
366         u8         ipv6[16][0x8];
367 };
368
369 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
370         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
371         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
372         u8         reserved_at_0[0x80];
373 };
374
375 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
376         u8         smac_47_16[0x20];
377
378         u8         smac_15_0[0x10];
379         u8         ethertype[0x10];
380
381         u8         dmac_47_16[0x20];
382
383         u8         dmac_15_0[0x10];
384         u8         first_prio[0x3];
385         u8         first_cfi[0x1];
386         u8         first_vid[0xc];
387
388         u8         ip_protocol[0x8];
389         u8         ip_dscp[0x6];
390         u8         ip_ecn[0x2];
391         u8         cvlan_tag[0x1];
392         u8         svlan_tag[0x1];
393         u8         frag[0x1];
394         u8         ip_version[0x4];
395         u8         tcp_flags[0x9];
396
397         u8         tcp_sport[0x10];
398         u8         tcp_dport[0x10];
399
400         u8         reserved_at_c0[0x18];
401         u8         ttl_hoplimit[0x8];
402
403         u8         udp_sport[0x10];
404         u8         udp_dport[0x10];
405
406         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
407
408         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
409 };
410
411 struct mlx5_ifc_fte_match_set_misc_bits {
412         u8         reserved_at_0[0x8];
413         u8         source_sqn[0x18];
414
415         u8         reserved_at_20[0x10];
416         u8         source_port[0x10];
417
418         u8         outer_second_prio[0x3];
419         u8         outer_second_cfi[0x1];
420         u8         outer_second_vid[0xc];
421         u8         inner_second_prio[0x3];
422         u8         inner_second_cfi[0x1];
423         u8         inner_second_vid[0xc];
424
425         u8         outer_second_cvlan_tag[0x1];
426         u8         inner_second_cvlan_tag[0x1];
427         u8         outer_second_svlan_tag[0x1];
428         u8         inner_second_svlan_tag[0x1];
429         u8         reserved_at_64[0xc];
430         u8         gre_protocol[0x10];
431
432         u8         gre_key_h[0x18];
433         u8         gre_key_l[0x8];
434
435         u8         vxlan_vni[0x18];
436         u8         reserved_at_b8[0x8];
437
438         u8         reserved_at_c0[0x20];
439
440         u8         reserved_at_e0[0xc];
441         u8         outer_ipv6_flow_label[0x14];
442
443         u8         reserved_at_100[0xc];
444         u8         inner_ipv6_flow_label[0x14];
445
446         u8         reserved_at_120[0x28];
447         u8         bth_dst_qp[0x18];
448         u8         reserved_at_160[0x20];
449         u8         outer_esp_spi[0x20];
450         u8         reserved_at_1a0[0x60];
451 };
452
453 struct mlx5_ifc_cmd_pas_bits {
454         u8         pa_h[0x20];
455
456         u8         pa_l[0x14];
457         u8         reserved_at_34[0xc];
458 };
459
460 struct mlx5_ifc_uint64_bits {
461         u8         hi[0x20];
462
463         u8         lo[0x20];
464 };
465
466 enum {
467         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
468         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
469         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
470         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
471         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
472         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
473         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
474         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
475         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
476         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
477 };
478
479 struct mlx5_ifc_ads_bits {
480         u8         fl[0x1];
481         u8         free_ar[0x1];
482         u8         reserved_at_2[0xe];
483         u8         pkey_index[0x10];
484
485         u8         reserved_at_20[0x8];
486         u8         grh[0x1];
487         u8         mlid[0x7];
488         u8         rlid[0x10];
489
490         u8         ack_timeout[0x5];
491         u8         reserved_at_45[0x3];
492         u8         src_addr_index[0x8];
493         u8         reserved_at_50[0x4];
494         u8         stat_rate[0x4];
495         u8         hop_limit[0x8];
496
497         u8         reserved_at_60[0x4];
498         u8         tclass[0x8];
499         u8         flow_label[0x14];
500
501         u8         rgid_rip[16][0x8];
502
503         u8         reserved_at_100[0x4];
504         u8         f_dscp[0x1];
505         u8         f_ecn[0x1];
506         u8         reserved_at_106[0x1];
507         u8         f_eth_prio[0x1];
508         u8         ecn[0x2];
509         u8         dscp[0x6];
510         u8         udp_sport[0x10];
511
512         u8         dei_cfi[0x1];
513         u8         eth_prio[0x3];
514         u8         sl[0x4];
515         u8         vhca_port_num[0x8];
516         u8         rmac_47_32[0x10];
517
518         u8         rmac_31_0[0x20];
519 };
520
521 struct mlx5_ifc_flow_table_nic_cap_bits {
522         u8         nic_rx_multi_path_tirs[0x1];
523         u8         nic_rx_multi_path_tirs_fts[0x1];
524         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
525         u8         reserved_at_3[0x1fd];
526
527         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
528
529         u8         reserved_at_400[0x200];
530
531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
532
533         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
534
535         u8         reserved_at_a00[0x200];
536
537         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
538
539         u8         reserved_at_e00[0x7200];
540 };
541
542 struct mlx5_ifc_flow_table_eswitch_cap_bits {
543         u8     reserved_at_0[0x200];
544
545         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
546
547         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
548
549         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
550
551         u8      reserved_at_800[0x7800];
552 };
553
554 struct mlx5_ifc_e_switch_cap_bits {
555         u8         vport_svlan_strip[0x1];
556         u8         vport_cvlan_strip[0x1];
557         u8         vport_svlan_insert[0x1];
558         u8         vport_cvlan_insert_if_not_exist[0x1];
559         u8         vport_cvlan_insert_overwrite[0x1];
560         u8         reserved_at_5[0x19];
561         u8         nic_vport_node_guid_modify[0x1];
562         u8         nic_vport_port_guid_modify[0x1];
563
564         u8         vxlan_encap_decap[0x1];
565         u8         nvgre_encap_decap[0x1];
566         u8         reserved_at_22[0x9];
567         u8         log_max_encap_headers[0x5];
568         u8         reserved_2b[0x6];
569         u8         max_encap_header_size[0xa];
570
571         u8         reserved_40[0x7c0];
572
573 };
574
575 struct mlx5_ifc_qos_cap_bits {
576         u8         packet_pacing[0x1];
577         u8         esw_scheduling[0x1];
578         u8         esw_bw_share[0x1];
579         u8         esw_rate_limit[0x1];
580         u8         reserved_at_4[0x1];
581         u8         packet_pacing_burst_bound[0x1];
582         u8         packet_pacing_typical_size[0x1];
583         u8         reserved_at_7[0x19];
584
585         u8         reserved_at_20[0x20];
586
587         u8         packet_pacing_max_rate[0x20];
588
589         u8         packet_pacing_min_rate[0x20];
590
591         u8         reserved_at_80[0x10];
592         u8         packet_pacing_rate_table_size[0x10];
593
594         u8         esw_element_type[0x10];
595         u8         esw_tsar_type[0x10];
596
597         u8         reserved_at_c0[0x10];
598         u8         max_qos_para_vport[0x10];
599
600         u8         max_tsar_bw_share[0x20];
601
602         u8         reserved_at_100[0x700];
603 };
604
605 struct mlx5_ifc_debug_cap_bits {
606         u8         reserved_at_0[0x20];
607
608         u8         reserved_at_20[0x2];
609         u8         stall_detect[0x1];
610         u8         reserved_at_23[0x1d];
611
612         u8         reserved_at_40[0x7c0];
613 };
614
615 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
616         u8         csum_cap[0x1];
617         u8         vlan_cap[0x1];
618         u8         lro_cap[0x1];
619         u8         lro_psh_flag[0x1];
620         u8         lro_time_stamp[0x1];
621         u8         reserved_at_5[0x2];
622         u8         wqe_vlan_insert[0x1];
623         u8         self_lb_en_modifiable[0x1];
624         u8         reserved_at_9[0x2];
625         u8         max_lso_cap[0x5];
626         u8         multi_pkt_send_wqe[0x2];
627         u8         wqe_inline_mode[0x2];
628         u8         rss_ind_tbl_cap[0x4];
629         u8         reg_umr_sq[0x1];
630         u8         scatter_fcs[0x1];
631         u8         enhanced_multi_pkt_send_wqe[0x1];
632         u8         tunnel_lso_const_out_ip_id[0x1];
633         u8         reserved_at_1c[0x2];
634         u8         tunnel_stateless_gre[0x1];
635         u8         tunnel_stateless_vxlan[0x1];
636
637         u8         swp[0x1];
638         u8         swp_csum[0x1];
639         u8         swp_lso[0x1];
640         u8         reserved_at_23[0x1b];
641         u8         max_geneve_opt_len[0x1];
642         u8         tunnel_stateless_geneve_rx[0x1];
643
644         u8         reserved_at_40[0x10];
645         u8         lro_min_mss_size[0x10];
646
647         u8         reserved_at_60[0x120];
648
649         u8         lro_timer_supported_periods[4][0x20];
650
651         u8         reserved_at_200[0x600];
652 };
653
654 struct mlx5_ifc_roce_cap_bits {
655         u8         roce_apm[0x1];
656         u8         reserved_at_1[0x1f];
657
658         u8         reserved_at_20[0x60];
659
660         u8         reserved_at_80[0xc];
661         u8         l3_type[0x4];
662         u8         reserved_at_90[0x8];
663         u8         roce_version[0x8];
664
665         u8         reserved_at_a0[0x10];
666         u8         r_roce_dest_udp_port[0x10];
667
668         u8         r_roce_max_src_udp_port[0x10];
669         u8         r_roce_min_src_udp_port[0x10];
670
671         u8         reserved_at_e0[0x10];
672         u8         roce_address_table_size[0x10];
673
674         u8         reserved_at_100[0x700];
675 };
676
677 struct mlx5_ifc_device_mem_cap_bits {
678         u8         memic[0x1];
679         u8         reserved_at_1[0x1f];
680
681         u8         reserved_at_20[0xb];
682         u8         log_min_memic_alloc_size[0x5];
683         u8         reserved_at_30[0x8];
684         u8         log_max_memic_addr_alignment[0x8];
685
686         u8         memic_bar_start_addr[0x40];
687
688         u8         memic_bar_size[0x20];
689
690         u8         max_memic_size[0x20];
691
692         u8         reserved_at_c0[0x740];
693 };
694
695 enum {
696         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
697         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
698         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
699         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
700         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
701         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
702         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
703         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
704         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
705 };
706
707 enum {
708         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
709         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
710         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
711         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
712         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
713         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
714         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
715         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
716         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
717 };
718
719 struct mlx5_ifc_atomic_caps_bits {
720         u8         reserved_at_0[0x40];
721
722         u8         atomic_req_8B_endianness_mode[0x2];
723         u8         reserved_at_42[0x4];
724         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
725
726         u8         reserved_at_47[0x19];
727
728         u8         reserved_at_60[0x20];
729
730         u8         reserved_at_80[0x10];
731         u8         atomic_operations[0x10];
732
733         u8         reserved_at_a0[0x10];
734         u8         atomic_size_qp[0x10];
735
736         u8         reserved_at_c0[0x10];
737         u8         atomic_size_dc[0x10];
738
739         u8         reserved_at_e0[0x720];
740 };
741
742 struct mlx5_ifc_odp_cap_bits {
743         u8         reserved_at_0[0x40];
744
745         u8         sig[0x1];
746         u8         reserved_at_41[0x1f];
747
748         u8         reserved_at_60[0x20];
749
750         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
751
752         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
753
754         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
755
756         u8         reserved_at_e0[0x720];
757 };
758
759 struct mlx5_ifc_calc_op {
760         u8        reserved_at_0[0x10];
761         u8        reserved_at_10[0x9];
762         u8        op_swap_endianness[0x1];
763         u8        op_min[0x1];
764         u8        op_xor[0x1];
765         u8        op_or[0x1];
766         u8        op_and[0x1];
767         u8        op_max[0x1];
768         u8        op_add[0x1];
769 };
770
771 struct mlx5_ifc_vector_calc_cap_bits {
772         u8         calc_matrix[0x1];
773         u8         reserved_at_1[0x1f];
774         u8         reserved_at_20[0x8];
775         u8         max_vec_count[0x8];
776         u8         reserved_at_30[0xd];
777         u8         max_chunk_size[0x3];
778         struct mlx5_ifc_calc_op calc0;
779         struct mlx5_ifc_calc_op calc1;
780         struct mlx5_ifc_calc_op calc2;
781         struct mlx5_ifc_calc_op calc3;
782
783         u8         reserved_at_e0[0x720];
784 };
785
786 enum {
787         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
788         MLX5_WQ_TYPE_CYCLIC       = 0x1,
789         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
790         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
791 };
792
793 enum {
794         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
795         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
796 };
797
798 enum {
799         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
800         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
801         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
802         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
803         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
804 };
805
806 enum {
807         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
808         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
809         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
810         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
811         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
812         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
813 };
814
815 enum {
816         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
817         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
818 };
819
820 enum {
821         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
822         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
823         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
824 };
825
826 enum {
827         MLX5_CAP_PORT_TYPE_IB  = 0x0,
828         MLX5_CAP_PORT_TYPE_ETH = 0x1,
829 };
830
831 enum {
832         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
833         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
834         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
835 };
836
837 struct mlx5_ifc_cmd_hca_cap_bits {
838         u8         reserved_at_0[0x30];
839         u8         vhca_id[0x10];
840
841         u8         reserved_at_40[0x40];
842
843         u8         log_max_srq_sz[0x8];
844         u8         log_max_qp_sz[0x8];
845         u8         reserved_at_90[0xb];
846         u8         log_max_qp[0x5];
847
848         u8         reserved_at_a0[0xb];
849         u8         log_max_srq[0x5];
850         u8         reserved_at_b0[0x10];
851
852         u8         reserved_at_c0[0x8];
853         u8         log_max_cq_sz[0x8];
854         u8         reserved_at_d0[0xb];
855         u8         log_max_cq[0x5];
856
857         u8         log_max_eq_sz[0x8];
858         u8         reserved_at_e8[0x2];
859         u8         log_max_mkey[0x6];
860         u8         reserved_at_f0[0xc];
861         u8         log_max_eq[0x4];
862
863         u8         max_indirection[0x8];
864         u8         fixed_buffer_size[0x1];
865         u8         log_max_mrw_sz[0x7];
866         u8         force_teardown[0x1];
867         u8         reserved_at_111[0x1];
868         u8         log_max_bsf_list_size[0x6];
869         u8         umr_extended_translation_offset[0x1];
870         u8         null_mkey[0x1];
871         u8         log_max_klm_list_size[0x6];
872
873         u8         reserved_at_120[0xa];
874         u8         log_max_ra_req_dc[0x6];
875         u8         reserved_at_130[0xa];
876         u8         log_max_ra_res_dc[0x6];
877
878         u8         reserved_at_140[0xa];
879         u8         log_max_ra_req_qp[0x6];
880         u8         reserved_at_150[0xa];
881         u8         log_max_ra_res_qp[0x6];
882
883         u8         end_pad[0x1];
884         u8         cc_query_allowed[0x1];
885         u8         cc_modify_allowed[0x1];
886         u8         start_pad[0x1];
887         u8         cache_line_128byte[0x1];
888         u8         reserved_at_165[0xa];
889         u8         qcam_reg[0x1];
890         u8         gid_table_size[0x10];
891
892         u8         out_of_seq_cnt[0x1];
893         u8         vport_counters[0x1];
894         u8         retransmission_q_counters[0x1];
895         u8         debug[0x1];
896         u8         modify_rq_counter_set_id[0x1];
897         u8         rq_delay_drop[0x1];
898         u8         max_qp_cnt[0xa];
899         u8         pkey_table_size[0x10];
900
901         u8         vport_group_manager[0x1];
902         u8         vhca_group_manager[0x1];
903         u8         ib_virt[0x1];
904         u8         eth_virt[0x1];
905         u8         vnic_env_queue_counters[0x1];
906         u8         ets[0x1];
907         u8         nic_flow_table[0x1];
908         u8         eswitch_flow_table[0x1];
909         u8         device_memory[0x1];
910         u8         mcam_reg[0x1];
911         u8         pcam_reg[0x1];
912         u8         local_ca_ack_delay[0x5];
913         u8         port_module_event[0x1];
914         u8         enhanced_error_q_counters[0x1];
915         u8         ports_check[0x1];
916         u8         reserved_at_1b3[0x1];
917         u8         disable_link_up[0x1];
918         u8         beacon_led[0x1];
919         u8         port_type[0x2];
920         u8         num_ports[0x8];
921
922         u8         reserved_at_1c0[0x1];
923         u8         pps[0x1];
924         u8         pps_modify[0x1];
925         u8         log_max_msg[0x5];
926         u8         reserved_at_1c8[0x4];
927         u8         max_tc[0x4];
928         u8         reserved_at_1d0[0x1];
929         u8         dcbx[0x1];
930         u8         general_notification_event[0x1];
931         u8         reserved_at_1d3[0x2];
932         u8         fpga[0x1];
933         u8         rol_s[0x1];
934         u8         rol_g[0x1];
935         u8         reserved_at_1d8[0x1];
936         u8         wol_s[0x1];
937         u8         wol_g[0x1];
938         u8         wol_a[0x1];
939         u8         wol_b[0x1];
940         u8         wol_m[0x1];
941         u8         wol_u[0x1];
942         u8         wol_p[0x1];
943
944         u8         stat_rate_support[0x10];
945         u8         reserved_at_1f0[0xc];
946         u8         cqe_version[0x4];
947
948         u8         compact_address_vector[0x1];
949         u8         striding_rq[0x1];
950         u8         reserved_at_202[0x1];
951         u8         ipoib_enhanced_offloads[0x1];
952         u8         ipoib_basic_offloads[0x1];
953         u8         reserved_at_205[0x1];
954         u8         repeated_block_disabled[0x1];
955         u8         umr_modify_entity_size_disabled[0x1];
956         u8         umr_modify_atomic_disabled[0x1];
957         u8         umr_indirect_mkey_disabled[0x1];
958         u8         umr_fence[0x2];
959         u8         reserved_at_20c[0x3];
960         u8         drain_sigerr[0x1];
961         u8         cmdif_checksum[0x2];
962         u8         sigerr_cqe[0x1];
963         u8         reserved_at_213[0x1];
964         u8         wq_signature[0x1];
965         u8         sctr_data_cqe[0x1];
966         u8         reserved_at_216[0x1];
967         u8         sho[0x1];
968         u8         tph[0x1];
969         u8         rf[0x1];
970         u8         dct[0x1];
971         u8         qos[0x1];
972         u8         eth_net_offloads[0x1];
973         u8         roce[0x1];
974         u8         atomic[0x1];
975         u8         reserved_at_21f[0x1];
976
977         u8         cq_oi[0x1];
978         u8         cq_resize[0x1];
979         u8         cq_moderation[0x1];
980         u8         reserved_at_223[0x3];
981         u8         cq_eq_remap[0x1];
982         u8         pg[0x1];
983         u8         block_lb_mc[0x1];
984         u8         reserved_at_229[0x1];
985         u8         scqe_break_moderation[0x1];
986         u8         cq_period_start_from_cqe[0x1];
987         u8         cd[0x1];
988         u8         reserved_at_22d[0x1];
989         u8         apm[0x1];
990         u8         vector_calc[0x1];
991         u8         umr_ptr_rlky[0x1];
992         u8         imaicl[0x1];
993         u8         reserved_at_232[0x4];
994         u8         qkv[0x1];
995         u8         pkv[0x1];
996         u8         set_deth_sqpn[0x1];
997         u8         reserved_at_239[0x3];
998         u8         xrc[0x1];
999         u8         ud[0x1];
1000         u8         uc[0x1];
1001         u8         rc[0x1];
1002
1003         u8         uar_4k[0x1];
1004         u8         reserved_at_241[0x9];
1005         u8         uar_sz[0x6];
1006         u8         reserved_at_250[0x8];
1007         u8         log_pg_sz[0x8];
1008
1009         u8         bf[0x1];
1010         u8         driver_version[0x1];
1011         u8         pad_tx_eth_packet[0x1];
1012         u8         reserved_at_263[0x8];
1013         u8         log_bf_reg_size[0x5];
1014
1015         u8         reserved_at_270[0xb];
1016         u8         lag_master[0x1];
1017         u8         num_lag_ports[0x4];
1018
1019         u8         reserved_at_280[0x10];
1020         u8         max_wqe_sz_sq[0x10];
1021
1022         u8         reserved_at_2a0[0x10];
1023         u8         max_wqe_sz_rq[0x10];
1024
1025         u8         max_flow_counter_31_16[0x10];
1026         u8         max_wqe_sz_sq_dc[0x10];
1027
1028         u8         reserved_at_2e0[0x7];
1029         u8         max_qp_mcg[0x19];
1030
1031         u8         reserved_at_300[0x18];
1032         u8         log_max_mcg[0x8];
1033
1034         u8         reserved_at_320[0x3];
1035         u8         log_max_transport_domain[0x5];
1036         u8         reserved_at_328[0x3];
1037         u8         log_max_pd[0x5];
1038         u8         reserved_at_330[0xb];
1039         u8         log_max_xrcd[0x5];
1040
1041         u8         nic_receive_steering_discard[0x1];
1042         u8         receive_discard_vport_down[0x1];
1043         u8         transmit_discard_vport_down[0x1];
1044         u8         reserved_at_343[0x5];
1045         u8         log_max_flow_counter_bulk[0x8];
1046         u8         max_flow_counter_15_0[0x10];
1047
1048
1049         u8         reserved_at_360[0x3];
1050         u8         log_max_rq[0x5];
1051         u8         reserved_at_368[0x3];
1052         u8         log_max_sq[0x5];
1053         u8         reserved_at_370[0x3];
1054         u8         log_max_tir[0x5];
1055         u8         reserved_at_378[0x3];
1056         u8         log_max_tis[0x5];
1057
1058         u8         basic_cyclic_rcv_wqe[0x1];
1059         u8         reserved_at_381[0x2];
1060         u8         log_max_rmp[0x5];
1061         u8         reserved_at_388[0x3];
1062         u8         log_max_rqt[0x5];
1063         u8         reserved_at_390[0x3];
1064         u8         log_max_rqt_size[0x5];
1065         u8         reserved_at_398[0x3];
1066         u8         log_max_tis_per_sq[0x5];
1067
1068         u8         ext_stride_num_range[0x1];
1069         u8         reserved_at_3a1[0x2];
1070         u8         log_max_stride_sz_rq[0x5];
1071         u8         reserved_at_3a8[0x3];
1072         u8         log_min_stride_sz_rq[0x5];
1073         u8         reserved_at_3b0[0x3];
1074         u8         log_max_stride_sz_sq[0x5];
1075         u8         reserved_at_3b8[0x3];
1076         u8         log_min_stride_sz_sq[0x5];
1077
1078         u8         hairpin[0x1];
1079         u8         reserved_at_3c1[0x2];
1080         u8         log_max_hairpin_queues[0x5];
1081         u8         reserved_at_3c8[0x3];
1082         u8         log_max_hairpin_wq_data_sz[0x5];
1083         u8         reserved_at_3d0[0x3];
1084         u8         log_max_hairpin_num_packets[0x5];
1085         u8         reserved_at_3d8[0x3];
1086         u8         log_max_wq_sz[0x5];
1087
1088         u8         nic_vport_change_event[0x1];
1089         u8         disable_local_lb_uc[0x1];
1090         u8         disable_local_lb_mc[0x1];
1091         u8         log_min_hairpin_wq_data_sz[0x5];
1092         u8         reserved_at_3e8[0x3];
1093         u8         log_max_vlan_list[0x5];
1094         u8         reserved_at_3f0[0x3];
1095         u8         log_max_current_mc_list[0x5];
1096         u8         reserved_at_3f8[0x3];
1097         u8         log_max_current_uc_list[0x5];
1098
1099         u8         reserved_at_400[0x80];
1100
1101         u8         reserved_at_480[0x3];
1102         u8         log_max_l2_table[0x5];
1103         u8         reserved_at_488[0x8];
1104         u8         log_uar_page_sz[0x10];
1105
1106         u8         reserved_at_4a0[0x20];
1107         u8         device_frequency_mhz[0x20];
1108         u8         device_frequency_khz[0x20];
1109
1110         u8         reserved_at_500[0x20];
1111         u8         num_of_uars_per_page[0x20];
1112         u8         reserved_at_540[0x40];
1113
1114         u8         reserved_at_580[0x3d];
1115         u8         cqe_128_always[0x1];
1116         u8         cqe_compression_128[0x1];
1117         u8         cqe_compression[0x1];
1118
1119         u8         cqe_compression_timeout[0x10];
1120         u8         cqe_compression_max_num[0x10];
1121
1122         u8         reserved_at_5e0[0x10];
1123         u8         tag_matching[0x1];
1124         u8         rndv_offload_rc[0x1];
1125         u8         rndv_offload_dc[0x1];
1126         u8         log_tag_matching_list_sz[0x5];
1127         u8         reserved_at_5f8[0x3];
1128         u8         log_max_xrq[0x5];
1129
1130         u8         affiliate_nic_vport_criteria[0x8];
1131         u8         native_port_num[0x8];
1132         u8         num_vhca_ports[0x8];
1133         u8         reserved_at_618[0x6];
1134         u8         sw_owner_id[0x1];
1135         u8         reserved_at_61f[0x1e1];
1136 };
1137
1138 enum mlx5_flow_destination_type {
1139         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1140         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1141         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1142
1143         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1144         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1145 };
1146
1147 struct mlx5_ifc_dest_format_struct_bits {
1148         u8         destination_type[0x8];
1149         u8         destination_id[0x18];
1150
1151         u8         reserved_at_20[0x20];
1152 };
1153
1154 struct mlx5_ifc_flow_counter_list_bits {
1155         u8         flow_counter_id[0x20];
1156
1157         u8         reserved_at_20[0x20];
1158 };
1159
1160 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1161         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1162         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1163         u8         reserved_at_0[0x40];
1164 };
1165
1166 struct mlx5_ifc_fte_match_param_bits {
1167         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1168
1169         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1170
1171         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1172
1173         u8         reserved_at_600[0xa00];
1174 };
1175
1176 enum {
1177         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1178         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1179         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1180         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1181         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1182 };
1183
1184 struct mlx5_ifc_rx_hash_field_select_bits {
1185         u8         l3_prot_type[0x1];
1186         u8         l4_prot_type[0x1];
1187         u8         selected_fields[0x1e];
1188 };
1189
1190 enum {
1191         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1192         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1193 };
1194
1195 enum {
1196         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1197         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1198 };
1199
1200 struct mlx5_ifc_wq_bits {
1201         u8         wq_type[0x4];
1202         u8         wq_signature[0x1];
1203         u8         end_padding_mode[0x2];
1204         u8         cd_slave[0x1];
1205         u8         reserved_at_8[0x18];
1206
1207         u8         hds_skip_first_sge[0x1];
1208         u8         log2_hds_buf_size[0x3];
1209         u8         reserved_at_24[0x7];
1210         u8         page_offset[0x5];
1211         u8         lwm[0x10];
1212
1213         u8         reserved_at_40[0x8];
1214         u8         pd[0x18];
1215
1216         u8         reserved_at_60[0x8];
1217         u8         uar_page[0x18];
1218
1219         u8         dbr_addr[0x40];
1220
1221         u8         hw_counter[0x20];
1222
1223         u8         sw_counter[0x20];
1224
1225         u8         reserved_at_100[0xc];
1226         u8         log_wq_stride[0x4];
1227         u8         reserved_at_110[0x3];
1228         u8         log_wq_pg_sz[0x5];
1229         u8         reserved_at_118[0x3];
1230         u8         log_wq_sz[0x5];
1231
1232         u8         reserved_at_120[0x3];
1233         u8         log_hairpin_num_packets[0x5];
1234         u8         reserved_at_128[0x3];
1235         u8         log_hairpin_data_sz[0x5];
1236
1237         u8         reserved_at_130[0x4];
1238         u8         log_wqe_num_of_strides[0x4];
1239         u8         two_byte_shift_en[0x1];
1240         u8         reserved_at_139[0x4];
1241         u8         log_wqe_stride_size[0x3];
1242
1243         u8         reserved_at_140[0x4c0];
1244
1245         struct mlx5_ifc_cmd_pas_bits pas[0];
1246 };
1247
1248 struct mlx5_ifc_rq_num_bits {
1249         u8         reserved_at_0[0x8];
1250         u8         rq_num[0x18];
1251 };
1252
1253 struct mlx5_ifc_mac_address_layout_bits {
1254         u8         reserved_at_0[0x10];
1255         u8         mac_addr_47_32[0x10];
1256
1257         u8         mac_addr_31_0[0x20];
1258 };
1259
1260 struct mlx5_ifc_vlan_layout_bits {
1261         u8         reserved_at_0[0x14];
1262         u8         vlan[0x0c];
1263
1264         u8         reserved_at_20[0x20];
1265 };
1266
1267 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1268         u8         reserved_at_0[0xa0];
1269
1270         u8         min_time_between_cnps[0x20];
1271
1272         u8         reserved_at_c0[0x12];
1273         u8         cnp_dscp[0x6];
1274         u8         reserved_at_d8[0x4];
1275         u8         cnp_prio_mode[0x1];
1276         u8         cnp_802p_prio[0x3];
1277
1278         u8         reserved_at_e0[0x720];
1279 };
1280
1281 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1282         u8         reserved_at_0[0x60];
1283
1284         u8         reserved_at_60[0x4];
1285         u8         clamp_tgt_rate[0x1];
1286         u8         reserved_at_65[0x3];
1287         u8         clamp_tgt_rate_after_time_inc[0x1];
1288         u8         reserved_at_69[0x17];
1289
1290         u8         reserved_at_80[0x20];
1291
1292         u8         rpg_time_reset[0x20];
1293
1294         u8         rpg_byte_reset[0x20];
1295
1296         u8         rpg_threshold[0x20];
1297
1298         u8         rpg_max_rate[0x20];
1299
1300         u8         rpg_ai_rate[0x20];
1301
1302         u8         rpg_hai_rate[0x20];
1303
1304         u8         rpg_gd[0x20];
1305
1306         u8         rpg_min_dec_fac[0x20];
1307
1308         u8         rpg_min_rate[0x20];
1309
1310         u8         reserved_at_1c0[0xe0];
1311
1312         u8         rate_to_set_on_first_cnp[0x20];
1313
1314         u8         dce_tcp_g[0x20];
1315
1316         u8         dce_tcp_rtt[0x20];
1317
1318         u8         rate_reduce_monitor_period[0x20];
1319
1320         u8         reserved_at_320[0x20];
1321
1322         u8         initial_alpha_value[0x20];
1323
1324         u8         reserved_at_360[0x4a0];
1325 };
1326
1327 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1328         u8         reserved_at_0[0x80];
1329
1330         u8         rppp_max_rps[0x20];
1331
1332         u8         rpg_time_reset[0x20];
1333
1334         u8         rpg_byte_reset[0x20];
1335
1336         u8         rpg_threshold[0x20];
1337
1338         u8         rpg_max_rate[0x20];
1339
1340         u8         rpg_ai_rate[0x20];
1341
1342         u8         rpg_hai_rate[0x20];
1343
1344         u8         rpg_gd[0x20];
1345
1346         u8         rpg_min_dec_fac[0x20];
1347
1348         u8         rpg_min_rate[0x20];
1349
1350         u8         reserved_at_1c0[0x640];
1351 };
1352
1353 enum {
1354         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1355         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1356         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1357 };
1358
1359 struct mlx5_ifc_resize_field_select_bits {
1360         u8         resize_field_select[0x20];
1361 };
1362
1363 enum {
1364         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1365         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1366         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1367         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1368 };
1369
1370 struct mlx5_ifc_modify_field_select_bits {
1371         u8         modify_field_select[0x20];
1372 };
1373
1374 struct mlx5_ifc_field_select_r_roce_np_bits {
1375         u8         field_select_r_roce_np[0x20];
1376 };
1377
1378 struct mlx5_ifc_field_select_r_roce_rp_bits {
1379         u8         field_select_r_roce_rp[0x20];
1380 };
1381
1382 enum {
1383         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1384         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1385         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1386         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1387         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1388         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1389         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1390         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1391         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1392         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1393 };
1394
1395 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1396         u8         field_select_8021qaurp[0x20];
1397 };
1398
1399 struct mlx5_ifc_phys_layer_cntrs_bits {
1400         u8         time_since_last_clear_high[0x20];
1401
1402         u8         time_since_last_clear_low[0x20];
1403
1404         u8         symbol_errors_high[0x20];
1405
1406         u8         symbol_errors_low[0x20];
1407
1408         u8         sync_headers_errors_high[0x20];
1409
1410         u8         sync_headers_errors_low[0x20];
1411
1412         u8         edpl_bip_errors_lane0_high[0x20];
1413
1414         u8         edpl_bip_errors_lane0_low[0x20];
1415
1416         u8         edpl_bip_errors_lane1_high[0x20];
1417
1418         u8         edpl_bip_errors_lane1_low[0x20];
1419
1420         u8         edpl_bip_errors_lane2_high[0x20];
1421
1422         u8         edpl_bip_errors_lane2_low[0x20];
1423
1424         u8         edpl_bip_errors_lane3_high[0x20];
1425
1426         u8         edpl_bip_errors_lane3_low[0x20];
1427
1428         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1429
1430         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1431
1432         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1433
1434         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1435
1436         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1437
1438         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1439
1440         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1441
1442         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1443
1444         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1445
1446         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1447
1448         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1449
1450         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1451
1452         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1453
1454         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1455
1456         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1457
1458         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1459
1460         u8         rs_fec_corrected_blocks_high[0x20];
1461
1462         u8         rs_fec_corrected_blocks_low[0x20];
1463
1464         u8         rs_fec_uncorrectable_blocks_high[0x20];
1465
1466         u8         rs_fec_uncorrectable_blocks_low[0x20];
1467
1468         u8         rs_fec_no_errors_blocks_high[0x20];
1469
1470         u8         rs_fec_no_errors_blocks_low[0x20];
1471
1472         u8         rs_fec_single_error_blocks_high[0x20];
1473
1474         u8         rs_fec_single_error_blocks_low[0x20];
1475
1476         u8         rs_fec_corrected_symbols_total_high[0x20];
1477
1478         u8         rs_fec_corrected_symbols_total_low[0x20];
1479
1480         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1481
1482         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1483
1484         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1485
1486         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1487
1488         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1489
1490         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1491
1492         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1493
1494         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1495
1496         u8         link_down_events[0x20];
1497
1498         u8         successful_recovery_events[0x20];
1499
1500         u8         reserved_at_640[0x180];
1501 };
1502
1503 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1504         u8         time_since_last_clear_high[0x20];
1505
1506         u8         time_since_last_clear_low[0x20];
1507
1508         u8         phy_received_bits_high[0x20];
1509
1510         u8         phy_received_bits_low[0x20];
1511
1512         u8         phy_symbol_errors_high[0x20];
1513
1514         u8         phy_symbol_errors_low[0x20];
1515
1516         u8         phy_corrected_bits_high[0x20];
1517
1518         u8         phy_corrected_bits_low[0x20];
1519
1520         u8         phy_corrected_bits_lane0_high[0x20];
1521
1522         u8         phy_corrected_bits_lane0_low[0x20];
1523
1524         u8         phy_corrected_bits_lane1_high[0x20];
1525
1526         u8         phy_corrected_bits_lane1_low[0x20];
1527
1528         u8         phy_corrected_bits_lane2_high[0x20];
1529
1530         u8         phy_corrected_bits_lane2_low[0x20];
1531
1532         u8         phy_corrected_bits_lane3_high[0x20];
1533
1534         u8         phy_corrected_bits_lane3_low[0x20];
1535
1536         u8         reserved_at_200[0x5c0];
1537 };
1538
1539 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1540         u8         symbol_error_counter[0x10];
1541
1542         u8         link_error_recovery_counter[0x8];
1543
1544         u8         link_downed_counter[0x8];
1545
1546         u8         port_rcv_errors[0x10];
1547
1548         u8         port_rcv_remote_physical_errors[0x10];
1549
1550         u8         port_rcv_switch_relay_errors[0x10];
1551
1552         u8         port_xmit_discards[0x10];
1553
1554         u8         port_xmit_constraint_errors[0x8];
1555
1556         u8         port_rcv_constraint_errors[0x8];
1557
1558         u8         reserved_at_70[0x8];
1559
1560         u8         link_overrun_errors[0x8];
1561
1562         u8         reserved_at_80[0x10];
1563
1564         u8         vl_15_dropped[0x10];
1565
1566         u8         reserved_at_a0[0x80];
1567
1568         u8         port_xmit_wait[0x20];
1569 };
1570
1571 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1572         u8         transmit_queue_high[0x20];
1573
1574         u8         transmit_queue_low[0x20];
1575
1576         u8         reserved_at_40[0x780];
1577 };
1578
1579 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1580         u8         rx_octets_high[0x20];
1581
1582         u8         rx_octets_low[0x20];
1583
1584         u8         reserved_at_40[0xc0];
1585
1586         u8         rx_frames_high[0x20];
1587
1588         u8         rx_frames_low[0x20];
1589
1590         u8         tx_octets_high[0x20];
1591
1592         u8         tx_octets_low[0x20];
1593
1594         u8         reserved_at_180[0xc0];
1595
1596         u8         tx_frames_high[0x20];
1597
1598         u8         tx_frames_low[0x20];
1599
1600         u8         rx_pause_high[0x20];
1601
1602         u8         rx_pause_low[0x20];
1603
1604         u8         rx_pause_duration_high[0x20];
1605
1606         u8         rx_pause_duration_low[0x20];
1607
1608         u8         tx_pause_high[0x20];
1609
1610         u8         tx_pause_low[0x20];
1611
1612         u8         tx_pause_duration_high[0x20];
1613
1614         u8         tx_pause_duration_low[0x20];
1615
1616         u8         rx_pause_transition_high[0x20];
1617
1618         u8         rx_pause_transition_low[0x20];
1619
1620         u8         reserved_at_3c0[0x40];
1621
1622         u8         device_stall_minor_watermark_cnt_high[0x20];
1623
1624         u8         device_stall_minor_watermark_cnt_low[0x20];
1625
1626         u8         device_stall_critical_watermark_cnt_high[0x20];
1627
1628         u8         device_stall_critical_watermark_cnt_low[0x20];
1629
1630         u8         reserved_at_480[0x340];
1631 };
1632
1633 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1634         u8         port_transmit_wait_high[0x20];
1635
1636         u8         port_transmit_wait_low[0x20];
1637
1638         u8         reserved_at_40[0x100];
1639
1640         u8         rx_buffer_almost_full_high[0x20];
1641
1642         u8         rx_buffer_almost_full_low[0x20];
1643
1644         u8         rx_buffer_full_high[0x20];
1645
1646         u8         rx_buffer_full_low[0x20];
1647
1648         u8         reserved_at_1c0[0x600];
1649 };
1650
1651 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1652         u8         dot3stats_alignment_errors_high[0x20];
1653
1654         u8         dot3stats_alignment_errors_low[0x20];
1655
1656         u8         dot3stats_fcs_errors_high[0x20];
1657
1658         u8         dot3stats_fcs_errors_low[0x20];
1659
1660         u8         dot3stats_single_collision_frames_high[0x20];
1661
1662         u8         dot3stats_single_collision_frames_low[0x20];
1663
1664         u8         dot3stats_multiple_collision_frames_high[0x20];
1665
1666         u8         dot3stats_multiple_collision_frames_low[0x20];
1667
1668         u8         dot3stats_sqe_test_errors_high[0x20];
1669
1670         u8         dot3stats_sqe_test_errors_low[0x20];
1671
1672         u8         dot3stats_deferred_transmissions_high[0x20];
1673
1674         u8         dot3stats_deferred_transmissions_low[0x20];
1675
1676         u8         dot3stats_late_collisions_high[0x20];
1677
1678         u8         dot3stats_late_collisions_low[0x20];
1679
1680         u8         dot3stats_excessive_collisions_high[0x20];
1681
1682         u8         dot3stats_excessive_collisions_low[0x20];
1683
1684         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1685
1686         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1687
1688         u8         dot3stats_carrier_sense_errors_high[0x20];
1689
1690         u8         dot3stats_carrier_sense_errors_low[0x20];
1691
1692         u8         dot3stats_frame_too_longs_high[0x20];
1693
1694         u8         dot3stats_frame_too_longs_low[0x20];
1695
1696         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1697
1698         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1699
1700         u8         dot3stats_symbol_errors_high[0x20];
1701
1702         u8         dot3stats_symbol_errors_low[0x20];
1703
1704         u8         dot3control_in_unknown_opcodes_high[0x20];
1705
1706         u8         dot3control_in_unknown_opcodes_low[0x20];
1707
1708         u8         dot3in_pause_frames_high[0x20];
1709
1710         u8         dot3in_pause_frames_low[0x20];
1711
1712         u8         dot3out_pause_frames_high[0x20];
1713
1714         u8         dot3out_pause_frames_low[0x20];
1715
1716         u8         reserved_at_400[0x3c0];
1717 };
1718
1719 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1720         u8         ether_stats_drop_events_high[0x20];
1721
1722         u8         ether_stats_drop_events_low[0x20];
1723
1724         u8         ether_stats_octets_high[0x20];
1725
1726         u8         ether_stats_octets_low[0x20];
1727
1728         u8         ether_stats_pkts_high[0x20];
1729
1730         u8         ether_stats_pkts_low[0x20];
1731
1732         u8         ether_stats_broadcast_pkts_high[0x20];
1733
1734         u8         ether_stats_broadcast_pkts_low[0x20];
1735
1736         u8         ether_stats_multicast_pkts_high[0x20];
1737
1738         u8         ether_stats_multicast_pkts_low[0x20];
1739
1740         u8         ether_stats_crc_align_errors_high[0x20];
1741
1742         u8         ether_stats_crc_align_errors_low[0x20];
1743
1744         u8         ether_stats_undersize_pkts_high[0x20];
1745
1746         u8         ether_stats_undersize_pkts_low[0x20];
1747
1748         u8         ether_stats_oversize_pkts_high[0x20];
1749
1750         u8         ether_stats_oversize_pkts_low[0x20];
1751
1752         u8         ether_stats_fragments_high[0x20];
1753
1754         u8         ether_stats_fragments_low[0x20];
1755
1756         u8         ether_stats_jabbers_high[0x20];
1757
1758         u8         ether_stats_jabbers_low[0x20];
1759
1760         u8         ether_stats_collisions_high[0x20];
1761
1762         u8         ether_stats_collisions_low[0x20];
1763
1764         u8         ether_stats_pkts64octets_high[0x20];
1765
1766         u8         ether_stats_pkts64octets_low[0x20];
1767
1768         u8         ether_stats_pkts65to127octets_high[0x20];
1769
1770         u8         ether_stats_pkts65to127octets_low[0x20];
1771
1772         u8         ether_stats_pkts128to255octets_high[0x20];
1773
1774         u8         ether_stats_pkts128to255octets_low[0x20];
1775
1776         u8         ether_stats_pkts256to511octets_high[0x20];
1777
1778         u8         ether_stats_pkts256to511octets_low[0x20];
1779
1780         u8         ether_stats_pkts512to1023octets_high[0x20];
1781
1782         u8         ether_stats_pkts512to1023octets_low[0x20];
1783
1784         u8         ether_stats_pkts1024to1518octets_high[0x20];
1785
1786         u8         ether_stats_pkts1024to1518octets_low[0x20];
1787
1788         u8         ether_stats_pkts1519to2047octets_high[0x20];
1789
1790         u8         ether_stats_pkts1519to2047octets_low[0x20];
1791
1792         u8         ether_stats_pkts2048to4095octets_high[0x20];
1793
1794         u8         ether_stats_pkts2048to4095octets_low[0x20];
1795
1796         u8         ether_stats_pkts4096to8191octets_high[0x20];
1797
1798         u8         ether_stats_pkts4096to8191octets_low[0x20];
1799
1800         u8         ether_stats_pkts8192to10239octets_high[0x20];
1801
1802         u8         ether_stats_pkts8192to10239octets_low[0x20];
1803
1804         u8         reserved_at_540[0x280];
1805 };
1806
1807 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1808         u8         if_in_octets_high[0x20];
1809
1810         u8         if_in_octets_low[0x20];
1811
1812         u8         if_in_ucast_pkts_high[0x20];
1813
1814         u8         if_in_ucast_pkts_low[0x20];
1815
1816         u8         if_in_discards_high[0x20];
1817
1818         u8         if_in_discards_low[0x20];
1819
1820         u8         if_in_errors_high[0x20];
1821
1822         u8         if_in_errors_low[0x20];
1823
1824         u8         if_in_unknown_protos_high[0x20];
1825
1826         u8         if_in_unknown_protos_low[0x20];
1827
1828         u8         if_out_octets_high[0x20];
1829
1830         u8         if_out_octets_low[0x20];
1831
1832         u8         if_out_ucast_pkts_high[0x20];
1833
1834         u8         if_out_ucast_pkts_low[0x20];
1835
1836         u8         if_out_discards_high[0x20];
1837
1838         u8         if_out_discards_low[0x20];
1839
1840         u8         if_out_errors_high[0x20];
1841
1842         u8         if_out_errors_low[0x20];
1843
1844         u8         if_in_multicast_pkts_high[0x20];
1845
1846         u8         if_in_multicast_pkts_low[0x20];
1847
1848         u8         if_in_broadcast_pkts_high[0x20];
1849
1850         u8         if_in_broadcast_pkts_low[0x20];
1851
1852         u8         if_out_multicast_pkts_high[0x20];
1853
1854         u8         if_out_multicast_pkts_low[0x20];
1855
1856         u8         if_out_broadcast_pkts_high[0x20];
1857
1858         u8         if_out_broadcast_pkts_low[0x20];
1859
1860         u8         reserved_at_340[0x480];
1861 };
1862
1863 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1864         u8         a_frames_transmitted_ok_high[0x20];
1865
1866         u8         a_frames_transmitted_ok_low[0x20];
1867
1868         u8         a_frames_received_ok_high[0x20];
1869
1870         u8         a_frames_received_ok_low[0x20];
1871
1872         u8         a_frame_check_sequence_errors_high[0x20];
1873
1874         u8         a_frame_check_sequence_errors_low[0x20];
1875
1876         u8         a_alignment_errors_high[0x20];
1877
1878         u8         a_alignment_errors_low[0x20];
1879
1880         u8         a_octets_transmitted_ok_high[0x20];
1881
1882         u8         a_octets_transmitted_ok_low[0x20];
1883
1884         u8         a_octets_received_ok_high[0x20];
1885
1886         u8         a_octets_received_ok_low[0x20];
1887
1888         u8         a_multicast_frames_xmitted_ok_high[0x20];
1889
1890         u8         a_multicast_frames_xmitted_ok_low[0x20];
1891
1892         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1893
1894         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1895
1896         u8         a_multicast_frames_received_ok_high[0x20];
1897
1898         u8         a_multicast_frames_received_ok_low[0x20];
1899
1900         u8         a_broadcast_frames_received_ok_high[0x20];
1901
1902         u8         a_broadcast_frames_received_ok_low[0x20];
1903
1904         u8         a_in_range_length_errors_high[0x20];
1905
1906         u8         a_in_range_length_errors_low[0x20];
1907
1908         u8         a_out_of_range_length_field_high[0x20];
1909
1910         u8         a_out_of_range_length_field_low[0x20];
1911
1912         u8         a_frame_too_long_errors_high[0x20];
1913
1914         u8         a_frame_too_long_errors_low[0x20];
1915
1916         u8         a_symbol_error_during_carrier_high[0x20];
1917
1918         u8         a_symbol_error_during_carrier_low[0x20];
1919
1920         u8         a_mac_control_frames_transmitted_high[0x20];
1921
1922         u8         a_mac_control_frames_transmitted_low[0x20];
1923
1924         u8         a_mac_control_frames_received_high[0x20];
1925
1926         u8         a_mac_control_frames_received_low[0x20];
1927
1928         u8         a_unsupported_opcodes_received_high[0x20];
1929
1930         u8         a_unsupported_opcodes_received_low[0x20];
1931
1932         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1933
1934         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1935
1936         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1937
1938         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1939
1940         u8         reserved_at_4c0[0x300];
1941 };
1942
1943 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1944         u8         life_time_counter_high[0x20];
1945
1946         u8         life_time_counter_low[0x20];
1947
1948         u8         rx_errors[0x20];
1949
1950         u8         tx_errors[0x20];
1951
1952         u8         l0_to_recovery_eieos[0x20];
1953
1954         u8         l0_to_recovery_ts[0x20];
1955
1956         u8         l0_to_recovery_framing[0x20];
1957
1958         u8         l0_to_recovery_retrain[0x20];
1959
1960         u8         crc_error_dllp[0x20];
1961
1962         u8         crc_error_tlp[0x20];
1963
1964         u8         tx_overflow_buffer_pkt_high[0x20];
1965
1966         u8         tx_overflow_buffer_pkt_low[0x20];
1967
1968         u8         outbound_stalled_reads[0x20];
1969
1970         u8         outbound_stalled_writes[0x20];
1971
1972         u8         outbound_stalled_reads_events[0x20];
1973
1974         u8         outbound_stalled_writes_events[0x20];
1975
1976         u8         reserved_at_200[0x5c0];
1977 };
1978
1979 struct mlx5_ifc_cmd_inter_comp_event_bits {
1980         u8         command_completion_vector[0x20];
1981
1982         u8         reserved_at_20[0xc0];
1983 };
1984
1985 struct mlx5_ifc_stall_vl_event_bits {
1986         u8         reserved_at_0[0x18];
1987         u8         port_num[0x1];
1988         u8         reserved_at_19[0x3];
1989         u8         vl[0x4];
1990
1991         u8         reserved_at_20[0xa0];
1992 };
1993
1994 struct mlx5_ifc_db_bf_congestion_event_bits {
1995         u8         event_subtype[0x8];
1996         u8         reserved_at_8[0x8];
1997         u8         congestion_level[0x8];
1998         u8         reserved_at_18[0x8];
1999
2000         u8         reserved_at_20[0xa0];
2001 };
2002
2003 struct mlx5_ifc_gpio_event_bits {
2004         u8         reserved_at_0[0x60];
2005
2006         u8         gpio_event_hi[0x20];
2007
2008         u8         gpio_event_lo[0x20];
2009
2010         u8         reserved_at_a0[0x40];
2011 };
2012
2013 struct mlx5_ifc_port_state_change_event_bits {
2014         u8         reserved_at_0[0x40];
2015
2016         u8         port_num[0x4];
2017         u8         reserved_at_44[0x1c];
2018
2019         u8         reserved_at_60[0x80];
2020 };
2021
2022 struct mlx5_ifc_dropped_packet_logged_bits {
2023         u8         reserved_at_0[0xe0];
2024 };
2025
2026 enum {
2027         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2028         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2029 };
2030
2031 struct mlx5_ifc_cq_error_bits {
2032         u8         reserved_at_0[0x8];
2033         u8         cqn[0x18];
2034
2035         u8         reserved_at_20[0x20];
2036
2037         u8         reserved_at_40[0x18];
2038         u8         syndrome[0x8];
2039
2040         u8         reserved_at_60[0x80];
2041 };
2042
2043 struct mlx5_ifc_rdma_page_fault_event_bits {
2044         u8         bytes_committed[0x20];
2045
2046         u8         r_key[0x20];
2047
2048         u8         reserved_at_40[0x10];
2049         u8         packet_len[0x10];
2050
2051         u8         rdma_op_len[0x20];
2052
2053         u8         rdma_va[0x40];
2054
2055         u8         reserved_at_c0[0x5];
2056         u8         rdma[0x1];
2057         u8         write[0x1];
2058         u8         requestor[0x1];
2059         u8         qp_number[0x18];
2060 };
2061
2062 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2063         u8         bytes_committed[0x20];
2064
2065         u8         reserved_at_20[0x10];
2066         u8         wqe_index[0x10];
2067
2068         u8         reserved_at_40[0x10];
2069         u8         len[0x10];
2070
2071         u8         reserved_at_60[0x60];
2072
2073         u8         reserved_at_c0[0x5];
2074         u8         rdma[0x1];
2075         u8         write_read[0x1];
2076         u8         requestor[0x1];
2077         u8         qpn[0x18];
2078 };
2079
2080 struct mlx5_ifc_qp_events_bits {
2081         u8         reserved_at_0[0xa0];
2082
2083         u8         type[0x8];
2084         u8         reserved_at_a8[0x18];
2085
2086         u8         reserved_at_c0[0x8];
2087         u8         qpn_rqn_sqn[0x18];
2088 };
2089
2090 struct mlx5_ifc_dct_events_bits {
2091         u8         reserved_at_0[0xc0];
2092
2093         u8         reserved_at_c0[0x8];
2094         u8         dct_number[0x18];
2095 };
2096
2097 struct mlx5_ifc_comp_event_bits {
2098         u8         reserved_at_0[0xc0];
2099
2100         u8         reserved_at_c0[0x8];
2101         u8         cq_number[0x18];
2102 };
2103
2104 enum {
2105         MLX5_QPC_STATE_RST        = 0x0,
2106         MLX5_QPC_STATE_INIT       = 0x1,
2107         MLX5_QPC_STATE_RTR        = 0x2,
2108         MLX5_QPC_STATE_RTS        = 0x3,
2109         MLX5_QPC_STATE_SQER       = 0x4,
2110         MLX5_QPC_STATE_ERR        = 0x6,
2111         MLX5_QPC_STATE_SQD        = 0x7,
2112         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2113 };
2114
2115 enum {
2116         MLX5_QPC_ST_RC            = 0x0,
2117         MLX5_QPC_ST_UC            = 0x1,
2118         MLX5_QPC_ST_UD            = 0x2,
2119         MLX5_QPC_ST_XRC           = 0x3,
2120         MLX5_QPC_ST_DCI           = 0x5,
2121         MLX5_QPC_ST_QP0           = 0x7,
2122         MLX5_QPC_ST_QP1           = 0x8,
2123         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2124         MLX5_QPC_ST_REG_UMR       = 0xc,
2125 };
2126
2127 enum {
2128         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2129         MLX5_QPC_PM_STATE_REARM     = 0x1,
2130         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2131         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2132 };
2133
2134 enum {
2135         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2136 };
2137
2138 enum {
2139         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2140         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2141 };
2142
2143 enum {
2144         MLX5_QPC_MTU_256_BYTES        = 0x1,
2145         MLX5_QPC_MTU_512_BYTES        = 0x2,
2146         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2147         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2148         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2149         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2150 };
2151
2152 enum {
2153         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2154         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2155         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2156         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2157         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2158         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2159         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2160         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2161 };
2162
2163 enum {
2164         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2165         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2166         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2167 };
2168
2169 enum {
2170         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2171         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2172         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2173 };
2174
2175 struct mlx5_ifc_qpc_bits {
2176         u8         state[0x4];
2177         u8         lag_tx_port_affinity[0x4];
2178         u8         st[0x8];
2179         u8         reserved_at_10[0x3];
2180         u8         pm_state[0x2];
2181         u8         reserved_at_15[0x3];
2182         u8         offload_type[0x4];
2183         u8         end_padding_mode[0x2];
2184         u8         reserved_at_1e[0x2];
2185
2186         u8         wq_signature[0x1];
2187         u8         block_lb_mc[0x1];
2188         u8         atomic_like_write_en[0x1];
2189         u8         latency_sensitive[0x1];
2190         u8         reserved_at_24[0x1];
2191         u8         drain_sigerr[0x1];
2192         u8         reserved_at_26[0x2];
2193         u8         pd[0x18];
2194
2195         u8         mtu[0x3];
2196         u8         log_msg_max[0x5];
2197         u8         reserved_at_48[0x1];
2198         u8         log_rq_size[0x4];
2199         u8         log_rq_stride[0x3];
2200         u8         no_sq[0x1];
2201         u8         log_sq_size[0x4];
2202         u8         reserved_at_55[0x6];
2203         u8         rlky[0x1];
2204         u8         ulp_stateless_offload_mode[0x4];
2205
2206         u8         counter_set_id[0x8];
2207         u8         uar_page[0x18];
2208
2209         u8         reserved_at_80[0x8];
2210         u8         user_index[0x18];
2211
2212         u8         reserved_at_a0[0x3];
2213         u8         log_page_size[0x5];
2214         u8         remote_qpn[0x18];
2215
2216         struct mlx5_ifc_ads_bits primary_address_path;
2217
2218         struct mlx5_ifc_ads_bits secondary_address_path;
2219
2220         u8         log_ack_req_freq[0x4];
2221         u8         reserved_at_384[0x4];
2222         u8         log_sra_max[0x3];
2223         u8         reserved_at_38b[0x2];
2224         u8         retry_count[0x3];
2225         u8         rnr_retry[0x3];
2226         u8         reserved_at_393[0x1];
2227         u8         fre[0x1];
2228         u8         cur_rnr_retry[0x3];
2229         u8         cur_retry_count[0x3];
2230         u8         reserved_at_39b[0x5];
2231
2232         u8         reserved_at_3a0[0x20];
2233
2234         u8         reserved_at_3c0[0x8];
2235         u8         next_send_psn[0x18];
2236
2237         u8         reserved_at_3e0[0x8];
2238         u8         cqn_snd[0x18];
2239
2240         u8         reserved_at_400[0x8];
2241         u8         deth_sqpn[0x18];
2242
2243         u8         reserved_at_420[0x20];
2244
2245         u8         reserved_at_440[0x8];
2246         u8         last_acked_psn[0x18];
2247
2248         u8         reserved_at_460[0x8];
2249         u8         ssn[0x18];
2250
2251         u8         reserved_at_480[0x8];
2252         u8         log_rra_max[0x3];
2253         u8         reserved_at_48b[0x1];
2254         u8         atomic_mode[0x4];
2255         u8         rre[0x1];
2256         u8         rwe[0x1];
2257         u8         rae[0x1];
2258         u8         reserved_at_493[0x1];
2259         u8         page_offset[0x6];
2260         u8         reserved_at_49a[0x3];
2261         u8         cd_slave_receive[0x1];
2262         u8         cd_slave_send[0x1];
2263         u8         cd_master[0x1];
2264
2265         u8         reserved_at_4a0[0x3];
2266         u8         min_rnr_nak[0x5];
2267         u8         next_rcv_psn[0x18];
2268
2269         u8         reserved_at_4c0[0x8];
2270         u8         xrcd[0x18];
2271
2272         u8         reserved_at_4e0[0x8];
2273         u8         cqn_rcv[0x18];
2274
2275         u8         dbr_addr[0x40];
2276
2277         u8         q_key[0x20];
2278
2279         u8         reserved_at_560[0x5];
2280         u8         rq_type[0x3];
2281         u8         srqn_rmpn_xrqn[0x18];
2282
2283         u8         reserved_at_580[0x8];
2284         u8         rmsn[0x18];
2285
2286         u8         hw_sq_wqebb_counter[0x10];
2287         u8         sw_sq_wqebb_counter[0x10];
2288
2289         u8         hw_rq_counter[0x20];
2290
2291         u8         sw_rq_counter[0x20];
2292
2293         u8         reserved_at_600[0x20];
2294
2295         u8         reserved_at_620[0xf];
2296         u8         cgs[0x1];
2297         u8         cs_req[0x8];
2298         u8         cs_res[0x8];
2299
2300         u8         dc_access_key[0x40];
2301
2302         u8         reserved_at_680[0xc0];
2303 };
2304
2305 struct mlx5_ifc_roce_addr_layout_bits {
2306         u8         source_l3_address[16][0x8];
2307
2308         u8         reserved_at_80[0x3];
2309         u8         vlan_valid[0x1];
2310         u8         vlan_id[0xc];
2311         u8         source_mac_47_32[0x10];
2312
2313         u8         source_mac_31_0[0x20];
2314
2315         u8         reserved_at_c0[0x14];
2316         u8         roce_l3_type[0x4];
2317         u8         roce_version[0x8];
2318
2319         u8         reserved_at_e0[0x20];
2320 };
2321
2322 union mlx5_ifc_hca_cap_union_bits {
2323         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2324         struct mlx5_ifc_odp_cap_bits odp_cap;
2325         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2326         struct mlx5_ifc_roce_cap_bits roce_cap;
2327         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2328         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2329         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2330         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2331         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2332         struct mlx5_ifc_qos_cap_bits qos_cap;
2333         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2334         u8         reserved_at_0[0x8000];
2335 };
2336
2337 enum {
2338         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2339         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2340         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2341         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2342         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2343         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2344         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2345         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2346         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2347 };
2348
2349 struct mlx5_ifc_vlan_bits {
2350         u8         ethtype[0x10];
2351         u8         prio[0x3];
2352         u8         cfi[0x1];
2353         u8         vid[0xc];
2354 };
2355
2356 struct mlx5_ifc_flow_context_bits {
2357         struct mlx5_ifc_vlan_bits push_vlan;
2358
2359         u8         group_id[0x20];
2360
2361         u8         reserved_at_40[0x8];
2362         u8         flow_tag[0x18];
2363
2364         u8         reserved_at_60[0x10];
2365         u8         action[0x10];
2366
2367         u8         reserved_at_80[0x8];
2368         u8         destination_list_size[0x18];
2369
2370         u8         reserved_at_a0[0x8];
2371         u8         flow_counter_list_size[0x18];
2372
2373         u8         encap_id[0x20];
2374
2375         u8         modify_header_id[0x20];
2376
2377         u8         reserved_at_100[0x100];
2378
2379         struct mlx5_ifc_fte_match_param_bits match_value;
2380
2381         u8         reserved_at_1200[0x600];
2382
2383         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2384 };
2385
2386 enum {
2387         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2388         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2389 };
2390
2391 struct mlx5_ifc_xrc_srqc_bits {
2392         u8         state[0x4];
2393         u8         log_xrc_srq_size[0x4];
2394         u8         reserved_at_8[0x18];
2395
2396         u8         wq_signature[0x1];
2397         u8         cont_srq[0x1];
2398         u8         reserved_at_22[0x1];
2399         u8         rlky[0x1];
2400         u8         basic_cyclic_rcv_wqe[0x1];
2401         u8         log_rq_stride[0x3];
2402         u8         xrcd[0x18];
2403
2404         u8         page_offset[0x6];
2405         u8         reserved_at_46[0x2];
2406         u8         cqn[0x18];
2407
2408         u8         reserved_at_60[0x20];
2409
2410         u8         user_index_equal_xrc_srqn[0x1];
2411         u8         reserved_at_81[0x1];
2412         u8         log_page_size[0x6];
2413         u8         user_index[0x18];
2414
2415         u8         reserved_at_a0[0x20];
2416
2417         u8         reserved_at_c0[0x8];
2418         u8         pd[0x18];
2419
2420         u8         lwm[0x10];
2421         u8         wqe_cnt[0x10];
2422
2423         u8         reserved_at_100[0x40];
2424
2425         u8         db_record_addr_h[0x20];
2426
2427         u8         db_record_addr_l[0x1e];
2428         u8         reserved_at_17e[0x2];
2429
2430         u8         reserved_at_180[0x80];
2431 };
2432
2433 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2434         u8         counter_error_queues[0x20];
2435
2436         u8         total_error_queues[0x20];
2437
2438         u8         send_queue_priority_update_flow[0x20];
2439
2440         u8         reserved_at_60[0x20];
2441
2442         u8         nic_receive_steering_discard[0x40];
2443
2444         u8         receive_discard_vport_down[0x40];
2445
2446         u8         transmit_discard_vport_down[0x40];
2447
2448         u8         reserved_at_140[0xec0];
2449 };
2450
2451 struct mlx5_ifc_traffic_counter_bits {
2452         u8         packets[0x40];
2453
2454         u8         octets[0x40];
2455 };
2456
2457 struct mlx5_ifc_tisc_bits {
2458         u8         strict_lag_tx_port_affinity[0x1];
2459         u8         reserved_at_1[0x3];
2460         u8         lag_tx_port_affinity[0x04];
2461
2462         u8         reserved_at_8[0x4];
2463         u8         prio[0x4];
2464         u8         reserved_at_10[0x10];
2465
2466         u8         reserved_at_20[0x100];
2467
2468         u8         reserved_at_120[0x8];
2469         u8         transport_domain[0x18];
2470
2471         u8         reserved_at_140[0x8];
2472         u8         underlay_qpn[0x18];
2473         u8         reserved_at_160[0x3a0];
2474 };
2475
2476 enum {
2477         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2478         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2479 };
2480
2481 enum {
2482         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2483         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2484 };
2485
2486 enum {
2487         MLX5_RX_HASH_FN_NONE           = 0x0,
2488         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2489         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2490 };
2491
2492 enum {
2493         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2494         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2495 };
2496
2497 struct mlx5_ifc_tirc_bits {
2498         u8         reserved_at_0[0x20];
2499
2500         u8         disp_type[0x4];
2501         u8         reserved_at_24[0x1c];
2502
2503         u8         reserved_at_40[0x40];
2504
2505         u8         reserved_at_80[0x4];
2506         u8         lro_timeout_period_usecs[0x10];
2507         u8         lro_enable_mask[0x4];
2508         u8         lro_max_ip_payload_size[0x8];
2509
2510         u8         reserved_at_a0[0x40];
2511
2512         u8         reserved_at_e0[0x8];
2513         u8         inline_rqn[0x18];
2514
2515         u8         rx_hash_symmetric[0x1];
2516         u8         reserved_at_101[0x1];
2517         u8         tunneled_offload_en[0x1];
2518         u8         reserved_at_103[0x5];
2519         u8         indirect_table[0x18];
2520
2521         u8         rx_hash_fn[0x4];
2522         u8         reserved_at_124[0x2];
2523         u8         self_lb_block[0x2];
2524         u8         transport_domain[0x18];
2525
2526         u8         rx_hash_toeplitz_key[10][0x20];
2527
2528         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2529
2530         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2531
2532         u8         reserved_at_2c0[0x4c0];
2533 };
2534
2535 enum {
2536         MLX5_SRQC_STATE_GOOD   = 0x0,
2537         MLX5_SRQC_STATE_ERROR  = 0x1,
2538 };
2539
2540 struct mlx5_ifc_srqc_bits {
2541         u8         state[0x4];
2542         u8         log_srq_size[0x4];
2543         u8         reserved_at_8[0x18];
2544
2545         u8         wq_signature[0x1];
2546         u8         cont_srq[0x1];
2547         u8         reserved_at_22[0x1];
2548         u8         rlky[0x1];
2549         u8         reserved_at_24[0x1];
2550         u8         log_rq_stride[0x3];
2551         u8         xrcd[0x18];
2552
2553         u8         page_offset[0x6];
2554         u8         reserved_at_46[0x2];
2555         u8         cqn[0x18];
2556
2557         u8         reserved_at_60[0x20];
2558
2559         u8         reserved_at_80[0x2];
2560         u8         log_page_size[0x6];
2561         u8         reserved_at_88[0x18];
2562
2563         u8         reserved_at_a0[0x20];
2564
2565         u8         reserved_at_c0[0x8];
2566         u8         pd[0x18];
2567
2568         u8         lwm[0x10];
2569         u8         wqe_cnt[0x10];
2570
2571         u8         reserved_at_100[0x40];
2572
2573         u8         dbr_addr[0x40];
2574
2575         u8         reserved_at_180[0x80];
2576 };
2577
2578 enum {
2579         MLX5_SQC_STATE_RST  = 0x0,
2580         MLX5_SQC_STATE_RDY  = 0x1,
2581         MLX5_SQC_STATE_ERR  = 0x3,
2582 };
2583
2584 struct mlx5_ifc_sqc_bits {
2585         u8         rlky[0x1];
2586         u8         cd_master[0x1];
2587         u8         fre[0x1];
2588         u8         flush_in_error_en[0x1];
2589         u8         allow_multi_pkt_send_wqe[0x1];
2590         u8         min_wqe_inline_mode[0x3];
2591         u8         state[0x4];
2592         u8         reg_umr[0x1];
2593         u8         allow_swp[0x1];
2594         u8         hairpin[0x1];
2595         u8         reserved_at_f[0x11];
2596
2597         u8         reserved_at_20[0x8];
2598         u8         user_index[0x18];
2599
2600         u8         reserved_at_40[0x8];
2601         u8         cqn[0x18];
2602
2603         u8         reserved_at_60[0x8];
2604         u8         hairpin_peer_rq[0x18];
2605
2606         u8         reserved_at_80[0x10];
2607         u8         hairpin_peer_vhca[0x10];
2608
2609         u8         reserved_at_a0[0x50];
2610
2611         u8         packet_pacing_rate_limit_index[0x10];
2612         u8         tis_lst_sz[0x10];
2613         u8         reserved_at_110[0x10];
2614
2615         u8         reserved_at_120[0x40];
2616
2617         u8         reserved_at_160[0x8];
2618         u8         tis_num_0[0x18];
2619
2620         struct mlx5_ifc_wq_bits wq;
2621 };
2622
2623 enum {
2624         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2625         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2626         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2627         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2628 };
2629
2630 struct mlx5_ifc_scheduling_context_bits {
2631         u8         element_type[0x8];
2632         u8         reserved_at_8[0x18];
2633
2634         u8         element_attributes[0x20];
2635
2636         u8         parent_element_id[0x20];
2637
2638         u8         reserved_at_60[0x40];
2639
2640         u8         bw_share[0x20];
2641
2642         u8         max_average_bw[0x20];
2643
2644         u8         reserved_at_e0[0x120];
2645 };
2646
2647 struct mlx5_ifc_rqtc_bits {
2648         u8         reserved_at_0[0xa0];
2649
2650         u8         reserved_at_a0[0x10];
2651         u8         rqt_max_size[0x10];
2652
2653         u8         reserved_at_c0[0x10];
2654         u8         rqt_actual_size[0x10];
2655
2656         u8         reserved_at_e0[0x6a0];
2657
2658         struct mlx5_ifc_rq_num_bits rq_num[0];
2659 };
2660
2661 enum {
2662         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2663         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2664 };
2665
2666 enum {
2667         MLX5_RQC_STATE_RST  = 0x0,
2668         MLX5_RQC_STATE_RDY  = 0x1,
2669         MLX5_RQC_STATE_ERR  = 0x3,
2670 };
2671
2672 struct mlx5_ifc_rqc_bits {
2673         u8         rlky[0x1];
2674         u8         delay_drop_en[0x1];
2675         u8         scatter_fcs[0x1];
2676         u8         vsd[0x1];
2677         u8         mem_rq_type[0x4];
2678         u8         state[0x4];
2679         u8         reserved_at_c[0x1];
2680         u8         flush_in_error_en[0x1];
2681         u8         hairpin[0x1];
2682         u8         reserved_at_f[0x11];
2683
2684         u8         reserved_at_20[0x8];
2685         u8         user_index[0x18];
2686
2687         u8         reserved_at_40[0x8];
2688         u8         cqn[0x18];
2689
2690         u8         counter_set_id[0x8];
2691         u8         reserved_at_68[0x18];
2692
2693         u8         reserved_at_80[0x8];
2694         u8         rmpn[0x18];
2695
2696         u8         reserved_at_a0[0x8];
2697         u8         hairpin_peer_sq[0x18];
2698
2699         u8         reserved_at_c0[0x10];
2700         u8         hairpin_peer_vhca[0x10];
2701
2702         u8         reserved_at_e0[0xa0];
2703
2704         struct mlx5_ifc_wq_bits wq;
2705 };
2706
2707 enum {
2708         MLX5_RMPC_STATE_RDY  = 0x1,
2709         MLX5_RMPC_STATE_ERR  = 0x3,
2710 };
2711
2712 struct mlx5_ifc_rmpc_bits {
2713         u8         reserved_at_0[0x8];
2714         u8         state[0x4];
2715         u8         reserved_at_c[0x14];
2716
2717         u8         basic_cyclic_rcv_wqe[0x1];
2718         u8         reserved_at_21[0x1f];
2719
2720         u8         reserved_at_40[0x140];
2721
2722         struct mlx5_ifc_wq_bits wq;
2723 };
2724
2725 struct mlx5_ifc_nic_vport_context_bits {
2726         u8         reserved_at_0[0x5];
2727         u8         min_wqe_inline_mode[0x3];
2728         u8         reserved_at_8[0x15];
2729         u8         disable_mc_local_lb[0x1];
2730         u8         disable_uc_local_lb[0x1];
2731         u8         roce_en[0x1];
2732
2733         u8         arm_change_event[0x1];
2734         u8         reserved_at_21[0x1a];
2735         u8         event_on_mtu[0x1];
2736         u8         event_on_promisc_change[0x1];
2737         u8         event_on_vlan_change[0x1];
2738         u8         event_on_mc_address_change[0x1];
2739         u8         event_on_uc_address_change[0x1];
2740
2741         u8         reserved_at_40[0xc];
2742
2743         u8         affiliation_criteria[0x4];
2744         u8         affiliated_vhca_id[0x10];
2745
2746         u8         reserved_at_60[0xd0];
2747
2748         u8         mtu[0x10];
2749
2750         u8         system_image_guid[0x40];
2751         u8         port_guid[0x40];
2752         u8         node_guid[0x40];
2753
2754         u8         reserved_at_200[0x140];
2755         u8         qkey_violation_counter[0x10];
2756         u8         reserved_at_350[0x430];
2757
2758         u8         promisc_uc[0x1];
2759         u8         promisc_mc[0x1];
2760         u8         promisc_all[0x1];
2761         u8         reserved_at_783[0x2];
2762         u8         allowed_list_type[0x3];
2763         u8         reserved_at_788[0xc];
2764         u8         allowed_list_size[0xc];
2765
2766         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2767
2768         u8         reserved_at_7e0[0x20];
2769
2770         u8         current_uc_mac_address[0][0x40];
2771 };
2772
2773 enum {
2774         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2775         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2776         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2777         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2778         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2779 };
2780
2781 struct mlx5_ifc_mkc_bits {
2782         u8         reserved_at_0[0x1];
2783         u8         free[0x1];
2784         u8         reserved_at_2[0x1];
2785         u8         access_mode_4_2[0x3];
2786         u8         reserved_at_6[0x7];
2787         u8         relaxed_ordering_write[0x1];
2788         u8         reserved_at_e[0x1];
2789         u8         small_fence_on_rdma_read_response[0x1];
2790         u8         umr_en[0x1];
2791         u8         a[0x1];
2792         u8         rw[0x1];
2793         u8         rr[0x1];
2794         u8         lw[0x1];
2795         u8         lr[0x1];
2796         u8         access_mode_1_0[0x2];
2797         u8         reserved_at_18[0x8];
2798
2799         u8         qpn[0x18];
2800         u8         mkey_7_0[0x8];
2801
2802         u8         reserved_at_40[0x20];
2803
2804         u8         length64[0x1];
2805         u8         bsf_en[0x1];
2806         u8         sync_umr[0x1];
2807         u8         reserved_at_63[0x2];
2808         u8         expected_sigerr_count[0x1];
2809         u8         reserved_at_66[0x1];
2810         u8         en_rinval[0x1];
2811         u8         pd[0x18];
2812
2813         u8         start_addr[0x40];
2814
2815         u8         len[0x40];
2816
2817         u8         bsf_octword_size[0x20];
2818
2819         u8         reserved_at_120[0x80];
2820
2821         u8         translations_octword_size[0x20];
2822
2823         u8         reserved_at_1c0[0x1b];
2824         u8         log_page_size[0x5];
2825
2826         u8         reserved_at_1e0[0x20];
2827 };
2828
2829 struct mlx5_ifc_pkey_bits {
2830         u8         reserved_at_0[0x10];
2831         u8         pkey[0x10];
2832 };
2833
2834 struct mlx5_ifc_array128_auto_bits {
2835         u8         array128_auto[16][0x8];
2836 };
2837
2838 struct mlx5_ifc_hca_vport_context_bits {
2839         u8         field_select[0x20];
2840
2841         u8         reserved_at_20[0xe0];
2842
2843         u8         sm_virt_aware[0x1];
2844         u8         has_smi[0x1];
2845         u8         has_raw[0x1];
2846         u8         grh_required[0x1];
2847         u8         reserved_at_104[0xc];
2848         u8         port_physical_state[0x4];
2849         u8         vport_state_policy[0x4];
2850         u8         port_state[0x4];
2851         u8         vport_state[0x4];
2852
2853         u8         reserved_at_120[0x20];
2854
2855         u8         system_image_guid[0x40];
2856
2857         u8         port_guid[0x40];
2858
2859         u8         node_guid[0x40];
2860
2861         u8         cap_mask1[0x20];
2862
2863         u8         cap_mask1_field_select[0x20];
2864
2865         u8         cap_mask2[0x20];
2866
2867         u8         cap_mask2_field_select[0x20];
2868
2869         u8         reserved_at_280[0x80];
2870
2871         u8         lid[0x10];
2872         u8         reserved_at_310[0x4];
2873         u8         init_type_reply[0x4];
2874         u8         lmc[0x3];
2875         u8         subnet_timeout[0x5];
2876
2877         u8         sm_lid[0x10];
2878         u8         sm_sl[0x4];
2879         u8         reserved_at_334[0xc];
2880
2881         u8         qkey_violation_counter[0x10];
2882         u8         pkey_violation_counter[0x10];
2883
2884         u8         reserved_at_360[0xca0];
2885 };
2886
2887 struct mlx5_ifc_esw_vport_context_bits {
2888         u8         reserved_at_0[0x3];
2889         u8         vport_svlan_strip[0x1];
2890         u8         vport_cvlan_strip[0x1];
2891         u8         vport_svlan_insert[0x1];
2892         u8         vport_cvlan_insert[0x2];
2893         u8         reserved_at_8[0x18];
2894
2895         u8         reserved_at_20[0x20];
2896
2897         u8         svlan_cfi[0x1];
2898         u8         svlan_pcp[0x3];
2899         u8         svlan_id[0xc];
2900         u8         cvlan_cfi[0x1];
2901         u8         cvlan_pcp[0x3];
2902         u8         cvlan_id[0xc];
2903
2904         u8         reserved_at_60[0x7a0];
2905 };
2906
2907 enum {
2908         MLX5_EQC_STATUS_OK                = 0x0,
2909         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2910 };
2911
2912 enum {
2913         MLX5_EQC_ST_ARMED  = 0x9,
2914         MLX5_EQC_ST_FIRED  = 0xa,
2915 };
2916
2917 struct mlx5_ifc_eqc_bits {
2918         u8         status[0x4];
2919         u8         reserved_at_4[0x9];
2920         u8         ec[0x1];
2921         u8         oi[0x1];
2922         u8         reserved_at_f[0x5];
2923         u8         st[0x4];
2924         u8         reserved_at_18[0x8];
2925
2926         u8         reserved_at_20[0x20];
2927
2928         u8         reserved_at_40[0x14];
2929         u8         page_offset[0x6];
2930         u8         reserved_at_5a[0x6];
2931
2932         u8         reserved_at_60[0x3];
2933         u8         log_eq_size[0x5];
2934         u8         uar_page[0x18];
2935
2936         u8         reserved_at_80[0x20];
2937
2938         u8         reserved_at_a0[0x18];
2939         u8         intr[0x8];
2940
2941         u8         reserved_at_c0[0x3];
2942         u8         log_page_size[0x5];
2943         u8         reserved_at_c8[0x18];
2944
2945         u8         reserved_at_e0[0x60];
2946
2947         u8         reserved_at_140[0x8];
2948         u8         consumer_counter[0x18];
2949
2950         u8         reserved_at_160[0x8];
2951         u8         producer_counter[0x18];
2952
2953         u8         reserved_at_180[0x80];
2954 };
2955
2956 enum {
2957         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2958         MLX5_DCTC_STATE_DRAINING  = 0x1,
2959         MLX5_DCTC_STATE_DRAINED   = 0x2,
2960 };
2961
2962 enum {
2963         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2964         MLX5_DCTC_CS_RES_NA         = 0x1,
2965         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2966 };
2967
2968 enum {
2969         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2970         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2971         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2972         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2973         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2974 };
2975
2976 struct mlx5_ifc_dctc_bits {
2977         u8         reserved_at_0[0x4];
2978         u8         state[0x4];
2979         u8         reserved_at_8[0x18];
2980
2981         u8         reserved_at_20[0x8];
2982         u8         user_index[0x18];
2983
2984         u8         reserved_at_40[0x8];
2985         u8         cqn[0x18];
2986
2987         u8         counter_set_id[0x8];
2988         u8         atomic_mode[0x4];
2989         u8         rre[0x1];
2990         u8         rwe[0x1];
2991         u8         rae[0x1];
2992         u8         atomic_like_write_en[0x1];
2993         u8         latency_sensitive[0x1];
2994         u8         rlky[0x1];
2995         u8         free_ar[0x1];
2996         u8         reserved_at_73[0xd];
2997
2998         u8         reserved_at_80[0x8];
2999         u8         cs_res[0x8];
3000         u8         reserved_at_90[0x3];
3001         u8         min_rnr_nak[0x5];
3002         u8         reserved_at_98[0x8];
3003
3004         u8         reserved_at_a0[0x8];
3005         u8         srqn_xrqn[0x18];
3006
3007         u8         reserved_at_c0[0x8];
3008         u8         pd[0x18];
3009
3010         u8         tclass[0x8];
3011         u8         reserved_at_e8[0x4];
3012         u8         flow_label[0x14];
3013
3014         u8         dc_access_key[0x40];
3015
3016         u8         reserved_at_140[0x5];
3017         u8         mtu[0x3];
3018         u8         port[0x8];
3019         u8         pkey_index[0x10];
3020
3021         u8         reserved_at_160[0x8];
3022         u8         my_addr_index[0x8];
3023         u8         reserved_at_170[0x8];
3024         u8         hop_limit[0x8];
3025
3026         u8         dc_access_key_violation_count[0x20];
3027
3028         u8         reserved_at_1a0[0x14];
3029         u8         dei_cfi[0x1];
3030         u8         eth_prio[0x3];
3031         u8         ecn[0x2];
3032         u8         dscp[0x6];
3033
3034         u8         reserved_at_1c0[0x40];
3035 };
3036
3037 enum {
3038         MLX5_CQC_STATUS_OK             = 0x0,
3039         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3040         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3041 };
3042
3043 enum {
3044         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3045         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3046 };
3047
3048 enum {
3049         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3050         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3051         MLX5_CQC_ST_FIRED                                 = 0xa,
3052 };
3053
3054 enum {
3055         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3056         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3057         MLX5_CQ_PERIOD_NUM_MODES
3058 };
3059
3060 struct mlx5_ifc_cqc_bits {
3061         u8         status[0x4];
3062         u8         reserved_at_4[0x4];
3063         u8         cqe_sz[0x3];
3064         u8         cc[0x1];
3065         u8         reserved_at_c[0x1];
3066         u8         scqe_break_moderation_en[0x1];
3067         u8         oi[0x1];
3068         u8         cq_period_mode[0x2];
3069         u8         cqe_comp_en[0x1];
3070         u8         mini_cqe_res_format[0x2];
3071         u8         st[0x4];
3072         u8         reserved_at_18[0x8];
3073
3074         u8         reserved_at_20[0x20];
3075
3076         u8         reserved_at_40[0x14];
3077         u8         page_offset[0x6];
3078         u8         reserved_at_5a[0x6];
3079
3080         u8         reserved_at_60[0x3];
3081         u8         log_cq_size[0x5];
3082         u8         uar_page[0x18];
3083
3084         u8         reserved_at_80[0x4];
3085         u8         cq_period[0xc];
3086         u8         cq_max_count[0x10];
3087
3088         u8         reserved_at_a0[0x18];
3089         u8         c_eqn[0x8];
3090
3091         u8         reserved_at_c0[0x3];
3092         u8         log_page_size[0x5];
3093         u8         reserved_at_c8[0x18];
3094
3095         u8         reserved_at_e0[0x20];
3096
3097         u8         reserved_at_100[0x8];
3098         u8         last_notified_index[0x18];
3099
3100         u8         reserved_at_120[0x8];
3101         u8         last_solicit_index[0x18];
3102
3103         u8         reserved_at_140[0x8];
3104         u8         consumer_counter[0x18];
3105
3106         u8         reserved_at_160[0x8];
3107         u8         producer_counter[0x18];
3108
3109         u8         reserved_at_180[0x40];
3110
3111         u8         dbr_addr[0x40];
3112 };
3113
3114 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3115         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3116         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3117         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3118         u8         reserved_at_0[0x800];
3119 };
3120
3121 struct mlx5_ifc_query_adapter_param_block_bits {
3122         u8         reserved_at_0[0xc0];
3123
3124         u8         reserved_at_c0[0x8];
3125         u8         ieee_vendor_id[0x18];
3126
3127         u8         reserved_at_e0[0x10];
3128         u8         vsd_vendor_id[0x10];
3129
3130         u8         vsd[208][0x8];
3131
3132         u8         vsd_contd_psid[16][0x8];
3133 };
3134
3135 enum {
3136         MLX5_XRQC_STATE_GOOD   = 0x0,
3137         MLX5_XRQC_STATE_ERROR  = 0x1,
3138 };
3139
3140 enum {
3141         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3142         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3143 };
3144
3145 enum {
3146         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3147 };
3148
3149 struct mlx5_ifc_tag_matching_topology_context_bits {
3150         u8         log_matching_list_sz[0x4];
3151         u8         reserved_at_4[0xc];
3152         u8         append_next_index[0x10];
3153
3154         u8         sw_phase_cnt[0x10];
3155         u8         hw_phase_cnt[0x10];
3156
3157         u8         reserved_at_40[0x40];
3158 };
3159
3160 struct mlx5_ifc_xrqc_bits {
3161         u8         state[0x4];
3162         u8         rlkey[0x1];
3163         u8         reserved_at_5[0xf];
3164         u8         topology[0x4];
3165         u8         reserved_at_18[0x4];
3166         u8         offload[0x4];
3167
3168         u8         reserved_at_20[0x8];
3169         u8         user_index[0x18];
3170
3171         u8         reserved_at_40[0x8];
3172         u8         cqn[0x18];
3173
3174         u8         reserved_at_60[0xa0];
3175
3176         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3177
3178         u8         reserved_at_180[0x280];
3179
3180         struct mlx5_ifc_wq_bits wq;
3181 };
3182
3183 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3184         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3185         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3186         u8         reserved_at_0[0x20];
3187 };
3188
3189 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3190         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3191         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3192         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3193         u8         reserved_at_0[0x20];
3194 };
3195
3196 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3197         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3198         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3199         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3200         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3201         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3202         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3203         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3204         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3205         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3206         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3207         u8         reserved_at_0[0x7c0];
3208 };
3209
3210 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3211         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3212         u8         reserved_at_0[0x7c0];
3213 };
3214
3215 union mlx5_ifc_event_auto_bits {
3216         struct mlx5_ifc_comp_event_bits comp_event;
3217         struct mlx5_ifc_dct_events_bits dct_events;
3218         struct mlx5_ifc_qp_events_bits qp_events;
3219         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3220         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3221         struct mlx5_ifc_cq_error_bits cq_error;
3222         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3223         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3224         struct mlx5_ifc_gpio_event_bits gpio_event;
3225         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3226         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3227         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3228         u8         reserved_at_0[0xe0];
3229 };
3230
3231 struct mlx5_ifc_health_buffer_bits {
3232         u8         reserved_at_0[0x100];
3233
3234         u8         assert_existptr[0x20];
3235
3236         u8         assert_callra[0x20];
3237
3238         u8         reserved_at_140[0x40];
3239
3240         u8         fw_version[0x20];
3241
3242         u8         hw_id[0x20];
3243
3244         u8         reserved_at_1c0[0x20];
3245
3246         u8         irisc_index[0x8];
3247         u8         synd[0x8];
3248         u8         ext_synd[0x10];
3249 };
3250
3251 struct mlx5_ifc_register_loopback_control_bits {
3252         u8         no_lb[0x1];
3253         u8         reserved_at_1[0x7];
3254         u8         port[0x8];
3255         u8         reserved_at_10[0x10];
3256
3257         u8         reserved_at_20[0x60];
3258 };
3259
3260 struct mlx5_ifc_vport_tc_element_bits {
3261         u8         traffic_class[0x4];
3262         u8         reserved_at_4[0xc];
3263         u8         vport_number[0x10];
3264 };
3265
3266 struct mlx5_ifc_vport_element_bits {
3267         u8         reserved_at_0[0x10];
3268         u8         vport_number[0x10];
3269 };
3270
3271 enum {
3272         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3273         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3274         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3275 };
3276
3277 struct mlx5_ifc_tsar_element_bits {
3278         u8         reserved_at_0[0x8];
3279         u8         tsar_type[0x8];
3280         u8         reserved_at_10[0x10];
3281 };
3282
3283 enum {
3284         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3285         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3286 };
3287
3288 struct mlx5_ifc_teardown_hca_out_bits {
3289         u8         status[0x8];
3290         u8         reserved_at_8[0x18];
3291
3292         u8         syndrome[0x20];
3293
3294         u8         reserved_at_40[0x3f];
3295
3296         u8         force_state[0x1];
3297 };
3298
3299 enum {
3300         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3301         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3302 };
3303
3304 struct mlx5_ifc_teardown_hca_in_bits {
3305         u8         opcode[0x10];
3306         u8         reserved_at_10[0x10];
3307
3308         u8         reserved_at_20[0x10];
3309         u8         op_mod[0x10];
3310
3311         u8         reserved_at_40[0x10];
3312         u8         profile[0x10];
3313
3314         u8         reserved_at_60[0x20];
3315 };
3316
3317 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3318         u8         status[0x8];
3319         u8         reserved_at_8[0x18];
3320
3321         u8         syndrome[0x20];
3322
3323         u8         reserved_at_40[0x40];
3324 };
3325
3326 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3327         u8         opcode[0x10];
3328         u8         reserved_at_10[0x10];
3329
3330         u8         reserved_at_20[0x10];
3331         u8         op_mod[0x10];
3332
3333         u8         reserved_at_40[0x8];
3334         u8         qpn[0x18];
3335
3336         u8         reserved_at_60[0x20];
3337
3338         u8         opt_param_mask[0x20];
3339
3340         u8         reserved_at_a0[0x20];
3341
3342         struct mlx5_ifc_qpc_bits qpc;
3343
3344         u8         reserved_at_800[0x80];
3345 };
3346
3347 struct mlx5_ifc_sqd2rts_qp_out_bits {
3348         u8         status[0x8];
3349         u8         reserved_at_8[0x18];
3350
3351         u8         syndrome[0x20];
3352
3353         u8         reserved_at_40[0x40];
3354 };
3355
3356 struct mlx5_ifc_sqd2rts_qp_in_bits {
3357         u8         opcode[0x10];
3358         u8         reserved_at_10[0x10];
3359
3360         u8         reserved_at_20[0x10];
3361         u8         op_mod[0x10];
3362
3363         u8         reserved_at_40[0x8];
3364         u8         qpn[0x18];
3365
3366         u8         reserved_at_60[0x20];
3367
3368         u8         opt_param_mask[0x20];
3369
3370         u8         reserved_at_a0[0x20];
3371
3372         struct mlx5_ifc_qpc_bits qpc;
3373
3374         u8         reserved_at_800[0x80];
3375 };
3376
3377 struct mlx5_ifc_set_roce_address_out_bits {
3378         u8         status[0x8];
3379         u8         reserved_at_8[0x18];
3380
3381         u8         syndrome[0x20];
3382
3383         u8         reserved_at_40[0x40];
3384 };
3385
3386 struct mlx5_ifc_set_roce_address_in_bits {
3387         u8         opcode[0x10];
3388         u8         reserved_at_10[0x10];
3389
3390         u8         reserved_at_20[0x10];
3391         u8         op_mod[0x10];
3392
3393         u8         roce_address_index[0x10];
3394         u8         reserved_at_50[0xc];
3395         u8         vhca_port_num[0x4];
3396
3397         u8         reserved_at_60[0x20];
3398
3399         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3400 };
3401
3402 struct mlx5_ifc_set_mad_demux_out_bits {
3403         u8         status[0x8];
3404         u8         reserved_at_8[0x18];
3405
3406         u8         syndrome[0x20];
3407
3408         u8         reserved_at_40[0x40];
3409 };
3410
3411 enum {
3412         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3413         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3414 };
3415
3416 struct mlx5_ifc_set_mad_demux_in_bits {
3417         u8         opcode[0x10];
3418         u8         reserved_at_10[0x10];
3419
3420         u8         reserved_at_20[0x10];
3421         u8         op_mod[0x10];
3422
3423         u8         reserved_at_40[0x20];
3424
3425         u8         reserved_at_60[0x6];
3426         u8         demux_mode[0x2];
3427         u8         reserved_at_68[0x18];
3428 };
3429
3430 struct mlx5_ifc_set_l2_table_entry_out_bits {
3431         u8         status[0x8];
3432         u8         reserved_at_8[0x18];
3433
3434         u8         syndrome[0x20];
3435
3436         u8         reserved_at_40[0x40];
3437 };
3438
3439 struct mlx5_ifc_set_l2_table_entry_in_bits {
3440         u8         opcode[0x10];