cd1c3b282657f2ec59ecc0b80401761a1a0c8a08
[muen/linux.git] / sound / hda / hdac_controller.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * HD-audio controller helpers
4  */
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <sound/core.h>
10 #include <sound/hdaudio.h>
11 #include <sound/hda_register.h>
12
13 /* clear CORB read pointer properly */
14 static void azx_clear_corbrp(struct hdac_bus *bus)
15 {
16         int timeout;
17
18         for (timeout = 1000; timeout > 0; timeout--) {
19                 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
20                         break;
21                 udelay(1);
22         }
23         if (timeout <= 0)
24                 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
25                         snd_hdac_chip_readw(bus, CORBRP));
26
27         snd_hdac_chip_writew(bus, CORBRP, 0);
28         for (timeout = 1000; timeout > 0; timeout--) {
29                 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
30                         break;
31                 udelay(1);
32         }
33         if (timeout <= 0)
34                 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
35                         snd_hdac_chip_readw(bus, CORBRP));
36 }
37
38 /**
39  * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
40  * @bus: HD-audio core bus
41  */
42 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
43 {
44         WARN_ON_ONCE(!bus->rb.area);
45
46         spin_lock_irq(&bus->reg_lock);
47         /* CORB set up */
48         bus->corb.addr = bus->rb.addr;
49         bus->corb.buf = (__le32 *)bus->rb.area;
50         snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
51         snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
52
53         /* set the corb size to 256 entries (ULI requires explicitly) */
54         snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
55         /* set the corb write pointer to 0 */
56         snd_hdac_chip_writew(bus, CORBWP, 0);
57
58         /* reset the corb hw read pointer */
59         snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
60         if (!bus->corbrp_self_clear)
61                 azx_clear_corbrp(bus);
62
63         /* enable corb dma */
64         snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
65
66         /* RIRB set up */
67         bus->rirb.addr = bus->rb.addr + 2048;
68         bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
69         bus->rirb.wp = bus->rirb.rp = 0;
70         memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
71         snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
72         snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
73
74         /* set the rirb size to 256 entries (ULI requires explicitly) */
75         snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
76         /* reset the rirb hw write pointer */
77         snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
78         /* set N=1, get RIRB response interrupt for new entry */
79         snd_hdac_chip_writew(bus, RINTCNT, 1);
80         /* enable rirb dma and response irq */
81         snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
82         /* Accept unsolicited responses */
83         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
84         spin_unlock_irq(&bus->reg_lock);
85 }
86 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
87
88 /* wait for cmd dmas till they are stopped */
89 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
90 {
91         unsigned long timeout;
92
93         timeout = jiffies + msecs_to_jiffies(100);
94         while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
95                 && time_before(jiffies, timeout))
96                 udelay(10);
97
98         timeout = jiffies + msecs_to_jiffies(100);
99         while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
100                 && time_before(jiffies, timeout))
101                 udelay(10);
102 }
103
104 /**
105  * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
106  * @bus: HD-audio core bus
107  */
108 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
109 {
110         spin_lock_irq(&bus->reg_lock);
111         /* disable ringbuffer DMAs */
112         snd_hdac_chip_writeb(bus, RIRBCTL, 0);
113         snd_hdac_chip_writeb(bus, CORBCTL, 0);
114         spin_unlock_irq(&bus->reg_lock);
115
116         hdac_wait_for_cmd_dmas(bus);
117
118         spin_lock_irq(&bus->reg_lock);
119         /* disable unsolicited responses */
120         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
121         spin_unlock_irq(&bus->reg_lock);
122 }
123 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
124
125 static unsigned int azx_command_addr(u32 cmd)
126 {
127         unsigned int addr = cmd >> 28;
128
129         if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
130                 addr = 0;
131         return addr;
132 }
133
134 /**
135  * snd_hdac_bus_send_cmd - send a command verb via CORB
136  * @bus: HD-audio core bus
137  * @val: encoded verb value to send
138  *
139  * Returns zero for success or a negative error code.
140  */
141 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
142 {
143         unsigned int addr = azx_command_addr(val);
144         unsigned int wp, rp;
145
146         spin_lock_irq(&bus->reg_lock);
147
148         bus->last_cmd[azx_command_addr(val)] = val;
149
150         /* add command to corb */
151         wp = snd_hdac_chip_readw(bus, CORBWP);
152         if (wp == 0xffff) {
153                 /* something wrong, controller likely turned to D3 */
154                 spin_unlock_irq(&bus->reg_lock);
155                 return -EIO;
156         }
157         wp++;
158         wp %= AZX_MAX_CORB_ENTRIES;
159
160         rp = snd_hdac_chip_readw(bus, CORBRP);
161         if (wp == rp) {
162                 /* oops, it's full */
163                 spin_unlock_irq(&bus->reg_lock);
164                 return -EAGAIN;
165         }
166
167         bus->rirb.cmds[addr]++;
168         bus->corb.buf[wp] = cpu_to_le32(val);
169         snd_hdac_chip_writew(bus, CORBWP, wp);
170
171         spin_unlock_irq(&bus->reg_lock);
172
173         return 0;
174 }
175 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
176
177 #define AZX_RIRB_EX_UNSOL_EV    (1<<4)
178
179 /**
180  * snd_hdac_bus_update_rirb - retrieve RIRB entries
181  * @bus: HD-audio core bus
182  *
183  * Usually called from interrupt handler.
184  */
185 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
186 {
187         unsigned int rp, wp;
188         unsigned int addr;
189         u32 res, res_ex;
190
191         wp = snd_hdac_chip_readw(bus, RIRBWP);
192         if (wp == 0xffff) {
193                 /* something wrong, controller likely turned to D3 */
194                 return;
195         }
196
197         if (wp == bus->rirb.wp)
198                 return;
199         bus->rirb.wp = wp;
200
201         while (bus->rirb.rp != wp) {
202                 bus->rirb.rp++;
203                 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
204
205                 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
206                 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
207                 res = le32_to_cpu(bus->rirb.buf[rp]);
208                 addr = res_ex & 0xf;
209                 if (addr >= HDA_MAX_CODECS) {
210                         dev_err(bus->dev,
211                                 "spurious response %#x:%#x, rp = %d, wp = %d",
212                                 res, res_ex, bus->rirb.rp, wp);
213                         snd_BUG();
214                 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
215                         snd_hdac_bus_queue_event(bus, res, res_ex);
216                 else if (bus->rirb.cmds[addr]) {
217                         bus->rirb.res[addr] = res;
218                         bus->rirb.cmds[addr]--;
219                         if (!bus->rirb.cmds[addr] &&
220                             waitqueue_active(&bus->rirb_wq))
221                                 wake_up(&bus->rirb_wq);
222                 } else {
223                         dev_err_ratelimited(bus->dev,
224                                 "spurious response %#x:%#x, last cmd=%#08x\n",
225                                 res, res_ex, bus->last_cmd[addr]);
226                 }
227         }
228 }
229 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
230
231 /**
232  * snd_hdac_bus_get_response - receive a response via RIRB
233  * @bus: HD-audio core bus
234  * @addr: codec address
235  * @res: pointer to store the value, NULL when not needed
236  *
237  * Returns zero if a value is read, or a negative error code.
238  */
239 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
240                               unsigned int *res)
241 {
242         unsigned long timeout;
243         unsigned long loopcounter;
244
245         timeout = jiffies + msecs_to_jiffies(1000);
246
247         for (loopcounter = 0;; loopcounter++) {
248                 spin_lock_irq(&bus->reg_lock);
249                 if (bus->polling_mode)
250                         snd_hdac_bus_update_rirb(bus);
251                 if (!bus->rirb.cmds[addr]) {
252                         if (res)
253                                 *res = bus->rirb.res[addr]; /* the last value */
254                         spin_unlock_irq(&bus->reg_lock);
255                         return 0;
256                 }
257                 spin_unlock_irq(&bus->reg_lock);
258                 if (time_after(jiffies, timeout))
259                         break;
260                 if (loopcounter > 3000)
261                         msleep(2); /* temporary workaround */
262                 else {
263                         udelay(10);
264                         cond_resched();
265                 }
266         }
267
268         return -EIO;
269 }
270 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
271
272 #define HDAC_MAX_CAPS 10
273 /**
274  * snd_hdac_bus_parse_capabilities - parse capability structure
275  * @bus: the pointer to bus object
276  *
277  * Returns 0 if successful, or a negative error code.
278  */
279 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
280 {
281         unsigned int cur_cap;
282         unsigned int offset;
283         unsigned int counter = 0;
284
285         offset = snd_hdac_chip_readw(bus, LLCH);
286
287         /* Lets walk the linked capabilities list */
288         do {
289                 cur_cap = _snd_hdac_chip_readl(bus, offset);
290
291                 dev_dbg(bus->dev, "Capability version: 0x%x\n",
292                         (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
293
294                 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
295                         (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
296
297                 if (cur_cap == -1) {
298                         dev_dbg(bus->dev, "Invalid capability reg read\n");
299                         break;
300                 }
301
302                 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
303                 case AZX_ML_CAP_ID:
304                         dev_dbg(bus->dev, "Found ML capability\n");
305                         bus->mlcap = bus->remap_addr + offset;
306                         break;
307
308                 case AZX_GTS_CAP_ID:
309                         dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
310                         bus->gtscap = bus->remap_addr + offset;
311                         break;
312
313                 case AZX_PP_CAP_ID:
314                         /* PP capability found, the Audio DSP is present */
315                         dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
316                         bus->ppcap = bus->remap_addr + offset;
317                         break;
318
319                 case AZX_SPB_CAP_ID:
320                         /* SPIB capability found, handler function */
321                         dev_dbg(bus->dev, "Found SPB capability\n");
322                         bus->spbcap = bus->remap_addr + offset;
323                         break;
324
325                 case AZX_DRSM_CAP_ID:
326                         /* DMA resume  capability found, handler function */
327                         dev_dbg(bus->dev, "Found DRSM capability\n");
328                         bus->drsmcap = bus->remap_addr + offset;
329                         break;
330
331                 default:
332                         dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
333                         cur_cap = 0;
334                         break;
335                 }
336
337                 counter++;
338
339                 if (counter > HDAC_MAX_CAPS) {
340                         dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
341                         break;
342                 }
343
344                 /* read the offset of next capability */
345                 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
346
347         } while (offset);
348
349         return 0;
350 }
351 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
352
353 /*
354  * Lowlevel interface
355  */
356
357 /**
358  * snd_hdac_bus_enter_link_reset - enter link reset
359  * @bus: HD-audio core bus
360  *
361  * Enter to the link reset state.
362  */
363 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
364 {
365         unsigned long timeout;
366
367         /* reset controller */
368         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
369
370         timeout = jiffies + msecs_to_jiffies(100);
371         while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
372                time_before(jiffies, timeout))
373                 usleep_range(500, 1000);
374 }
375 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
376
377 /**
378  * snd_hdac_bus_exit_link_reset - exit link reset
379  * @bus: HD-audio core bus
380  *
381  * Exit from the link reset state.
382  */
383 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
384 {
385         unsigned long timeout;
386
387         snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
388
389         timeout = jiffies + msecs_to_jiffies(100);
390         while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
391                 usleep_range(500, 1000);
392 }
393 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
394
395 /* reset codec link */
396 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
397 {
398         if (!full_reset)
399                 goto skip_reset;
400
401         /* clear STATESTS */
402         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
403
404         /* reset controller */
405         snd_hdac_bus_enter_link_reset(bus);
406
407         /* delay for >= 100us for codec PLL to settle per spec
408          * Rev 0.9 section 5.5.1
409          */
410         usleep_range(500, 1000);
411
412         /* Bring controller out of reset */
413         snd_hdac_bus_exit_link_reset(bus);
414
415         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
416         usleep_range(1000, 1200);
417
418  skip_reset:
419         /* check to see if controller is ready */
420         if (!snd_hdac_chip_readb(bus, GCTL)) {
421                 dev_dbg(bus->dev, "controller not ready!\n");
422                 return -EBUSY;
423         }
424
425         /* detect codecs */
426         if (!bus->codec_mask) {
427                 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
428                 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
429         }
430
431         return 0;
432 }
433 EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
434
435 /* enable interrupts */
436 static void azx_int_enable(struct hdac_bus *bus)
437 {
438         /* enable controller CIE and GIE */
439         snd_hdac_chip_updatel(bus, INTCTL,
440                               AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN,
441                               AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
442 }
443
444 /* disable interrupts */
445 static void azx_int_disable(struct hdac_bus *bus)
446 {
447         struct hdac_stream *azx_dev;
448
449         /* disable interrupts in stream descriptor */
450         list_for_each_entry(azx_dev, &bus->stream_list, list)
451                 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
452
453         /* disable SIE for all streams */
454         snd_hdac_chip_writeb(bus, INTCTL, 0);
455
456         /* disable controller CIE and GIE */
457         snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
458 }
459
460 /* clear interrupts */
461 static void azx_int_clear(struct hdac_bus *bus)
462 {
463         struct hdac_stream *azx_dev;
464
465         /* clear stream status */
466         list_for_each_entry(azx_dev, &bus->stream_list, list)
467                 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
468
469         /* clear STATESTS */
470         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
471
472         /* clear rirb status */
473         snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
474
475         /* clear int status */
476         snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
477 }
478
479 /**
480  * snd_hdac_bus_init_chip - reset and start the controller registers
481  * @bus: HD-audio core bus
482  * @full_reset: Do full reset
483  */
484 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
485 {
486         if (bus->chip_init)
487                 return false;
488
489         /* reset controller */
490         snd_hdac_bus_reset_link(bus, full_reset);
491
492         /* clear interrupts */
493         azx_int_clear(bus);
494
495         /* initialize the codec command I/O */
496         snd_hdac_bus_init_cmd_io(bus);
497
498         /* enable interrupts after CORB/RIRB buffers are initialized above */
499         azx_int_enable(bus);
500
501         /* program the position buffer */
502         if (bus->use_posbuf && bus->posbuf.addr) {
503                 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
504                 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
505         }
506
507         bus->chip_init = true;
508         return true;
509 }
510 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
511
512 /**
513  * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
514  * @bus: HD-audio core bus
515  */
516 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
517 {
518         if (!bus->chip_init)
519                 return;
520
521         /* disable interrupts */
522         azx_int_disable(bus);
523         azx_int_clear(bus);
524
525         /* disable CORB/RIRB */
526         snd_hdac_bus_stop_cmd_io(bus);
527
528         /* disable position buffer */
529         if (bus->posbuf.addr) {
530                 snd_hdac_chip_writel(bus, DPLBASE, 0);
531                 snd_hdac_chip_writel(bus, DPUBASE, 0);
532         }
533
534         bus->chip_init = false;
535 }
536 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
537
538 /**
539  * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
540  * @bus: HD-audio core bus
541  * @status: INTSTS register value
542  * @ask: callback to be called for woken streams
543  *
544  * Returns the bits of handled streams, or zero if no stream is handled.
545  */
546 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
547                                     void (*ack)(struct hdac_bus *,
548                                                 struct hdac_stream *))
549 {
550         struct hdac_stream *azx_dev;
551         u8 sd_status;
552         int handled = 0;
553
554         list_for_each_entry(azx_dev, &bus->stream_list, list) {
555                 if (status & azx_dev->sd_int_sta_mask) {
556                         sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
557                         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
558                         handled |= 1 << azx_dev->index;
559                         if (!azx_dev->substream || !azx_dev->running ||
560                             !(sd_status & SD_INT_COMPLETE))
561                                 continue;
562                         if (ack)
563                                 ack(bus, azx_dev);
564                 }
565         }
566         return handled;
567 }
568 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
569
570 /**
571  * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
572  * @bus: HD-audio core bus
573  *
574  * Call this after assigning the all streams.
575  * Returns zero for success, or a negative error code.
576  */
577 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
578 {
579         struct hdac_stream *s;
580         int num_streams = 0;
581         int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
582         int err;
583
584         list_for_each_entry(s, &bus->stream_list, list) {
585                 /* allocate memory for the BDL for each stream */
586                 err = snd_dma_alloc_pages(dma_type, bus->dev,
587                                           BDL_SIZE, &s->bdl);
588                 num_streams++;
589                 if (err < 0)
590                         return -ENOMEM;
591         }
592
593         if (WARN_ON(!num_streams))
594                 return -EINVAL;
595         /* allocate memory for the position buffer */
596         err = snd_dma_alloc_pages(dma_type, bus->dev,
597                                   num_streams * 8, &bus->posbuf);
598         if (err < 0)
599                 return -ENOMEM;
600         list_for_each_entry(s, &bus->stream_list, list)
601                 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
602
603         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
604         return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
605 }
606 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
607
608 /**
609  * snd_hdac_bus_free_stream_pages - release BDL and other buffers
610  * @bus: HD-audio core bus
611  */
612 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
613 {
614         struct hdac_stream *s;
615
616         list_for_each_entry(s, &bus->stream_list, list) {
617                 if (s->bdl.area)
618                         snd_dma_free_pages(&s->bdl);
619         }
620
621         if (bus->rb.area)
622                 snd_dma_free_pages(&bus->rb);
623         if (bus->posbuf.area)
624                 snd_dma_free_pages(&bus->posbuf);
625 }
626 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);