Merge tag 'drm-fixes-for-v4.17-rc1' of git://people.freedesktop.org/~airlied/linux
[muen/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/set_memory.h>
57 #include <asm/cpufeature.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <sound/hdaudio.h>
62 #include <sound/hda_i915.h>
63 #include <linux/vgaarb.h>
64 #include <linux/vga_switcheroo.h>
65 #include <linux/firmware.h>
66 #include "hda_codec.h"
67 #include "hda_controller.h"
68 #include "hda_intel.h"
69
70 #define CREATE_TRACE_POINTS
71 #include "hda_intel_trace.h"
72
73 /* position fix mode */
74 enum {
75         POS_FIX_AUTO,
76         POS_FIX_LPIB,
77         POS_FIX_POSBUF,
78         POS_FIX_VIACOMBO,
79         POS_FIX_COMBO,
80         POS_FIX_SKL,
81 };
82
83 /* Defines for ATI HD Audio support in SB450 south bridge */
84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
86
87 /* Defines for Nvidia HDA support */
88 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
89 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
90 #define NVIDIA_HDA_ISTRM_COH          0x4d
91 #define NVIDIA_HDA_OSTRM_COH          0x4c
92 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
93
94 /* Defines for Intel SCH HDA snoop control */
95 #define INTEL_HDA_CGCTL  0x48
96 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
97 #define INTEL_SCH_HDA_DEVC      0x78
98 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
99
100 /* Define IN stream 0 FIFO size offset in VIA controller */
101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102 /* Define VIA HD Audio Device ID*/
103 #define VIA_HDAC_DEVICE_ID              0x3288
104
105 /* max number of SDs */
106 /* ICH, ATI and VIA have 4 playback and 4 capture */
107 #define ICH6_NUM_CAPTURE        4
108 #define ICH6_NUM_PLAYBACK       4
109
110 /* ULI has 6 playback and 5 capture */
111 #define ULI_NUM_CAPTURE         5
112 #define ULI_NUM_PLAYBACK        6
113
114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
115 #define ATIHDMI_NUM_CAPTURE     0
116 #define ATIHDMI_NUM_PLAYBACK    8
117
118 /* TERA has 4 playback and 3 capture */
119 #define TERA_NUM_CAPTURE        3
120 #define TERA_NUM_PLAYBACK       4
121
122
123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
126 static char *model[SNDRV_CARDS];
127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
130 static int probe_only[SNDRV_CARDS];
131 static int jackpoll_ms[SNDRV_CARDS];
132 static int single_cmd = -1;
133 static int enable_msi = -1;
134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
135 static char *patch[SNDRV_CARDS];
136 #endif
137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
139                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
140 #endif
141
142 module_param_array(index, int, NULL, 0444);
143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
144 module_param_array(id, charp, NULL, 0444);
145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
146 module_param_array(enable, bool, NULL, 0444);
147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148 module_param_array(model, charp, NULL, 0444);
149 MODULE_PARM_DESC(model, "Use the given board model.");
150 module_param_array(position_fix, int, NULL, 0444);
151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
152                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
153 module_param_array(bdl_pos_adj, int, NULL, 0644);
154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
155 module_param_array(probe_mask, int, NULL, 0444);
156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
157 module_param_array(probe_only, int, NULL, 0444);
158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
159 module_param_array(jackpoll_ms, int, NULL, 0444);
160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
161 module_param(single_cmd, bint, 0444);
162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163                  "(for debugging only).");
164 module_param(enable_msi, bint, 0444);
165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
167 module_param_array(patch, charp, NULL, 0444);
168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169 #endif
170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
171 module_param_array(beep_mode, bool, NULL, 0444);
172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
173                             "(0=off, 1=on) (default=1).");
174 #endif
175
176 #ifdef CONFIG_PM
177 static int param_set_xint(const char *val, const struct kernel_param *kp);
178 static const struct kernel_param_ops param_ops_xint = {
179         .set = param_set_xint,
180         .get = param_get_int,
181 };
182 #define param_check_xint param_check_int
183
184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
185 module_param(power_save, xint, 0644);
186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187                  "(in second, 0 = disable).");
188
189 static bool pm_blacklist = true;
190 module_param(pm_blacklist, bool, 0644);
191 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
192
193 /* reset the HD-audio controller in power save mode.
194  * this may give more power-saving, but will take longer time to
195  * wake up.
196  */
197 static bool power_save_controller = 1;
198 module_param(power_save_controller, bool, 0644);
199 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
200 #else
201 #define power_save      0
202 #endif /* CONFIG_PM */
203
204 static int align_buffer_size = -1;
205 module_param(align_buffer_size, bint, 0644);
206 MODULE_PARM_DESC(align_buffer_size,
207                 "Force buffer and period sizes to be multiple of 128 bytes.");
208
209 #ifdef CONFIG_X86
210 static int hda_snoop = -1;
211 module_param_named(snoop, hda_snoop, bint, 0444);
212 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
213 #else
214 #define hda_snoop               true
215 #endif
216
217
218 MODULE_LICENSE("GPL");
219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
220                          "{Intel, ICH6M},"
221                          "{Intel, ICH7},"
222                          "{Intel, ESB2},"
223                          "{Intel, ICH8},"
224                          "{Intel, ICH9},"
225                          "{Intel, ICH10},"
226                          "{Intel, PCH},"
227                          "{Intel, CPT},"
228                          "{Intel, PPT},"
229                          "{Intel, LPT},"
230                          "{Intel, LPT_LP},"
231                          "{Intel, WPT_LP},"
232                          "{Intel, SPT},"
233                          "{Intel, SPT_LP},"
234                          "{Intel, HPT},"
235                          "{Intel, PBG},"
236                          "{Intel, SCH},"
237                          "{ATI, SB450},"
238                          "{ATI, SB600},"
239                          "{ATI, RS600},"
240                          "{ATI, RS690},"
241                          "{ATI, RS780},"
242                          "{ATI, R600},"
243                          "{ATI, RV630},"
244                          "{ATI, RV610},"
245                          "{ATI, RV670},"
246                          "{ATI, RV635},"
247                          "{ATI, RV620},"
248                          "{ATI, RV770},"
249                          "{VIA, VT8251},"
250                          "{VIA, VT8237A},"
251                          "{SiS, SIS966},"
252                          "{ULI, M5461}}");
253 MODULE_DESCRIPTION("Intel HDA driver");
254
255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
257 #define SUPPORT_VGA_SWITCHEROO
258 #endif
259 #endif
260
261
262 /*
263  */
264
265 /* driver types */
266 enum {
267         AZX_DRIVER_ICH,
268         AZX_DRIVER_PCH,
269         AZX_DRIVER_SCH,
270         AZX_DRIVER_SKL,
271         AZX_DRIVER_HDMI,
272         AZX_DRIVER_ATI,
273         AZX_DRIVER_ATIHDMI,
274         AZX_DRIVER_ATIHDMI_NS,
275         AZX_DRIVER_VIA,
276         AZX_DRIVER_SIS,
277         AZX_DRIVER_ULI,
278         AZX_DRIVER_NVIDIA,
279         AZX_DRIVER_TERA,
280         AZX_DRIVER_CTX,
281         AZX_DRIVER_CTHDA,
282         AZX_DRIVER_CMEDIA,
283         AZX_DRIVER_GENERIC,
284         AZX_NUM_DRIVERS, /* keep this as last entry */
285 };
286
287 #define azx_get_snoop_type(chip) \
288         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
290
291 /* quirks for old Intel chipsets */
292 #define AZX_DCAPS_INTEL_ICH \
293         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
294
295 /* quirks for Intel PCH */
296 #define AZX_DCAPS_INTEL_PCH_BASE \
297         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
298          AZX_DCAPS_SNOOP_TYPE(SCH))
299
300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
301 #define AZX_DCAPS_INTEL_PCH_NOPM \
302         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
303
304 /* PCH for HSW/BDW; with runtime PM */
305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
306 #define AZX_DCAPS_INTEL_PCH \
307         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
308
309 /* HSW HDMI */
310 #define AZX_DCAPS_INTEL_HASWELL \
311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
313          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
314
315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
316 #define AZX_DCAPS_INTEL_BROADWELL \
317         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
318          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
319          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
320
321 #define AZX_DCAPS_INTEL_BAYTRAIL \
322         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
323          AZX_DCAPS_I915_POWERWELL)
324
325 #define AZX_DCAPS_INTEL_BRASWELL \
326         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
327          AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
328
329 #define AZX_DCAPS_INTEL_SKYLAKE \
330         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
331          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
332          AZX_DCAPS_I915_POWERWELL)
333
334 #define AZX_DCAPS_INTEL_BROXTON \
335         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
336          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
337          AZX_DCAPS_I915_POWERWELL)
338
339 /* quirks for ATI SB / AMD Hudson */
340 #define AZX_DCAPS_PRESET_ATI_SB \
341         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
342          AZX_DCAPS_SNOOP_TYPE(ATI))
343
344 /* quirks for ATI/AMD HDMI */
345 #define AZX_DCAPS_PRESET_ATI_HDMI \
346         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
347          AZX_DCAPS_NO_MSI64)
348
349 /* quirks for ATI HDMI with snoop off */
350 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
351         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
352
353 /* quirks for Nvidia */
354 #define AZX_DCAPS_PRESET_NVIDIA \
355         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
356          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
357
358 #define AZX_DCAPS_PRESET_CTHDA \
359         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
360          AZX_DCAPS_NO_64BIT |\
361          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
362
363 /*
364  * vga_switcheroo support
365  */
366 #ifdef SUPPORT_VGA_SWITCHEROO
367 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
368 #else
369 #define use_vga_switcheroo(chip)        0
370 #endif
371
372 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
373                                         ((pci)->device == 0x0c0c) || \
374                                         ((pci)->device == 0x0d0c) || \
375                                         ((pci)->device == 0x160c))
376
377 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
378 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
379
380 static char *driver_short_names[] = {
381         [AZX_DRIVER_ICH] = "HDA Intel",
382         [AZX_DRIVER_PCH] = "HDA Intel PCH",
383         [AZX_DRIVER_SCH] = "HDA Intel MID",
384         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
385         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
386         [AZX_DRIVER_ATI] = "HDA ATI SB",
387         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
388         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
389         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
390         [AZX_DRIVER_SIS] = "HDA SIS966",
391         [AZX_DRIVER_ULI] = "HDA ULI M5461",
392         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
393         [AZX_DRIVER_TERA] = "HDA Teradici", 
394         [AZX_DRIVER_CTX] = "HDA Creative", 
395         [AZX_DRIVER_CTHDA] = "HDA Creative",
396         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
397         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
398 };
399
400 #ifdef CONFIG_X86
401 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
402 {
403         int pages;
404
405         if (azx_snoop(chip))
406                 return;
407         if (!dmab || !dmab->area || !dmab->bytes)
408                 return;
409
410 #ifdef CONFIG_SND_DMA_SGBUF
411         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
412                 struct snd_sg_buf *sgbuf = dmab->private_data;
413                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
414                         return; /* deal with only CORB/RIRB buffers */
415                 if (on)
416                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
417                 else
418                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
419                 return;
420         }
421 #endif
422
423         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
424         if (on)
425                 set_memory_wc((unsigned long)dmab->area, pages);
426         else
427                 set_memory_wb((unsigned long)dmab->area, pages);
428 }
429
430 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
431                                  bool on)
432 {
433         __mark_pages_wc(chip, buf, on);
434 }
435 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
436                                    struct snd_pcm_substream *substream, bool on)
437 {
438         if (azx_dev->wc_marked != on) {
439                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
440                 azx_dev->wc_marked = on;
441         }
442 }
443 #else
444 /* NOP for other archs */
445 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
446                                  bool on)
447 {
448 }
449 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
450                                    struct snd_pcm_substream *substream, bool on)
451 {
452 }
453 #endif
454
455 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
456
457 /*
458  * initialize the PCI registers
459  */
460 /* update bits in a PCI register byte */
461 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
462                             unsigned char mask, unsigned char val)
463 {
464         unsigned char data;
465
466         pci_read_config_byte(pci, reg, &data);
467         data &= ~mask;
468         data |= (val & mask);
469         pci_write_config_byte(pci, reg, data);
470 }
471
472 static void azx_init_pci(struct azx *chip)
473 {
474         int snoop_type = azx_get_snoop_type(chip);
475
476         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
477          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
478          * Ensuring these bits are 0 clears playback static on some HD Audio
479          * codecs.
480          * The PCI register TCSEL is defined in the Intel manuals.
481          */
482         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
483                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
484                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
485         }
486
487         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
488          * we need to enable snoop.
489          */
490         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
491                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
492                         azx_snoop(chip));
493                 update_pci_byte(chip->pci,
494                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
495                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
496         }
497
498         /* For NVIDIA HDA, enable snoop */
499         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
500                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
501                         azx_snoop(chip));
502                 update_pci_byte(chip->pci,
503                                 NVIDIA_HDA_TRANSREG_ADDR,
504                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
505                 update_pci_byte(chip->pci,
506                                 NVIDIA_HDA_ISTRM_COH,
507                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
508                 update_pci_byte(chip->pci,
509                                 NVIDIA_HDA_OSTRM_COH,
510                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
511         }
512
513         /* Enable SCH/PCH snoop if needed */
514         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
515                 unsigned short snoop;
516                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
517                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
518                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
519                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
520                         if (!azx_snoop(chip))
521                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
522                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
523                         pci_read_config_word(chip->pci,
524                                 INTEL_SCH_HDA_DEVC, &snoop);
525                 }
526                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
527                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
528                         "Disabled" : "Enabled");
529         }
530 }
531
532 /*
533  * In BXT-P A0, HD-Audio DMA requests is later than expected,
534  * and makes an audio stream sensitive to system latencies when
535  * 24/32 bits are playing.
536  * Adjusting threshold of DMA fifo to force the DMA request
537  * sooner to improve latency tolerance at the expense of power.
538  */
539 static void bxt_reduce_dma_latency(struct azx *chip)
540 {
541         u32 val;
542
543         val = azx_readl(chip, VS_EM4L);
544         val &= (0x3 << 20);
545         azx_writel(chip, VS_EM4L, val);
546 }
547
548 /*
549  * ML_LCAP bits:
550  *  bit 0: 6 MHz Supported
551  *  bit 1: 12 MHz Supported
552  *  bit 2: 24 MHz Supported
553  *  bit 3: 48 MHz Supported
554  *  bit 4: 96 MHz Supported
555  *  bit 5: 192 MHz Supported
556  */
557 static int intel_get_lctl_scf(struct azx *chip)
558 {
559         struct hdac_bus *bus = azx_bus(chip);
560         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
561         u32 val, t;
562         int i;
563
564         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
565
566         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
567                 t = preferred_bits[i];
568                 if (val & (1 << t))
569                         return t;
570         }
571
572         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
573         return 0;
574 }
575
576 static int intel_ml_lctl_set_power(struct azx *chip, int state)
577 {
578         struct hdac_bus *bus = azx_bus(chip);
579         u32 val;
580         int timeout;
581
582         /*
583          * the codecs are sharing the first link setting by default
584          * If other links are enabled for stream, they need similar fix
585          */
586         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
587         val &= ~AZX_MLCTL_SPA;
588         val |= state << AZX_MLCTL_SPA_SHIFT;
589         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
590         /* wait for CPA */
591         timeout = 50;
592         while (timeout) {
593                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
594                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
595                         return 0;
596                 timeout--;
597                 udelay(10);
598         }
599
600         return -1;
601 }
602
603 static void intel_init_lctl(struct azx *chip)
604 {
605         struct hdac_bus *bus = azx_bus(chip);
606         u32 val;
607         int ret;
608
609         /* 0. check lctl register value is correct or not */
610         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
611         /* if SCF is already set, let's use it */
612         if ((val & ML_LCTL_SCF_MASK) != 0)
613                 return;
614
615         /*
616          * Before operating on SPA, CPA must match SPA.
617          * Any deviation may result in undefined behavior.
618          */
619         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
620                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
621                 return;
622
623         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
624         ret = intel_ml_lctl_set_power(chip, 0);
625         udelay(100);
626         if (ret)
627                 goto set_spa;
628
629         /* 2. update SCF to select a properly audio clock*/
630         val &= ~ML_LCTL_SCF_MASK;
631         val |= intel_get_lctl_scf(chip);
632         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
633
634 set_spa:
635         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
636         intel_ml_lctl_set_power(chip, 1);
637         udelay(100);
638 }
639
640 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
641 {
642         struct hdac_bus *bus = azx_bus(chip);
643         struct pci_dev *pci = chip->pci;
644         u32 val;
645
646         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
647                 snd_hdac_set_codec_wakeup(bus, true);
648         if (chip->driver_type == AZX_DRIVER_SKL) {
649                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
650                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
651                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
652         }
653         azx_init_chip(chip, full_reset);
654         if (chip->driver_type == AZX_DRIVER_SKL) {
655                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
656                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
657                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
658         }
659         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
660                 snd_hdac_set_codec_wakeup(bus, false);
661
662         /* reduce dma latency to avoid noise */
663         if (IS_BXT(pci))
664                 bxt_reduce_dma_latency(chip);
665
666         if (bus->mlcap != NULL)
667                 intel_init_lctl(chip);
668 }
669
670 /* calculate runtime delay from LPIB */
671 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
672                                    unsigned int pos)
673 {
674         struct snd_pcm_substream *substream = azx_dev->core.substream;
675         int stream = substream->stream;
676         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
677         int delay;
678
679         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
680                 delay = pos - lpib_pos;
681         else
682                 delay = lpib_pos - pos;
683         if (delay < 0) {
684                 if (delay >= azx_dev->core.delay_negative_threshold)
685                         delay = 0;
686                 else
687                         delay += azx_dev->core.bufsize;
688         }
689
690         if (delay >= azx_dev->core.period_bytes) {
691                 dev_info(chip->card->dev,
692                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
693                          delay, azx_dev->core.period_bytes);
694                 delay = 0;
695                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
696                 chip->get_delay[stream] = NULL;
697         }
698
699         return bytes_to_frames(substream->runtime, delay);
700 }
701
702 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
703
704 /* called from IRQ */
705 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
706 {
707         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
708         int ok;
709
710         ok = azx_position_ok(chip, azx_dev);
711         if (ok == 1) {
712                 azx_dev->irq_pending = 0;
713                 return ok;
714         } else if (ok == 0) {
715                 /* bogus IRQ, process it later */
716                 azx_dev->irq_pending = 1;
717                 schedule_work(&hda->irq_pending_work);
718         }
719         return 0;
720 }
721
722 /* Enable/disable i915 display power for the link */
723 static int azx_intel_link_power(struct azx *chip, bool enable)
724 {
725         struct hdac_bus *bus = azx_bus(chip);
726
727         return snd_hdac_display_power(bus, enable);
728 }
729
730 /*
731  * Check whether the current DMA position is acceptable for updating
732  * periods.  Returns non-zero if it's OK.
733  *
734  * Many HD-audio controllers appear pretty inaccurate about
735  * the update-IRQ timing.  The IRQ is issued before actually the
736  * data is processed.  So, we need to process it afterwords in a
737  * workqueue.
738  */
739 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
740 {
741         struct snd_pcm_substream *substream = azx_dev->core.substream;
742         int stream = substream->stream;
743         u32 wallclk;
744         unsigned int pos;
745
746         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
747         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
748                 return -1;      /* bogus (too early) interrupt */
749
750         if (chip->get_position[stream])
751                 pos = chip->get_position[stream](chip, azx_dev);
752         else { /* use the position buffer as default */
753                 pos = azx_get_pos_posbuf(chip, azx_dev);
754                 if (!pos || pos == (u32)-1) {
755                         dev_info(chip->card->dev,
756                                  "Invalid position buffer, using LPIB read method instead.\n");
757                         chip->get_position[stream] = azx_get_pos_lpib;
758                         if (chip->get_position[0] == azx_get_pos_lpib &&
759                             chip->get_position[1] == azx_get_pos_lpib)
760                                 azx_bus(chip)->use_posbuf = false;
761                         pos = azx_get_pos_lpib(chip, azx_dev);
762                         chip->get_delay[stream] = NULL;
763                 } else {
764                         chip->get_position[stream] = azx_get_pos_posbuf;
765                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
766                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
767                 }
768         }
769
770         if (pos >= azx_dev->core.bufsize)
771                 pos = 0;
772
773         if (WARN_ONCE(!azx_dev->core.period_bytes,
774                       "hda-intel: zero azx_dev->period_bytes"))
775                 return -1; /* this shouldn't happen! */
776         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
777             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
778                 /* NG - it's below the first next period boundary */
779                 return chip->bdl_pos_adj ? 0 : -1;
780         azx_dev->core.start_wallclk += wallclk;
781         return 1; /* OK, it's fine */
782 }
783
784 /*
785  * The work for pending PCM period updates.
786  */
787 static void azx_irq_pending_work(struct work_struct *work)
788 {
789         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
790         struct azx *chip = &hda->chip;
791         struct hdac_bus *bus = azx_bus(chip);
792         struct hdac_stream *s;
793         int pending, ok;
794
795         if (!hda->irq_pending_warned) {
796                 dev_info(chip->card->dev,
797                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
798                          chip->card->number);
799                 hda->irq_pending_warned = 1;
800         }
801
802         for (;;) {
803                 pending = 0;
804                 spin_lock_irq(&bus->reg_lock);
805                 list_for_each_entry(s, &bus->stream_list, list) {
806                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
807                         if (!azx_dev->irq_pending ||
808                             !s->substream ||
809                             !s->running)
810                                 continue;
811                         ok = azx_position_ok(chip, azx_dev);
812                         if (ok > 0) {
813                                 azx_dev->irq_pending = 0;
814                                 spin_unlock(&bus->reg_lock);
815                                 snd_pcm_period_elapsed(s->substream);
816                                 spin_lock(&bus->reg_lock);
817                         } else if (ok < 0) {
818                                 pending = 0;    /* too early */
819                         } else
820                                 pending++;
821                 }
822                 spin_unlock_irq(&bus->reg_lock);
823                 if (!pending)
824                         return;
825                 msleep(1);
826         }
827 }
828
829 /* clear irq_pending flags and assure no on-going workq */
830 static void azx_clear_irq_pending(struct azx *chip)
831 {
832         struct hdac_bus *bus = azx_bus(chip);
833         struct hdac_stream *s;
834
835         spin_lock_irq(&bus->reg_lock);
836         list_for_each_entry(s, &bus->stream_list, list) {
837                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
838                 azx_dev->irq_pending = 0;
839         }
840         spin_unlock_irq(&bus->reg_lock);
841 }
842
843 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
844 {
845         struct hdac_bus *bus = azx_bus(chip);
846
847         if (request_irq(chip->pci->irq, azx_interrupt,
848                         chip->msi ? 0 : IRQF_SHARED,
849                         chip->card->irq_descr, chip)) {
850                 dev_err(chip->card->dev,
851                         "unable to grab IRQ %d, disabling device\n",
852                         chip->pci->irq);
853                 if (do_disconnect)
854                         snd_card_disconnect(chip->card);
855                 return -1;
856         }
857         bus->irq = chip->pci->irq;
858         pci_intx(chip->pci, !chip->msi);
859         return 0;
860 }
861
862 /* get the current DMA position with correction on VIA chips */
863 static unsigned int azx_via_get_position(struct azx *chip,
864                                          struct azx_dev *azx_dev)
865 {
866         unsigned int link_pos, mini_pos, bound_pos;
867         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
868         unsigned int fifo_size;
869
870         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
871         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
872                 /* Playback, no problem using link position */
873                 return link_pos;
874         }
875
876         /* Capture */
877         /* For new chipset,
878          * use mod to get the DMA position just like old chipset
879          */
880         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
881         mod_dma_pos %= azx_dev->core.period_bytes;
882
883         /* azx_dev->fifo_size can't get FIFO size of in stream.
884          * Get from base address + offset.
885          */
886         fifo_size = readw(azx_bus(chip)->remap_addr +
887                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
888
889         if (azx_dev->insufficient) {
890                 /* Link position never gather than FIFO size */
891                 if (link_pos <= fifo_size)
892                         return 0;
893
894                 azx_dev->insufficient = 0;
895         }
896
897         if (link_pos <= fifo_size)
898                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
899         else
900                 mini_pos = link_pos - fifo_size;
901
902         /* Find nearest previous boudary */
903         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
904         mod_link_pos = link_pos % azx_dev->core.period_bytes;
905         if (mod_link_pos >= fifo_size)
906                 bound_pos = link_pos - mod_link_pos;
907         else if (mod_dma_pos >= mod_mini_pos)
908                 bound_pos = mini_pos - mod_mini_pos;
909         else {
910                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
911                 if (bound_pos >= azx_dev->core.bufsize)
912                         bound_pos = 0;
913         }
914
915         /* Calculate real DMA position we want */
916         return bound_pos + mod_dma_pos;
917 }
918
919 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
920                                          struct azx_dev *azx_dev)
921 {
922         return _snd_hdac_chip_readl(azx_bus(chip),
923                                     AZX_REG_VS_SDXDPIB_XBASE +
924                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
925                                      azx_dev->core.index));
926 }
927
928 /* get the current DMA position with correction on SKL+ chips */
929 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
930 {
931         /* DPIB register gives a more accurate position for playback */
932         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
933                 return azx_skl_get_dpib_pos(chip, azx_dev);
934
935         /* For capture, we need to read posbuf, but it requires a delay
936          * for the possible boundary overlap; the read of DPIB fetches the
937          * actual posbuf
938          */
939         udelay(20);
940         azx_skl_get_dpib_pos(chip, azx_dev);
941         return azx_get_pos_posbuf(chip, azx_dev);
942 }
943
944 #ifdef CONFIG_PM
945 static DEFINE_MUTEX(card_list_lock);
946 static LIST_HEAD(card_list);
947
948 static void azx_add_card_list(struct azx *chip)
949 {
950         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
951         mutex_lock(&card_list_lock);
952         list_add(&hda->list, &card_list);
953         mutex_unlock(&card_list_lock);
954 }
955
956 static void azx_del_card_list(struct azx *chip)
957 {
958         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
959         mutex_lock(&card_list_lock);
960         list_del_init(&hda->list);
961         mutex_unlock(&card_list_lock);
962 }
963
964 /* trigger power-save check at writing parameter */
965 static int param_set_xint(const char *val, const struct kernel_param *kp)
966 {
967         struct hda_intel *hda;
968         struct azx *chip;
969         int prev = power_save;
970         int ret = param_set_int(val, kp);
971
972         if (ret || prev == power_save)
973                 return ret;
974
975         mutex_lock(&card_list_lock);
976         list_for_each_entry(hda, &card_list, list) {
977                 chip = &hda->chip;
978                 if (!hda->probe_continued || chip->disabled)
979                         continue;
980                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
981         }
982         mutex_unlock(&card_list_lock);
983         return 0;
984 }
985 #else
986 #define azx_add_card_list(chip) /* NOP */
987 #define azx_del_card_list(chip) /* NOP */
988 #endif /* CONFIG_PM */
989
990 #ifdef CONFIG_PM_SLEEP
991 /*
992  * power management
993  */
994 static int azx_suspend(struct device *dev)
995 {
996         struct snd_card *card = dev_get_drvdata(dev);
997         struct azx *chip;
998         struct hda_intel *hda;
999         struct hdac_bus *bus;
1000
1001         if (!card)
1002                 return 0;
1003
1004         chip = card->private_data;
1005         hda = container_of(chip, struct hda_intel, chip);
1006         if (chip->disabled || hda->init_failed || !chip->running)
1007                 return 0;
1008
1009         bus = azx_bus(chip);
1010         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1011         azx_clear_irq_pending(chip);
1012         azx_stop_chip(chip);
1013         azx_enter_link_reset(chip);
1014         if (bus->irq >= 0) {
1015                 free_irq(bus->irq, chip);
1016                 bus->irq = -1;
1017         }
1018
1019         if (chip->msi)
1020                 pci_disable_msi(chip->pci);
1021         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1022                 && hda->need_i915_power)
1023                 snd_hdac_display_power(bus, false);
1024
1025         trace_azx_suspend(chip);
1026         return 0;
1027 }
1028
1029 static int azx_resume(struct device *dev)
1030 {
1031         struct pci_dev *pci = to_pci_dev(dev);
1032         struct snd_card *card = dev_get_drvdata(dev);
1033         struct azx *chip;
1034         struct hda_intel *hda;
1035         struct hdac_bus *bus;
1036
1037         if (!card)
1038                 return 0;
1039
1040         chip = card->private_data;
1041         hda = container_of(chip, struct hda_intel, chip);
1042         bus = azx_bus(chip);
1043         if (chip->disabled || hda->init_failed || !chip->running)
1044                 return 0;
1045
1046         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1047                 snd_hdac_display_power(bus, true);
1048                 if (hda->need_i915_power)
1049                         snd_hdac_i915_set_bclk(bus);
1050         }
1051
1052         if (chip->msi)
1053                 if (pci_enable_msi(pci) < 0)
1054                         chip->msi = 0;
1055         if (azx_acquire_irq(chip, 1) < 0)
1056                 return -EIO;
1057         azx_init_pci(chip);
1058
1059         hda_intel_init_chip(chip, true);
1060
1061         /* power down again for link-controlled chips */
1062         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1063             !hda->need_i915_power)
1064                 snd_hdac_display_power(bus, false);
1065
1066         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1067
1068         trace_azx_resume(chip);
1069         return 0;
1070 }
1071
1072 /* put codec down to D3 at hibernation for Intel SKL+;
1073  * otherwise BIOS may still access the codec and screw up the driver
1074  */
1075 static int azx_freeze_noirq(struct device *dev)
1076 {
1077         struct snd_card *card = dev_get_drvdata(dev);
1078         struct azx *chip = card->private_data;
1079         struct pci_dev *pci = to_pci_dev(dev);
1080
1081         if (chip->driver_type == AZX_DRIVER_SKL)
1082                 pci_set_power_state(pci, PCI_D3hot);
1083
1084         return 0;
1085 }
1086
1087 static int azx_thaw_noirq(struct device *dev)
1088 {
1089         struct snd_card *card = dev_get_drvdata(dev);
1090         struct azx *chip = card->private_data;
1091         struct pci_dev *pci = to_pci_dev(dev);
1092
1093         if (chip->driver_type == AZX_DRIVER_SKL)
1094                 pci_set_power_state(pci, PCI_D0);
1095
1096         return 0;
1097 }
1098 #endif /* CONFIG_PM_SLEEP */
1099
1100 #ifdef CONFIG_PM
1101 static int azx_runtime_suspend(struct device *dev)
1102 {
1103         struct snd_card *card = dev_get_drvdata(dev);
1104         struct azx *chip;
1105         struct hda_intel *hda;
1106
1107         if (!card)
1108                 return 0;
1109
1110         chip = card->private_data;
1111         hda = container_of(chip, struct hda_intel, chip);
1112         if (chip->disabled || hda->init_failed)
1113                 return 0;
1114
1115         if (!azx_has_pm_runtime(chip))
1116                 return 0;
1117
1118         /* enable controller wake up event */
1119         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1120                   STATESTS_INT_MASK);
1121
1122         azx_stop_chip(chip);
1123         azx_enter_link_reset(chip);
1124         azx_clear_irq_pending(chip);
1125         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1126                 && hda->need_i915_power)
1127                 snd_hdac_display_power(azx_bus(chip), false);
1128
1129         trace_azx_runtime_suspend(chip);
1130         return 0;
1131 }
1132
1133 static int azx_runtime_resume(struct device *dev)
1134 {
1135         struct snd_card *card = dev_get_drvdata(dev);
1136         struct azx *chip;
1137         struct hda_intel *hda;
1138         struct hdac_bus *bus;
1139         struct hda_codec *codec;
1140         int status;
1141
1142         if (!card)
1143                 return 0;
1144
1145         chip = card->private_data;
1146         hda = container_of(chip, struct hda_intel, chip);
1147         bus = azx_bus(chip);
1148         if (chip->disabled || hda->init_failed)
1149                 return 0;
1150
1151         if (!azx_has_pm_runtime(chip))
1152                 return 0;
1153
1154         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1155                 snd_hdac_display_power(bus, true);
1156                 if (hda->need_i915_power)
1157                         snd_hdac_i915_set_bclk(bus);
1158         }
1159
1160         /* Read STATESTS before controller reset */
1161         status = azx_readw(chip, STATESTS);
1162
1163         azx_init_pci(chip);
1164         hda_intel_init_chip(chip, true);
1165
1166         if (status) {
1167                 list_for_each_codec(codec, &chip->bus)
1168                         if (status & (1 << codec->addr))
1169                                 schedule_delayed_work(&codec->jackpoll_work,
1170                                                       codec->jackpoll_interval);
1171         }
1172
1173         /* disable controller Wake Up event*/
1174         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1175                         ~STATESTS_INT_MASK);
1176
1177         /* power down again for link-controlled chips */
1178         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1179             !hda->need_i915_power)
1180                 snd_hdac_display_power(bus, false);
1181
1182         trace_azx_runtime_resume(chip);
1183         return 0;
1184 }
1185
1186 static int azx_runtime_idle(struct device *dev)
1187 {
1188         struct snd_card *card = dev_get_drvdata(dev);
1189         struct azx *chip;
1190         struct hda_intel *hda;
1191
1192         if (!card)
1193                 return 0;
1194
1195         chip = card->private_data;
1196         hda = container_of(chip, struct hda_intel, chip);
1197         if (chip->disabled || hda->init_failed)
1198                 return 0;
1199
1200         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1201             azx_bus(chip)->codec_powered || !chip->running)
1202                 return -EBUSY;
1203
1204         return 0;
1205 }
1206
1207 static const struct dev_pm_ops azx_pm = {
1208         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1209 #ifdef CONFIG_PM_SLEEP
1210         .freeze_noirq = azx_freeze_noirq,
1211         .thaw_noirq = azx_thaw_noirq,
1212 #endif
1213         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1214 };
1215
1216 #define AZX_PM_OPS      &azx_pm
1217 #else
1218 #define AZX_PM_OPS      NULL
1219 #endif /* CONFIG_PM */
1220
1221
1222 static int azx_probe_continue(struct azx *chip);
1223
1224 #ifdef SUPPORT_VGA_SWITCHEROO
1225 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1226
1227 static void azx_vs_set_state(struct pci_dev *pci,
1228                              enum vga_switcheroo_state state)
1229 {
1230         struct snd_card *card = pci_get_drvdata(pci);
1231         struct azx *chip = card->private_data;
1232         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1233         struct hda_codec *codec;
1234         bool disabled;
1235
1236         wait_for_completion(&hda->probe_wait);
1237         if (hda->init_failed)
1238                 return;
1239
1240         disabled = (state == VGA_SWITCHEROO_OFF);
1241         if (chip->disabled == disabled)
1242                 return;
1243
1244         if (!hda->probe_continued) {
1245                 chip->disabled = disabled;
1246                 if (!disabled) {
1247                         dev_info(chip->card->dev,
1248                                  "Start delayed initialization\n");
1249                         if (azx_probe_continue(chip) < 0) {
1250                                 dev_err(chip->card->dev, "initialization error\n");
1251                                 hda->init_failed = true;
1252                         }
1253                 }
1254         } else {
1255                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1256                          disabled ? "Disabling" : "Enabling");
1257                 if (disabled) {
1258                         list_for_each_codec(codec, &chip->bus) {
1259                                 pm_runtime_suspend(hda_codec_dev(codec));
1260                                 pm_runtime_disable(hda_codec_dev(codec));
1261                         }
1262                         pm_runtime_suspend(card->dev);
1263                         pm_runtime_disable(card->dev);
1264                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1265                          * however we have no ACPI handle, so pci/acpi can't put us there,
1266                          * put ourselves there */
1267                         pci->current_state = PCI_D3cold;
1268                         chip->disabled = true;
1269                         if (snd_hda_lock_devices(&chip->bus))
1270                                 dev_warn(chip->card->dev,
1271                                          "Cannot lock devices!\n");
1272                 } else {
1273                         snd_hda_unlock_devices(&chip->bus);
1274                         chip->disabled = false;
1275                         pm_runtime_enable(card->dev);
1276                         list_for_each_codec(codec, &chip->bus) {
1277                                 pm_runtime_enable(hda_codec_dev(codec));
1278                                 pm_runtime_resume(hda_codec_dev(codec));
1279                         }
1280                 }
1281         }
1282 }
1283
1284 static bool azx_vs_can_switch(struct pci_dev *pci)
1285 {
1286         struct snd_card *card = pci_get_drvdata(pci);
1287         struct azx *chip = card->private_data;
1288         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1289
1290         wait_for_completion(&hda->probe_wait);
1291         if (hda->init_failed)
1292                 return false;
1293         if (chip->disabled || !hda->probe_continued)
1294                 return true;
1295         if (snd_hda_lock_devices(&chip->bus))
1296                 return false;
1297         snd_hda_unlock_devices(&chip->bus);
1298         return true;
1299 }
1300
1301 static void init_vga_switcheroo(struct azx *chip)
1302 {
1303         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1304         struct pci_dev *p = get_bound_vga(chip->pci);
1305         if (p) {
1306                 dev_info(chip->card->dev,
1307                          "Handle vga_switcheroo audio client\n");
1308                 hda->use_vga_switcheroo = 1;
1309                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1310                 pci_dev_put(p);
1311         }
1312 }
1313
1314 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1315         .set_gpu_state = azx_vs_set_state,
1316         .can_switch = azx_vs_can_switch,
1317 };
1318
1319 static int register_vga_switcheroo(struct azx *chip)
1320 {
1321         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1322         int err;
1323
1324         if (!hda->use_vga_switcheroo)
1325                 return 0;
1326         /* FIXME: currently only handling DIS controller
1327          * is there any machine with two switchable HDMI audio controllers?
1328          */
1329         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1330                                                    VGA_SWITCHEROO_DIS);
1331         if (err < 0)
1332                 return err;
1333         hda->vga_switcheroo_registered = 1;
1334
1335         return 0;
1336 }
1337 #else
1338 #define init_vga_switcheroo(chip)               /* NOP */
1339 #define register_vga_switcheroo(chip)           0
1340 #define check_hdmi_disabled(pci)        false
1341 #endif /* SUPPORT_VGA_SWITCHER */
1342
1343 /*
1344  * destructor
1345  */
1346 static int azx_free(struct azx *chip)
1347 {
1348         struct pci_dev *pci = chip->pci;
1349         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1350         struct hdac_bus *bus = azx_bus(chip);
1351
1352         if (azx_has_pm_runtime(chip) && chip->running)
1353                 pm_runtime_get_noresume(&pci->dev);
1354
1355         azx_del_card_list(chip);
1356
1357         hda->init_failed = 1; /* to be sure */
1358         complete_all(&hda->probe_wait);
1359
1360         if (use_vga_switcheroo(hda)) {
1361                 if (chip->disabled && hda->probe_continued)
1362                         snd_hda_unlock_devices(&chip->bus);
1363                 if (hda->vga_switcheroo_registered)
1364                         vga_switcheroo_unregister_client(chip->pci);
1365         }
1366
1367         if (bus->chip_init) {
1368                 azx_clear_irq_pending(chip);
1369                 azx_stop_all_streams(chip);
1370                 azx_stop_chip(chip);
1371         }
1372
1373         if (bus->irq >= 0)
1374                 free_irq(bus->irq, (void*)chip);
1375         if (chip->msi)
1376                 pci_disable_msi(chip->pci);
1377         iounmap(bus->remap_addr);
1378
1379         azx_free_stream_pages(chip);
1380         azx_free_streams(chip);
1381         snd_hdac_bus_exit(bus);
1382
1383         if (chip->region_requested)
1384                 pci_release_regions(chip->pci);
1385
1386         pci_disable_device(chip->pci);
1387 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1388         release_firmware(chip->fw);
1389 #endif
1390
1391         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1392                 if (hda->need_i915_power)
1393                         snd_hdac_display_power(bus, false);
1394         }
1395         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1396                 snd_hdac_i915_exit(bus);
1397         kfree(hda);
1398
1399         return 0;
1400 }
1401
1402 static int azx_dev_disconnect(struct snd_device *device)
1403 {
1404         struct azx *chip = device->device_data;
1405
1406         chip->bus.shutdown = 1;
1407         return 0;
1408 }
1409
1410 static int azx_dev_free(struct snd_device *device)
1411 {
1412         return azx_free(device->device_data);
1413 }
1414
1415 #ifdef SUPPORT_VGA_SWITCHEROO
1416 /*
1417  * Check of disabled HDMI controller by vga_switcheroo
1418  */
1419 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1420 {
1421         struct pci_dev *p;
1422
1423         /* check only discrete GPU */
1424         switch (pci->vendor) {
1425         case PCI_VENDOR_ID_ATI:
1426         case PCI_VENDOR_ID_AMD:
1427         case PCI_VENDOR_ID_NVIDIA:
1428                 if (pci->devfn == 1) {
1429                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1430                                                         pci->bus->number, 0);
1431                         if (p) {
1432                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1433                                         return p;
1434                                 pci_dev_put(p);
1435                         }
1436                 }
1437                 break;
1438         }
1439         return NULL;
1440 }
1441
1442 static bool check_hdmi_disabled(struct pci_dev *pci)
1443 {
1444         bool vga_inactive = false;
1445         struct pci_dev *p = get_bound_vga(pci);
1446
1447         if (p) {
1448                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1449                         vga_inactive = true;
1450                 pci_dev_put(p);
1451         }
1452         return vga_inactive;
1453 }
1454 #endif /* SUPPORT_VGA_SWITCHEROO */
1455
1456 /*
1457  * white/black-listing for position_fix
1458  */
1459 static struct snd_pci_quirk position_fix_list[] = {
1460         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1461         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1462         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1463         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1464         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1465         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1466         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1467         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1468         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1469         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1470         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1471         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1472         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1473         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1474         {}
1475 };
1476
1477 static int check_position_fix(struct azx *chip, int fix)
1478 {
1479         const struct snd_pci_quirk *q;
1480
1481         switch (fix) {
1482         case POS_FIX_AUTO:
1483         case POS_FIX_LPIB:
1484         case POS_FIX_POSBUF:
1485         case POS_FIX_VIACOMBO:
1486         case POS_FIX_COMBO:
1487         case POS_FIX_SKL:
1488                 return fix;
1489         }
1490
1491         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1492         if (q) {
1493                 dev_info(chip->card->dev,
1494                          "position_fix set to %d for device %04x:%04x\n",
1495                          q->value, q->subvendor, q->subdevice);
1496                 return q->value;
1497         }
1498
1499         /* Check VIA/ATI HD Audio Controller exist */
1500         if (chip->driver_type == AZX_DRIVER_VIA) {
1501                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1502                 return POS_FIX_VIACOMBO;
1503         }
1504         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1505                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1506                 return POS_FIX_LPIB;
1507         }
1508         if (chip->driver_type == AZX_DRIVER_SKL) {
1509                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1510                 return POS_FIX_SKL;
1511         }
1512         return POS_FIX_AUTO;
1513 }
1514
1515 static void assign_position_fix(struct azx *chip, int fix)
1516 {
1517         static azx_get_pos_callback_t callbacks[] = {
1518                 [POS_FIX_AUTO] = NULL,
1519                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1520                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1521                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1522                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1523                 [POS_FIX_SKL] = azx_get_pos_skl,
1524         };
1525
1526         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1527
1528         /* combo mode uses LPIB only for playback */
1529         if (fix == POS_FIX_COMBO)
1530                 chip->get_position[1] = NULL;
1531
1532         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1533             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1534                 chip->get_delay[0] = chip->get_delay[1] =
1535                         azx_get_delay_from_lpib;
1536         }
1537
1538 }
1539
1540 /*
1541  * black-lists for probe_mask
1542  */
1543 static struct snd_pci_quirk probe_mask_list[] = {
1544         /* Thinkpad often breaks the controller communication when accessing
1545          * to the non-working (or non-existing) modem codec slot.
1546          */
1547         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1548         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1549         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1550         /* broken BIOS */
1551         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1552         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1553         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1554         /* forced codec slots */
1555         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1556         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1557         /* WinFast VP200 H (Teradici) user reported broken communication */
1558         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1559         {}
1560 };
1561
1562 #define AZX_FORCE_CODEC_MASK    0x100
1563
1564 static void check_probe_mask(struct azx *chip, int dev)
1565 {
1566         const struct snd_pci_quirk *q;
1567
1568         chip->codec_probe_mask = probe_mask[dev];
1569         if (chip->codec_probe_mask == -1) {
1570                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1571                 if (q) {
1572                         dev_info(chip->card->dev,
1573                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1574                                  q->value, q->subvendor, q->subdevice);
1575                         chip->codec_probe_mask = q->value;
1576                 }
1577         }
1578
1579         /* check forced option */
1580         if (chip->codec_probe_mask != -1 &&
1581             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1582                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1583                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1584                          (int)azx_bus(chip)->codec_mask);
1585         }
1586 }
1587
1588 /*
1589  * white/black-list for enable_msi
1590  */
1591 static struct snd_pci_quirk msi_black_list[] = {
1592         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1593         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1594         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1595         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1596         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1597         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1598         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1599         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1600         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1601         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1602         {}
1603 };
1604
1605 static void check_msi(struct azx *chip)
1606 {
1607         const struct snd_pci_quirk *q;
1608
1609         if (enable_msi >= 0) {
1610                 chip->msi = !!enable_msi;
1611                 return;
1612         }
1613         chip->msi = 1;  /* enable MSI as default */
1614         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1615         if (q) {
1616                 dev_info(chip->card->dev,
1617                          "msi for device %04x:%04x set to %d\n",
1618                          q->subvendor, q->subdevice, q->value);
1619                 chip->msi = q->value;
1620                 return;
1621         }
1622
1623         /* NVidia chipsets seem to cause troubles with MSI */
1624         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1625                 dev_info(chip->card->dev, "Disabling MSI\n");
1626                 chip->msi = 0;
1627         }
1628 }
1629
1630 /* check the snoop mode availability */
1631 static void azx_check_snoop_available(struct azx *chip)
1632 {
1633         int snoop = hda_snoop;
1634
1635         if (snoop >= 0) {
1636                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1637                          snoop ? "snoop" : "non-snoop");
1638                 chip->snoop = snoop;
1639                 return;
1640         }
1641
1642         snoop = true;
1643         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1644             chip->driver_type == AZX_DRIVER_VIA) {
1645                 /* force to non-snoop mode for a new VIA controller
1646                  * when BIOS is set
1647                  */
1648                 u8 val;
1649                 pci_read_config_byte(chip->pci, 0x42, &val);
1650                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1651                         snoop = false;
1652         }
1653
1654         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1655                 snoop = false;
1656
1657         chip->snoop = snoop;
1658         if (!snoop)
1659                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1660 }
1661
1662 static void azx_probe_work(struct work_struct *work)
1663 {
1664         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1665         azx_probe_continue(&hda->chip);
1666 }
1667
1668 static int default_bdl_pos_adj(struct azx *chip)
1669 {
1670         /* some exceptions: Atoms seem problematic with value 1 */
1671         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1672                 switch (chip->pci->device) {
1673                 case 0x0f04: /* Baytrail */
1674                 case 0x2284: /* Braswell */
1675                         return 32;
1676                 }
1677         }
1678
1679         switch (chip->driver_type) {
1680         case AZX_DRIVER_ICH:
1681         case AZX_DRIVER_PCH:
1682                 return 1;
1683         default:
1684                 return 32;
1685         }
1686 }
1687
1688 /*
1689  * constructor
1690  */
1691 static const struct hdac_io_ops pci_hda_io_ops;
1692 static const struct hda_controller_ops pci_hda_ops;
1693
1694 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1695                       int dev, unsigned int driver_caps,
1696                       struct azx **rchip)
1697 {
1698         static struct snd_device_ops ops = {
1699                 .dev_disconnect = azx_dev_disconnect,
1700                 .dev_free = azx_dev_free,
1701         };
1702         struct hda_intel *hda;
1703         struct azx *chip;
1704         int err;
1705
1706         *rchip = NULL;
1707
1708         err = pci_enable_device(pci);
1709         if (err < 0)
1710                 return err;
1711
1712         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1713         if (!hda) {
1714                 pci_disable_device(pci);
1715                 return -ENOMEM;
1716         }
1717
1718         chip = &hda->chip;
1719         mutex_init(&chip->open_mutex);
1720         chip->card = card;
1721         chip->pci = pci;
1722         chip->ops = &pci_hda_ops;
1723         chip->driver_caps = driver_caps;
1724         chip->driver_type = driver_caps & 0xff;
1725         check_msi(chip);
1726         chip->dev_index = dev;
1727         chip->jackpoll_ms = jackpoll_ms;
1728         INIT_LIST_HEAD(&chip->pcm_list);
1729         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1730         INIT_LIST_HEAD(&hda->list);
1731         init_vga_switcheroo(chip);
1732         init_completion(&hda->probe_wait);
1733
1734         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1735
1736         check_probe_mask(chip, dev);
1737
1738         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1739                 chip->fallback_to_single_cmd = 1;
1740         else /* explicitly set to single_cmd or not */
1741                 chip->single_cmd = single_cmd;
1742
1743         azx_check_snoop_available(chip);
1744
1745         if (bdl_pos_adj[dev] < 0)
1746                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1747         else
1748                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1749
1750         /* Workaround for a communication error on CFL (bko#199007) */
1751         if (IS_CFL(pci))
1752                 chip->polling_mode = 1;
1753
1754         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1755         if (err < 0) {
1756                 kfree(hda);
1757                 pci_disable_device(pci);
1758                 return err;
1759         }
1760
1761         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1762                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1763                 chip->bus.needs_damn_long_delay = 1;
1764         }
1765
1766         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1767         if (err < 0) {
1768                 dev_err(card->dev, "Error creating device [card]!\n");
1769                 azx_free(chip);
1770                 return err;
1771         }
1772
1773         /* continue probing in work context as may trigger request module */
1774         INIT_WORK(&hda->probe_work, azx_probe_work);
1775
1776         *rchip = chip;
1777
1778         return 0;
1779 }
1780
1781 static int azx_first_init(struct azx *chip)
1782 {
1783         int dev = chip->dev_index;
1784         struct pci_dev *pci = chip->pci;
1785         struct snd_card *card = chip->card;
1786         struct hdac_bus *bus = azx_bus(chip);
1787         int err;
1788         unsigned short gcap;
1789         unsigned int dma_bits = 64;
1790
1791 #if BITS_PER_LONG != 64
1792         /* Fix up base address on ULI M5461 */
1793         if (chip->driver_type == AZX_DRIVER_ULI) {
1794                 u16 tmp3;
1795                 pci_read_config_word(pci, 0x40, &tmp3);
1796                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1797                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1798         }
1799 #endif
1800
1801         err = pci_request_regions(pci, "ICH HD audio");
1802         if (err < 0)
1803                 return err;
1804         chip->region_requested = 1;
1805
1806         bus->addr = pci_resource_start(pci, 0);
1807         bus->remap_addr = pci_ioremap_bar(pci, 0);
1808         if (bus->remap_addr == NULL) {
1809                 dev_err(card->dev, "ioremap error\n");
1810                 return -ENXIO;
1811         }
1812
1813         if (chip->driver_type == AZX_DRIVER_SKL)
1814                 snd_hdac_bus_parse_capabilities(bus);
1815
1816         /*
1817          * Some Intel CPUs has always running timer (ART) feature and
1818          * controller may have Global time sync reporting capability, so
1819          * check both of these before declaring synchronized time reporting
1820          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1821          */
1822         chip->gts_present = false;
1823
1824 #ifdef CONFIG_X86
1825         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1826                 chip->gts_present = true;
1827 #endif
1828
1829         if (chip->msi) {
1830                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1831                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1832                         pci->no_64bit_msi = true;
1833                 }
1834                 if (pci_enable_msi(pci) < 0)
1835                         chip->msi = 0;
1836         }
1837
1838         if (azx_acquire_irq(chip, 0) < 0)
1839                 return -EBUSY;
1840
1841         pci_set_master(pci);
1842         synchronize_irq(bus->irq);
1843
1844         gcap = azx_readw(chip, GCAP);
1845         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1846
1847         /* AMD devices support 40 or 48bit DMA, take the safe one */
1848         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1849                 dma_bits = 40;
1850
1851         /* disable SB600 64bit support for safety */
1852         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1853                 struct pci_dev *p_smbus;
1854                 dma_bits = 40;
1855                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1856                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1857                                          NULL);
1858                 if (p_smbus) {
1859                         if (p_smbus->revision < 0x30)
1860                                 gcap &= ~AZX_GCAP_64OK;
1861                         pci_dev_put(p_smbus);
1862                 }
1863         }
1864
1865         /* NVidia hardware normally only supports up to 40 bits of DMA */
1866         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1867                 dma_bits = 40;
1868
1869         /* disable 64bit DMA address on some devices */
1870         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1871                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1872                 gcap &= ~AZX_GCAP_64OK;
1873         }
1874
1875         /* disable buffer size rounding to 128-byte multiples if supported */
1876         if (align_buffer_size >= 0)
1877                 chip->align_buffer_size = !!align_buffer_size;
1878         else {
1879                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1880                         chip->align_buffer_size = 0;
1881                 else
1882                         chip->align_buffer_size = 1;
1883         }
1884
1885         /* allow 64bit DMA address if supported by H/W */
1886         if (!(gcap & AZX_GCAP_64OK))
1887                 dma_bits = 32;
1888         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1889                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1890         } else {
1891                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1892                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1893         }
1894
1895         /* read number of streams from GCAP register instead of using
1896          * hardcoded value
1897          */
1898         chip->capture_streams = (gcap >> 8) & 0x0f;
1899         chip->playback_streams = (gcap >> 12) & 0x0f;
1900         if (!chip->playback_streams && !chip->capture_streams) {
1901                 /* gcap didn't give any info, switching to old method */
1902
1903                 switch (chip->driver_type) {
1904                 case AZX_DRIVER_ULI:
1905                         chip->playback_streams = ULI_NUM_PLAYBACK;
1906                         chip->capture_streams = ULI_NUM_CAPTURE;
1907                         break;
1908                 case AZX_DRIVER_ATIHDMI:
1909                 case AZX_DRIVER_ATIHDMI_NS:
1910                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1911                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1912                         break;
1913                 case AZX_DRIVER_GENERIC:
1914                 default:
1915                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1916                         chip->capture_streams = ICH6_NUM_CAPTURE;
1917                         break;
1918                 }
1919         }
1920         chip->capture_index_offset = 0;
1921         chip->playback_index_offset = chip->capture_streams;
1922         chip->num_streams = chip->playback_streams + chip->capture_streams;
1923
1924         /* sanity check for the SDxCTL.STRM field overflow */
1925         if (chip->num_streams > 15 &&
1926             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1927                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1928                          "forcing separate stream tags", chip->num_streams);
1929                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1930         }
1931
1932         /* initialize streams */
1933         err = azx_init_streams(chip);
1934         if (err < 0)
1935                 return err;
1936
1937         err = azx_alloc_stream_pages(chip);
1938         if (err < 0)
1939                 return err;
1940
1941         /* initialize chip */
1942         azx_init_pci(chip);
1943
1944         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1945                 snd_hdac_i915_set_bclk(bus);
1946
1947         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1948
1949         /* codec detection */
1950         if (!azx_bus(chip)->codec_mask) {
1951                 dev_err(card->dev, "no codecs found!\n");
1952                 return -ENODEV;
1953         }
1954
1955         strcpy(card->driver, "HDA-Intel");
1956         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1957                 sizeof(card->shortname));
1958         snprintf(card->longname, sizeof(card->longname),
1959                  "%s at 0x%lx irq %i",
1960                  card->shortname, bus->addr, bus->irq);
1961
1962         return 0;
1963 }
1964
1965 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1966 /* callback from request_firmware_nowait() */
1967 static void azx_firmware_cb(const struct firmware *fw, void *context)
1968 {
1969         struct snd_card *card = context;
1970         struct azx *chip = card->private_data;
1971         struct pci_dev *pci = chip->pci;
1972
1973         if (!fw) {
1974                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1975                 goto error;
1976         }
1977
1978         chip->fw = fw;
1979         if (!chip->disabled) {
1980                 /* continue probing */
1981                 if (azx_probe_continue(chip))
1982                         goto error;
1983         }
1984         return; /* OK */
1985
1986  error:
1987         snd_card_free(card);
1988         pci_set_drvdata(pci, NULL);
1989 }
1990 #endif
1991
1992 /*
1993  * HDA controller ops.
1994  */
1995
1996 /* PCI register access. */
1997 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1998 {
1999         writel(value, addr);
2000 }
2001
2002 static u32 pci_azx_readl(u32 __iomem *addr)
2003 {
2004         return readl(addr);
2005 }
2006
2007 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2008 {
2009         writew(value, addr);
2010 }
2011
2012 static u16 pci_azx_readw(u16 __iomem *addr)
2013 {
2014         return readw(addr);
2015 }
2016
2017 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2018 {
2019         writeb(value, addr);
2020 }
2021
2022 static u8 pci_azx_readb(u8 __iomem *addr)
2023 {
2024         return readb(addr);
2025 }
2026
2027 static int disable_msi_reset_irq(struct azx *chip)
2028 {
2029         struct hdac_bus *bus = azx_bus(chip);
2030         int err;
2031
2032         free_irq(bus->irq, chip);
2033         bus->irq = -1;
2034         pci_disable_msi(chip->pci);
2035         chip->msi = 0;
2036         err = azx_acquire_irq(chip, 1);
2037         if (err < 0)
2038                 return err;
2039
2040         return 0;
2041 }
2042
2043 /* DMA page allocation helpers.  */
2044 static int dma_alloc_pages(struct hdac_bus *bus,
2045                            int type,
2046                            size_t size,
2047                            struct snd_dma_buffer *buf)
2048 {
2049         struct azx *chip = bus_to_azx(bus);
2050         int err;
2051
2052         err = snd_dma_alloc_pages(type,
2053                                   bus->dev,
2054                                   size, buf);
2055         if (err < 0)
2056                 return err;
2057         mark_pages_wc(chip, buf, true);
2058         return 0;
2059 }
2060
2061 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2062 {
2063         struct azx *chip = bus_to_azx(bus);
2064
2065         mark_pages_wc(chip, buf, false);
2066         snd_dma_free_pages(buf);
2067 }
2068
2069 static int substream_alloc_pages(struct azx *chip,
2070                                  struct snd_pcm_substream *substream,
2071                                  size_t size)
2072 {
2073         struct azx_dev *azx_dev = get_azx_dev(substream);
2074         int ret;
2075
2076         mark_runtime_wc(chip, azx_dev, substream, false);
2077         ret = snd_pcm_lib_malloc_pages(substream, size);
2078         if (ret < 0)
2079                 return ret;
2080         mark_runtime_wc(chip, azx_dev, substream, true);
2081         return 0;
2082 }
2083
2084 static int substream_free_pages(struct azx *chip,
2085                                 struct snd_pcm_substream *substream)
2086 {
2087         struct azx_dev *azx_dev = get_azx_dev(substream);
2088         mark_runtime_wc(chip, azx_dev, substream, false);
2089         return snd_pcm_lib_free_pages(substream);
2090 }
2091
2092 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2093                              struct vm_area_struct *area)
2094 {
2095 #ifdef CONFIG_X86
2096         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2097         struct azx *chip = apcm->chip;
2098         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
2099                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2100 #endif
2101 }
2102
2103 static const struct hdac_io_ops pci_hda_io_ops = {
2104         .reg_writel = pci_azx_writel,
2105         .reg_readl = pci_azx_readl,
2106         .reg_writew = pci_azx_writew,
2107         .reg_readw = pci_azx_readw,
2108         .reg_writeb = pci_azx_writeb,
2109         .reg_readb = pci_azx_readb,
2110         .dma_alloc_pages = dma_alloc_pages,
2111         .dma_free_pages = dma_free_pages,
2112 };
2113
2114 static const struct hda_controller_ops pci_hda_ops = {
2115         .disable_msi_reset_irq = disable_msi_reset_irq,
2116         .substream_alloc_pages = substream_alloc_pages,
2117         .substream_free_pages = substream_free_pages,
2118         .pcm_mmap_prepare = pcm_mmap_prepare,
2119         .position_check = azx_position_check,
2120         .link_power = azx_intel_link_power,
2121 };
2122
2123 static int azx_probe(struct pci_dev *pci,
2124                      const struct pci_device_id *pci_id)
2125 {
2126         static int dev;
2127         struct snd_card *card;
2128         struct hda_intel *hda;
2129         struct azx *chip;
2130         bool schedule_probe;
2131         int err;
2132
2133         if (dev >= SNDRV_CARDS)
2134                 return -ENODEV;
2135         if (!enable[dev]) {
2136                 dev++;
2137                 return -ENOENT;
2138         }
2139
2140         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2141                            0, &card);
2142         if (err < 0) {
2143                 dev_err(&pci->dev, "Error creating card!\n");
2144                 return err;
2145         }
2146
2147         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2148         if (err < 0)
2149                 goto out_free;
2150         card->private_data = chip;
2151         hda = container_of(chip, struct hda_intel, chip);
2152
2153         pci_set_drvdata(pci, card);
2154
2155         err = register_vga_switcheroo(chip);
2156         if (err < 0) {
2157                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2158                 goto out_free;
2159         }
2160
2161         if (check_hdmi_disabled(pci)) {
2162                 dev_info(card->dev, "VGA controller is disabled\n");
2163                 dev_info(card->dev, "Delaying initialization\n");
2164                 chip->disabled = true;
2165         }
2166
2167         schedule_probe = !chip->disabled;
2168
2169 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2170         if (patch[dev] && *patch[dev]) {
2171                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2172                          patch[dev]);
2173                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2174                                               &pci->dev, GFP_KERNEL, card,
2175                                               azx_firmware_cb);
2176                 if (err < 0)
2177                         goto out_free;
2178                 schedule_probe = false; /* continued in azx_firmware_cb() */
2179         }
2180 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2181
2182 #ifndef CONFIG_SND_HDA_I915
2183         if (CONTROLLER_IN_GPU(pci))
2184                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2185 #endif
2186
2187         if (schedule_probe)
2188                 schedule_work(&hda->probe_work);
2189
2190         dev++;
2191         if (chip->disabled)
2192                 complete_all(&hda->probe_wait);
2193         return 0;
2194
2195 out_free:
2196         snd_card_free(card);
2197         return err;
2198 }
2199
2200 #ifdef CONFIG_PM
2201 /* On some boards setting power_save to a non 0 value leads to clicking /
2202  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2203  * figure out how to avoid these sounds, but that is not always feasible.
2204  * So we keep a list of devices where we disable powersaving as its known
2205  * to causes problems on these devices.
2206  */
2207 static struct snd_pci_quirk power_save_blacklist[] = {
2208         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2209         SND_PCI_QUIRK(0x1849, 0x0c0c, "Asrock B85M-ITX", 0),
2210         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2211         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2212         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2213         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2214         {}
2215 };
2216 #endif /* CONFIG_PM */
2217
2218 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2219 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2220         [AZX_DRIVER_NVIDIA] = 8,
2221         [AZX_DRIVER_TERA] = 1,
2222 };
2223
2224 static int azx_probe_continue(struct azx *chip)
2225 {
2226         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2227         struct hdac_bus *bus = azx_bus(chip);
2228         struct pci_dev *pci = chip->pci;
2229         struct hda_codec *codec;
2230         int dev = chip->dev_index;
2231         int val;
2232         int err;
2233
2234         hda->probe_continued = 1;
2235
2236         /* bind with i915 if needed */
2237         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2238                 err = snd_hdac_i915_init(bus);
2239                 if (err < 0) {
2240                         /* if the controller is bound only with HDMI/DP
2241                          * (for HSW and BDW), we need to abort the probe;
2242                          * for other chips, still continue probing as other
2243                          * codecs can be on the same link.
2244                          */
2245                         if (CONTROLLER_IN_GPU(pci)) {
2246                                 dev_err(chip->card->dev,
2247                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2248                                 goto out_free;
2249                         } else {
2250                                 /* don't bother any longer */
2251                                 chip->driver_caps &=
2252                                         ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2253                         }
2254                 }
2255         }
2256
2257         /* Request display power well for the HDA controller or codec. For
2258          * Haswell/Broadwell, both the display HDA controller and codec need
2259          * this power. For other platforms, like Baytrail/Braswell, only the
2260          * display codec needs the power and it can be released after probe.
2261          */
2262         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2263                 /* HSW/BDW controllers need this power */
2264                 if (CONTROLLER_IN_GPU(pci))
2265                         hda->need_i915_power = 1;
2266
2267                 err = snd_hdac_display_power(bus, true);
2268                 if (err < 0) {
2269                         dev_err(chip->card->dev,
2270                                 "Cannot turn on display power on i915\n");
2271                         goto i915_power_fail;
2272                 }
2273         }
2274
2275         err = azx_first_init(chip);
2276         if (err < 0)
2277                 goto out_free;
2278
2279 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2280         chip->beep_mode = beep_mode[dev];
2281 #endif
2282
2283         /* create codec instances */
2284         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2285         if (err < 0)
2286                 goto out_free;
2287
2288 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2289         if (chip->fw) {
2290                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2291                                          chip->fw->data);
2292                 if (err < 0)
2293                         goto out_free;
2294 #ifndef CONFIG_PM
2295                 release_firmware(chip->fw); /* no longer needed */
2296                 chip->fw = NULL;
2297 #endif
2298         }
2299 #endif
2300         if ((probe_only[dev] & 1) == 0) {
2301                 err = azx_codec_configure(chip);
2302                 if (err < 0)
2303                         goto out_free;
2304         }
2305
2306         err = snd_card_register(chip->card);
2307         if (err < 0)
2308                 goto out_free;
2309
2310         chip->running = 1;
2311         azx_add_card_list(chip);
2312
2313         val = power_save;
2314 #ifdef CONFIG_PM
2315         if (pm_blacklist) {
2316                 const struct snd_pci_quirk *q;
2317
2318                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2319                 if (q && val) {
2320                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2321                                  q->subvendor, q->subdevice);
2322                         val = 0;
2323                 }
2324         }
2325 #endif /* CONFIG_PM */
2326         /*
2327          * The discrete GPU cannot power down unless the HDA controller runtime
2328          * suspends, so activate runtime PM on codecs even if power_save == 0.
2329          */
2330         if (use_vga_switcheroo(hda))
2331                 list_for_each_codec(codec, &chip->bus)
2332                         codec->auto_runtime_pm = 1;
2333
2334         snd_hda_set_power_save(&chip->bus, val * 1000);
2335         if (azx_has_pm_runtime(chip))
2336                 pm_runtime_put_autosuspend(&pci->dev);
2337
2338 out_free:
2339         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2340                 && !hda->need_i915_power)
2341                 snd_hdac_display_power(bus, false);
2342
2343 i915_power_fail:
2344         if (err < 0)
2345                 hda->init_failed = 1;
2346         complete_all(&hda->probe_wait);
2347         return err;
2348 }
2349
2350 static void azx_remove(struct pci_dev *pci)
2351 {
2352         struct snd_card *card = pci_get_drvdata(pci);
2353         struct azx *chip;
2354         struct hda_intel *hda;
2355
2356         if (card) {
2357                 /* cancel the pending probing work */
2358                 chip = card->private_data;
2359                 hda = container_of(chip, struct hda_intel, chip);
2360                 /* FIXME: below is an ugly workaround.
2361                  * Both device_release_driver() and driver_probe_device()
2362                  * take *both* the device's and its parent's lock before
2363                  * calling the remove() and probe() callbacks.  The codec
2364                  * probe takes the locks of both the codec itself and its
2365                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2366                  * the PCI controller is unbound, it takes its lock, too
2367                  * ==> ouch, a deadlock!
2368                  * As a workaround, we unlock temporarily here the controller
2369                  * device during cancel_work_sync() call.
2370                  */
2371                 device_unlock(&pci->dev);
2372                 cancel_work_sync(&hda->probe_work);
2373                 device_lock(&pci->dev);
2374
2375                 snd_card_free(card);
2376         }
2377 }
2378
2379 static void azx_shutdown(struct pci_dev *pci)
2380 {
2381         struct snd_card *card = pci_get_drvdata(pci);
2382         struct azx *chip;
2383
2384         if (!card)
2385                 return;
2386         chip = card->private_data;
2387         if (chip && chip->running)
2388                 azx_stop_chip(chip);
2389 }
2390
2391 /* PCI IDs */
2392 static const struct pci_device_id azx_ids[] = {
2393         /* CPT */
2394         { PCI_DEVICE(0x8086, 0x1c20),
2395           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2396         /* PBG */
2397         { PCI_DEVICE(0x8086, 0x1d20),
2398           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2399         /* Panther Point */
2400         { PCI_DEVICE(0x8086, 0x1e20),
2401           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2402         /* Lynx Point */
2403         { PCI_DEVICE(0x8086, 0x8c20),
2404           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2405         /* 9 Series */
2406         { PCI_DEVICE(0x8086, 0x8ca0),
2407           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2408         /* Wellsburg */
2409         { PCI_DEVICE(0x8086, 0x8d20),
2410           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2411         { PCI_DEVICE(0x8086, 0x8d21),
2412           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2413         /* Lewisburg */
2414         { PCI_DEVICE(0x8086, 0xa1f0),
2415           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2416         { PCI_DEVICE(0x8086, 0xa270),
2417           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2418         /* Lynx Point-LP */
2419         { PCI_DEVICE(0x8086, 0x9c20),
2420           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2421         /* Lynx Point-LP */
2422         { PCI_DEVICE(0x8086, 0x9c21),
2423           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2424         /* Wildcat Point-LP */
2425         { PCI_DEVICE(0x8086, 0x9ca0),
2426           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2427         /* Sunrise Point */
2428         { PCI_DEVICE(0x8086, 0xa170),
2429           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2430         /* Sunrise Point-LP */
2431         { PCI_DEVICE(0x8086, 0x9d70),
2432           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2433         /* Kabylake */
2434         { PCI_DEVICE(0x8086, 0xa171),
2435           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2436         /* Kabylake-LP */
2437         { PCI_DEVICE(0x8086, 0x9d71),
2438           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2439         /* Kabylake-H */
2440         { PCI_DEVICE(0x8086, 0xa2f0),
2441           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2442         /* Coffelake */
2443         { PCI_DEVICE(0x8086, 0xa348),
2444           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2445         /* Cannonlake */
2446         { PCI_DEVICE(0x8086, 0x9dc8),
2447           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2448         /* Icelake */
2449         { PCI_DEVICE(0x8086, 0x34c8),
2450           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2451         /* Broxton-P(Apollolake) */
2452         { PCI_DEVICE(0x8086, 0x5a98),
2453           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2454         /* Broxton-T */
2455         { PCI_DEVICE(0x8086, 0x1a98),
2456           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2457         /* Gemini-Lake */
2458         { PCI_DEVICE(0x8086, 0x3198),
2459           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2460         /* Haswell */
2461         { PCI_DEVICE(0x8086, 0x0a0c),
2462           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2463         { PCI_DEVICE(0x8086, 0x0c0c),
2464           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2465         { PCI_DEVICE(0x8086, 0x0d0c),
2466           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2467         /* Broadwell */
2468         { PCI_DEVICE(0x8086, 0x160c),
2469           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2470         /* 5 Series/3400 */
2471         { PCI_DEVICE(0x8086, 0x3b56),
2472           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2473         /* Poulsbo */
2474         { PCI_DEVICE(0x8086, 0x811b),
2475           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2476         /* Oaktrail */
2477         { PCI_DEVICE(0x8086, 0x080a),
2478           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2479         /* BayTrail */
2480         { PCI_DEVICE(0x8086, 0x0f04),
2481           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2482         /* Braswell */
2483         { PCI_DEVICE(0x8086, 0x2284),
2484           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2485         /* ICH6 */
2486         { PCI_DEVICE(0x8086, 0x2668),
2487           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2488         /* ICH7 */
2489         { PCI_DEVICE(0x8086, 0x27d8),
2490           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2491         /* ESB2 */
2492         { PCI_DEVICE(0x8086, 0x269a),
2493           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2494         /* ICH8 */
2495         { PCI_DEVICE(0x8086, 0x284b),
2496           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2497         /* ICH9 */
2498         { PCI_DEVICE(0x8086, 0x293e),
2499           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2500         /* ICH9 */
2501         { PCI_DEVICE(0x8086, 0x293f),
2502           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2503         /* ICH10 */
2504         { PCI_DEVICE(0x8086, 0x3a3e),
2505           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2506         /* ICH10 */
2507         { PCI_DEVICE(0x8086, 0x3a6e),
2508           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2509         /* Generic Intel */
2510         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2511           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2512           .class_mask = 0xffffff,
2513           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2514         /* ATI SB 450/600/700/800/900 */
2515         { PCI_DEVICE(0x1002, 0x437b),
2516           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2517         { PCI_DEVICE(0x1002, 0x4383),
2518           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2519         /* AMD Hudson */
2520         { PCI_DEVICE(0x1022, 0x780d),
2521           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2522         /* AMD Raven */
2523         { PCI_DEVICE(0x1022, 0x15e3),
2524           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2525         /* ATI HDMI */
2526         { PCI_DEVICE(0x1002, 0x0002),
2527           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2528         { PCI_DEVICE(0x1002, 0x1308),
2529           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2530         { PCI_DEVICE(0x1002, 0x157a),
2531           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2532         { PCI_DEVICE(0x1002, 0x15b3),
2533           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2534         { PCI_DEVICE(0x1002, 0x793b),
2535           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536         { PCI_DEVICE(0x1002, 0x7919),
2537           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538         { PCI_DEVICE(0x1002, 0x960f),
2539           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540         { PCI_DEVICE(0x1002, 0x970f),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0x9840),
2543           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2544         { PCI_DEVICE(0x1002, 0xaa00),
2545           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546         { PCI_DEVICE(0x1002, 0xaa08),
2547           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548         { PCI_DEVICE(0x1002, 0xaa10),
2549           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2550         { PCI_DEVICE(0x1002, 0xaa18),
2551           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2552         { PCI_DEVICE(0x1002, 0xaa20),
2553           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2554         { PCI_DEVICE(0x1002, 0xaa28),
2555           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2556         { PCI_DEVICE(0x1002, 0xaa30),
2557           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2558         { PCI_DEVICE(0x1002, 0xaa38),
2559           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2560         { PCI_DEVICE(0x1002, 0xaa40),
2561           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2562         { PCI_DEVICE(0x1002, 0xaa48),
2563           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2564         { PCI_DEVICE(0x1002, 0xaa50),
2565           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2566         { PCI_DEVICE(0x1002, 0xaa58),
2567           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2568         { PCI_DEVICE(0x1002, 0xaa60),
2569           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2570         { PCI_DEVICE(0x1002, 0xaa68),
2571           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2572         { PCI_DEVICE(0x1002, 0xaa80),
2573           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2574         { PCI_DEVICE(0x1002, 0xaa88),
2575           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2576         { PCI_DEVICE(0x1002, 0xaa90),
2577           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2578         { PCI_DEVICE(0x1002, 0xaa98),
2579           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2580         { PCI_DEVICE(0x1002, 0x9902),
2581           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2582         { PCI_DEVICE(0x1002, 0xaaa0),
2583           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2584         { PCI_DEVICE(0x1002, 0xaaa8),
2585           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2586         { PCI_DEVICE(0x1002, 0xaab0),
2587           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2588         { PCI_DEVICE(0x1002, 0xaac0),
2589           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2590         { PCI_DEVICE(0x1002, 0xaac8),
2591           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2592         { PCI_DEVICE(0x1002, 0xaad8),
2593           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2594         { PCI_DEVICE(0x1002, 0xaae8),
2595           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2596         { PCI_DEVICE(0x1002, 0xaae0),
2597           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2598         { PCI_DEVICE(0x1002, 0xaaf0),
2599           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2600         /* VIA VT8251/VT8237A */
2601         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2602         /* VIA GFX VT7122/VX900 */
2603         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2604         /* VIA GFX VT6122/VX11 */
2605         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2606         /* SIS966 */
2607         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2608         /* ULI M5461 */
2609         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2610         /* NVIDIA MCP */
2611         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2612           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2613           .class_mask = 0xffffff,
2614           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2615         /* Teradici */
2616         { PCI_DEVICE(0x6549, 0x1200),
2617           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2618         { PCI_DEVICE(0x6549, 0x2200),
2619           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2620         /* Creative X-Fi (CA0110-IBG) */
2621         /* CTHDA chips */
2622         { PCI_DEVICE(0x1102, 0x0010),
2623           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2624         { PCI_DEVICE(0x1102, 0x0012),
2625           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2626 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2627         /* the following entry conflicts with snd-ctxfi driver,
2628          * as ctxfi driver mutates from HD-audio to native mode with
2629          * a special command sequence.
2630          */
2631         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2632           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2633           .class_mask = 0xffffff,
2634           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2635           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2636 #else
2637         /* this entry seems still valid -- i.e. without emu20kx chip */
2638         { PCI_DEVICE(0x1102, 0x0009),
2639           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2640           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2641 #endif
2642         /* CM8888 */
2643         { PCI_DEVICE(0x13f6, 0x5011),
2644           .driver_data = AZX_DRIVER_CMEDIA |
2645           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2646         /* Vortex86MX */
2647         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2648         /* VMware HDAudio */
2649         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2650         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2651         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2652           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2653           .class_mask = 0xffffff,
2654           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2655         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2656           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2657           .class_mask = 0xffffff,
2658           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2659         { 0, }
2660 };
2661 MODULE_DEVICE_TABLE(pci, azx_ids);
2662
2663 /* pci_driver definition */
2664 static struct pci_driver azx_driver = {
2665         .name = KBUILD_MODNAME,
2666         .id_table = azx_ids,
2667         .probe = azx_probe,
2668         .remove = azx_remove,
2669         .shutdown = azx_shutdown,
2670         .driver = {
2671                 .pm = AZX_PM_OPS,
2672         },
2673 };
2674
2675 module_pci_driver(azx_driver);