dbd8da5685cb5bb8ad18c4e366795ef0fa8c73d4
[muen/linux.git] / sound / pci / hda / hda_tegra.c
1 /*
2  *
3  * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  *
17  */
18
19 #include <linux/clk.h>
20 #include <linux/clocksource.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mutex.h>
31 #include <linux/of_device.h>
32 #include <linux/slab.h>
33 #include <linux/time.h>
34 #include <linux/string.h>
35 #include <linux/pm_runtime.h>
36
37 #include <sound/core.h>
38 #include <sound/initval.h>
39
40 #include <sound/hda_codec.h>
41 #include "hda_controller.h"
42
43 /* Defines for Nvidia Tegra HDA support */
44 #define HDA_BAR0           0x8000
45
46 #define HDA_CFG_CMD        0x1004
47 #define HDA_CFG_BAR0       0x1010
48
49 #define HDA_ENABLE_IO_SPACE       (1 << 0)
50 #define HDA_ENABLE_MEM_SPACE      (1 << 1)
51 #define HDA_ENABLE_BUS_MASTER     (1 << 2)
52 #define HDA_ENABLE_SERR           (1 << 8)
53 #define HDA_DISABLE_INTR          (1 << 10)
54 #define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
55 #define HDA_BAR0_FINAL_PROGRAM    (1 << 14)
56
57 /* IPFS */
58 #define HDA_IPFS_CONFIG           0x180
59 #define HDA_IPFS_EN_FPCI          0x1
60
61 #define HDA_IPFS_FPCI_BAR0        0x80
62 #define HDA_FPCI_BAR0_START       0x40
63
64 #define HDA_IPFS_INTR_MASK        0x188
65 #define HDA_IPFS_EN_INTR          (1 << 16)
66
67 /* max number of SDs */
68 #define NUM_CAPTURE_SD 1
69 #define NUM_PLAYBACK_SD 1
70
71 struct hda_tegra {
72         struct azx chip;
73         struct device *dev;
74         struct clk *hda_clk;
75         struct clk *hda2codec_2x_clk;
76         struct clk *hda2hdmi_clk;
77         void __iomem *regs;
78         struct work_struct probe_work;
79 };
80
81 #ifdef CONFIG_PM
82 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
83 module_param(power_save, bint, 0644);
84 MODULE_PARM_DESC(power_save,
85                  "Automatic power-saving timeout (in seconds, 0 = disable).");
86 #else
87 #define power_save      0
88 #endif
89
90 /*
91  * DMA page allocation ops.
92  */
93 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
94                            struct snd_dma_buffer *buf)
95 {
96         return snd_dma_alloc_pages(type, bus->dev, size, buf);
97 }
98
99 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
100 {
101         snd_dma_free_pages(buf);
102 }
103
104 /*
105  * Register access ops. Tegra HDA register access is DWORD only.
106  */
107 static void hda_tegra_writel(u32 value, u32 __iomem *addr)
108 {
109         writel(value, addr);
110 }
111
112 static u32 hda_tegra_readl(u32 __iomem *addr)
113 {
114         return readl(addr);
115 }
116
117 static void hda_tegra_writew(u16 value, u16 __iomem  *addr)
118 {
119         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
120         void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
121         u32 v;
122
123         v = readl(dword_addr);
124         v &= ~(0xffff << shift);
125         v |= value << shift;
126         writel(v, dword_addr);
127 }
128
129 static u16 hda_tegra_readw(u16 __iomem *addr)
130 {
131         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
132         void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
133         u32 v;
134
135         v = readl(dword_addr);
136         return (v >> shift) & 0xffff;
137 }
138
139 static void hda_tegra_writeb(u8 value, u8 __iomem *addr)
140 {
141         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
142         void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
143         u32 v;
144
145         v = readl(dword_addr);
146         v &= ~(0xff << shift);
147         v |= value << shift;
148         writel(v, dword_addr);
149 }
150
151 static u8 hda_tegra_readb(u8 __iomem *addr)
152 {
153         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
154         void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
155         u32 v;
156
157         v = readl(dword_addr);
158         return (v >> shift) & 0xff;
159 }
160
161 static const struct hdac_io_ops hda_tegra_io_ops = {
162         .reg_writel = hda_tegra_writel,
163         .reg_readl = hda_tegra_readl,
164         .reg_writew = hda_tegra_writew,
165         .reg_readw = hda_tegra_readw,
166         .reg_writeb = hda_tegra_writeb,
167         .reg_readb = hda_tegra_readb,
168         .dma_alloc_pages = dma_alloc_pages,
169         .dma_free_pages = dma_free_pages,
170 };
171
172 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
173
174 static void hda_tegra_init(struct hda_tegra *hda)
175 {
176         u32 v;
177
178         /* Enable PCI access */
179         v = readl(hda->regs + HDA_IPFS_CONFIG);
180         v |= HDA_IPFS_EN_FPCI;
181         writel(v, hda->regs + HDA_IPFS_CONFIG);
182
183         /* Enable MEM/IO space and bus master */
184         v = readl(hda->regs + HDA_CFG_CMD);
185         v &= ~HDA_DISABLE_INTR;
186         v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
187                 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
188         writel(v, hda->regs + HDA_CFG_CMD);
189
190         writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
191         writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
192         writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
193
194         v = readl(hda->regs + HDA_IPFS_INTR_MASK);
195         v |= HDA_IPFS_EN_INTR;
196         writel(v, hda->regs + HDA_IPFS_INTR_MASK);
197 }
198
199 static int hda_tegra_enable_clocks(struct hda_tegra *data)
200 {
201         int rc;
202
203         rc = clk_prepare_enable(data->hda_clk);
204         if (rc)
205                 return rc;
206         rc = clk_prepare_enable(data->hda2codec_2x_clk);
207         if (rc)
208                 goto disable_hda;
209         rc = clk_prepare_enable(data->hda2hdmi_clk);
210         if (rc)
211                 goto disable_codec_2x;
212
213         return 0;
214
215 disable_codec_2x:
216         clk_disable_unprepare(data->hda2codec_2x_clk);
217 disable_hda:
218         clk_disable_unprepare(data->hda_clk);
219         return rc;
220 }
221
222 #ifdef CONFIG_PM_SLEEP
223 static void hda_tegra_disable_clocks(struct hda_tegra *data)
224 {
225         clk_disable_unprepare(data->hda2hdmi_clk);
226         clk_disable_unprepare(data->hda2codec_2x_clk);
227         clk_disable_unprepare(data->hda_clk);
228 }
229
230 /*
231  * power management
232  */
233 static int hda_tegra_suspend(struct device *dev)
234 {
235         struct snd_card *card = dev_get_drvdata(dev);
236         int rc;
237
238         rc = pm_runtime_force_suspend(dev);
239         if (rc < 0)
240                 return rc;
241         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
242
243         return 0;
244 }
245
246 static int hda_tegra_resume(struct device *dev)
247 {
248         struct snd_card *card = dev_get_drvdata(dev);
249         int rc;
250
251         rc = pm_runtime_force_resume(dev);
252         if (rc < 0)
253                 return rc;
254         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
255
256         return 0;
257 }
258 #endif /* CONFIG_PM_SLEEP */
259
260 #ifdef CONFIG_PM
261 static int hda_tegra_runtime_suspend(struct device *dev)
262 {
263         struct snd_card *card = dev_get_drvdata(dev);
264         struct azx *chip = card->private_data;
265         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
266         struct hdac_bus *bus = azx_bus(chip);
267
268         if (chip && chip->running) {
269                 azx_stop_chip(chip);
270                 synchronize_irq(bus->irq);
271                 azx_enter_link_reset(chip);
272         }
273         hda_tegra_disable_clocks(hda);
274
275         return 0;
276 }
277
278 static int hda_tegra_runtime_resume(struct device *dev)
279 {
280         struct snd_card *card = dev_get_drvdata(dev);
281         struct azx *chip = card->private_data;
282         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
283         int rc;
284
285         rc = hda_tegra_enable_clocks(hda);
286         if (rc != 0)
287                 return rc;
288         if (chip && chip->running) {
289                 hda_tegra_init(hda);
290                 azx_init_chip(chip, 1);
291         }
292
293         return 0;
294 }
295 #endif /* CONFIG_PM */
296
297 static const struct dev_pm_ops hda_tegra_pm = {
298         SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
299         SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
300                            hda_tegra_runtime_resume,
301                            NULL)
302 };
303
304 static int hda_tegra_dev_disconnect(struct snd_device *device)
305 {
306         struct azx *chip = device->device_data;
307
308         chip->bus.shutdown = 1;
309         return 0;
310 }
311
312 /*
313  * destructor
314  */
315 static int hda_tegra_dev_free(struct snd_device *device)
316 {
317         struct azx *chip = device->device_data;
318         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
319
320         cancel_work_sync(&hda->probe_work);
321         if (azx_bus(chip)->chip_init) {
322                 azx_stop_all_streams(chip);
323                 azx_stop_chip(chip);
324         }
325
326         azx_free_stream_pages(chip);
327         azx_free_streams(chip);
328         snd_hdac_bus_exit(azx_bus(chip));
329
330         return 0;
331 }
332
333 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
334 {
335         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
336         struct hdac_bus *bus = azx_bus(chip);
337         struct device *dev = hda->dev;
338         struct resource *res;
339
340         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341         hda->regs = devm_ioremap_resource(dev, res);
342         if (IS_ERR(hda->regs))
343                 return PTR_ERR(hda->regs);
344
345         bus->remap_addr = hda->regs + HDA_BAR0;
346         bus->addr = res->start + HDA_BAR0;
347
348         hda_tegra_init(hda);
349
350         return 0;
351 }
352
353 static int hda_tegra_init_clk(struct hda_tegra *hda)
354 {
355         struct device *dev = hda->dev;
356
357         hda->hda_clk = devm_clk_get(dev, "hda");
358         if (IS_ERR(hda->hda_clk)) {
359                 dev_err(dev, "failed to get hda clock\n");
360                 return PTR_ERR(hda->hda_clk);
361         }
362         hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
363         if (IS_ERR(hda->hda2codec_2x_clk)) {
364                 dev_err(dev, "failed to get hda2codec_2x clock\n");
365                 return PTR_ERR(hda->hda2codec_2x_clk);
366         }
367         hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
368         if (IS_ERR(hda->hda2hdmi_clk)) {
369                 dev_err(dev, "failed to get hda2hdmi clock\n");
370                 return PTR_ERR(hda->hda2hdmi_clk);
371         }
372
373         return 0;
374 }
375
376 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
377 {
378         struct hdac_bus *bus = azx_bus(chip);
379         struct snd_card *card = chip->card;
380         int err;
381         unsigned short gcap;
382         int irq_id = platform_get_irq(pdev, 0);
383         const char *sname, *drv_name = "tegra-hda";
384         struct device_node *np = pdev->dev.of_node;
385
386         err = hda_tegra_init_chip(chip, pdev);
387         if (err)
388                 return err;
389
390         err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
391                              IRQF_SHARED, KBUILD_MODNAME, chip);
392         if (err) {
393                 dev_err(chip->card->dev,
394                         "unable to request IRQ %d, disabling device\n",
395                         irq_id);
396                 return err;
397         }
398         bus->irq = irq_id;
399
400         synchronize_irq(bus->irq);
401
402         gcap = azx_readw(chip, GCAP);
403         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
404
405         /* read number of streams from GCAP register instead of using
406          * hardcoded value
407          */
408         chip->capture_streams = (gcap >> 8) & 0x0f;
409         chip->playback_streams = (gcap >> 12) & 0x0f;
410         if (!chip->playback_streams && !chip->capture_streams) {
411                 /* gcap didn't give any info, switching to old method */
412                 chip->playback_streams = NUM_PLAYBACK_SD;
413                 chip->capture_streams = NUM_CAPTURE_SD;
414         }
415         chip->capture_index_offset = 0;
416         chip->playback_index_offset = chip->capture_streams;
417         chip->num_streams = chip->playback_streams + chip->capture_streams;
418
419         /* initialize streams */
420         err = azx_init_streams(chip);
421         if (err < 0) {
422                 dev_err(card->dev, "failed to initialize streams: %d\n", err);
423                 return err;
424         }
425
426         err = azx_alloc_stream_pages(chip);
427         if (err < 0) {
428                 dev_err(card->dev, "failed to allocate stream pages: %d\n",
429                         err);
430                 return err;
431         }
432
433         /* initialize chip */
434         azx_init_chip(chip, 1);
435
436         /* codec detection */
437         if (!bus->codec_mask) {
438                 dev_err(card->dev, "no codecs found!\n");
439                 return -ENODEV;
440         }
441
442         /* driver name */
443         strncpy(card->driver, drv_name, sizeof(card->driver));
444         /* shortname for card */
445         sname = of_get_property(np, "nvidia,model", NULL);
446         if (!sname)
447                 sname = drv_name;
448         if (strlen(sname) > sizeof(card->shortname))
449                 dev_info(card->dev, "truncating shortname for card\n");
450         strncpy(card->shortname, sname, sizeof(card->shortname));
451
452         /* longname for card */
453         snprintf(card->longname, sizeof(card->longname),
454                  "%s at 0x%lx irq %i",
455                  card->shortname, bus->addr, bus->irq);
456
457         return 0;
458 }
459
460 /*
461  * constructor
462  */
463
464 static void hda_tegra_probe_work(struct work_struct *work);
465
466 static int hda_tegra_create(struct snd_card *card,
467                             unsigned int driver_caps,
468                             struct hda_tegra *hda)
469 {
470         static struct snd_device_ops ops = {
471                 .dev_disconnect = hda_tegra_dev_disconnect,
472                 .dev_free = hda_tegra_dev_free,
473         };
474         struct azx *chip;
475         int err;
476
477         chip = &hda->chip;
478
479         mutex_init(&chip->open_mutex);
480         chip->card = card;
481         chip->ops = &hda_tegra_ops;
482         chip->driver_caps = driver_caps;
483         chip->driver_type = driver_caps & 0xff;
484         chip->dev_index = 0;
485         INIT_LIST_HEAD(&chip->pcm_list);
486
487         chip->codec_probe_mask = -1;
488
489         chip->single_cmd = false;
490         chip->snoop = true;
491
492         INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
493
494         err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
495         if (err < 0)
496                 return err;
497
498         chip->bus.needs_damn_long_delay = 1;
499
500         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
501         if (err < 0) {
502                 dev_err(card->dev, "Error creating device\n");
503                 return err;
504         }
505
506         return 0;
507 }
508
509 static const struct of_device_id hda_tegra_match[] = {
510         { .compatible = "nvidia,tegra30-hda" },
511         {},
512 };
513 MODULE_DEVICE_TABLE(of, hda_tegra_match);
514
515 static int hda_tegra_probe(struct platform_device *pdev)
516 {
517         const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
518                                           AZX_DCAPS_PM_RUNTIME;
519         struct snd_card *card;
520         struct azx *chip;
521         struct hda_tegra *hda;
522         int err;
523
524         hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
525         if (!hda)
526                 return -ENOMEM;
527         hda->dev = &pdev->dev;
528         chip = &hda->chip;
529
530         err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
531                            THIS_MODULE, 0, &card);
532         if (err < 0) {
533                 dev_err(&pdev->dev, "Error creating card!\n");
534                 return err;
535         }
536
537         err = hda_tegra_init_clk(hda);
538         if (err < 0)
539                 goto out_free;
540
541         err = hda_tegra_create(card, driver_flags, hda);
542         if (err < 0)
543                 goto out_free;
544         card->private_data = chip;
545
546         dev_set_drvdata(&pdev->dev, card);
547
548         pm_runtime_enable(hda->dev);
549         if (!azx_has_pm_runtime(chip))
550                 pm_runtime_forbid(hda->dev);
551
552         schedule_work(&hda->probe_work);
553
554         return 0;
555
556 out_free:
557         snd_card_free(card);
558         return err;
559 }
560
561 static void hda_tegra_probe_work(struct work_struct *work)
562 {
563         struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
564         struct azx *chip = &hda->chip;
565         struct platform_device *pdev = to_platform_device(hda->dev);
566         int err;
567
568         pm_runtime_get_sync(hda->dev);
569         err = hda_tegra_first_init(chip, pdev);
570         if (err < 0)
571                 goto out_free;
572
573         /* create codec instances */
574         err = azx_probe_codecs(chip, 8);
575         if (err < 0)
576                 goto out_free;
577
578         err = azx_codec_configure(chip);
579         if (err < 0)
580                 goto out_free;
581
582         err = snd_card_register(chip->card);
583         if (err < 0)
584                 goto out_free;
585
586         chip->running = 1;
587         snd_hda_set_power_save(&chip->bus, power_save * 1000);
588
589  out_free:
590         pm_runtime_put(hda->dev);
591         return; /* no error return from async probe */
592 }
593
594 static int hda_tegra_remove(struct platform_device *pdev)
595 {
596         int ret;
597
598         ret = snd_card_free(dev_get_drvdata(&pdev->dev));
599         pm_runtime_disable(&pdev->dev);
600
601         return ret;
602 }
603
604 static void hda_tegra_shutdown(struct platform_device *pdev)
605 {
606         struct snd_card *card = dev_get_drvdata(&pdev->dev);
607         struct azx *chip;
608
609         if (!card)
610                 return;
611         chip = card->private_data;
612         if (chip && chip->running)
613                 azx_stop_chip(chip);
614 }
615
616 static struct platform_driver tegra_platform_hda = {
617         .driver = {
618                 .name = "tegra-hda",
619                 .pm = &hda_tegra_pm,
620                 .of_match_table = hda_tegra_match,
621         },
622         .probe = hda_tegra_probe,
623         .remove = hda_tegra_remove,
624         .shutdown = hda_tegra_shutdown,
625 };
626 module_platform_driver(tegra_platform_hda);
627
628 MODULE_DESCRIPTION("Tegra HDA bus driver");
629 MODULE_LICENSE("GPL v2");