632f7878ff3e75ddf41705035402e4941391793c
[muen/linux.git] / sound / pci / rme9652 / hdsp.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *   ALSA driver for RME Hammerfall DSP audio interface(s)
4  *
5  *      Copyright (c) 2002  Paul Davis
6  *                          Marcus Andersson
7  *                          Thomas Charbonnel
8  */
9
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
18 #include <linux/io.h>
19 #include <linux/nospec.h>
20
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
30
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
33
34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
37
38 module_param_array(index, int, NULL, 0444);
39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id, charp, NULL, 0444);
41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable, bool, NULL, 0444);
43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
48                 "{RME HDSP-9652},"
49                 "{RME HDSP-9632}}");
50 MODULE_FIRMWARE("rpm_firmware.bin");
51 MODULE_FIRMWARE("multiface_firmware.bin");
52 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
53 MODULE_FIRMWARE("digiface_firmware.bin");
54 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
55
56 #define HDSP_MAX_CHANNELS        26
57 #define HDSP_MAX_DS_CHANNELS     14
58 #define HDSP_MAX_QS_CHANNELS     8
59 #define DIGIFACE_SS_CHANNELS     26
60 #define DIGIFACE_DS_CHANNELS     14
61 #define MULTIFACE_SS_CHANNELS    18
62 #define MULTIFACE_DS_CHANNELS    14
63 #define H9652_SS_CHANNELS        26
64 #define H9652_DS_CHANNELS        14
65 /* This does not include possible Analog Extension Boards
66    AEBs are detected at card initialization
67 */
68 #define H9632_SS_CHANNELS        12
69 #define H9632_DS_CHANNELS        8
70 #define H9632_QS_CHANNELS        4
71 #define RPM_CHANNELS             6
72
73 /* Write registers. These are defined as byte-offsets from the iobase value.
74  */
75 #define HDSP_resetPointer               0
76 #define HDSP_freqReg                    0
77 #define HDSP_outputBufferAddress        32
78 #define HDSP_inputBufferAddress         36
79 #define HDSP_controlRegister            64
80 #define HDSP_interruptConfirmation      96
81 #define HDSP_outputEnable               128
82 #define HDSP_control2Reg                256
83 #define HDSP_midiDataOut0               352
84 #define HDSP_midiDataOut1               356
85 #define HDSP_fifoData                   368
86 #define HDSP_inputEnable                384
87
88 /* Read registers. These are defined as byte-offsets from the iobase value
89  */
90
91 #define HDSP_statusRegister    0
92 #define HDSP_timecode        128
93 #define HDSP_status2Register 192
94 #define HDSP_midiDataIn0     360
95 #define HDSP_midiDataIn1     364
96 #define HDSP_midiStatusOut0  384
97 #define HDSP_midiStatusOut1  388
98 #define HDSP_midiStatusIn0   392
99 #define HDSP_midiStatusIn1   396
100 #define HDSP_fifoStatus      400
101
102 /* the meters are regular i/o-mapped registers, but offset
103    considerably from the rest. the peak registers are reset
104    when read; the least-significant 4 bits are full-scale counters;
105    the actual peak value is in the most-significant 24 bits.
106 */
107
108 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
109 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
110 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
111 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
112 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
113
114
115 /* This is for H9652 cards
116    Peak values are read downward from the base
117    Rms values are read upward
118    There are rms values for the outputs too
119    26*3 values are read in ss mode
120    14*3 in ds mode, with no gap between values
121 */
122 #define HDSP_9652_peakBase      7164
123 #define HDSP_9652_rmsBase       4096
124
125 /* c.f. the hdsp_9632_meters_t struct */
126 #define HDSP_9632_metersBase    4096
127
128 #define HDSP_IO_EXTENT     7168
129
130 /* control2 register bits */
131
132 #define HDSP_TMS                0x01
133 #define HDSP_TCK                0x02
134 #define HDSP_TDI                0x04
135 #define HDSP_JTAG               0x08
136 #define HDSP_PWDN               0x10
137 #define HDSP_PROGRAM            0x020
138 #define HDSP_CONFIG_MODE_0      0x040
139 #define HDSP_CONFIG_MODE_1      0x080
140 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
141 #define HDSP_BIGENDIAN_MODE     0x200
142 #define HDSP_RD_MULTIPLE        0x400
143 #define HDSP_9652_ENABLE_MIXER  0x800
144 #define HDSP_S200               0x800
145 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
146 #define HDSP_CYCLIC_MODE        0x1000
147 #define HDSP_TDO                0x10000000
148
149 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
150 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
151
152 /* Control Register bits */
153
154 #define HDSP_Start                (1<<0)  /* start engine */
155 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
156 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
157 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
158 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
159 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
160 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
161 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
162 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
163 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
164 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
165 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
166 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
167 #define HDSP_SyncRef2             (1<<13)
168 #define HDSP_SPDIFInputSelect0    (1<<14)
169 #define HDSP_SPDIFInputSelect1    (1<<15)
170 #define HDSP_SyncRef0             (1<<16)
171 #define HDSP_SyncRef1             (1<<17)
172 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
173 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
174 #define HDSP_Midi0InterruptEnable (1<<22)
175 #define HDSP_Midi1InterruptEnable (1<<23)
176 #define HDSP_LineOut              (1<<24)
177 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
178 #define HDSP_ADGain1              (1<<26)
179 #define HDSP_DAGain0              (1<<27)
180 #define HDSP_DAGain1              (1<<28)
181 #define HDSP_PhoneGain0           (1<<29)
182 #define HDSP_PhoneGain1           (1<<30)
183 #define HDSP_QuadSpeed            (1<<31)
184
185 /* RPM uses some of the registers for special purposes */
186 #define HDSP_RPM_Inp12            0x04A00
187 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
188 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
189 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
190 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
191 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
192
193 #define HDSP_RPM_Inp34            0x32000
194 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
195 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
196 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
197 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
198 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
199
200 #define HDSP_RPM_Bypass           0x01000
201
202 #define HDSP_RPM_Disconnect       0x00001
203
204 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
205 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
206 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
207 #define HDSP_ADGainLowGain     0
208
209 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
210 #define HDSP_DAGainHighGain      HDSP_DAGainMask
211 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
212 #define HDSP_DAGainMinus10dBV    0
213
214 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
215 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
216 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
217 #define HDSP_PhoneGainMinus12dB  0
218
219 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
220 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
221
222 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
223 #define HDSP_SPDIFInputADAT1    0
224 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
225 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
226 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
227
228 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
229 #define HDSP_SyncRef_ADAT1       0
230 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
231 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
232 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
233 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
234 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
235
236 /* Sample Clock Sources */
237
238 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
239 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
240 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
241 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
242 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
243 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
244 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
245 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
246 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
247 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
248
249 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
250
251 #define HDSP_SYNC_FROM_WORD      0
252 #define HDSP_SYNC_FROM_SPDIF     1
253 #define HDSP_SYNC_FROM_ADAT1     2
254 #define HDSP_SYNC_FROM_ADAT_SYNC 3
255 #define HDSP_SYNC_FROM_ADAT2     4
256 #define HDSP_SYNC_FROM_ADAT3     5
257
258 /* SyncCheck status */
259
260 #define HDSP_SYNC_CHECK_NO_LOCK 0
261 #define HDSP_SYNC_CHECK_LOCK    1
262 #define HDSP_SYNC_CHECK_SYNC    2
263
264 /* AutoSync references - used by "autosync_ref" control switch */
265
266 #define HDSP_AUTOSYNC_FROM_WORD      0
267 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
268 #define HDSP_AUTOSYNC_FROM_SPDIF     2
269 #define HDSP_AUTOSYNC_FROM_NONE      3
270 #define HDSP_AUTOSYNC_FROM_ADAT1     4
271 #define HDSP_AUTOSYNC_FROM_ADAT2     5
272 #define HDSP_AUTOSYNC_FROM_ADAT3     6
273
274 /* Possible sources of S/PDIF input */
275
276 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
277 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
278 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
279 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
280
281 #define HDSP_Frequency32KHz    HDSP_Frequency0
282 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
283 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
284 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
285 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
286 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
287 /* For H9632 cards */
288 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
289 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
290 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
291 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
292         return 104857600000000 / rate; // 100 MHz
293         return 110100480000000 / rate; // 105 MHz
294 */
295 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
296
297 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
298 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
299
300 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
301 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
302
303 /* Status Register bits */
304
305 #define HDSP_audioIRQPending    (1<<0)
306 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
307 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
308 #define HDSP_Lock1              (1<<2)
309 #define HDSP_Lock0              (1<<3)
310 #define HDSP_SPDIFSync          (1<<4)
311 #define HDSP_TimecodeLock       (1<<5)
312 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
313 #define HDSP_Sync2              (1<<16)
314 #define HDSP_Sync1              (1<<17)
315 #define HDSP_Sync0              (1<<18)
316 #define HDSP_DoubleSpeedStatus  (1<<19)
317 #define HDSP_ConfigError        (1<<20)
318 #define HDSP_DllError           (1<<21)
319 #define HDSP_spdifFrequency0    (1<<22)
320 #define HDSP_spdifFrequency1    (1<<23)
321 #define HDSP_spdifFrequency2    (1<<24)
322 #define HDSP_SPDIFErrorFlag     (1<<25)
323 #define HDSP_BufferID           (1<<26)
324 #define HDSP_TimecodeSync       (1<<27)
325 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
326 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
327 #define HDSP_midi0IRQPending    (1<<30)
328 #define HDSP_midi1IRQPending    (1<<31)
329
330 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
331 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
332                                       HDSP_spdifFrequency1|\
333                                       HDSP_spdifFrequency2|\
334                                       HDSP_spdifFrequency3)
335
336 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
337 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
338 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
339
340 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
341 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
342 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
343
344 /* This is for H9632 cards */
345 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
346                                      HDSP_spdifFrequency1|\
347                                      HDSP_spdifFrequency2)
348 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
349 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
350
351 /* Status2 Register bits */
352
353 #define HDSP_version0     (1<<0)
354 #define HDSP_version1     (1<<1)
355 #define HDSP_version2     (1<<2)
356 #define HDSP_wc_lock      (1<<3)
357 #define HDSP_wc_sync      (1<<4)
358 #define HDSP_inp_freq0    (1<<5)
359 #define HDSP_inp_freq1    (1<<6)
360 #define HDSP_inp_freq2    (1<<7)
361 #define HDSP_SelSyncRef0  (1<<8)
362 #define HDSP_SelSyncRef1  (1<<9)
363 #define HDSP_SelSyncRef2  (1<<10)
364
365 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
366
367 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
368 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
369 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
370 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
371 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
372 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
373 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
374 /* FIXME : more values for 9632 cards ? */
375
376 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
377 #define HDSP_SelSyncRef_ADAT1      0
378 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
379 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
380 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
381 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
382 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
383
384 /* Card state flags */
385
386 #define HDSP_InitializationComplete  (1<<0)
387 #define HDSP_FirmwareLoaded          (1<<1)
388 #define HDSP_FirmwareCached          (1<<2)
389
390 /* FIFO wait times, defined in terms of 1/10ths of msecs */
391
392 #define HDSP_LONG_WAIT   5000
393 #define HDSP_SHORT_WAIT  30
394
395 #define UNITY_GAIN                       32768
396 #define MINUS_INFINITY_GAIN              0
397
398 /* the size of a substream (1 mono data stream) */
399
400 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
401 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
402
403 /* the size of the area we need to allocate for DMA transfers. the
404    size is the same regardless of the number of channels - the
405    Multiface still uses the same memory area.
406
407    Note that we allocate 1 more channel than is apparently needed
408    because the h/w seems to write 1 byte beyond the end of the last
409    page. Sigh.
410 */
411
412 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
413 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
414
415 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
416
417 struct hdsp_9632_meters {
418     u32 input_peak[16];
419     u32 playback_peak[16];
420     u32 output_peak[16];
421     u32 xxx_peak[16];
422     u32 padding[64];
423     u32 input_rms_low[16];
424     u32 playback_rms_low[16];
425     u32 output_rms_low[16];
426     u32 xxx_rms_low[16];
427     u32 input_rms_high[16];
428     u32 playback_rms_high[16];
429     u32 output_rms_high[16];
430     u32 xxx_rms_high[16];
431 };
432
433 struct hdsp_midi {
434     struct hdsp             *hdsp;
435     int                      id;
436     struct snd_rawmidi           *rmidi;
437     struct snd_rawmidi_substream *input;
438     struct snd_rawmidi_substream *output;
439     char                     istimer; /* timer in use */
440     struct timer_list        timer;
441     spinlock_t               lock;
442     int                      pending;
443 };
444
445 struct hdsp {
446         spinlock_t            lock;
447         struct snd_pcm_substream *capture_substream;
448         struct snd_pcm_substream *playback_substream;
449         struct hdsp_midi      midi[2];
450         struct tasklet_struct midi_tasklet;
451         int                   use_midi_tasklet;
452         int                   precise_ptr;
453         u32                   control_register;      /* cached value */
454         u32                   control2_register;     /* cached value */
455         u32                   creg_spdif;
456         u32                   creg_spdif_stream;
457         int                   clock_source_locked;
458         char                 *card_name;         /* digiface/multiface/rpm */
459         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
460         unsigned short        firmware_rev;
461         unsigned short        state;                 /* stores state bits */
462         const struct firmware *firmware;
463         u32                  *fw_uploaded;
464         size_t                period_bytes;          /* guess what this is */
465         unsigned char         max_channels;
466         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
467         unsigned char         ds_in_channels;
468         unsigned char         ss_in_channels;       /* different for multiface/digiface */
469         unsigned char         qs_out_channels;
470         unsigned char         ds_out_channels;
471         unsigned char         ss_out_channels;
472
473         struct snd_dma_buffer capture_dma_buf;
474         struct snd_dma_buffer playback_dma_buf;
475         unsigned char        *capture_buffer;       /* suitably aligned address */
476         unsigned char        *playback_buffer;      /* suitably aligned address */
477
478         pid_t                 capture_pid;
479         pid_t                 playback_pid;
480         int                   running;
481         int                   system_sample_rate;
482         char                 *channel_map;
483         int                   dev;
484         int                   irq;
485         unsigned long         port;
486         void __iomem         *iobase;
487         struct snd_card *card;
488         struct snd_pcm *pcm;
489         struct snd_hwdep          *hwdep;
490         struct pci_dev       *pci;
491         struct snd_kcontrol *spdif_ctl;
492         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
493         unsigned int          dds_value; /* last value written to freq register */
494 };
495
496 /* These tables map the ALSA channels 1..N to the channels that we
497    need to use in order to find the relevant channel buffer. RME
498    refer to this kind of mapping as between "the ADAT channel and
499    the DMA channel." We index it using the logical audio channel,
500    and the value is the DMA channel (i.e. channel buffer number)
501    where the data for that channel can be read/written from/to.
502 */
503
504 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
505         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
506         18, 19, 20, 21, 22, 23, 24, 25
507 };
508
509 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
510         /* Analog */
511         0, 1, 2, 3, 4, 5, 6, 7,
512         /* ADAT 2 */
513         16, 17, 18, 19, 20, 21, 22, 23,
514         /* SPDIF */
515         24, 25,
516         -1, -1, -1, -1, -1, -1, -1, -1
517 };
518
519 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
520         /* ADAT channels are remapped */
521         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
522         /* channels 12 and 13 are S/PDIF */
523         24, 25,
524         /* others don't exist */
525         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
526 };
527
528 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
529         /* ADAT channels */
530         0, 1, 2, 3, 4, 5, 6, 7,
531         /* SPDIF */
532         8, 9,
533         /* Analog */
534         10, 11,
535         /* AO4S-192 and AI4S-192 extension boards */
536         12, 13, 14, 15,
537         /* others don't exist */
538         -1, -1, -1, -1, -1, -1, -1, -1,
539         -1, -1
540 };
541
542 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
543         /* ADAT */
544         1, 3, 5, 7,
545         /* SPDIF */
546         8, 9,
547         /* Analog */
548         10, 11,
549         /* AO4S-192 and AI4S-192 extension boards */
550         12, 13, 14, 15,
551         /* others don't exist */
552         -1, -1, -1, -1, -1, -1, -1, -1,
553         -1, -1, -1, -1, -1, -1
554 };
555
556 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
557         /* ADAT is disabled in this mode */
558         /* SPDIF */
559         8, 9,
560         /* Analog */
561         10, 11,
562         /* AO4S-192 and AI4S-192 extension boards */
563         12, 13, 14, 15,
564         /* others don't exist */
565         -1, -1, -1, -1, -1, -1, -1, -1,
566         -1, -1, -1, -1, -1, -1, -1, -1,
567         -1, -1
568 };
569
570 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
571 {
572         return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab);
573 }
574
575 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
576 {
577         if (dmab->area)
578                 snd_dma_free_pages(dmab);
579 }
580
581
582 static const struct pci_device_id snd_hdsp_ids[] = {
583         {
584                 .vendor = PCI_VENDOR_ID_XILINX,
585                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
586                 .subvendor = PCI_ANY_ID,
587                 .subdevice = PCI_ANY_ID,
588         }, /* RME Hammerfall-DSP */
589         { 0, },
590 };
591
592 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
593
594 /* prototypes */
595 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
596 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
597 static int snd_hdsp_enable_io (struct hdsp *hdsp);
598 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
599 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
600 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
601 static int hdsp_autosync_ref(struct hdsp *hdsp);
602 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
603 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
604
605 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
606 {
607         switch (hdsp->io_type) {
608         case Multiface:
609         case Digiface:
610         case RPM:
611         default:
612                 if (hdsp->firmware_rev == 0xa)
613                         return (64 * out) + (32 + (in));
614                 else
615                         return (52 * out) + (26 + (in));
616         case H9632:
617                 return (32 * out) + (16 + (in));
618         case H9652:
619                 return (52 * out) + (26 + (in));
620         }
621 }
622
623 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
624 {
625         switch (hdsp->io_type) {
626         case Multiface:
627         case Digiface:
628         case RPM:
629         default:
630                 if (hdsp->firmware_rev == 0xa)
631                         return (64 * out) + in;
632                 else
633                         return (52 * out) + in;
634         case H9632:
635                 return (32 * out) + in;
636         case H9652:
637                 return (52 * out) + in;
638         }
639 }
640
641 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
642 {
643         writel(val, hdsp->iobase + reg);
644 }
645
646 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
647 {
648         return readl (hdsp->iobase + reg);
649 }
650
651 static int hdsp_check_for_iobox (struct hdsp *hdsp)
652 {
653         int i;
654
655         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
656         for (i = 0; i < 500; i++) {
657                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
658                                         HDSP_ConfigError)) {
659                         if (i) {
660                                 dev_dbg(hdsp->card->dev,
661                                         "IO box found after %d ms\n",
662                                                 (20 * i));
663                         }
664                         return 0;
665                 }
666                 msleep(20);
667         }
668         dev_err(hdsp->card->dev, "no IO box connected!\n");
669         hdsp->state &= ~HDSP_FirmwareLoaded;
670         return -EIO;
671 }
672
673 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
674                                unsigned int delay)
675 {
676         unsigned int i;
677
678         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
679                 return 0;
680
681         for (i = 0; i != loops; ++i) {
682                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
683                         msleep(delay);
684                 else {
685                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
686                                    i * delay);
687                         return 0;
688                 }
689         }
690
691         dev_info(hdsp->card->dev, "no IO box connected!\n");
692         hdsp->state &= ~HDSP_FirmwareLoaded;
693         return -EIO;
694 }
695
696 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
697
698         int i;
699         unsigned long flags;
700         const u32 *cache;
701
702         if (hdsp->fw_uploaded)
703                 cache = hdsp->fw_uploaded;
704         else {
705                 if (!hdsp->firmware)
706                         return -ENODEV;
707                 cache = (u32 *)hdsp->firmware->data;
708                 if (!cache)
709                         return -ENODEV;
710         }
711
712         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
713
714                 dev_info(hdsp->card->dev, "loading firmware\n");
715
716                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
717                 hdsp_write (hdsp, HDSP_fifoData, 0);
718
719                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
720                         dev_info(hdsp->card->dev,
721                                  "timeout waiting for download preparation\n");
722                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
723                         return -EIO;
724                 }
725
726                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
727
728                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
729                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
730                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
731                                 dev_info(hdsp->card->dev,
732                                          "timeout during firmware loading\n");
733                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
734                                 return -EIO;
735                         }
736                 }
737
738                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
739                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
740
741                 ssleep(3);
742 #ifdef SNDRV_BIG_ENDIAN
743                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
744 #else
745                 hdsp->control2_register = 0;
746 #endif
747                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
748                 dev_info(hdsp->card->dev, "finished firmware loading\n");
749
750         }
751         if (hdsp->state & HDSP_InitializationComplete) {
752                 dev_info(hdsp->card->dev,
753                          "firmware loaded from cache, restoring defaults\n");
754                 spin_lock_irqsave(&hdsp->lock, flags);
755                 snd_hdsp_set_defaults(hdsp);
756                 spin_unlock_irqrestore(&hdsp->lock, flags);
757         }
758
759         hdsp->state |= HDSP_FirmwareLoaded;
760
761         return 0;
762 }
763
764 static int hdsp_get_iobox_version (struct hdsp *hdsp)
765 {
766         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
767
768                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
769                 hdsp_write(hdsp, HDSP_fifoData, 0);
770
771                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
772                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
773                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
774                 }
775
776                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
777                 hdsp_write (hdsp, HDSP_fifoData, 0);
778                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
779                         goto set_multi;
780
781                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
782                 hdsp_write(hdsp, HDSP_fifoData, 0);
783                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
784                         hdsp->io_type = Digiface;
785                         dev_info(hdsp->card->dev, "Digiface found\n");
786                         return 0;
787                 }
788
789                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
790                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
791                 hdsp_write(hdsp, HDSP_fifoData, 0);
792                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
793                         goto set_multi;
794
795                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
796                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
797                 hdsp_write(hdsp, HDSP_fifoData, 0);
798                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
799                         goto set_multi;
800
801                 hdsp->io_type = RPM;
802                 dev_info(hdsp->card->dev, "RPM found\n");
803                 return 0;
804         } else {
805                 /* firmware was already loaded, get iobox type */
806                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
807                         hdsp->io_type = RPM;
808                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
809                         hdsp->io_type = Multiface;
810                 else
811                         hdsp->io_type = Digiface;
812         }
813         return 0;
814
815 set_multi:
816         hdsp->io_type = Multiface;
817         dev_info(hdsp->card->dev, "Multiface found\n");
818         return 0;
819 }
820
821
822 static int hdsp_request_fw_loader(struct hdsp *hdsp);
823
824 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
825 {
826         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
827                 return 0;
828         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
829                 hdsp->state &= ~HDSP_FirmwareLoaded;
830                 if (! load_on_demand)
831                         return -EIO;
832                 dev_err(hdsp->card->dev, "firmware not present.\n");
833                 /* try to load firmware */
834                 if (! (hdsp->state & HDSP_FirmwareCached)) {
835                         if (! hdsp_request_fw_loader(hdsp))
836                                 return 0;
837                         dev_err(hdsp->card->dev,
838                                    "No firmware loaded nor cached, please upload firmware.\n");
839                         return -EIO;
840                 }
841                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
842                         dev_err(hdsp->card->dev,
843                                    "Firmware loading from cache failed, please upload manually.\n");
844                         return -EIO;
845                 }
846         }
847         return 0;
848 }
849
850
851 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
852 {
853         int i;
854
855         /* the fifoStatus registers reports on how many words
856            are available in the command FIFO.
857         */
858
859         for (i = 0; i < timeout; i++) {
860
861                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
862                         return 0;
863
864                 /* not very friendly, but we only do this during a firmware
865                    load and changing the mixer, so we just put up with it.
866                 */
867
868                 udelay (100);
869         }
870
871         dev_warn(hdsp->card->dev,
872                  "wait for FIFO status <= %d failed after %d iterations\n",
873                     count, timeout);
874         return -1;
875 }
876
877 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
878 {
879         if (addr >= HDSP_MATRIX_MIXER_SIZE)
880                 return 0;
881
882         return hdsp->mixer_matrix[addr];
883 }
884
885 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
886 {
887         unsigned int ad;
888
889         if (addr >= HDSP_MATRIX_MIXER_SIZE)
890                 return -1;
891
892         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
893
894                 /* from martin bjornsen:
895
896                    "You can only write dwords to the
897                    mixer memory which contain two
898                    mixer values in the low and high
899                    word. So if you want to change
900                    value 0 you have to read value 1
901                    from the cache and write both to
902                    the first dword in the mixer
903                    memory."
904                 */
905
906                 if (hdsp->io_type == H9632 && addr >= 512)
907                         return 0;
908
909                 if (hdsp->io_type == H9652 && addr >= 1352)
910                         return 0;
911
912                 hdsp->mixer_matrix[addr] = data;
913
914
915                 /* `addr' addresses a 16-bit wide address, but
916                    the address space accessed via hdsp_write
917                    uses byte offsets. put another way, addr
918                    varies from 0 to 1351, but to access the
919                    corresponding memory location, we need
920                    to access 0 to 2703 ...
921                 */
922                 ad = addr/2;
923
924                 hdsp_write (hdsp, 4096 + (ad*4),
925                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
926                             hdsp->mixer_matrix[addr&0x7fe]);
927
928                 return 0;
929
930         } else {
931
932                 ad = (addr << 16) + data;
933
934                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
935                         return -1;
936
937                 hdsp_write (hdsp, HDSP_fifoData, ad);
938                 hdsp->mixer_matrix[addr] = data;
939
940         }
941
942         return 0;
943 }
944
945 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
946 {
947         unsigned long flags;
948         int ret = 1;
949
950         spin_lock_irqsave(&hdsp->lock, flags);
951         if ((hdsp->playback_pid != hdsp->capture_pid) &&
952             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
953                 ret = 0;
954         spin_unlock_irqrestore(&hdsp->lock, flags);
955         return ret;
956 }
957
958 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
959 {
960         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
961         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
962
963         /* For the 9632, the mask is different */
964         if (hdsp->io_type == H9632)
965                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
966
967         if (status & HDSP_SPDIFErrorFlag)
968                 return 0;
969
970         switch (rate_bits) {
971         case HDSP_spdifFrequency32KHz: return 32000;
972         case HDSP_spdifFrequency44_1KHz: return 44100;
973         case HDSP_spdifFrequency48KHz: return 48000;
974         case HDSP_spdifFrequency64KHz: return 64000;
975         case HDSP_spdifFrequency88_2KHz: return 88200;
976         case HDSP_spdifFrequency96KHz: return 96000;
977         case HDSP_spdifFrequency128KHz:
978                 if (hdsp->io_type == H9632) return 128000;
979                 break;
980         case HDSP_spdifFrequency176_4KHz:
981                 if (hdsp->io_type == H9632) return 176400;
982                 break;
983         case HDSP_spdifFrequency192KHz:
984                 if (hdsp->io_type == H9632) return 192000;
985                 break;
986         default:
987                 break;
988         }
989         dev_warn(hdsp->card->dev,
990                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
991                  rate_bits, status);
992         return 0;
993 }
994
995 static int hdsp_external_sample_rate(struct hdsp *hdsp)
996 {
997         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
998         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
999
1000         /* For the 9632 card, there seems to be no bit for indicating external
1001          * sample rate greater than 96kHz. The card reports the corresponding
1002          * single speed. So the best means seems to get spdif rate when
1003          * autosync reference is spdif */
1004         if (hdsp->io_type == H9632 &&
1005             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1006                  return hdsp_spdif_sample_rate(hdsp);
1007
1008         switch (rate_bits) {
1009         case HDSP_systemFrequency32:   return 32000;
1010         case HDSP_systemFrequency44_1: return 44100;
1011         case HDSP_systemFrequency48:   return 48000;
1012         case HDSP_systemFrequency64:   return 64000;
1013         case HDSP_systemFrequency88_2: return 88200;
1014         case HDSP_systemFrequency96:   return 96000;
1015         default:
1016                 return 0;
1017         }
1018 }
1019
1020 static void hdsp_compute_period_size(struct hdsp *hdsp)
1021 {
1022         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1023 }
1024
1025 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1026 {
1027         int position;
1028
1029         position = hdsp_read(hdsp, HDSP_statusRegister);
1030
1031         if (!hdsp->precise_ptr)
1032                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1033
1034         position &= HDSP_BufferPositionMask;
1035         position /= 4;
1036         position &= (hdsp->period_bytes/2) - 1;
1037         return position;
1038 }
1039
1040 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1041 {
1042         hdsp_write (hdsp, HDSP_resetPointer, 0);
1043         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1044                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1045                  * requires (?) to write again DDS value after a reset pointer
1046                  * (at least, it works like this) */
1047                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1048 }
1049
1050 static void hdsp_start_audio(struct hdsp *s)
1051 {
1052         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1053         hdsp_write(s, HDSP_controlRegister, s->control_register);
1054 }
1055
1056 static void hdsp_stop_audio(struct hdsp *s)
1057 {
1058         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1059         hdsp_write(s, HDSP_controlRegister, s->control_register);
1060 }
1061
1062 static void hdsp_silence_playback(struct hdsp *hdsp)
1063 {
1064         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1065 }
1066
1067 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1068 {
1069         int n;
1070
1071         spin_lock_irq(&s->lock);
1072
1073         frames >>= 7;
1074         n = 0;
1075         while (frames) {
1076                 n++;
1077                 frames >>= 1;
1078         }
1079
1080         s->control_register &= ~HDSP_LatencyMask;
1081         s->control_register |= hdsp_encode_latency(n);
1082
1083         hdsp_write(s, HDSP_controlRegister, s->control_register);
1084
1085         hdsp_compute_period_size(s);
1086
1087         spin_unlock_irq(&s->lock);
1088
1089         return 0;
1090 }
1091
1092 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1093 {
1094         u64 n;
1095
1096         if (rate >= 112000)
1097                 rate /= 4;
1098         else if (rate >= 56000)
1099                 rate /= 2;
1100
1101         n = DDS_NUMERATOR;
1102         n = div_u64(n, rate);
1103         /* n should be less than 2^32 for being written to FREQ register */
1104         snd_BUG_ON(n >> 32);
1105         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1106            value to write it after a reset */
1107         hdsp->dds_value = n;
1108         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1109 }
1110
1111 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1112 {
1113         int reject_if_open = 0;
1114         int current_rate;
1115         int rate_bits;
1116
1117         /* ASSUMPTION: hdsp->lock is either held, or
1118            there is no need for it (e.g. during module
1119            initialization).
1120         */
1121
1122         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1123                 if (called_internally) {
1124                         /* request from ctl or card initialization */
1125                         dev_err(hdsp->card->dev,
1126                                 "device is not running as a clock master: cannot set sample rate.\n");
1127                         return -1;
1128                 } else {
1129                         /* hw_param request while in AutoSync mode */
1130                         int external_freq = hdsp_external_sample_rate(hdsp);
1131                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1132
1133                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1134                                 dev_info(hdsp->card->dev,
1135                                          "Detected ADAT in double speed mode\n");
1136                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1137                                 dev_info(hdsp->card->dev,
1138                                          "Detected ADAT in quad speed mode\n");
1139                         else if (rate != external_freq) {
1140                                 dev_info(hdsp->card->dev,
1141                                          "No AutoSync source for requested rate\n");
1142                                 return -1;
1143                         }
1144                 }
1145         }
1146
1147         current_rate = hdsp->system_sample_rate;
1148
1149         /* Changing from a "single speed" to a "double speed" rate is
1150            not allowed if any substreams are open. This is because
1151            such a change causes a shift in the location of
1152            the DMA buffers and a reduction in the number of available
1153            buffers.
1154
1155            Note that a similar but essentially insoluble problem
1156            exists for externally-driven rate changes. All we can do
1157            is to flag rate changes in the read/write routines.  */
1158
1159         if (rate > 96000 && hdsp->io_type != H9632)
1160                 return -EINVAL;
1161
1162         switch (rate) {
1163         case 32000:
1164                 if (current_rate > 48000)
1165                         reject_if_open = 1;
1166                 rate_bits = HDSP_Frequency32KHz;
1167                 break;
1168         case 44100:
1169                 if (current_rate > 48000)
1170                         reject_if_open = 1;
1171                 rate_bits = HDSP_Frequency44_1KHz;
1172                 break;
1173         case 48000:
1174                 if (current_rate > 48000)
1175                         reject_if_open = 1;
1176                 rate_bits = HDSP_Frequency48KHz;
1177                 break;
1178         case 64000:
1179                 if (current_rate <= 48000 || current_rate > 96000)
1180                         reject_if_open = 1;
1181                 rate_bits = HDSP_Frequency64KHz;
1182                 break;
1183         case 88200:
1184                 if (current_rate <= 48000 || current_rate > 96000)
1185                         reject_if_open = 1;
1186                 rate_bits = HDSP_Frequency88_2KHz;
1187                 break;
1188         case 96000:
1189                 if (current_rate <= 48000 || current_rate > 96000)
1190                         reject_if_open = 1;
1191                 rate_bits = HDSP_Frequency96KHz;
1192                 break;
1193         case 128000:
1194                 if (current_rate < 128000)
1195                         reject_if_open = 1;
1196                 rate_bits = HDSP_Frequency128KHz;
1197                 break;
1198         case 176400:
1199                 if (current_rate < 128000)
1200                         reject_if_open = 1;
1201                 rate_bits = HDSP_Frequency176_4KHz;
1202                 break;
1203         case 192000:
1204                 if (current_rate < 128000)
1205                         reject_if_open = 1;
1206                 rate_bits = HDSP_Frequency192KHz;
1207                 break;
1208         default:
1209                 return -EINVAL;
1210         }
1211
1212         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1213                 dev_warn(hdsp->card->dev,
1214                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1215                             hdsp->capture_pid,
1216                             hdsp->playback_pid);
1217                 return -EBUSY;
1218         }
1219
1220         hdsp->control_register &= ~HDSP_FrequencyMask;
1221         hdsp->control_register |= rate_bits;
1222         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1223
1224         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1225         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1226                 hdsp_set_dds_value(hdsp, rate);
1227
1228         if (rate >= 128000) {
1229                 hdsp->channel_map = channel_map_H9632_qs;
1230         } else if (rate > 48000) {
1231                 if (hdsp->io_type == H9632)
1232                         hdsp->channel_map = channel_map_H9632_ds;
1233                 else
1234                         hdsp->channel_map = channel_map_ds;
1235         } else {
1236                 switch (hdsp->io_type) {
1237                 case RPM:
1238                 case Multiface:
1239                         hdsp->channel_map = channel_map_mf_ss;
1240                         break;
1241                 case Digiface:
1242                 case H9652:
1243                         hdsp->channel_map = channel_map_df_ss;
1244                         break;
1245                 case H9632:
1246                         hdsp->channel_map = channel_map_H9632_ss;
1247                         break;
1248                 default:
1249                         /* should never happen */
1250                         break;
1251                 }
1252         }
1253
1254         hdsp->system_sample_rate = rate;
1255
1256         return 0;
1257 }
1258
1259 /*----------------------------------------------------------------------------
1260    MIDI
1261   ----------------------------------------------------------------------------*/
1262
1263 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1264 {
1265         /* the hardware already does the relevant bit-mask with 0xff */
1266         if (id)
1267                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1268         else
1269                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1270 }
1271
1272 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1273 {
1274         /* the hardware already does the relevant bit-mask with 0xff */
1275         if (id)
1276                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1277         else
1278                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1279 }
1280
1281 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1282 {
1283         if (id)
1284                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1285         else
1286                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1287 }
1288
1289 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1290 {
1291         int fifo_bytes_used;
1292
1293         if (id)
1294                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1295         else
1296                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1297
1298         if (fifo_bytes_used < 128)
1299                 return  128 - fifo_bytes_used;
1300         else
1301                 return 0;
1302 }
1303
1304 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1305 {
1306         while (snd_hdsp_midi_input_available (hdsp, id))
1307                 snd_hdsp_midi_read_byte (hdsp, id);
1308 }
1309
1310 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1311 {
1312         unsigned long flags;
1313         int n_pending;
1314         int to_write;
1315         int i;
1316         unsigned char buf[128];
1317
1318         /* Output is not interrupt driven */
1319
1320         spin_lock_irqsave (&hmidi->lock, flags);
1321         if (hmidi->output) {
1322                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1323                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1324                                 if (n_pending > (int)sizeof (buf))
1325                                         n_pending = sizeof (buf);
1326
1327                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1328                                         for (i = 0; i < to_write; ++i)
1329                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1330                                 }
1331                         }
1332                 }
1333         }
1334         spin_unlock_irqrestore (&hmidi->lock, flags);
1335         return 0;
1336 }
1337
1338 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1339 {
1340         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1341         unsigned long flags;
1342         int n_pending;
1343         int i;
1344
1345         spin_lock_irqsave (&hmidi->lock, flags);
1346         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1347                 if (hmidi->input) {
1348                         if (n_pending > (int)sizeof (buf))
1349                                 n_pending = sizeof (buf);
1350                         for (i = 0; i < n_pending; ++i)
1351                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1352                         if (n_pending)
1353                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1354                 } else {
1355                         /* flush the MIDI input FIFO */
1356                         while (--n_pending)
1357                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1358                 }
1359         }
1360         hmidi->pending = 0;
1361         if (hmidi->id)
1362                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1363         else
1364                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1365         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1366         spin_unlock_irqrestore (&hmidi->lock, flags);
1367         return snd_hdsp_midi_output_write (hmidi);
1368 }
1369
1370 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1371 {
1372         struct hdsp *hdsp;
1373         struct hdsp_midi *hmidi;
1374         unsigned long flags;
1375         u32 ie;
1376
1377         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1378         hdsp = hmidi->hdsp;
1379         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1380         spin_lock_irqsave (&hdsp->lock, flags);
1381         if (up) {
1382                 if (!(hdsp->control_register & ie)) {
1383                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1384                         hdsp->control_register |= ie;
1385                 }
1386         } else {
1387                 hdsp->control_register &= ~ie;
1388                 tasklet_kill(&hdsp->midi_tasklet);
1389         }
1390
1391         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1392         spin_unlock_irqrestore (&hdsp->lock, flags);
1393 }
1394
1395 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1396 {
1397         struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1398         unsigned long flags;
1399
1400         snd_hdsp_midi_output_write(hmidi);
1401         spin_lock_irqsave (&hmidi->lock, flags);
1402
1403         /* this does not bump hmidi->istimer, because the
1404            kernel automatically removed the timer when it
1405            expired, and we are now adding it back, thus
1406            leaving istimer wherever it was set before.
1407         */
1408
1409         if (hmidi->istimer)
1410                 mod_timer(&hmidi->timer, 1 + jiffies);
1411
1412         spin_unlock_irqrestore (&hmidi->lock, flags);
1413 }
1414
1415 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1416 {
1417         struct hdsp_midi *hmidi;
1418         unsigned long flags;
1419
1420         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1421         spin_lock_irqsave (&hmidi->lock, flags);
1422         if (up) {
1423                 if (!hmidi->istimer) {
1424                         timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1425                                     0);
1426                         mod_timer(&hmidi->timer, 1 + jiffies);
1427                         hmidi->istimer++;
1428                 }
1429         } else {
1430                 if (hmidi->istimer && --hmidi->istimer <= 0)
1431                         del_timer (&hmidi->timer);
1432         }
1433         spin_unlock_irqrestore (&hmidi->lock, flags);
1434         if (up)
1435                 snd_hdsp_midi_output_write(hmidi);
1436 }
1437
1438 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1439 {
1440         struct hdsp_midi *hmidi;
1441
1442         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1443         spin_lock_irq (&hmidi->lock);
1444         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1445         hmidi->input = substream;
1446         spin_unlock_irq (&hmidi->lock);
1447
1448         return 0;
1449 }
1450
1451 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1452 {
1453         struct hdsp_midi *hmidi;
1454
1455         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1456         spin_lock_irq (&hmidi->lock);
1457         hmidi->output = substream;
1458         spin_unlock_irq (&hmidi->lock);
1459
1460         return 0;
1461 }
1462
1463 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1464 {
1465         struct hdsp_midi *hmidi;
1466
1467         snd_hdsp_midi_input_trigger (substream, 0);
1468
1469         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1470         spin_lock_irq (&hmidi->lock);
1471         hmidi->input = NULL;
1472         spin_unlock_irq (&hmidi->lock);
1473
1474         return 0;
1475 }
1476
1477 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1478 {
1479         struct hdsp_midi *hmidi;
1480
1481         snd_hdsp_midi_output_trigger (substream, 0);
1482
1483         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1484         spin_lock_irq (&hmidi->lock);
1485         hmidi->output = NULL;
1486         spin_unlock_irq (&hmidi->lock);
1487
1488         return 0;
1489 }
1490
1491 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1492 {
1493         .open =         snd_hdsp_midi_output_open,
1494         .close =        snd_hdsp_midi_output_close,
1495         .trigger =      snd_hdsp_midi_output_trigger,
1496 };
1497
1498 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1499 {
1500         .open =         snd_hdsp_midi_input_open,
1501         .close =        snd_hdsp_midi_input_close,
1502         .trigger =      snd_hdsp_midi_input_trigger,
1503 };
1504
1505 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1506 {
1507         char buf[40];
1508
1509         hdsp->midi[id].id = id;
1510         hdsp->midi[id].rmidi = NULL;
1511         hdsp->midi[id].input = NULL;
1512         hdsp->midi[id].output = NULL;
1513         hdsp->midi[id].hdsp = hdsp;
1514         hdsp->midi[id].istimer = 0;
1515         hdsp->midi[id].pending = 0;
1516         spin_lock_init (&hdsp->midi[id].lock);
1517
1518         snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1519         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1520                 return -1;
1521
1522         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1523         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1524
1525         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1526         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1527
1528         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1529                 SNDRV_RAWMIDI_INFO_INPUT |
1530                 SNDRV_RAWMIDI_INFO_DUPLEX;
1531
1532         return 0;
1533 }
1534
1535 /*-----------------------------------------------------------------------------
1536   Control Interface
1537   ----------------------------------------------------------------------------*/
1538
1539 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1540 {
1541         u32 val = 0;
1542         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1543         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1544         if (val & HDSP_SPDIFProfessional)
1545                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1546         else
1547                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1548         return val;
1549 }
1550
1551 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1552 {
1553         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1554                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1555         if (val & HDSP_SPDIFProfessional)
1556                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1557         else
1558                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1559 }
1560
1561 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1562 {
1563         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1564         uinfo->count = 1;
1565         return 0;
1566 }
1567
1568 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1569 {
1570         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1571
1572         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1573         return 0;
1574 }
1575
1576 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1577 {
1578         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1579         int change;
1580         u32 val;
1581
1582         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1583         spin_lock_irq(&hdsp->lock);
1584         change = val != hdsp->creg_spdif;
1585         hdsp->creg_spdif = val;
1586         spin_unlock_irq(&hdsp->lock);
1587         return change;
1588 }
1589
1590 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1591 {
1592         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1593         uinfo->count = 1;
1594         return 0;
1595 }
1596
1597 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1598 {
1599         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1600
1601         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1602         return 0;
1603 }
1604
1605 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1606 {
1607         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1608         int change;
1609         u32 val;
1610
1611         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1612         spin_lock_irq(&hdsp->lock);
1613         change = val != hdsp->creg_spdif_stream;
1614         hdsp->creg_spdif_stream = val;
1615         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1616         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1617         spin_unlock_irq(&hdsp->lock);
1618         return change;
1619 }
1620
1621 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1622 {
1623         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1624         uinfo->count = 1;
1625         return 0;
1626 }
1627
1628 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1629 {
1630         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1631         return 0;
1632 }
1633
1634 #define HDSP_SPDIF_IN(xname, xindex) \
1635 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1636   .name = xname, \
1637   .index = xindex, \
1638   .info = snd_hdsp_info_spdif_in, \
1639   .get = snd_hdsp_get_spdif_in, \
1640   .put = snd_hdsp_put_spdif_in }
1641
1642 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1643 {
1644         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1645 }
1646
1647 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1648 {
1649         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1650         hdsp->control_register |= hdsp_encode_spdif_in(in);
1651         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1652         return 0;
1653 }
1654
1655 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1656 {
1657         static const char * const texts[4] = {
1658                 "Optical", "Coaxial", "Internal", "AES"
1659         };
1660         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1661
1662         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1663                                  texts);
1664 }
1665
1666 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1667 {
1668         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1669
1670         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1671         return 0;
1672 }
1673
1674 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1675 {
1676         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1677         int change;
1678         unsigned int val;
1679
1680         if (!snd_hdsp_use_is_exclusive(hdsp))
1681                 return -EBUSY;
1682         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1683         spin_lock_irq(&hdsp->lock);
1684         change = val != hdsp_spdif_in(hdsp);
1685         if (change)
1686                 hdsp_set_spdif_input(hdsp, val);
1687         spin_unlock_irq(&hdsp->lock);
1688         return change;
1689 }
1690
1691 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1692 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1693         .name = xname, \
1694         .private_value = xindex, \
1695         .info = snd_hdsp_info_toggle_setting, \
1696         .get = snd_hdsp_get_toggle_setting, \
1697         .put = snd_hdsp_put_toggle_setting \
1698 }
1699
1700 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1701 {
1702         return (hdsp->control_register & regmask) ? 1 : 0;
1703 }
1704
1705 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1706 {
1707         if (out)
1708                 hdsp->control_register |= regmask;
1709         else
1710                 hdsp->control_register &= ~regmask;
1711         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1712
1713         return 0;
1714 }
1715
1716 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1717
1718 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1719                 struct snd_ctl_elem_value *ucontrol)
1720 {
1721         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1722         u32 regmask = kcontrol->private_value;
1723
1724         spin_lock_irq(&hdsp->lock);
1725         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1726         spin_unlock_irq(&hdsp->lock);
1727         return 0;
1728 }
1729
1730 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1731                 struct snd_ctl_elem_value *ucontrol)
1732 {
1733         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1734         u32 regmask = kcontrol->private_value;
1735         int change;
1736         unsigned int val;
1737
1738         if (!snd_hdsp_use_is_exclusive(hdsp))
1739                 return -EBUSY;
1740         val = ucontrol->value.integer.value[0] & 1;
1741         spin_lock_irq(&hdsp->lock);
1742         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1743         if (change)
1744                 hdsp_set_toggle_setting(hdsp, regmask, val);
1745         spin_unlock_irq(&hdsp->lock);
1746         return change;
1747 }
1748
1749 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1750 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1751   .name = xname, \
1752   .index = xindex, \
1753   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1754   .info = snd_hdsp_info_spdif_sample_rate, \
1755   .get = snd_hdsp_get_spdif_sample_rate \
1756 }
1757
1758 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1759 {
1760         static const char * const texts[] = {
1761                 "32000", "44100", "48000", "64000", "88200", "96000",
1762                 "None", "128000", "176400", "192000"
1763         };
1764         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1765
1766         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1767                                  texts);
1768 }
1769
1770 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1771 {
1772         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1773
1774         switch (hdsp_spdif_sample_rate(hdsp)) {
1775         case 32000:
1776                 ucontrol->value.enumerated.item[0] = 0;
1777                 break;
1778         case 44100:
1779                 ucontrol->value.enumerated.item[0] = 1;
1780                 break;
1781         case 48000:
1782                 ucontrol->value.enumerated.item[0] = 2;
1783                 break;
1784         case 64000:
1785                 ucontrol->value.enumerated.item[0] = 3;
1786                 break;
1787         case 88200:
1788                 ucontrol->value.enumerated.item[0] = 4;
1789                 break;
1790         case 96000:
1791                 ucontrol->value.enumerated.item[0] = 5;
1792                 break;
1793         case 128000:
1794                 ucontrol->value.enumerated.item[0] = 7;
1795                 break;
1796         case 176400:
1797                 ucontrol->value.enumerated.item[0] = 8;
1798                 break;
1799         case 192000:
1800                 ucontrol->value.enumerated.item[0] = 9;
1801                 break;
1802         default:
1803                 ucontrol->value.enumerated.item[0] = 6;
1804         }
1805         return 0;
1806 }
1807
1808 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1809 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1810   .name = xname, \
1811   .index = xindex, \
1812   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1813   .info = snd_hdsp_info_system_sample_rate, \
1814   .get = snd_hdsp_get_system_sample_rate \
1815 }
1816
1817 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1818 {
1819         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1820         uinfo->count = 1;
1821         return 0;
1822 }
1823
1824 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1825 {
1826         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1827
1828         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1829         return 0;
1830 }
1831
1832 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1833 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1834   .name = xname, \
1835   .index = xindex, \
1836   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1837   .info = snd_hdsp_info_autosync_sample_rate, \
1838   .get = snd_hdsp_get_autosync_sample_rate \
1839 }
1840
1841 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1842 {
1843         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1844         static const char * const texts[] = {
1845                 "32000", "44100", "48000", "64000", "88200", "96000",
1846                 "None", "128000", "176400", "192000"
1847         };
1848
1849         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1850                                  texts);
1851 }
1852
1853 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1854 {
1855         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1856
1857         switch (hdsp_external_sample_rate(hdsp)) {
1858         case 32000:
1859                 ucontrol->value.enumerated.item[0] = 0;
1860                 break;
1861         case 44100:
1862                 ucontrol->value.enumerated.item[0] = 1;
1863                 break;
1864         case 48000:
1865                 ucontrol->value.enumerated.item[0] = 2;
1866                 break;
1867         case 64000:
1868                 ucontrol->value.enumerated.item[0] = 3;
1869                 break;
1870         case 88200:
1871                 ucontrol->value.enumerated.item[0] = 4;
1872                 break;
1873         case 96000:
1874                 ucontrol->value.enumerated.item[0] = 5;
1875                 break;
1876         case 128000:
1877                 ucontrol->value.enumerated.item[0] = 7;
1878                 break;
1879         case 176400:
1880                 ucontrol->value.enumerated.item[0] = 8;
1881                 break;
1882         case 192000:
1883                 ucontrol->value.enumerated.item[0] = 9;
1884                 break;
1885         default:
1886                 ucontrol->value.enumerated.item[0] = 6;
1887         }
1888         return 0;
1889 }
1890
1891 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1892 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1893   .name = xname, \
1894   .index = xindex, \
1895   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1896   .info = snd_hdsp_info_system_clock_mode, \
1897   .get = snd_hdsp_get_system_clock_mode \
1898 }
1899
1900 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1901 {
1902         if (hdsp->control_register & HDSP_ClockModeMaster)
1903                 return 0;
1904         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1905                         return 0;
1906         return 1;
1907 }
1908
1909 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1910 {
1911         static const char * const texts[] = {"Master", "Slave" };
1912
1913         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1914 }
1915
1916 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1917 {
1918         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1919
1920         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1921         return 0;
1922 }
1923
1924 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1925 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1926   .name = xname, \
1927   .index = xindex, \
1928   .info = snd_hdsp_info_clock_source, \
1929   .get = snd_hdsp_get_clock_source, \
1930   .put = snd_hdsp_put_clock_source \
1931 }
1932
1933 static int hdsp_clock_source(struct hdsp *hdsp)
1934 {
1935         if (hdsp->control_register & HDSP_ClockModeMaster) {
1936                 switch (hdsp->system_sample_rate) {
1937                 case 32000:
1938                         return 1;
1939                 case 44100:
1940                         return 2;
1941                 case 48000:
1942                         return 3;
1943                 case 64000:
1944                         return 4;
1945                 case 88200:
1946                         return 5;
1947                 case 96000:
1948                         return 6;
1949                 case 128000:
1950                         return 7;
1951                 case 176400:
1952                         return 8;
1953                 case 192000:
1954                         return 9;
1955                 default:
1956                         return 3;
1957                 }
1958         } else {
1959                 return 0;
1960         }
1961 }
1962
1963 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1964 {
1965         int rate;
1966         switch (mode) {
1967         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1968                 if (hdsp_external_sample_rate(hdsp) != 0) {
1969                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1970                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1971                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1972                         return 0;
1973                     }
1974                 }
1975                 return -1;
1976         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1977                 rate = 32000;
1978                 break;
1979         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1980                 rate = 44100;
1981                 break;
1982         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1983                 rate = 48000;
1984                 break;
1985         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1986                 rate = 64000;
1987                 break;
1988         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1989                 rate = 88200;
1990                 break;
1991         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1992                 rate = 96000;
1993                 break;
1994         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1995                 rate = 128000;
1996                 break;
1997         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1998                 rate = 176400;
1999                 break;
2000         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2001                 rate = 192000;
2002                 break;
2003         default:
2004                 rate = 48000;
2005         }
2006         hdsp->control_register |= HDSP_ClockModeMaster;
2007         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2008         hdsp_set_rate(hdsp, rate, 1);
2009         return 0;
2010 }
2011
2012 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2013 {
2014         static const char * const texts[] = {
2015                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2016                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2017                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2018                 "Internal 192.0 KHz"
2019         };
2020         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2021
2022         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2023                                  texts);
2024 }
2025
2026 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2027 {
2028         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2029
2030         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2031         return 0;
2032 }
2033
2034 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2035 {
2036         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2037         int change;
2038         int val;
2039
2040         if (!snd_hdsp_use_is_exclusive(hdsp))
2041                 return -EBUSY;
2042         val = ucontrol->value.enumerated.item[0];
2043         if (val < 0) val = 0;
2044         if (hdsp->io_type == H9632) {
2045                 if (val > 9)
2046                         val = 9;
2047         } else {
2048                 if (val > 6)
2049                         val = 6;
2050         }
2051         spin_lock_irq(&hdsp->lock);
2052         if (val != hdsp_clock_source(hdsp))
2053                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2054         else
2055                 change = 0;
2056         spin_unlock_irq(&hdsp->lock);
2057         return change;
2058 }
2059
2060 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2061
2062 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2063 {
2064         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2065
2066         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2067         return 0;
2068 }
2069
2070 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2071 {
2072         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2073         int change;
2074
2075         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2076         if (change)
2077                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2078         return change;
2079 }
2080
2081 #define HDSP_DA_GAIN(xname, xindex) \
2082 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2083   .name = xname, \
2084   .index = xindex, \
2085   .info = snd_hdsp_info_da_gain, \
2086   .get = snd_hdsp_get_da_gain, \
2087   .put = snd_hdsp_put_da_gain \
2088 }
2089
2090 static int hdsp_da_gain(struct hdsp *hdsp)
2091 {
2092         switch (hdsp->control_register & HDSP_DAGainMask) {
2093         case HDSP_DAGainHighGain:
2094                 return 0;
2095         case HDSP_DAGainPlus4dBu:
2096                 return 1;
2097         case HDSP_DAGainMinus10dBV:
2098                 return 2;
2099         default:
2100                 return 1;
2101         }
2102 }
2103
2104 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2105 {
2106         hdsp->control_register &= ~HDSP_DAGainMask;
2107         switch (mode) {
2108         case 0:
2109                 hdsp->control_register |= HDSP_DAGainHighGain;
2110                 break;
2111         case 1:
2112                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2113                 break;
2114         case 2:
2115                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2116                 break;
2117         default:
2118                 return -1;
2119
2120         }
2121         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2122         return 0;
2123 }
2124
2125 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2126 {
2127         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2128
2129         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2130 }
2131
2132 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2133 {
2134         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2135
2136         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2137         return 0;
2138 }
2139
2140 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2141 {
2142         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2143         int change;
2144         int val;
2145
2146         if (!snd_hdsp_use_is_exclusive(hdsp))
2147                 return -EBUSY;
2148         val = ucontrol->value.enumerated.item[0];
2149         if (val < 0) val = 0;
2150         if (val > 2) val = 2;
2151         spin_lock_irq(&hdsp->lock);
2152         if (val != hdsp_da_gain(hdsp))
2153                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2154         else
2155                 change = 0;
2156         spin_unlock_irq(&hdsp->lock);
2157         return change;
2158 }
2159
2160 #define HDSP_AD_GAIN(xname, xindex) \
2161 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2162   .name = xname, \
2163   .index = xindex, \
2164   .info = snd_hdsp_info_ad_gain, \
2165   .get = snd_hdsp_get_ad_gain, \
2166   .put = snd_hdsp_put_ad_gain \
2167 }
2168
2169 static int hdsp_ad_gain(struct hdsp *hdsp)
2170 {
2171         switch (hdsp->control_register & HDSP_ADGainMask) {
2172         case HDSP_ADGainMinus10dBV:
2173                 return 0;
2174         case HDSP_ADGainPlus4dBu:
2175                 return 1;
2176         case HDSP_ADGainLowGain:
2177                 return 2;
2178         default:
2179                 return 1;
2180         }
2181 }
2182
2183 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2184 {
2185         hdsp->control_register &= ~HDSP_ADGainMask;
2186         switch (mode) {
2187         case 0:
2188                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2189                 break;
2190         case 1:
2191                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2192                 break;
2193         case 2:
2194                 hdsp->control_register |= HDSP_ADGainLowGain;
2195                 break;
2196         default:
2197                 return -1;
2198
2199         }
2200         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2201         return 0;
2202 }
2203
2204 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2205 {
2206         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2207
2208         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2209 }
2210
2211 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2212 {
2213         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2214
2215         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2216         return 0;
2217 }
2218
2219 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2220 {
2221         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2222         int change;
2223         int val;
2224
2225         if (!snd_hdsp_use_is_exclusive(hdsp))
2226                 return -EBUSY;
2227         val = ucontrol->value.enumerated.item[0];
2228         if (val < 0) val = 0;
2229         if (val > 2) val = 2;
2230         spin_lock_irq(&hdsp->lock);
2231         if (val != hdsp_ad_gain(hdsp))
2232                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2233         else
2234                 change = 0;
2235         spin_unlock_irq(&hdsp->lock);
2236         return change;
2237 }
2238
2239 #define HDSP_PHONE_GAIN(xname, xindex) \
2240 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2241   .name = xname, \
2242   .index = xindex, \
2243   .info = snd_hdsp_info_phone_gain, \
2244   .get = snd_hdsp_get_phone_gain, \
2245   .put = snd_hdsp_put_phone_gain \
2246 }
2247
2248 static int hdsp_phone_gain(struct hdsp *hdsp)
2249 {
2250         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2251         case HDSP_PhoneGain0dB:
2252                 return 0;
2253         case HDSP_PhoneGainMinus6dB:
2254                 return 1;
2255         case HDSP_PhoneGainMinus12dB:
2256                 return 2;
2257         default:
2258                 return 0;
2259         }
2260 }
2261
2262 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2263 {
2264         hdsp->control_register &= ~HDSP_PhoneGainMask;
2265         switch (mode) {
2266         case 0:
2267                 hdsp->control_register |= HDSP_PhoneGain0dB;
2268                 break;
2269         case 1:
2270                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2271                 break;
2272         case 2:
2273                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2274                 break;
2275         default:
2276                 return -1;
2277
2278         }
2279         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2280         return 0;
2281 }
2282
2283 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2284 {
2285         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2286
2287         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2288 }
2289
2290 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2291 {
2292         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2293
2294         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2295         return 0;
2296 }
2297
2298 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2299 {
2300         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2301         int change;
2302         int val;
2303
2304         if (!snd_hdsp_use_is_exclusive(hdsp))
2305                 return -EBUSY;
2306         val = ucontrol->value.enumerated.item[0];
2307         if (val < 0) val = 0;
2308         if (val > 2) val = 2;
2309         spin_lock_irq(&hdsp->lock);
2310         if (val != hdsp_phone_gain(hdsp))
2311                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2312         else
2313                 change = 0;
2314         spin_unlock_irq(&hdsp->lock);
2315         return change;
2316 }
2317
2318 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2319 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2320   .name = xname, \
2321   .index = xindex, \
2322   .info = snd_hdsp_info_pref_sync_ref, \
2323   .get = snd_hdsp_get_pref_sync_ref, \
2324   .put = snd_hdsp_put_pref_sync_ref \
2325 }
2326
2327 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2328 {
2329         /* Notice that this looks at the requested sync source,
2330            not the one actually in use.
2331         */
2332
2333         switch (hdsp->control_register & HDSP_SyncRefMask) {
2334         case HDSP_SyncRef_ADAT1:
2335                 return HDSP_SYNC_FROM_ADAT1;
2336         case HDSP_SyncRef_ADAT2:
2337                 return HDSP_SYNC_FROM_ADAT2;
2338         case HDSP_SyncRef_ADAT3:
2339                 return HDSP_SYNC_FROM_ADAT3;
2340         case HDSP_SyncRef_SPDIF:
2341                 return HDSP_SYNC_FROM_SPDIF;
2342         case HDSP_SyncRef_WORD:
2343                 return HDSP_SYNC_FROM_WORD;
2344         case HDSP_SyncRef_ADAT_SYNC:
2345                 return HDSP_SYNC_FROM_ADAT_SYNC;
2346         default:
2347                 return HDSP_SYNC_FROM_WORD;
2348         }
2349         return 0;
2350 }
2351
2352 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2353 {
2354         hdsp->control_register &= ~HDSP_SyncRefMask;
2355         switch (pref) {
2356         case HDSP_SYNC_FROM_ADAT1:
2357                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2358                 break;
2359         case HDSP_SYNC_FROM_ADAT2:
2360                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2361                 break;
2362         case HDSP_SYNC_FROM_ADAT3:
2363                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2364                 break;
2365         case HDSP_SYNC_FROM_SPDIF:
2366                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2367                 break;
2368         case HDSP_SYNC_FROM_WORD:
2369                 hdsp->control_register |= HDSP_SyncRef_WORD;
2370                 break;
2371         case HDSP_SYNC_FROM_ADAT_SYNC:
2372                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2373                 break;
2374         default:
2375                 return -1;
2376         }
2377         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2378         return 0;
2379 }
2380
2381 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2382 {
2383         static const char * const texts[] = {
2384                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2385         };
2386         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2387         int num_items;
2388
2389         switch (hdsp->io_type) {
2390         case Digiface:
2391         case H9652:
2392                 num_items = 6;
2393                 break;
2394         case Multiface:
2395                 num_items = 4;
2396                 break;
2397         case H9632:
2398                 num_items = 3;
2399                 break;
2400         default:
2401                 return -EINVAL;
2402         }
2403
2404         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2405 }
2406
2407 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2408 {
2409         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2410
2411         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2412         return 0;
2413 }
2414
2415 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2416 {
2417         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2418         int change, max;
2419         unsigned int val;
2420
2421         if (!snd_hdsp_use_is_exclusive(hdsp))
2422                 return -EBUSY;
2423
2424         switch (hdsp->io_type) {
2425         case Digiface:
2426         case H9652:
2427                 max = 6;
2428                 break;
2429         case Multiface:
2430                 max = 4;
2431                 break;
2432         case H9632:
2433                 max = 3;
2434                 break;
2435         default:
2436                 return -EIO;
2437         }
2438
2439         val = ucontrol->value.enumerated.item[0] % max;
2440         spin_lock_irq(&hdsp->lock);
2441         change = (int)val != hdsp_pref_sync_ref(hdsp);
2442         hdsp_set_pref_sync_ref(hdsp, val);
2443         spin_unlock_irq(&hdsp->lock);
2444         return change;
2445 }
2446
2447 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2448 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2449   .name = xname, \
2450   .index = xindex, \
2451   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2452   .info = snd_hdsp_info_autosync_ref, \
2453   .get = snd_hdsp_get_autosync_ref, \
2454 }
2455
2456 static int hdsp_autosync_ref(struct hdsp *hdsp)
2457 {
2458         /* This looks at the autosync selected sync reference */
2459         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2460
2461         switch (status2 & HDSP_SelSyncRefMask) {
2462         case HDSP_SelSyncRef_WORD:
2463                 return HDSP_AUTOSYNC_FROM_WORD;
2464         case HDSP_SelSyncRef_ADAT_SYNC:
2465                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2466         case HDSP_SelSyncRef_SPDIF:
2467                 return HDSP_AUTOSYNC_FROM_SPDIF;
2468         case HDSP_SelSyncRefMask:
2469                 return HDSP_AUTOSYNC_FROM_NONE;
2470         case HDSP_SelSyncRef_ADAT1:
2471                 return HDSP_AUTOSYNC_FROM_ADAT1;
2472         case HDSP_SelSyncRef_ADAT2:
2473                 return HDSP_AUTOSYNC_FROM_ADAT2;
2474         case HDSP_SelSyncRef_ADAT3:
2475                 return HDSP_AUTOSYNC_FROM_ADAT3;
2476         default:
2477                 return HDSP_AUTOSYNC_FROM_WORD;
2478         }
2479         return 0;
2480 }
2481
2482 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2483 {
2484         static const char * const texts[] = {
2485                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2486         };
2487
2488         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2489 }
2490
2491 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2492 {
2493         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2494
2495         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2496         return 0;
2497 }
2498
2499 #define HDSP_PRECISE_POINTER(xname, xindex) \
2500 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2501   .name = xname, \
2502   .index = xindex, \
2503   .info = snd_hdsp_info_precise_pointer, \
2504   .get = snd_hdsp_get_precise_pointer, \
2505   .put = snd_hdsp_put_precise_pointer \
2506 }
2507
2508 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2509 {
2510         if (precise)
2511                 hdsp->precise_ptr = 1;
2512         else
2513                 hdsp->precise_ptr = 0;
2514         return 0;
2515 }
2516
2517 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2518
2519 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2520 {
2521         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2522
2523         spin_lock_irq(&hdsp->lock);
2524         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2525         spin_unlock_irq(&hdsp->lock);
2526         return 0;
2527 }
2528
2529 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2530 {
2531         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2532         int change;
2533         unsigned int val;
2534
2535         if (!snd_hdsp_use_is_exclusive(hdsp))
2536                 return -EBUSY;
2537         val = ucontrol->value.integer.value[0] & 1;
2538         spin_lock_irq(&hdsp->lock);
2539         change = (int)val != hdsp->precise_ptr;
2540         hdsp_set_precise_pointer(hdsp, val);
2541         spin_unlock_irq(&hdsp->lock);
2542         return change;
2543 }
2544
2545 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2546 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2547   .name = xname, \
2548   .index = xindex, \
2549   .info = snd_hdsp_info_use_midi_tasklet, \
2550   .get = snd_hdsp_get_use_midi_tasklet, \
2551   .put = snd_hdsp_put_use_midi_tasklet \
2552 }
2553
2554 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2555 {
2556         if (use_tasklet)
2557                 hdsp->use_midi_tasklet = 1;
2558         else
2559                 hdsp->use_midi_tasklet = 0;
2560         return 0;
2561 }
2562
2563 #define snd_hdsp_info_use_midi_tasklet          snd_ctl_boolean_mono_info
2564
2565 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2566 {
2567         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2568
2569         spin_lock_irq(&hdsp->lock);
2570         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2571         spin_unlock_irq(&hdsp->lock);
2572         return 0;
2573 }
2574
2575 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2576 {
2577         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2578         int change;
2579         unsigned int val;
2580
2581         if (!snd_hdsp_use_is_exclusive(hdsp))
2582                 return -EBUSY;
2583         val = ucontrol->value.integer.value[0] & 1;
2584         spin_lock_irq(&hdsp->lock);
2585         change = (int)val != hdsp->use_midi_tasklet;
2586         hdsp_set_use_midi_tasklet(hdsp, val);
2587         spin_unlock_irq(&hdsp->lock);
2588         return change;
2589 }
2590
2591 #define HDSP_MIXER(xname, xindex) \
2592 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2593   .name = xname, \
2594   .index = xindex, \
2595   .device = 0, \
2596   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2597                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2598   .info = snd_hdsp_info_mixer, \
2599   .get = snd_hdsp_get_mixer, \
2600   .put = snd_hdsp_put_mixer \
2601 }
2602
2603 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2604 {
2605         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2606         uinfo->count = 3;
2607         uinfo->value.integer.min = 0;
2608         uinfo->value.integer.max = 65536;
2609         uinfo->value.integer.step = 1;
2610         return 0;
2611 }
2612
2613 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2614 {
2615         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2616         int source;
2617         int destination;
2618         int addr;
2619
2620         source = ucontrol->value.integer.value[0];
2621         destination = ucontrol->value.integer.value[1];
2622
2623         if (source >= hdsp->max_channels)
2624                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2625         else
2626                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2627
2628         spin_lock_irq(&hdsp->lock);
2629         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2630         spin_unlock_irq(&hdsp->lock);
2631         return 0;
2632 }
2633
2634 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2635 {
2636         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2637         int change;
2638         int source;
2639         int destination;
2640         int gain;
2641         int addr;
2642
2643         if (!snd_hdsp_use_is_exclusive(hdsp))
2644                 return -EBUSY;
2645
2646         source = ucontrol->value.integer.value[0];
2647         destination = ucontrol->value.integer.value[1];
2648
2649         if (source >= hdsp->max_channels)
2650                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2651         else
2652                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2653
2654         gain = ucontrol->value.integer.value[2];
2655
2656         spin_lock_irq(&hdsp->lock);
2657         change = gain != hdsp_read_gain(hdsp, addr);
2658         if (change)
2659                 hdsp_write_gain(hdsp, addr, gain);
2660         spin_unlock_irq(&hdsp->lock);
2661         return change;
2662 }
2663
2664 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2665 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2666   .name = xname, \
2667   .index = xindex, \
2668   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2669   .info = snd_hdsp_info_sync_check, \
2670   .get = snd_hdsp_get_wc_sync_check \
2671 }
2672
2673 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2674 {
2675         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2676
2677         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2678 }
2679
2680 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2681 {
2682         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2683         if (status2 & HDSP_wc_lock) {
2684                 if (status2 & HDSP_wc_sync)
2685                         return 2;
2686                 else
2687                          return 1;
2688         } else
2689                 return 0;
2690         return 0;
2691 }
2692
2693 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2694 {
2695         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2696
2697         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2698         return 0;
2699 }
2700
2701 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2702 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2703   .name = xname, \
2704   .index = xindex, \
2705   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2706   .info = snd_hdsp_info_sync_check, \
2707   .get = snd_hdsp_get_spdif_sync_check \
2708 }
2709
2710 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2711 {
2712         int status = hdsp_read(hdsp, HDSP_statusRegister);
2713         if (status & HDSP_SPDIFErrorFlag)
2714                 return 0;
2715         else {
2716                 if (status & HDSP_SPDIFSync)
2717                         return 2;
2718                 else
2719                         return 1;
2720         }
2721         return 0;
2722 }
2723
2724 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2725 {
2726         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2727
2728         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2729         return 0;
2730 }
2731
2732 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2733 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2734   .name = xname, \
2735   .index = xindex, \
2736   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2737   .info = snd_hdsp_info_sync_check, \
2738   .get = snd_hdsp_get_adatsync_sync_check \
2739 }
2740
2741 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2742 {
2743         int status = hdsp_read(hdsp, HDSP_statusRegister);
2744         if (status & HDSP_TimecodeLock) {
2745                 if (status & HDSP_TimecodeSync)
2746                         return 2;
2747                 else
2748                         return 1;
2749         } else
2750                 return 0;
2751 }
2752
2753 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2754 {
2755         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2756
2757         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2758         return 0;
2759 }
2760
2761 #define HDSP_ADAT_SYNC_CHECK \
2762 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2763   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2764   .info = snd_hdsp_info_sync_check, \
2765   .get = snd_hdsp_get_adat_sync_check \
2766 }
2767
2768 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2769 {
2770         int status = hdsp_read(hdsp, HDSP_statusRegister);
2771
2772         if (status & (HDSP_Lock0>>idx)) {
2773                 if (status & (HDSP_Sync0>>idx))
2774                         return 2;
2775                 else
2776                         return 1;
2777         } else
2778                 return 0;
2779 }
2780
2781 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2782 {
2783         int offset;
2784         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2785
2786         offset = ucontrol->id.index - 1;
2787         if (snd_BUG_ON(offset < 0))
2788                 return -EINVAL;
2789
2790         switch (hdsp->io_type) {
2791         case Digiface:
2792         case H9652:
2793                 if (offset >= 3)
2794                         return -EINVAL;
2795                 break;
2796         case Multiface:
2797         case H9632:
2798                 if (offset >= 1)
2799                         return -EINVAL;
2800                 break;
2801         default:
2802                 return -EIO;
2803         }
2804
2805         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2806         return 0;
2807 }
2808
2809 #define HDSP_DDS_OFFSET(xname, xindex) \
2810 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2811   .name = xname, \
2812   .index = xindex, \
2813   .info = snd_hdsp_info_dds_offset, \
2814   .get = snd_hdsp_get_dds_offset, \
2815   .put = snd_hdsp_put_dds_offset \
2816 }
2817
2818 static int hdsp_dds_offset(struct hdsp *hdsp)
2819 {
2820         u64 n;
2821         unsigned int dds_value = hdsp->dds_value;
2822         int system_sample_rate = hdsp->system_sample_rate;
2823
2824         if (!dds_value)
2825                 return 0;
2826
2827         n = DDS_NUMERATOR;
2828         /*
2829          * dds_value = n / rate
2830          * rate = n / dds_value
2831          */
2832         n = div_u64(n, dds_value);
2833         if (system_sample_rate >= 112000)
2834                 n *= 4;
2835         else if (system_sample_rate >= 56000)
2836                 n *= 2;
2837         return ((int)n) - system_sample_rate;
2838 }
2839
2840 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2841 {
2842         int rate = hdsp->system_sample_rate + offset_hz;
2843         hdsp_set_dds_value(hdsp, rate);
2844         return 0;
2845 }
2846
2847 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2848 {
2849         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2850         uinfo->count = 1;
2851         uinfo->value.integer.min = -5000;
2852         uinfo->value.integer.max = 5000;
2853         return 0;
2854 }
2855
2856 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2857 {
2858         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2859
2860         ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2861         return 0;
2862 }
2863
2864 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2865 {
2866         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2867         int change;
2868         int val;
2869
2870         if (!snd_hdsp_use_is_exclusive(hdsp))
2871                 return -EBUSY;
2872         val = ucontrol->value.integer.value[0];
2873         spin_lock_irq(&hdsp->lock);
2874         if (val != hdsp_dds_offset(hdsp))
2875                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2876         else
2877                 change = 0;
2878         spin_unlock_irq(&hdsp->lock);
2879         return change;
2880 }
2881
2882 static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2883 HDSP_DA_GAIN("DA Gain", 0),
2884 HDSP_AD_GAIN("AD Gain", 0),
2885 HDSP_PHONE_GAIN("Phones Gain", 0),
2886 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2887 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2888 };
2889
2890 static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2891 {
2892         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2893         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2894         .info =         snd_hdsp_control_spdif_info,
2895         .get =          snd_hdsp_control_spdif_get,
2896         .put =          snd_hdsp_control_spdif_put,
2897 },
2898 {
2899         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2900         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2901         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2902         .info =         snd_hdsp_control_spdif_stream_info,
2903         .get =          snd_hdsp_control_spdif_stream_get,
2904         .put =          snd_hdsp_control_spdif_stream_put,
2905 },
2906 {
2907         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2908         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2909         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2910         .info =         snd_hdsp_control_spdif_mask_info,
2911         .get =          snd_hdsp_control_spdif_mask_get,
2912         .private_value = IEC958_AES0_NONAUDIO |
2913                          IEC958_AES0_PROFESSIONAL |
2914                          IEC958_AES0_CON_EMPHASIS,
2915 },
2916 {
2917         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2918         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2919         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2920         .info =         snd_hdsp_control_spdif_mask_info,
2921         .get =          snd_hdsp_control_spdif_mask_get,
2922         .private_value = IEC958_AES0_NONAUDIO |
2923                          IEC958_AES0_PROFESSIONAL |
2924                          IEC958_AES0_PRO_EMPHASIS,
2925 },
2926 HDSP_MIXER("Mixer", 0),
2927 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2928 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2929 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2930 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2931 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2932 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2933 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2934 {
2935         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2936         .name = "Sample Clock Source Locking",
2937         .info = snd_hdsp_info_clock_source_lock,
2938         .get = snd_hdsp_get_clock_source_lock,
2939         .put = snd_hdsp_put_clock_source_lock,
2940 },
2941 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2942 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2943 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2944 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2945 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2946 /* 'External Rate' complies with the alsa control naming scheme */
2947 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2948 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2949 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2950 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2951 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2952 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2953 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2954 };
2955
2956
2957 static int hdsp_rpm_input12(struct hdsp *hdsp)
2958 {
2959         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2960         case HDSP_RPM_Inp12_Phon_6dB:
2961                 return 0;
2962         case HDSP_RPM_Inp12_Phon_n6dB:
2963                 return 2;
2964         case HDSP_RPM_Inp12_Line_0dB:
2965                 return 3;
2966         case HDSP_RPM_Inp12_Line_n6dB:
2967                 return 4;
2968         }
2969         return 1;
2970 }
2971
2972
2973 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2974 {
2975         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2976
2977         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2978         return 0;
2979 }
2980
2981
2982 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2983 {
2984         hdsp->control_register &= ~HDSP_RPM_Inp12;
2985         switch (mode) {
2986         case 0:
2987                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2988                 break;
2989         case 1:
2990                 break;
2991         case 2:
2992                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2993                 break;
2994         case 3:
2995                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2996                 break;
2997         case 4:
2998                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2999                 break;
3000         default:
3001                 return -1;
3002         }
3003
3004         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3005         return 0;
3006 }
3007
3008
3009 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3010 {
3011         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3012         int change;
3013         int val;
3014
3015         if (!snd_hdsp_use_is_exclusive(hdsp))
3016                 return -EBUSY;
3017         val = ucontrol->value.enumerated.item[0];
3018         if (val < 0)
3019                 val = 0;
3020         if (val > 4)
3021                 val = 4;
3022         spin_lock_irq(&hdsp->lock);
3023         if (val != hdsp_rpm_input12(hdsp))
3024                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3025         else
3026                 change = 0;
3027         spin_unlock_irq(&hdsp->lock);
3028         return change;
3029 }
3030
3031
3032 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3033 {
3034         static const char * const texts[] = {
3035                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3036         };
3037
3038         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3039 }
3040
3041
3042 static int hdsp_rpm_input34(struct hdsp *hdsp)
3043 {
3044         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3045         case HDSP_RPM_Inp34_Phon_6dB:
3046                 return 0;
3047         case HDSP_RPM_Inp34_Phon_n6dB:
3048                 return 2;
3049         case HDSP_RPM_Inp34_Line_0dB:
3050                 return 3;
3051         case HDSP_RPM_Inp34_Line_n6dB:
3052                 return 4;
3053         }
3054         return 1;
3055 }
3056
3057
3058 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3059 {
3060         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3061
3062         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3063         return 0;
3064 }
3065
3066
3067 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3068 {
3069         hdsp->control_register &= ~HDSP_RPM_Inp34;
3070         switch (mode) {
3071         case 0:
3072                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3073                 break;
3074         case 1:
3075                 break;
3076         case 2:
3077                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3078                 break;
3079         case 3:
3080                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3081                 break;
3082         case 4:
3083                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3084                 break;
3085         default:
3086                 return -1;
3087         }
3088
3089         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3090         return 0;
3091 }
3092
3093
3094 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3095 {
3096         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3097         int change;
3098         int val;
3099
3100         if (!snd_hdsp_use_is_exclusive(hdsp))
3101                 return -EBUSY;
3102         val = ucontrol->value.enumerated.item[0];
3103         if (val < 0)
3104                 val = 0;
3105         if (val > 4)
3106                 val = 4;
3107         spin_lock_irq(&hdsp->lock);
3108         if (val != hdsp_rpm_input34(hdsp))
3109                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3110         else
3111                 change = 0;
3112         spin_unlock_irq(&hdsp->lock);
3113         return change;
3114 }
3115
3116
3117 /* RPM Bypass switch */
3118 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3119 {
3120         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3121 }
3122
3123
3124 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3125 {
3126         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3127
3128         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3129         return 0;
3130 }
3131
3132
3133 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3134 {
3135         if (on)
3136                 hdsp->control_register |= HDSP_RPM_Bypass;
3137         else
3138                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3139         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3140         return 0;
3141 }
3142
3143
3144 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3145 {
3146         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3147         int change;
3148         unsigned int val;
3149
3150         if (!snd_hdsp_use_is_exclusive(hdsp))
3151                 return -EBUSY;
3152         val = ucontrol->value.integer.value[0] & 1;
3153         spin_lock_irq(&hdsp->lock);
3154         change = (int)val != hdsp_rpm_bypass(hdsp);
3155         hdsp_set_rpm_bypass(hdsp, val);
3156         spin_unlock_irq(&hdsp->lock);
3157         return change;
3158 }
3159
3160
3161 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3162 {
3163         static const char * const texts[] = {"On", "Off"};
3164
3165         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3166 }
3167
3168
3169 /* RPM Disconnect switch */
3170 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3171 {
3172         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3173 }
3174
3175
3176 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3177 {
3178         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3179
3180         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3181         return 0;
3182 }
3183
3184
3185 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3186 {
3187         if (on)
3188                 hdsp->control_register |= HDSP_RPM_Disconnect;
3189         else
3190                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3191         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3192         return 0;
3193 }
3194
3195
3196 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3197 {
3198         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3199         int change;
3200         unsigned int val;
3201
3202         if (!snd_hdsp_use_is_exclusive(hdsp))
3203                 return -EBUSY;
3204         val = ucontrol->value.integer.value[0] & 1;
3205         spin_lock_irq(&hdsp->lock);
3206         change = (int)val != hdsp_rpm_disconnect(hdsp);
3207         hdsp_set_rpm_disconnect(hdsp, val);
3208         spin_unlock_irq(&hdsp->lock);
3209         return change;
3210 }
3211
3212 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3213 {
3214         static const char * const texts[] = {"On", "Off"};
3215
3216         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3217 }
3218
3219 static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3220         {
3221                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3222                 .name = "RPM Bypass",
3223                 .get = snd_hdsp_get_rpm_bypass,
3224                 .put = snd_hdsp_put_rpm_bypass,
3225                 .info = snd_hdsp_info_rpm_bypass
3226         },
3227         {
3228                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3229                 .name = "RPM Disconnect",
3230                 .get = snd_hdsp_get_rpm_disconnect,
3231                 .put = snd_hdsp_put_rpm_disconnect,
3232                 .info = snd_hdsp_info_rpm_disconnect
3233         },
3234         {
3235                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3236                 .name = "Input 1/2",
3237                 .get = snd_hdsp_get_rpm_input12,
3238                 .put = snd_hdsp_put_rpm_input12,
3239                 .info = snd_hdsp_info_rpm_input
3240         },
3241         {
3242                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3243                 .name = "Input 3/4",
3244                 .get = snd_hdsp_get_rpm_input34,
3245                 .put = snd_hdsp_put_rpm_input34,
3246                 .info = snd_hdsp_info_rpm_input
3247         },
3248         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3249         HDSP_MIXER("Mixer", 0)
3250 };
3251
3252 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3253         HDSP_TOGGLE_SETTING("Analog Extension Board",
3254                         HDSP_AnalogExtensionBoard);
3255 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3256
3257 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3258 {
3259         unsigned int idx;
3260         int err;
3261         struct snd_kcontrol *kctl;
3262
3263         if (hdsp->io_type == RPM) {
3264                 /* RPM Bypass, Disconnect and Input switches */
3265                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3266                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3267                         if (err < 0)
3268                                 return err;
3269                 }
3270                 return 0;
3271         }
3272
3273         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3274                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3275                         return err;
3276                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3277                         hdsp->spdif_ctl = kctl;
3278         }
3279
3280         /* ADAT SyncCheck status */
3281         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3282         snd_hdsp_adat_sync_check.index = 1;
3283         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3284                 return err;
3285         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3286                 for (idx = 1; idx < 3; ++idx) {
3287                         snd_hdsp_adat_sync_check.index = idx+1;
3288                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3289                                 return err;
3290                 }
3291         }
3292
3293         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3294         if (hdsp->io_type == H9632) {
3295                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3296                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3297                                 return err;
3298                 }
3299         }
3300
3301         /* AEB control for H96xx card */
3302         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3303                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3304                                 return err;
3305         }
3306
3307         return 0;
3308 }
3309
3310 /*------------------------------------------------------------
3311    /proc interface
3312  ------------------------------------------------------------*/
3313
3314 static void
3315 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3316 {
3317         struct hdsp *hdsp = entry->private_data;
3318         unsigned int status;
3319         unsigned int status2;
3320         char *pref_sync_ref;
3321         char *autosync_ref;
3322         char *system_clock_mode;
3323         char *clock_source;
3324         int x;
3325
3326         status = hdsp_read(hdsp, HDSP_statusRegister);
3327         status2 = hdsp_read(hdsp, HDSP_status2Register);
3328
3329         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3330                     hdsp->card->number + 1);
3331         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3332                     hdsp->capture_buffer, hdsp->playback_buffer);
3333         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3334                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3335         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3336         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3337                     hdsp->control2_register);
3338         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3339         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3340
3341         if (hdsp_check_for_iobox(hdsp)) {
3342                 snd_iprintf(buffer, "No I/O box connected.\n"
3343                             "Please connect one and upload firmware.\n");
3344                 return;
3345         }
3346
3347         if (hdsp_check_for_firmware(hdsp, 0)) {
3348                 if (hdsp->state & HDSP_FirmwareCached) {
3349                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3350                                 snd_iprintf(buffer, "Firmware loading from "
3351                                             "cache failed, "
3352                                             "please upload manually.\n");
3353                                 return;
3354                         }
3355                 } else {
3356                         int err = -EINVAL;
3357                         err = hdsp_request_fw_loader(hdsp);
3358                         if (err < 0) {
3359                                 snd_iprintf(buffer,
3360                                             "No firmware loaded nor cached, "
3361                                             "please upload firmware.\n");
3362                                 return;
3363                         }
3364                 }
3365         }
3366
3367         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3368         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3369         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3370         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3371         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3372         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3373
3374         snd_iprintf(buffer, "\n");
3375
3376         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3377
3378         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3379         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3380         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3381         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3382
3383         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3384
3385         snd_iprintf(buffer, "\n");
3386
3387         switch (hdsp_clock_source(hdsp)) {
3388         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3389                 clock_source = "AutoSync";
3390                 break;
3391         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3392                 clock_source = "Internal 32 kHz";
3393                 break;
3394         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3395                 clock_source = "Internal 44.1 kHz";
3396                 break;
3397         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3398                 clock_source = "Internal 48 kHz";
3399                 break;
3400         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3401                 clock_source = "Internal 64 kHz";
3402                 break;
3403         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3404                 clock_source = "Internal 88.2 kHz";
3405                 break;
3406         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3407                 clock_source = "Internal 96 kHz";
3408                 break;
3409         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3410                 clock_source = "Internal 128 kHz";
3411                 break;
3412         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3413                 clock_source = "Internal 176.4 kHz";
3414                 break;
3415                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3416                 clock_source = "Internal 192 kHz";
3417                 break;
3418         default:
3419                 clock_source = "Error";
3420         }
3421         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3422
3423         if (hdsp_system_clock_mode(hdsp))
3424                 system_clock_mode = "Slave";
3425         else
3426                 system_clock_mode = "Master";
3427
3428         switch (hdsp_pref_sync_ref (hdsp)) {
3429         case HDSP_SYNC_FROM_WORD:
3430                 pref_sync_ref = "Word Clock";
3431                 break;
3432         case HDSP_SYNC_FROM_ADAT_SYNC:
3433                 pref_sync_ref = "ADAT Sync";
3434                 break;
3435         case HDSP_SYNC_FROM_SPDIF:
3436                 pref_sync_ref = "SPDIF";
3437                 break;
3438         case HDSP_SYNC_FROM_ADAT1:
3439                 pref_sync_ref = "ADAT1";
3440                 break;
3441         case HDSP_SYNC_FROM_ADAT2:
3442                 pref_sync_ref = "ADAT2";
3443                 break;
3444         case HDSP_SYNC_FROM_ADAT3:
3445                 pref_sync_ref = "ADAT3";
3446                 break;
3447         default:
3448                 pref_sync_ref = "Word Clock";
3449                 break;
3450         }
3451         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3452
3453         switch (hdsp_autosync_ref (hdsp)) {
3454         case HDSP_AUTOSYNC_FROM_WORD:
3455                 autosync_ref = "Word Clock";
3456                 break;
3457         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3458                 autosync_ref = "ADAT Sync";
3459                 break;
3460         case HDSP_AUTOSYNC_FROM_SPDIF:
3461                 autosync_ref = "SPDIF";
3462                 break;
3463         case HDSP_AUTOSYNC_FROM_NONE:
3464                 autosync_ref = "None";
3465                 break;
3466         case HDSP_AUTOSYNC_FROM_ADAT1:
3467                 autosync_ref = "ADAT1";
3468                 break;
3469         case HDSP_AUTOSYNC_FROM_ADAT2:
3470                 autosync_ref = "ADAT2";
3471                 break;
3472         case HDSP_AUTOSYNC_FROM_ADAT3:
3473                 autosync_ref = "ADAT3";
3474                 break;
3475         default:
3476                 autosync_ref = "---";
3477                 break;
3478         }
3479         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3480
3481         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3482
3483         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3484
3485         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3486         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3487
3488         snd_iprintf(buffer, "\n");
3489
3490         if (hdsp->io_type != RPM) {
3491                 switch (hdsp_spdif_in(hdsp)) {
3492                 case HDSP_SPDIFIN_OPTICAL:
3493                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3494                         break;
3495                 case HDSP_SPDIFIN_COAXIAL:
3496                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3497                         break;
3498                 case HDSP_SPDIFIN_INTERNAL:
3499                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3500                         break;
3501                 case HDSP_SPDIFIN_AES:
3502                         snd_iprintf(buffer, "IEC958 input: AES\n");
3503                         break;
3504                 default:
3505                         snd_iprintf(buffer, "IEC958 input: ???\n");
3506                         break;
3507                 }
3508         }
3509
3510         if (RPM == hdsp->io_type) {
3511                 if (hdsp->control_register & HDSP_RPM_Bypass)
3512                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3513                 else
3514                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3515                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3516                         snd_iprintf(buffer, "RPM disconnected\n");
3517                 else
3518                         snd_iprintf(buffer, "RPM connected\n");
3519
3520                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3521                 case HDSP_RPM_Inp12_Phon_6dB:
3522                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3523                         break;
3524                 case HDSP_RPM_Inp12_Phon_0dB:
3525                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3526                         break;
3527                 case HDSP_RPM_Inp12_Phon_n6dB:
3528                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3529                         break;
3530                 case HDSP_RPM_Inp12_Line_0dB:
3531                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3532                         break;
3533                 case HDSP_RPM_Inp12_Line_n6dB:
3534                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3535                         break;
3536                 default:
3537                         snd_iprintf(buffer, "Input 1/2: ???\n");
3538                 }
3539
3540                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3541                 case HDSP_RPM_Inp34_Phon_6dB:
3542                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3543                         break;
3544                 case HDSP_RPM_Inp34_Phon_0dB:
3545                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3546                         break;
3547                 case HDSP_RPM_Inp34_Phon_n6dB:
3548                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3549                         break;
3550                 case HDSP_RPM_Inp34_Line_0dB:
3551                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3552                         break;
3553                 case HDSP_RPM_Inp34_Line_n6dB:
3554                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3555                         break;
3556                 default:
3557                         snd_iprintf(buffer, "Input 3/4: ???\n");
3558                 }
3559
3560         } else {
3561                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3562                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3563                 else
3564                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3565
3566                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3567                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3568                 else
3569                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3570
3571                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3572                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3573                 else
3574                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3575
3576                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3577                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3578                 else
3579                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3580                 x = hdsp_spdif_sample_rate(hdsp);
3581                 if (x != 0)
3582                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3583                 else
3584                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3585         }
3586         snd_iprintf(buffer, "\n");
3587
3588         /* Sync Check */
3589         x = status & HDSP_Sync0;
3590         if (status & HDSP_Lock0)
3591                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3592         else
3593                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3594
3595         switch (hdsp->io_type) {
3596         case Digiface:
3597         case H9652:
3598                 x = status & HDSP_Sync1;
3599                 if (status & HDSP_Lock1)
3600                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3601                 else
3602                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3603                 x = status & HDSP_Sync2;
3604                 if (status & HDSP_Lock2)
3605                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3606                 else
3607                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3608                 break;
3609         default:
3610                 /* relax */
3611                 break;
3612         }
3613
3614         x = status & HDSP_SPDIFSync;
3615         if (status & HDSP_SPDIFErrorFlag)
3616                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3617         else
3618                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3619
3620         x = status2 & HDSP_wc_sync;
3621         if (status2 & HDSP_wc_lock)
3622                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3623         else
3624                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3625
3626         x = status & HDSP_TimecodeSync;
3627         if (status & HDSP_TimecodeLock)
3628                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3629         else
3630                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3631
3632         snd_iprintf(buffer, "\n");
3633
3634         /* Informations about H9632 specific controls */
3635         if (hdsp->io_type == H9632) {
3636                 char *tmp;
3637
3638                 switch (hdsp_ad_gain(hdsp)) {
3639                 case 0:
3640                         tmp = "-10 dBV";
3641                         break;
3642                 case 1:
3643                         tmp = "+4 dBu";
3644                         break;
3645                 default:
3646                         tmp = "Lo Gain";
3647                         break;
3648                 }
3649                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3650
3651                 switch (hdsp_da_gain(hdsp)) {
3652                 case 0:
3653                         tmp = "Hi Gain";
3654                         break;
3655                 case 1:
3656                         tmp = "+4 dBu";
3657                         break;
3658                 default:
3659                         tmp = "-10 dBV";
3660                         break;
3661                 }
3662                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3663
3664                 switch (hdsp_phone_gain(hdsp)) {
3665                 case 0:
3666                         tmp = "0 dB";
3667                         break;
3668                 case 1:
3669                         tmp = "-6 dB";
3670                         break;
3671                 default:
3672                         tmp = "-12 dB";
3673                         break;
3674                 }
3675                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3676
3677                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3678                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3679                         "yes" : "no");
3680
3681                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3682                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3683                 else
3684                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3685                 snd_iprintf(buffer, "\n");
3686         }
3687
3688 }
3689
3690 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3691 {
3692         snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3693 }
3694
3695 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3696 {
3697         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3698         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3699 }
3700
3701 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3702 {
3703         unsigned long pb_bus, cb_bus;
3704
3705         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3706             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3707                 if (hdsp->capture_dma_buf.area)
3708                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3709                 dev_err(hdsp->card->dev,
3710                         "%s: no buffers available\n", hdsp->card_name);
3711                 return -ENOMEM;
3712         }
3713
3714         /* Align to bus-space 64K boundary */
3715
3716         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3717         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3718
3719         /* Tell the card where it is */
3720
3721         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3722         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3723
3724         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3725         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3726
3727         return 0;
3728 }
3729
3730 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3731 {
3732         unsigned int i;
3733
3734         /* ASSUMPTION: hdsp->lock is either held, or
3735            there is no need to hold it (e.g. during module
3736            initialization).
3737          */
3738
3739         /* set defaults:
3740
3741            SPDIF Input via Coax
3742            Master clock mode
3743            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3744                             which implies 2 4096 sample, 32Kbyte periods).
3745            Enable line out.
3746          */
3747
3748         hdsp->control_register = HDSP_ClockModeMaster |
3749                                  HDSP_SPDIFInputCoaxial |
3750                                  hdsp_encode_latency(7) |
3751                                  HDSP_LineOut;
3752
3753
3754         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3755
3756 #ifdef SNDRV_BIG_ENDIAN
3757         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3758 #else
3759         hdsp->control2_register = 0;
3760 #endif
3761         if (hdsp->io_type == H9652)
3762                 snd_hdsp_9652_enable_mixer (hdsp);
3763         else
3764                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3765
3766         hdsp_reset_hw_pointer(hdsp);
3767         hdsp_compute_period_size(hdsp);
3768
3769         /* silence everything */
3770
3771         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3772                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3773
3774         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3775                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3776                         return -EIO;
3777         }
3778
3779         /* H9632 specific defaults */
3780         if (hdsp->io_type == H9632) {
3781                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3782                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3783         }
3784
3785         /* set a default rate so that the channel map is set up.
3786          */
3787
3788         hdsp_set_rate(hdsp, 48000, 1);
3789
3790         return 0;
3791 }
3792
3793 static void hdsp_midi_tasklet(unsigned long arg)
3794 {
3795         struct hdsp *hdsp = (struct hdsp *)arg;
3796
3797         if (hdsp->midi[0].pending)
3798                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3799         if (hdsp->midi[1].pending)
3800                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3801 }
3802
3803 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3804 {
3805         struct hdsp *hdsp = (struct hdsp *) dev_id;
3806         unsigned int status;
3807         int audio;
3808         int midi0;
3809         int midi1;
3810         unsigned int midi0status;
3811         unsigned int midi1status;
3812         int schedule = 0;
3813
3814         status = hdsp_read(hdsp, HDSP_statusRegister);
3815
3816         audio = status & HDSP_audioIRQPending;
3817         midi0 = status & HDSP_midi0IRQPending;
3818         midi1 = status & HDSP_midi1IRQPending;
3819
3820         if (!audio && !midi0 && !midi1)
3821                 return IRQ_NONE;
3822
3823         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3824
3825         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3826         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3827
3828         if (!(hdsp->state & HDSP_InitializationComplete))
3829                 return IRQ_HANDLED;
3830
3831         if (audio) {
3832                 if (hdsp->capture_substream)
3833                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3834
3835                 if (hdsp->playback_substream)
3836                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3837         }
3838
3839         if (midi0 && midi0status) {
3840                 if (hdsp->use_midi_tasklet) {
3841                         /* we disable interrupts for this input until processing is done */
3842                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3843                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3844                         hdsp->midi[0].pending = 1;
3845                         schedule = 1;
3846                 } else {
3847                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3848                 }
3849         }
3850         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3851                 if (hdsp->use_midi_tasklet) {
3852                         /* we disable interrupts for this input until processing is done */
3853                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3854                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3855                         hdsp->midi[1].pending = 1;
3856                         schedule = 1;
3857                 } else {
3858                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3859                 }
3860         }
3861         if (hdsp->use_midi_tasklet && schedule)
3862                 tasklet_schedule(&hdsp->midi_tasklet);
3863         return IRQ_HANDLED;
3864 }
3865
3866 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3867 {
3868         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3869         return hdsp_hw_pointer(hdsp);
3870 }
3871
3872 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3873                                              int stream,
3874                                              int channel)
3875
3876 {
3877         int mapped_channel;
3878
3879         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3880                 return NULL;
3881
3882         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3883                 return NULL;
3884
3885         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3886                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3887         else
3888                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3889 }
3890
3891 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3892                                   int channel, unsigned long pos,
3893                                   void __user *src, unsigned long count)
3894 {
3895         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3896         char *channel_buf;
3897
3898         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3899                 return -EINVAL;
3900
3901         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3902         if (snd_BUG_ON(!channel_buf))
3903                 return -EIO;
3904         if (copy_from_user(channel_buf + pos, src, count))
3905                 return -EFAULT;
3906         return 0;
3907 }
3908
3909 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3910                                          int channel, unsigned long pos,
3911                                          void *src, unsigned long count)
3912 {
3913         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3914         char *channel_buf;
3915
3916         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3917         if (snd_BUG_ON(!channel_buf))
3918                 return -EIO;
3919         memcpy(channel_buf + pos, src, count);
3920         return 0;
3921 }
3922
3923 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3924                                  int channel, unsigned long pos,
3925                                  void __user *dst, unsigned long count)
3926 {
3927         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3928         char *channel_buf;
3929
3930         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3931                 return -EINVAL;
3932
3933         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3934         if (snd_BUG_ON(!channel_buf))
3935                 return -EIO;
3936         if (copy_to_user(dst, channel_buf + pos, count))
3937                 return -EFAULT;
3938         return 0;
3939 }
3940
3941 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3942                                         int channel, unsigned long pos,
3943                                         void *dst, unsigned long count)
3944 {
3945         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3946         char *channel_buf;
3947
3948         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3949         if (snd_BUG_ON(!channel_buf))
3950                 return -EIO;
3951         memcpy(dst, channel_buf + pos, count);
3952         return 0;
3953 }
3954
3955 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3956                                int channel, unsigned long pos,
3957                                unsigned long count)
3958 {
3959         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3960         char *channel_buf;
3961
3962         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3963         if (snd_BUG_ON(!channel_buf))
3964                 return -EIO;
3965         memset(channel_buf + pos, 0, count);
3966         return 0;
3967 }
3968
3969 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3970 {
3971         struct snd_pcm_runtime *runtime = substream->runtime;
3972         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3973         struct snd_pcm_substream *other;
3974         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3975                 other = hdsp->capture_substream;
3976         else
3977                 other = hdsp->playback_substream;
3978         if (hdsp->running)
3979                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3980         else
3981                 runtime->status->hw_ptr = 0;
3982         if (other) {
3983                 struct snd_pcm_substream *s;
3984                 struct snd_pcm_runtime *oruntime = other->runtime;
3985                 snd_pcm_group_for_each_entry(s, substream) {
3986                         if (s == other) {
3987                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3988                                 break;
3989                         }
3990                 }
3991         }
3992         return 0;
3993 }
3994
3995 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3996                                  struct snd_pcm_hw_params *params)
3997 {
3998         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3999         int err;
4000         pid_t this_pid;
4001         pid_t other_pid;
4002
4003         if (hdsp_check_for_iobox (hdsp))
4004                 return -EIO;
4005
4006         if (hdsp_check_for_firmware(hdsp, 1))
4007                 return -EIO;
4008
4009         spin_lock_irq(&hdsp->lock);
4010
4011         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4012                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4013                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4014                 this_pid = hdsp->playback_pid;
4015                 other_pid = hdsp->capture_pid;
4016         } else {
4017                 this_pid = hdsp->capture_pid;
4018                 other_pid = hdsp->playback_pid;
4019         }
4020
4021         if ((other_pid > 0) && (this_pid != other_pid)) {
4022
4023                 /* The other stream is open, and not by the same
4024                    task as this one. Make sure that the parameters
4025                    that matter are the same.
4026                  */
4027
4028                 if (params_rate(params) != hdsp->system_sample_rate) {
4029                         spin_unlock_irq(&hdsp->lock);
4030                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4031                         return -EBUSY;
4032                 }
4033
4034                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4035                         spin_unlock_irq(&hdsp->lock);
4036                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4037                         return -EBUSY;
4038                 }
4039
4040                 /* We're fine. */
4041
4042                 spin_unlock_irq(&hdsp->lock);
4043                 return 0;
4044
4045         } else {
4046                 spin_unlock_irq(&hdsp->lock);
4047         }
4048
4049         /* how to make sure that the rate matches an externally-set one ?
4050          */
4051
4052         spin_lock_irq(&hdsp->lock);
4053         if (! hdsp->clock_source_locked) {
4054                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4055                         spin_unlock_irq(&hdsp->lock);
4056                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4057                         return err;
4058                 }
4059         }
4060         spin_unlock_irq(&hdsp->lock);
4061
4062         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4063                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PER