2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/acpi.h>
20 #include <linux/workqueue.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
33 #define RT5663_DEVICE_ID_2 0x6451
34 #define RT5663_DEVICE_ID_1 0x6406
42 struct snd_soc_codec *codec;
43 struct rt5663_platform_data pdata;
44 struct regmap *regmap;
45 struct delayed_work jack_detect_work;
46 struct snd_soc_jack *hs_jack;
47 struct timer_list btn_check_timer;
61 static const struct reg_sequence rt5663_patch_list[] = {
66 static const struct reg_default rt5663_v2_reg[] = {
468 static const struct reg_default rt5663_reg[] = {
726 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
730 case RT5663_SIL_DET_CTL:
731 case RT5663_HP_IMP_GAIN_2:
732 case RT5663_AD_DA_MIXER:
733 case RT5663_FRAC_DIV_2:
734 case RT5663_MICBIAS_1:
735 case RT5663_ASRC_11_2:
736 case RT5663_ADC_EQ_1:
737 case RT5663_INT_ST_1:
738 case RT5663_INT_ST_2:
739 case RT5663_GPIO_STA1:
740 case RT5663_SIN_GEN_1:
741 case RT5663_IL_CMD_1:
742 case RT5663_IL_CMD_5:
743 case RT5663_IL_CMD_PWRSAV1:
744 case RT5663_EM_JACK_TYPE_1:
745 case RT5663_EM_JACK_TYPE_2:
746 case RT5663_EM_JACK_TYPE_3:
747 case RT5663_JD_CTRL2:
748 case RT5663_VENDOR_ID:
749 case RT5663_VENDOR_ID_1:
750 case RT5663_VENDOR_ID_2:
751 case RT5663_PLL_INT_REG:
752 case RT5663_SOFT_RAMP:
753 case RT5663_STO_DRE_1:
754 case RT5663_STO_DRE_5:
755 case RT5663_STO_DRE_6:
756 case RT5663_STO_DRE_7:
757 case RT5663_MIC_DECRO_1:
758 case RT5663_MIC_DECRO_4:
759 case RT5663_HP_IMP_SEN_1:
760 case RT5663_HP_IMP_SEN_3:
761 case RT5663_HP_IMP_SEN_4:
762 case RT5663_HP_IMP_SEN_5:
763 case RT5663_HP_CALIB_1_1:
764 case RT5663_HP_CALIB_9:
765 case RT5663_HP_CALIB_ST1:
766 case RT5663_HP_CALIB_ST2:
767 case RT5663_HP_CALIB_ST3:
768 case RT5663_HP_CALIB_ST4:
769 case RT5663_HP_CALIB_ST5:
770 case RT5663_HP_CALIB_ST6:
771 case RT5663_HP_CALIB_ST7:
772 case RT5663_HP_CALIB_ST8:
773 case RT5663_HP_CALIB_ST9:
781 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
785 case RT5663_HP_OUT_EN:
786 case RT5663_HP_LCH_DRE:
787 case RT5663_HP_RCH_DRE:
788 case RT5663_CALIB_BST:
790 case RT5663_SIL_DET_CTL:
791 case RT5663_PWR_SAV_SILDET:
792 case RT5663_SIDETONE_CTL:
793 case RT5663_STO1_DAC_DIG_VOL:
794 case RT5663_STO1_ADC_DIG_VOL:
795 case RT5663_STO1_BOOST:
796 case RT5663_HP_IMP_GAIN_1:
797 case RT5663_HP_IMP_GAIN_2:
798 case RT5663_STO1_ADC_MIXER:
799 case RT5663_AD_DA_MIXER:
800 case RT5663_STO_DAC_MIXER:
801 case RT5663_DIG_SIDE_MIXER:
802 case RT5663_BYPASS_STO_DAC:
803 case RT5663_CALIB_REC_MIX:
804 case RT5663_PWR_DIG_1:
805 case RT5663_PWR_DIG_2:
806 case RT5663_PWR_ANLG_1:
807 case RT5663_PWR_ANLG_2:
808 case RT5663_PWR_ANLG_3:
809 case RT5663_PWR_MIXER:
810 case RT5663_SIG_CLK_DET:
811 case RT5663_PRE_DIV_GATING_1:
812 case RT5663_PRE_DIV_GATING_2:
813 case RT5663_I2S1_SDP:
814 case RT5663_ADDA_CLK_1:
815 case RT5663_ADDA_RST:
816 case RT5663_FRAC_DIV_1:
817 case RT5663_FRAC_DIV_2:
829 case RT5663_DUMMY_REG:
836 case RT5663_HP_CHARGE_PUMP_1:
837 case RT5663_HP_CHARGE_PUMP_2:
838 case RT5663_MICBIAS_1:
840 case RT5663_ASRC_11_2:
841 case RT5663_DUMMY_REG_2:
842 case RT5663_REC_PATH_GAIN:
843 case RT5663_AUTO_1MRC_CLK:
844 case RT5663_ADC_EQ_1:
845 case RT5663_ADC_EQ_2:
851 case RT5663_INT_ST_1:
852 case RT5663_INT_ST_2:
855 case RT5663_GPIO_STA1:
856 case RT5663_SIN_GEN_1:
857 case RT5663_SIN_GEN_2:
858 case RT5663_SIN_GEN_3:
859 case RT5663_SOF_VOL_ZC1:
860 case RT5663_IL_CMD_1:
861 case RT5663_IL_CMD_2:
862 case RT5663_IL_CMD_3:
863 case RT5663_IL_CMD_4:
864 case RT5663_IL_CMD_5:
865 case RT5663_IL_CMD_6:
866 case RT5663_IL_CMD_7:
867 case RT5663_IL_CMD_8:
868 case RT5663_IL_CMD_PWRSAV1:
869 case RT5663_IL_CMD_PWRSAV2:
870 case RT5663_EM_JACK_TYPE_1:
871 case RT5663_EM_JACK_TYPE_2:
872 case RT5663_EM_JACK_TYPE_3:
873 case RT5663_EM_JACK_TYPE_4:
874 case RT5663_EM_JACK_TYPE_5:
875 case RT5663_EM_JACK_TYPE_6:
876 case RT5663_STO1_HPF_ADJ1:
877 case RT5663_STO1_HPF_ADJ2:
878 case RT5663_FAST_OFF_MICBIAS:
879 case RT5663_JD_CTRL1:
880 case RT5663_JD_CTRL2:
881 case RT5663_DIG_MISC:
882 case RT5663_VENDOR_ID:
883 case RT5663_VENDOR_ID_1:
884 case RT5663_VENDOR_ID_2:
885 case RT5663_DIG_VOL_ZCD:
886 case RT5663_ANA_BIAS_CUR_1:
887 case RT5663_ANA_BIAS_CUR_2:
888 case RT5663_ANA_BIAS_CUR_3:
889 case RT5663_ANA_BIAS_CUR_4:
890 case RT5663_ANA_BIAS_CUR_5:
891 case RT5663_ANA_BIAS_CUR_6:
892 case RT5663_BIAS_CUR_5:
893 case RT5663_BIAS_CUR_6:
894 case RT5663_BIAS_CUR_7:
895 case RT5663_BIAS_CUR_8:
896 case RT5663_DACREF_LDO:
897 case RT5663_DUMMY_REG_3:
898 case RT5663_BIAS_CUR_9:
899 case RT5663_DUMMY_REG_4:
900 case RT5663_VREFADJ_OP:
901 case RT5663_VREF_RECMIX:
902 case RT5663_CHARGE_PUMP_1:
903 case RT5663_CHARGE_PUMP_1_2:
904 case RT5663_CHARGE_PUMP_1_3:
905 case RT5663_CHARGE_PUMP_2:
906 case RT5663_DIG_IN_PIN1:
907 case RT5663_PAD_DRV_CTL:
908 case RT5663_PLL_INT_REG:
909 case RT5663_CHOP_DAC_L:
910 case RT5663_CHOP_ADC:
911 case RT5663_CALIB_ADC:
912 case RT5663_CHOP_DAC_R:
913 case RT5663_DUMMY_CTL_DACLR:
914 case RT5663_DUMMY_REG_5:
915 case RT5663_SOFT_RAMP:
916 case RT5663_TEST_MODE_1:
917 case RT5663_TEST_MODE_2:
918 case RT5663_TEST_MODE_3:
919 case RT5663_STO_DRE_1:
920 case RT5663_STO_DRE_2:
921 case RT5663_STO_DRE_3:
922 case RT5663_STO_DRE_4:
923 case RT5663_STO_DRE_5:
924 case RT5663_STO_DRE_6:
925 case RT5663_STO_DRE_7:
926 case RT5663_STO_DRE_8:
927 case RT5663_STO_DRE_9:
928 case RT5663_STO_DRE_10:
929 case RT5663_MIC_DECRO_1:
930 case RT5663_MIC_DECRO_2:
931 case RT5663_MIC_DECRO_3:
932 case RT5663_MIC_DECRO_4:
933 case RT5663_MIC_DECRO_5:
934 case RT5663_MIC_DECRO_6:
935 case RT5663_HP_DECRO_1:
936 case RT5663_HP_DECRO_2:
937 case RT5663_HP_DECRO_3:
938 case RT5663_HP_DECRO_4:
939 case RT5663_HP_DECOUP:
940 case RT5663_HP_IMP_SEN_MAP8:
941 case RT5663_HP_IMP_SEN_MAP9:
942 case RT5663_HP_IMP_SEN_MAP10:
943 case RT5663_HP_IMP_SEN_MAP11:
944 case RT5663_HP_IMP_SEN_1:
945 case RT5663_HP_IMP_SEN_2:
946 case RT5663_HP_IMP_SEN_3:
947 case RT5663_HP_IMP_SEN_4:
948 case RT5663_HP_IMP_SEN_5:
949 case RT5663_HP_IMP_SEN_6:
950 case RT5663_HP_IMP_SEN_7:
951 case RT5663_HP_IMP_SEN_8:
952 case RT5663_HP_IMP_SEN_9:
953 case RT5663_HP_IMP_SEN_10:
954 case RT5663_HP_IMP_SEN_11:
955 case RT5663_HP_IMP_SEN_12:
956 case RT5663_HP_IMP_SEN_13:
957 case RT5663_HP_IMP_SEN_14:
958 case RT5663_HP_IMP_SEN_15:
959 case RT5663_HP_IMP_SEN_16:
960 case RT5663_HP_IMP_SEN_17:
961 case RT5663_HP_IMP_SEN_18:
962 case RT5663_HP_IMP_SEN_19:
963 case RT5663_HP_IMPSEN_DIG5:
964 case RT5663_HP_IMPSEN_MAP1:
965 case RT5663_HP_IMPSEN_MAP2:
966 case RT5663_HP_IMPSEN_MAP3:
967 case RT5663_HP_IMPSEN_MAP4:
968 case RT5663_HP_IMPSEN_MAP5:
969 case RT5663_HP_IMPSEN_MAP7:
970 case RT5663_HP_LOGIC_1:
971 case RT5663_HP_LOGIC_2:
972 case RT5663_HP_CALIB_1:
973 case RT5663_HP_CALIB_1_1:
974 case RT5663_HP_CALIB_2:
975 case RT5663_HP_CALIB_3:
976 case RT5663_HP_CALIB_4:
977 case RT5663_HP_CALIB_5:
978 case RT5663_HP_CALIB_5_1:
979 case RT5663_HP_CALIB_6:
980 case RT5663_HP_CALIB_7:
981 case RT5663_HP_CALIB_9:
982 case RT5663_HP_CALIB_10:
983 case RT5663_HP_CALIB_11:
984 case RT5663_HP_CALIB_ST1:
985 case RT5663_HP_CALIB_ST2:
986 case RT5663_HP_CALIB_ST3:
987 case RT5663_HP_CALIB_ST4:
988 case RT5663_HP_CALIB_ST5:
989 case RT5663_HP_CALIB_ST6:
990 case RT5663_HP_CALIB_ST7:
991 case RT5663_HP_CALIB_ST8:
992 case RT5663_HP_CALIB_ST9:
993 case RT5663_HP_AMP_DET:
994 case RT5663_DUMMY_REG_6:
1000 case RT5663_DUMMY_2:
1001 case RT5663_DUMMY_3:
1003 case RT5663_ADC_LCH_LPF1_A1:
1004 case RT5663_ADC_RCH_LPF1_A1:
1005 case RT5663_ADC_LCH_LPF1_H0:
1006 case RT5663_ADC_RCH_LPF1_H0:
1007 case RT5663_ADC_LCH_BPF1_A1:
1008 case RT5663_ADC_RCH_BPF1_A1:
1009 case RT5663_ADC_LCH_BPF1_A2:
1010 case RT5663_ADC_RCH_BPF1_A2:
1011 case RT5663_ADC_LCH_BPF1_H0:
1012 case RT5663_ADC_RCH_BPF1_H0:
1013 case RT5663_ADC_LCH_BPF2_A1:
1014 case RT5663_ADC_RCH_BPF2_A1:
1015 case RT5663_ADC_LCH_BPF2_A2:
1016 case RT5663_ADC_RCH_BPF2_A2:
1017 case RT5663_ADC_LCH_BPF2_H0:
1018 case RT5663_ADC_RCH_BPF2_H0:
1019 case RT5663_ADC_LCH_BPF3_A1:
1020 case RT5663_ADC_RCH_BPF3_A1:
1021 case RT5663_ADC_LCH_BPF3_A2:
1022 case RT5663_ADC_RCH_BPF3_A2:
1023 case RT5663_ADC_LCH_BPF3_H0:
1024 case RT5663_ADC_RCH_BPF3_H0:
1025 case RT5663_ADC_LCH_BPF4_A1:
1026 case RT5663_ADC_RCH_BPF4_A1:
1027 case RT5663_ADC_LCH_BPF4_A2:
1028 case RT5663_ADC_RCH_BPF4_A2:
1029 case RT5663_ADC_LCH_BPF4_H0:
1030 case RT5663_ADC_RCH_BPF4_H0:
1031 case RT5663_ADC_LCH_HPF1_A1:
1032 case RT5663_ADC_RCH_HPF1_A1:
1033 case RT5663_ADC_LCH_HPF1_H0:
1034 case RT5663_ADC_RCH_HPF1_H0:
1035 case RT5663_ADC_EQ_PRE_VOL_L:
1036 case RT5663_ADC_EQ_PRE_VOL_R:
1037 case RT5663_ADC_EQ_POST_VOL_L:
1038 case RT5663_ADC_EQ_POST_VOL_R:
1045 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1049 case RT5663_CBJ_TYPE_2:
1050 case RT5663_PDM_OUT_CTL:
1051 case RT5663_PDM_I2C_DATA_CTL1:
1052 case RT5663_PDM_I2C_DATA_CTL4:
1053 case RT5663_ALC_BK_GAIN:
1055 case RT5663_MICBIAS_1:
1056 case RT5663_ADC_EQ_1:
1057 case RT5663_INT_ST_1:
1058 case RT5663_GPIO_STA2:
1059 case RT5663_IL_CMD_1:
1060 case RT5663_IL_CMD_5:
1061 case RT5663_A_JD_CTRL:
1062 case RT5663_JD_CTRL2:
1063 case RT5663_VENDOR_ID:
1064 case RT5663_VENDOR_ID_1:
1065 case RT5663_VENDOR_ID_2:
1066 case RT5663_STO_DRE_1:
1067 case RT5663_STO_DRE_5:
1068 case RT5663_STO_DRE_6:
1069 case RT5663_STO_DRE_7:
1070 case RT5663_MONO_DYNA_6:
1071 case RT5663_STO1_SIL_DET:
1072 case RT5663_MONOL_SIL_DET:
1073 case RT5663_MONOR_SIL_DET:
1074 case RT5663_STO2_DAC_SIL:
1075 case RT5663_MONO_AMP_CAL_ST1:
1076 case RT5663_MONO_AMP_CAL_ST2:
1077 case RT5663_MONO_AMP_CAL_ST3:
1078 case RT5663_MONO_AMP_CAL_ST4:
1079 case RT5663_HP_IMP_SEN_2:
1080 case RT5663_HP_IMP_SEN_3:
1081 case RT5663_HP_IMP_SEN_4:
1082 case RT5663_HP_IMP_SEN_10:
1083 case RT5663_HP_CALIB_1:
1084 case RT5663_HP_CALIB_10:
1085 case RT5663_HP_CALIB_ST1:
1086 case RT5663_HP_CALIB_ST4:
1087 case RT5663_HP_CALIB_ST5:
1088 case RT5663_HP_CALIB_ST6:
1089 case RT5663_HP_CALIB_ST7:
1090 case RT5663_HP_CALIB_ST8:
1091 case RT5663_HP_CALIB_ST9:
1092 case RT5663_HP_CALIB_ST10:
1093 case RT5663_HP_CALIB_ST11:
1100 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1103 case RT5663_LOUT_CTRL:
1104 case RT5663_HP_AMP_2:
1105 case RT5663_MONO_OUT:
1106 case RT5663_MONO_GAIN:
1107 case RT5663_AEC_BST:
1108 case RT5663_IN1_IN2:
1109 case RT5663_IN3_IN4:
1110 case RT5663_INL1_INR1:
1111 case RT5663_CBJ_TYPE_2:
1112 case RT5663_CBJ_TYPE_3:
1113 case RT5663_CBJ_TYPE_4:
1114 case RT5663_CBJ_TYPE_5:
1115 case RT5663_CBJ_TYPE_8:
1116 case RT5663_DAC3_DIG_VOL:
1117 case RT5663_DAC3_CTRL:
1118 case RT5663_MONO_ADC_DIG_VOL:
1119 case RT5663_STO2_ADC_DIG_VOL:
1120 case RT5663_MONO_ADC_BST_GAIN:
1121 case RT5663_STO2_ADC_BST_GAIN:
1122 case RT5663_SIDETONE_CTRL:
1123 case RT5663_MONO1_ADC_MIXER:
1124 case RT5663_STO2_ADC_MIXER:
1125 case RT5663_MONO_DAC_MIXER:
1126 case RT5663_DAC2_SRC_CTRL:
1127 case RT5663_IF_3_4_DATA_CTL:
1128 case RT5663_IF_5_DATA_CTL:
1129 case RT5663_PDM_OUT_CTL:
1130 case RT5663_PDM_I2C_DATA_CTL1:
1131 case RT5663_PDM_I2C_DATA_CTL2:
1132 case RT5663_PDM_I2C_DATA_CTL3:
1133 case RT5663_PDM_I2C_DATA_CTL4:
1134 case RT5663_RECMIX1_NEW:
1135 case RT5663_RECMIX1L_0:
1136 case RT5663_RECMIX1L:
1137 case RT5663_RECMIX1R_0:
1138 case RT5663_RECMIX1R:
1139 case RT5663_RECMIX2_NEW:
1140 case RT5663_RECMIX2_L_2:
1141 case RT5663_RECMIX2_R:
1142 case RT5663_RECMIX2_R_2:
1143 case RT5663_CALIB_REC_LR:
1144 case RT5663_ALC_BK_GAIN:
1145 case RT5663_MONOMIX_GAIN:
1146 case RT5663_MONOMIX_IN_GAIN:
1147 case RT5663_OUT_MIXL_GAIN:
1148 case RT5663_OUT_LMIX_IN_GAIN:
1149 case RT5663_OUT_RMIX_IN_GAIN:
1150 case RT5663_OUT_RMIX_IN_GAIN1:
1151 case RT5663_LOUT_MIXER_CTRL:
1152 case RT5663_PWR_VOL:
1153 case RT5663_ADCDAC_RST:
1154 case RT5663_I2S34_SDP:
1155 case RT5663_I2S5_SDP:
1163 case RT5663_PLL_TRK_13:
1164 case RT5663_I2S_M_CLK_CTL:
1165 case RT5663_FDIV_I2S34_M_CLK:
1166 case RT5663_FDIV_I2S34_M_CLK2:
1167 case RT5663_FDIV_I2S5_M_CLK:
1168 case RT5663_FDIV_I2S5_M_CLK2:
1169 case RT5663_V2_IRQ_4:
1172 case RT5663_GPIO_STA2:
1173 case RT5663_HP_AMP_DET1:
1174 case RT5663_HP_AMP_DET2:
1175 case RT5663_HP_AMP_DET3:
1176 case RT5663_MID_BD_HP_AMP:
1177 case RT5663_LOW_BD_HP_AMP:
1178 case RT5663_SOF_VOL_ZC2:
1179 case RT5663_ADC_STO2_ADJ1:
1180 case RT5663_ADC_STO2_ADJ2:
1181 case RT5663_A_JD_CTRL:
1182 case RT5663_JD1_TRES_CTRL:
1183 case RT5663_JD2_TRES_CTRL:
1184 case RT5663_V2_JD_CTRL2:
1185 case RT5663_DUM_REG_2:
1186 case RT5663_DUM_REG_3:
1187 case RT5663_VENDOR_ID:
1188 case RT5663_VENDOR_ID_1:
1189 case RT5663_VENDOR_ID_2:
1190 case RT5663_DACADC_DIG_VOL2:
1191 case RT5663_DIG_IN_PIN2:
1192 case RT5663_PAD_DRV_CTL1:
1193 case RT5663_SOF_RAM_DEPOP:
1194 case RT5663_VOL_TEST:
1195 case RT5663_TEST_MODE_4:
1196 case RT5663_TEST_MODE_5:
1197 case RT5663_STO_DRE_9:
1198 case RT5663_MONO_DYNA_1:
1199 case RT5663_MONO_DYNA_2:
1200 case RT5663_MONO_DYNA_3:
1201 case RT5663_MONO_DYNA_4:
1202 case RT5663_MONO_DYNA_5:
1203 case RT5663_MONO_DYNA_6:
1204 case RT5663_STO1_SIL_DET:
1205 case RT5663_MONOL_SIL_DET:
1206 case RT5663_MONOR_SIL_DET:
1207 case RT5663_STO2_DAC_SIL:
1208 case RT5663_PWR_SAV_CTL1:
1209 case RT5663_PWR_SAV_CTL2:
1210 case RT5663_PWR_SAV_CTL3:
1211 case RT5663_PWR_SAV_CTL4:
1212 case RT5663_PWR_SAV_CTL5:
1213 case RT5663_PWR_SAV_CTL6:
1214 case RT5663_MONO_AMP_CAL1:
1215 case RT5663_MONO_AMP_CAL2:
1216 case RT5663_MONO_AMP_CAL3:
1217 case RT5663_MONO_AMP_CAL4:
1218 case RT5663_MONO_AMP_CAL5:
1219 case RT5663_MONO_AMP_CAL6:
1220 case RT5663_MONO_AMP_CAL7:
1221 case RT5663_MONO_AMP_CAL_ST1:
1222 case RT5663_MONO_AMP_CAL_ST2:
1223 case RT5663_MONO_AMP_CAL_ST3:
1224 case RT5663_MONO_AMP_CAL_ST4:
1225 case RT5663_MONO_AMP_CAL_ST5:
1226 case RT5663_V2_HP_IMP_SEN_13:
1227 case RT5663_V2_HP_IMP_SEN_14:
1228 case RT5663_V2_HP_IMP_SEN_6:
1229 case RT5663_V2_HP_IMP_SEN_7:
1230 case RT5663_V2_HP_IMP_SEN_8:
1231 case RT5663_V2_HP_IMP_SEN_9:
1232 case RT5663_V2_HP_IMP_SEN_10:
1233 case RT5663_HP_LOGIC_3:
1234 case RT5663_HP_CALIB_ST10:
1235 case RT5663_HP_CALIB_ST11:
1236 case RT5663_PRO_REG_TBL_4:
1237 case RT5663_PRO_REG_TBL_5:
1238 case RT5663_PRO_REG_TBL_6:
1239 case RT5663_PRO_REG_TBL_7:
1240 case RT5663_PRO_REG_TBL_8:
1241 case RT5663_PRO_REG_TBL_9:
1242 case RT5663_SAR_ADC_INL_1:
1243 case RT5663_SAR_ADC_INL_2:
1244 case RT5663_SAR_ADC_INL_3:
1245 case RT5663_SAR_ADC_INL_4:
1246 case RT5663_SAR_ADC_INL_5:
1247 case RT5663_SAR_ADC_INL_6:
1248 case RT5663_SAR_ADC_INL_7:
1249 case RT5663_SAR_ADC_INL_8:
1250 case RT5663_SAR_ADC_INL_9:
1251 case RT5663_SAR_ADC_INL_10:
1252 case RT5663_SAR_ADC_INL_11:
1253 case RT5663_SAR_ADC_INL_12:
1254 case RT5663_DRC_CTRL_1:
1255 case RT5663_DRC1_CTRL_2:
1256 case RT5663_DRC1_CTRL_3:
1257 case RT5663_DRC1_CTRL_4:
1258 case RT5663_DRC1_CTRL_5:
1259 case RT5663_DRC1_CTRL_6:
1260 case RT5663_DRC1_HD_CTRL_1:
1261 case RT5663_DRC1_HD_CTRL_2:
1262 case RT5663_DRC1_PRI_REG_1:
1263 case RT5663_DRC1_PRI_REG_2:
1264 case RT5663_DRC1_PRI_REG_3:
1265 case RT5663_DRC1_PRI_REG_4:
1266 case RT5663_DRC1_PRI_REG_5:
1267 case RT5663_DRC1_PRI_REG_6:
1268 case RT5663_DRC1_PRI_REG_7:
1269 case RT5663_DRC1_PRI_REG_8:
1270 case RT5663_ALC_PGA_CTL_1:
1271 case RT5663_ALC_PGA_CTL_2:
1272 case RT5663_ALC_PGA_CTL_3:
1273 case RT5663_ALC_PGA_CTL_4:
1274 case RT5663_ALC_PGA_CTL_5:
1275 case RT5663_ALC_PGA_CTL_6:
1276 case RT5663_ALC_PGA_CTL_7:
1277 case RT5663_ALC_PGA_CTL_8:
1278 case RT5663_ALC_PGA_REG_1:
1279 case RT5663_ALC_PGA_REG_2:
1280 case RT5663_ALC_PGA_REG_3:
1281 case RT5663_ADC_EQ_RECOV_1:
1282 case RT5663_ADC_EQ_RECOV_2:
1283 case RT5663_ADC_EQ_RECOV_3:
1284 case RT5663_ADC_EQ_RECOV_4:
1285 case RT5663_ADC_EQ_RECOV_5:
1286 case RT5663_ADC_EQ_RECOV_6:
1287 case RT5663_ADC_EQ_RECOV_7:
1288 case RT5663_ADC_EQ_RECOV_8:
1289 case RT5663_ADC_EQ_RECOV_9:
1290 case RT5663_ADC_EQ_RECOV_10:
1291 case RT5663_ADC_EQ_RECOV_11:
1292 case RT5663_ADC_EQ_RECOV_12:
1293 case RT5663_ADC_EQ_RECOV_13:
1294 case RT5663_VID_HIDDEN:
1295 case RT5663_VID_CUSTOMER:
1296 case RT5663_SCAN_MODE:
1297 case RT5663_I2C_BYPA:
1300 case RT5663_DEPOP_3:
1301 case RT5663_ASRC_11_2:
1302 case RT5663_INT_ST_2:
1303 case RT5663_GPIO_STA1:
1304 case RT5663_SIN_GEN_1:
1305 case RT5663_SIN_GEN_2:
1306 case RT5663_SIN_GEN_3:
1307 case RT5663_IL_CMD_PWRSAV1:
1308 case RT5663_IL_CMD_PWRSAV2:
1309 case RT5663_EM_JACK_TYPE_1:
1310 case RT5663_EM_JACK_TYPE_2:
1311 case RT5663_EM_JACK_TYPE_3:
1312 case RT5663_EM_JACK_TYPE_4:
1313 case RT5663_FAST_OFF_MICBIAS:
1314 case RT5663_ANA_BIAS_CUR_1:
1315 case RT5663_ANA_BIAS_CUR_2:
1316 case RT5663_BIAS_CUR_9:
1317 case RT5663_DUMMY_REG_4:
1318 case RT5663_VREF_RECMIX:
1319 case RT5663_CHARGE_PUMP_1_2:
1320 case RT5663_CHARGE_PUMP_1_3:
1321 case RT5663_CHARGE_PUMP_2:
1322 case RT5663_CHOP_DAC_R:
1323 case RT5663_DUMMY_CTL_DACLR:
1324 case RT5663_DUMMY_REG_5:
1325 case RT5663_SOFT_RAMP:
1326 case RT5663_TEST_MODE_1:
1327 case RT5663_STO_DRE_10:
1328 case RT5663_MIC_DECRO_1:
1329 case RT5663_MIC_DECRO_2:
1330 case RT5663_MIC_DECRO_3:
1331 case RT5663_MIC_DECRO_4:
1332 case RT5663_MIC_DECRO_5:
1333 case RT5663_MIC_DECRO_6:
1334 case RT5663_HP_DECRO_1:
1335 case RT5663_HP_DECRO_2:
1336 case RT5663_HP_DECRO_3:
1337 case RT5663_HP_DECRO_4:
1338 case RT5663_HP_DECOUP:
1339 case RT5663_HP_IMPSEN_MAP4:
1340 case RT5663_HP_IMPSEN_MAP5:
1341 case RT5663_HP_IMPSEN_MAP7:
1342 case RT5663_HP_CALIB_1:
1348 return rt5663_readable_register(dev, reg);
1352 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1353 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1354 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1355 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1357 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1358 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1359 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1360 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1361 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1362 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1363 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1364 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1365 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1368 /* Interface data select */
1369 static const char * const rt5663_if1_adc_data_select[] = {
1370 "L/R", "R/L", "L/L", "R/R"
1373 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1374 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1376 static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1379 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1383 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1384 /* reset in-line command */
1385 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1386 RT5663_RESET_4BTN_INL_MASK,
1387 RT5663_RESET_4BTN_INL_RESET);
1388 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1389 RT5663_RESET_4BTN_INL_MASK,
1390 RT5663_RESET_4BTN_INL_NOR);
1391 switch (rt5663->codec_ver) {
1393 snd_soc_update_bits(codec, RT5663_IRQ_3,
1394 RT5663_V2_EN_IRQ_INLINE_MASK,
1395 RT5663_V2_EN_IRQ_INLINE_NOR);
1398 snd_soc_update_bits(codec, RT5663_IRQ_2,
1399 RT5663_EN_IRQ_INLINE_MASK,
1400 RT5663_EN_IRQ_INLINE_NOR);
1403 dev_err(codec->dev, "Unknown CODEC Version\n");
1406 switch (rt5663->codec_ver) {
1408 snd_soc_update_bits(codec, RT5663_IRQ_3,
1409 RT5663_V2_EN_IRQ_INLINE_MASK,
1410 RT5663_V2_EN_IRQ_INLINE_BYP);
1413 snd_soc_update_bits(codec, RT5663_IRQ_2,
1414 RT5663_EN_IRQ_INLINE_MASK,
1415 RT5663_EN_IRQ_INLINE_BYP);
1418 dev_err(codec->dev, "Unknown CODEC Version\n");
1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1421 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1422 /* reset in-line command */
1423 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1424 RT5663_RESET_4BTN_INL_MASK,
1425 RT5663_RESET_4BTN_INL_RESET);
1426 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1427 RT5663_RESET_4BTN_INL_MASK,
1428 RT5663_RESET_4BTN_INL_NOR);
1433 * rt5663_v2_jack_detect - Detect headset.
1434 * @codec: SoC audio codec device.
1435 * @jack_insert: Jack insert or not.
1437 * Detect whether is headset or not when jack inserted.
1439 * Returns detect status.
1442 static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1444 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1445 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1446 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1448 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1450 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
1451 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
1453 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1454 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1455 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1456 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1457 snd_soc_dapm_sync(dapm);
1458 snd_soc_update_bits(codec, RT5663_RC_CLK,
1459 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1460 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1463 msleep(sleep_time[i]);
1464 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
1465 if (val == 0x1 || val == 0x2 || val == 0x3)
1467 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
1468 __func__, val, sleep_time[i]);
1471 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1475 rt5663->jack_type = SND_JACK_HEADSET;
1476 rt5663_enable_push_button_irq(codec, true);
1479 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1480 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1481 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1482 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1483 snd_soc_dapm_sync(dapm);
1484 rt5663->jack_type = SND_JACK_HEADPHONE;
1488 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1490 if (rt5663->jack_type == SND_JACK_HEADSET) {
1491 rt5663_enable_push_button_irq(codec, false);
1492 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1493 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1494 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1495 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1496 snd_soc_dapm_sync(dapm);
1498 rt5663->jack_type = 0;
1501 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1502 return rt5663->jack_type;
1506 * rt5663_jack_detect - Detect headset.
1507 * @codec: SoC audio codec device.
1508 * @jack_insert: Jack insert or not.
1510 * Detect whether is headset or not when jack inserted.
1512 * Returns detect status.
1514 static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1516 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1519 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1522 snd_soc_update_bits(codec, RT5663_DIG_MISC,
1523 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1524 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
1525 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1526 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1527 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1528 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1529 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1530 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1531 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1532 snd_soc_update_bits(codec, RT5663_CBJ_1,
1533 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1534 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1535 snd_soc_update_bits(codec, RT5663_IL_CMD_2,
1536 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1537 /* BST1 power on for JD */
1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1539 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1540 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1541 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1542 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1543 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1544 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1545 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1546 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1547 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1548 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
1549 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1550 snd_soc_update_bits(codec, RT5663_IRQ_1,
1551 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1554 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1556 usleep_range(10000, 10005);
1565 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 0x0003;
1566 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1568 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
1569 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1570 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1575 rt5663->jack_type = SND_JACK_HEADSET;
1576 rt5663_enable_push_button_irq(codec, true);
1578 if (rt5663->pdata.dc_offset_l_manual_mic) {
1579 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1580 rt5663->pdata.dc_offset_l_manual_mic >>
1582 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1583 rt5663->pdata.dc_offset_l_manual_mic &
1587 if (rt5663->pdata.dc_offset_r_manual_mic) {
1588 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1589 rt5663->pdata.dc_offset_r_manual_mic >>
1591 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1592 rt5663->pdata.dc_offset_r_manual_mic &
1597 rt5663->jack_type = SND_JACK_HEADPHONE;
1599 if (rt5663->pdata.dc_offset_l_manual) {
1600 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1601 rt5663->pdata.dc_offset_l_manual >> 16);
1602 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1603 rt5663->pdata.dc_offset_l_manual &
1607 if (rt5663->pdata.dc_offset_r_manual) {
1608 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1609 rt5663->pdata.dc_offset_r_manual >> 16);
1610 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1611 rt5663->pdata.dc_offset_r_manual &
1617 if (rt5663->jack_type == SND_JACK_HEADSET)
1618 rt5663_enable_push_button_irq(codec, false);
1619 rt5663->jack_type = 0;
1622 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1623 return rt5663->jack_type;
1626 static int rt5663_button_detect(struct snd_soc_codec *codec)
1630 val = snd_soc_read(codec, RT5663_IL_CMD_5);
1631 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val);
1632 btn_type = val & 0xfff0;
1633 snd_soc_write(codec, RT5663_IL_CMD_5, val);
1638 static irqreturn_t rt5663_irq(int irq, void *data)
1640 struct rt5663_priv *rt5663 = data;
1642 dev_dbg(rt5663->codec->dev, "%s IRQ queue work\n", __func__);
1644 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1645 msecs_to_jiffies(250));
1650 int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1651 struct snd_soc_jack *hs_jack)
1653 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1655 rt5663->hs_jack = hs_jack;
1657 rt5663_irq(0, rt5663);
1661 EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1663 static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1665 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1666 int val = snd_soc_read(codec, RT5663_INT_ST_1);
1668 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1671 switch (rt5663->codec_ver) {
1673 return !(val & 0x2000);
1675 return !(val & 0x1000);
1677 dev_err(codec->dev, "Unknown CODEC Version\n");
1683 static void rt5663_jack_detect_work(struct work_struct *work)
1685 struct rt5663_priv *rt5663 =
1686 container_of(work, struct rt5663_priv, jack_detect_work.work);
1687 struct snd_soc_codec *codec = rt5663->codec;
1688 int btn_type, report = 0;
1693 if (rt5663_check_jd_status(codec)) {
1695 if (rt5663->jack_type == 0) {
1696 /* jack was out, report jack type */
1697 switch (rt5663->codec_ver) {
1699 report = rt5663_v2_jack_detect(
1703 report = rt5663_jack_detect(rt5663->codec, 1);
1706 dev_err(codec->dev, "Unknown CODEC Version\n");
1709 /* Delay the jack insert report to avoid pop noise */
1712 /* jack is already in, report button event */
1713 report = SND_JACK_HEADSET;
1714 btn_type = rt5663_button_detect(rt5663->codec);
1716 * rt5663 can report three kinds of button behavior,
1717 * one click, double click and hold. However,
1718 * currently we will report button pressed/released
1719 * event. So all the three button behaviors are
1720 * treated as button pressed.
1726 report |= SND_JACK_BTN_0;
1731 report |= SND_JACK_BTN_1;
1736 report |= SND_JACK_BTN_2;
1741 report |= SND_JACK_BTN_3;
1743 case 0x0000: /* unpressed */
1747 dev_err(rt5663->codec->dev,
1748 "Unexpected button code 0x%04x\n",
1752 /* button release or spurious interrput*/
1754 report = rt5663->jack_type;
1758 switch (rt5663->codec_ver) {
1760 report = rt5663_v2_jack_detect(rt5663->codec, 0);
1763 report = rt5663_jack_detect(rt5663->codec, 0);
1766 dev_err(codec->dev, "Unknown CODEC Version\n");
1769 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
1770 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1771 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1772 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1775 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
1776 /* DAC Digital Volume */
1777 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
1778 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
1779 87, 0, dac_vol_tlv),
1780 /* ADC Digital Volume Control */
1781 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
1782 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
1783 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
1784 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
1785 63, 0, adc_vol_tlv),
1788 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
1789 /* Headphone Output Volume */
1790 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
1791 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
1792 rt5663_v2_hp_vol_tlv),
1793 /* Mic Boost Volume */
1794 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
1795 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
1798 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
1799 /* Headphone Output Volume */
1800 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
1801 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
1803 /* Mic Boost Volume*/
1804 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
1805 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
1806 /* Data Swap for Slot0/1 in ADCDAT1 */
1807 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
1810 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1811 struct snd_soc_dapm_widget *sink)
1814 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1816 val = snd_soc_read(codec, RT5663_GLB_CLK);
1817 val &= RT5663_SCLK_SRC_MASK;
1818 if (val == RT5663_SCLK_SRC_PLL1)
1824 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
1825 struct snd_soc_dapm_widget *sink)
1827 unsigned int reg, shift, val;
1828 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1829 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1831 if (rt5663->codec_ver == CODEC_VER_1) {
1833 case RT5663_ADC_STO1_ASRC_SHIFT:
1834 reg = RT5663_ASRC_3;
1835 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
1837 case RT5663_DAC_STO1_ASRC_SHIFT:
1838 reg = RT5663_ASRC_2;
1839 shift = RT5663_DA_STO1_TRACK_SHIFT;
1846 case RT5663_ADC_STO1_ASRC_SHIFT:
1847 reg = RT5663_ASRC_2;
1848 shift = RT5663_AD_STO1_TRACK_SHIFT;
1850 case RT5663_DAC_STO1_ASRC_SHIFT:
1851 reg = RT5663_ASRC_2;
1852 shift = RT5663_DA_STO1_TRACK_SHIFT;
1859 val = (snd_soc_read(codec, reg) >> shift) & 0x7;
1867 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1868 struct snd_soc_dapm_widget *sink)
1870 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1871 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1872 int da_asrc_en, ad_asrc_en;
1874 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1875 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
1876 switch (rt5663->codec_ver) {
1878 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
1879 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
1882 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1883 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
1886 dev_err(codec->dev, "Unknown CODEC Version\n");
1890 if (da_asrc_en || ad_asrc_en)
1891 if (rt5663->sysclk > rt5663->lrck * 384)
1894 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n");
1900 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
1901 * @codec: SoC audio codec device.
1902 * @filter_mask: mask of filters.
1903 * @clk_src: clock source
1905 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
1906 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1907 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1908 * ASRC function will track i2s clock and generate a corresponding system clock
1909 * for codec. This function provides an API to select the clock source for a
1910 * set of filters specified by the mask. And the codec driver will turn on ASRC
1911 * for these filters if ASRC is selected as their clock source.
1913 int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1914 unsigned int filter_mask, unsigned int clk_src)
1916 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1917 unsigned int asrc2_mask = 0;
1918 unsigned int asrc2_value = 0;
1919 unsigned int asrc3_mask = 0;
1920 unsigned int asrc3_value = 0;
1923 case RT5663_CLK_SEL_SYS:
1924 case RT5663_CLK_SEL_I2S1_ASRC:
1931 if (filter_mask & RT5663_DA_STEREO_FILTER) {
1932 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
1933 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
1936 if (filter_mask & RT5663_AD_STEREO_FILTER) {
1937 switch (rt5663->codec_ver) {
1939 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
1940 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
1943 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
1944 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
1947 dev_err(codec->dev, "Unknown CODEC Version\n");
1952 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask,
1956 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
1961 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
1964 static const struct snd_kcontrol_new rt5663_recmix1l[] = {
1965 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
1966 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
1967 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
1968 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
1971 static const struct snd_kcontrol_new rt5663_recmix1r[] = {
1972 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
1973 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
1977 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
1978 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
1979 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
1980 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
1981 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
1984 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
1985 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
1986 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
1987 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
1988 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
1991 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
1992 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
1993 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
1994 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
1995 RT5663_M_DAC1_L_SHIFT, 1, 1),
1998 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
1999 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2000 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2001 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2002 RT5663_M_DAC1_R_SHIFT, 1, 1),
2005 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2006 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2007 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2010 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2011 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2012 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2016 static const struct snd_kcontrol_new rt5663_hpo_switch =
2017 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2018 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2020 /* Stereo ADC source */
2021 static const char * const rt5663_sto1_adc_src[] = {
2025 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2026 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2028 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2029 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2031 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2032 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2034 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2035 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2037 /* RT5663: Analog DACL1 input source */
2038 static const char * const rt5663_alg_dacl_src[] = {
2039 "DAC L", "STO DAC MIXL"
2042 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2043 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2045 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2046 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2048 /* RT5663: Analog DACR1 input source */
2049 static const char * const rt5663_alg_dacr_src[] = {
2050 "DAC R", "STO DAC MIXR"
2053 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2054 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2056 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2057 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2059 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2060 struct snd_kcontrol *kcontrol, int event)
2062 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2063 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2066 case SND_SOC_DAPM_POST_PMU:
2067 if (rt5663->codec_ver == CODEC_VER_1) {
2068 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2069 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2070 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2071 RT5663_HP_SIG_SRC1_MASK,
2072 RT5663_HP_SIG_SRC1_SILENCE);
2074 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
2075 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2076 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2077 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2078 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2079 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
2080 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
2081 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
2082 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
2083 snd_soc_update_bits(codec, RT5663_STO_DRE_1, 0x8000,
2085 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
2090 case SND_SOC_DAPM_PRE_PMD:
2091 if (rt5663->codec_ver == CODEC_VER_1) {
2092 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2093 RT5663_HP_SIG_SRC1_MASK,
2094 RT5663_HP_SIG_SRC1_REG);
2096 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2097 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2098 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2109 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2110 struct snd_kcontrol *kcontrol, int event)
2112 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2113 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2116 case SND_SOC_DAPM_PRE_PMU:
2117 if (rt5663->codec_ver == CODEC_VER_0) {
2118 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
2120 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003,
2125 case SND_SOC_DAPM_POST_PMD:
2126 if (rt5663->codec_ver == CODEC_VER_0) {
2127 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0);
2128 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0);
2139 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2140 struct snd_kcontrol *kcontrol, int event)
2142 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2145 case SND_SOC_DAPM_POST_PMU:
2146 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2147 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2148 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2151 case SND_SOC_DAPM_PRE_PMD:
2152 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2153 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2163 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2164 struct snd_kcontrol *kcontrol, int event)
2166 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2169 case SND_SOC_DAPM_POST_PMU:
2170 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
2171 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
2174 case SND_SOC_DAPM_PRE_PMD:
2175 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000);
2176 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000);
2186 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2187 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2191 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2192 RT5663_PWR_MB1_SHIFT, 0),
2193 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2194 RT5663_PWR_MB2_SHIFT, 0),
2197 SND_SOC_DAPM_INPUT("IN1P"),
2198 SND_SOC_DAPM_INPUT("IN1N"),
2200 /* REC Mixer Power */
2201 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2202 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2205 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2206 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2207 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2208 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2209 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2212 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2213 0, 0, rt5663_sto1_adc_l_mix,
2214 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2216 /* ADC Filter Power */
2217 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2218 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2220 /* Digital Interface */
2221 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2223 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2224 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2225 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2226 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2227 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2229 /* Audio Interface */
2230 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2231 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2233 /* DAC mixer before sound effect */
2234 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2235 ARRAY_SIZE(rt5663_adda_l_mix)),
2236 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2237 ARRAY_SIZE(rt5663_adda_r_mix)),
2238 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2239 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2242 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2243 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2244 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2245 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2246 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2247 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2250 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2251 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2252 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2253 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2254 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2255 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2258 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2259 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2260 SND_SOC_DAPM_POST_PMD),
2261 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2262 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2265 SND_SOC_DAPM_OUTPUT("HPOL"),
2266 SND_SOC_DAPM_OUTPUT("HPOR"),
2269 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2270 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2271 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2272 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2273 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2274 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2275 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2278 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2279 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2280 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2281 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2282 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2283 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2286 SND_SOC_DAPM_INPUT("IN2P"),
2287 SND_SOC_DAPM_INPUT("IN2N"),
2290 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2291 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2292 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2293 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2294 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2295 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2296 SND_SOC_DAPM_POST_PMU),
2299 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2300 ARRAY_SIZE(rt5663_recmix1l)),
2301 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2302 ARRAY_SIZE(rt5663_recmix1r)),
2303 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2304 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2307 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2308 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2309 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2312 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2313 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2314 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2315 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2316 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2317 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2318 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2319 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2321 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2322 &rt5663_sto1_adcl_mux),
2323 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2324 &rt5663_sto1_adcr_mux),
2327 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2328 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2330 /* Analog DAC Clock */
2331 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2332 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2335 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2336 &rt5663_hpo_switch),
2339 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2340 /* System Clock Pre Divider Gating */
2341 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2342 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2343 SND_SOC_DAPM_PRE_PMD),
2346 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2347 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2350 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2351 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2352 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2353 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2354 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2355 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2358 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2361 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2362 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2364 /* Analog DAC source */
2365 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2366 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2369 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2371 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2374 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2375 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2376 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2378 { "ADC L", NULL, "ADC L Power" },
2379 { "ADC L", NULL, "ADC Clock" },
2381 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2383 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2384 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2385 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2387 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2388 { "IF ADC", NULL, "IF1 ADC1" },
2389 { "AIFTX", NULL, "IF ADC" },
2390 { "AIFTX", NULL, "I2S" },
2392 { "AIFRX", NULL, "I2S" },
2393 { "IF DAC", NULL, "AIFRX" },
2394 { "IF1 DAC1 L", NULL, "IF DAC" },
2395 { "IF1 DAC1 R", NULL, "IF DAC" },
2397 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2398 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2399 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2400 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2401 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2402 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2403 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2405 { "DAC L1", NULL, "ADDA MIXL" },
2406 { "DAC R1", NULL, "ADDA MIXR" },
2408 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2409 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2410 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2411 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2412 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2413 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2415 { "HP Amp", NULL, "HP Charge Pump" },
2416 { "HP Amp", NULL, "DAC L" },
2417 { "HP Amp", NULL, "DAC R" },
2420 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2421 { "MICBIAS1", NULL, "LDO2" },
2422 { "MICBIAS2", NULL, "LDO2" },
2424 { "BST1 CBJ", NULL, "IN1P" },
2425 { "BST1 CBJ", NULL, "IN1N" },
2426 { "BST1 CBJ", NULL, "CBJ Power" },
2428 { "BST2", NULL, "IN2P" },
2429 { "BST2", NULL, "IN2N" },
2430 { "BST2", NULL, "BST2 Power" },
2432 { "RECMIX1L", "BST2 Switch", "BST2" },
2433 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2434 { "RECMIX1L", NULL, "RECMIX1L Power" },
2435 { "RECMIX1R", "BST2 Switch", "BST2" },
2436 { "RECMIX1R", NULL, "RECMIX1R Power" },
2438 { "ADC L", NULL, "RECMIX1L" },
2439 { "ADC R", NULL, "RECMIX1R" },
2440 { "ADC R", NULL, "ADC R Power" },
2441 { "ADC R", NULL, "ADC Clock" },
2443 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2444 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2445 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2447 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2448 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2449 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2450 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2452 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2453 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2454 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2456 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2458 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2460 { "DAC L", NULL, "STO1 DAC MIXL" },
2461 { "DAC L", NULL, "LDO DAC" },
2462 { "DAC L", NULL, "DAC Clock" },
2463 { "DAC R", NULL, "STO1 DAC MIXR" },
2464 { "DAC R", NULL, "LDO DAC" },
2465 { "DAC R", NULL, "DAC Clock" },
2467 { "HPO Playback", "Switch", "HP Amp" },
2468 { "HPOL", NULL, "HPO Playback" },
2469 { "HPOR", NULL, "HPO Playback" },
2472 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2473 { "I2S", NULL, "Pre Div Power" },
2475 { "BST1", NULL, "IN1P" },
2476 { "BST1", NULL, "IN1N" },
2477 { "BST1", NULL, "RECMIX1L Power" },
2479 { "ADC L", NULL, "BST1" },
2481 { "STO1 ADC L1", NULL, "ADC L" },
2483 { "DAC L Mux", "DAC L", "DAC L1" },
2484 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2485 { "DAC R Mux", "DAC R", "DAC R1"},
2486 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2488 { "DAC L", NULL, "DAC L Mux" },
2489 { "DAC R", NULL, "DAC R Mux" },
2491 { "HPOL", NULL, "HP Amp" },
2492 { "HPOR", NULL, "HP Amp" },
2495 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2496 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2498 struct snd_soc_codec *codec = dai->codec;
2499 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2500 unsigned int val_len = 0;
2503 rt5663->lrck = params_rate(params);
2505 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2506 rt5663->lrck, rt5663->sysclk);
2508 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2510 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2511 rt5663->lrck, dai->id);
2515 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2517 switch (params_width(params)) {
2519 val_len = RT5663_I2S_DL_8;
2522 val_len = RT5663_I2S_DL_16;
2525 val_len = RT5663_I2S_DL_20;
2528 val_len = RT5663_I2S_DL_24;
2534 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
2535 RT5663_I2S_DL_MASK, val_len);
2537 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
2538 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2543 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2545 struct snd_soc_codec *codec = dai->codec;
2546 unsigned int reg_val = 0;
2548 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2549 case SND_SOC_DAIFMT_CBM_CFM:
2551 case SND_SOC_DAIFMT_CBS_CFS:
2552 reg_val |= RT5663_I2S_MS_S;
2558 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2559 case SND_SOC_DAIFMT_NB_NF:
2561 case SND_SOC_DAIFMT_IB_NF:
2562 reg_val |= RT5663_I2S_BP_INV;
2568 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2569 case SND_SOC_DAIFMT_I2S:
2571 case SND_SOC_DAIFMT_LEFT_J:
2572 reg_val |= RT5663_I2S_DF_LEFT;
2574 case SND_SOC_DAIFMT_DSP_A:
2575 reg_val |= RT5663_I2S_DF_PCM_A;
2577 case SND_SOC_DAIFMT_DSP_B:
2578 reg_val |= RT5663_I2S_DF_PCM_B;
2584 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2585 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2590 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2591 unsigned int freq, int dir)
2593 struct snd_soc_codec *codec = dai->codec;
2594 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2595 unsigned int reg_val = 0;
2597 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2601 case RT5663_SCLK_S_MCLK:
2602 reg_val |= RT5663_SCLK_SRC_MCLK;
2604 case RT5663_SCLK_S_PLL1:
2605 reg_val |= RT5663_SCLK_SRC_PLL1;
2607 case RT5663_SCLK_S_RCCLK:
2608 reg_val |= RT5663_SCLK_SRC_RCCLK;
2611 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2614 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2616 rt5663->sysclk = freq;
2617 rt5663->sysclk_src = clk_id;
2619 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
2625 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2626 unsigned int freq_in, unsigned int freq_out)
2628 struct snd_soc_codec *codec = dai->codec;
2629 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2630 struct rl6231_pll_code pll_code;
2632 int mask, shift, val;
2634 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2635 freq_out == rt5663->pll_out)
2638 if (!freq_in || !freq_out) {
2639 dev_dbg(codec->dev, "PLL disabled\n");
2642 rt5663->pll_out = 0;
2643 snd_soc_update_bits(codec, RT5663_GLB_CLK,
2644 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2648 switch (rt5663->codec_ver) {
2650 mask = RT5663_V2_PLL1_SRC_MASK;
2651 shift = RT5663_V2_PLL1_SRC_SHIFT;
2654 mask = RT5663_PLL1_SRC_MASK;
2655 shift = RT5663_PLL1_SRC_SHIFT;
2658 dev_err(codec->dev, "Unknown CODEC Version\n");
2663 case RT5663_PLL1_S_MCLK:
2666 case RT5663_PLL1_S_BCLK1:
2670 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2673 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift));
2675 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2677 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2681 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2682 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2685 snd_soc_write(codec, RT5663_PLL_1,
2686 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2687 snd_soc_write(codec, RT5663_PLL_2,
2688 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2689 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
2691 rt5663->pll_in = freq_in;
2692 rt5663->pll_out = freq_out;
2693 rt5663->pll_src = source;
2698 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2699 unsigned int rx_mask, int slots, int slot_width)
2701 struct snd_soc_codec *codec = dai->codec;
2702 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2703 unsigned int val = 0, reg;
2705 if (rx_mask || tx_mask)
2706 val |= RT5663_TDM_MODE_TDM;
2710 val |= RT5663_TDM_IN_CH_4;
2711 val |= RT5663_TDM_OUT_CH_4;
2714 val |= RT5663_TDM_IN_CH_6;
2715 val |= RT5663_TDM_OUT_CH_6;
2718 val |= RT5663_TDM_IN_CH_8;
2719 val |= RT5663_TDM_OUT_CH_8;
2727 switch (slot_width) {
2729 val |= RT5663_TDM_IN_LEN_20;
2730 val |= RT5663_TDM_OUT_LEN_20;
2733 val |= RT5663_TDM_IN_LEN_24;
2734 val |= RT5663_TDM_OUT_LEN_24;
2737 val |= RT5663_TDM_IN_LEN_32;
2738 val |= RT5663_TDM_OUT_LEN_32;
2746 switch (rt5663->codec_ver) {
2754 dev_err(codec->dev, "Unknown CODEC Version\n");
2758 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
2759 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
2760 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
2765 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2767 struct snd_soc_codec *codec = dai->codec;
2768 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2771 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
2773 if (rt5663->codec_ver == CODEC_VER_1)
2780 snd_soc_update_bits(codec, reg,
2781 RT5663_TDM_LENGTN_MASK,
2782 RT5663_TDM_LENGTN_16);
2785 snd_soc_update_bits(codec, reg,
2786 RT5663_TDM_LENGTN_MASK,
2787 RT5663_TDM_LENGTN_20);
2790 snd_soc_update_bits(codec, reg,
2791 RT5663_TDM_LENGTN_MASK,
2792 RT5663_TDM_LENGTN_24);
2795 snd_soc_update_bits(codec, reg,
2796 RT5663_TDM_LENGTN_MASK,
2797 RT5663_TDM_LENGTN_32);
2800 dev_err(codec->dev, "Invalid ratio!\n");
2807 static int rt5663_set_bias_level(struct snd_soc_codec *codec,
2808 enum snd_soc_bias_level level)
2810 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2813 case SND_SOC_BIAS_ON:
2814 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2815 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
2816 RT5663_PWR_FV1 | RT5663_PWR_FV2);
2819 case SND_SOC_BIAS_PREPARE:
2820 if (rt5663->codec_ver == CODEC_VER_1) {
2821 snd_soc_update_bits(codec, RT5663_DIG_MISC,
2822 RT5663_DIG_GATE_CTRL_MASK,
2823 RT5663_DIG_GATE_CTRL_EN);
2824 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
2825 RT5663_EN_ANA_CLK_DET_MASK |
2826 RT5663_PWR_CLK_DET_MASK,
2827 RT5663_EN_ANA_CLK_DET_AUTO |
2828 RT5663_PWR_CLK_DET_EN);
2832 case SND_SOC_BIAS_STANDBY:
2833 if (rt5663->codec_ver == CODEC_VER_1)
2834 snd_soc_update_bits(codec, RT5663_DIG_MISC,
2835 RT5663_DIG_GATE_CTRL_MASK,
2836 RT5663_DIG_GATE_CTRL_DIS);
2837 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2838 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2839 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
2840 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
2841 RT5663_PWR_VREF2 | RT5663_PWR_MB);
2842 usleep_range(10000, 10005);
2843 if (rt5663->codec_ver == CODEC_VER_1) {
2844 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
2845 RT5663_EN_ANA_CLK_DET_MASK |
2846 RT5663_PWR_CLK_DET_MASK,
2847 RT5663_EN_ANA_CLK_DET_DIS |
2848 RT5663_PWR_CLK_DET_DIS);
2852 case SND_SOC_BIAS_OFF:
2853 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2854 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2855 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
2865 static int rt5663_probe(struct snd_soc_codec *codec)
2867 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2868 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2870 rt5663->codec = codec;
2872 switch (rt5663->codec_ver) {
2874 snd_soc_dapm_new_controls(dapm,
2875 rt5663_v2_specific_dapm_widgets,
2876 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
2877 snd_soc_dapm_add_routes(dapm,
2878 rt5663_v2_specific_dapm_routes,
2879 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
2880 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
2881 ARRAY_SIZE(rt5663_v2_specific_controls));
2884 snd_soc_dapm_new_controls(dapm,
2885 rt5663_specific_dapm_widgets,
2886 ARRAY_SIZE(rt5663_specific_dapm_widgets));
2887 snd_soc_dapm_add_routes(dapm,
2888 rt5663_specific_dapm_routes,
2889 ARRAY_SIZE(rt5663_specific_dapm_routes));
2890 snd_soc_add_codec_controls(codec, rt5663_specific_controls,
2891 ARRAY_SIZE(rt5663_specific_controls));
2898 static int rt5663_remove(struct snd_soc_codec *codec)
2900 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2902 regmap_write(rt5663->regmap, RT5663_RESET, 0);
2908 static int rt5663_suspend(struct snd_soc_codec *codec)
2910 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2912 regcache_cache_only(rt5663->regmap, true);
2913 regcache_mark_dirty(rt5663->regmap);
2918 static int rt5663_resume(struct snd_soc_codec *codec)
2920 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2922 regcache_cache_only(rt5663->regmap, false);
2923 regcache_sync(rt5663->regmap);
2925 rt5663_irq(0, rt5663);
2930 #define rt5663_suspend NULL
2931 #define rt5663_resume NULL
2934 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2935 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2936 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2938 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
2939 .hw_params = rt5663_hw_params,
2940 .set_fmt = rt5663_set_dai_fmt,
2941 .set_sysclk = rt5663_set_dai_sysclk,
2942 .set_pll = rt5663_set_dai_pll,
2943 .set_tdm_slot = rt5663_set_tdm_slot,
2944 .set_bclk_ratio = rt5663_set_bclk_ratio,
2947 static struct snd_soc_dai_driver rt5663_dai[] = {
2949 .name = "rt5663-aif",
2952 .stream_name = "AIF Playback",
2955 .rates = RT5663_STEREO_RATES,
2956 .formats = RT5663_FORMATS,
2959 .stream_name = "AIF Capture",
2962 .rates = RT5663_STEREO_RATES,
2963 .formats = RT5663_FORMATS,
2965 .ops = &rt5663_aif_dai_ops,
2969 static const struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
2970 .probe = rt5663_probe,
2971 .remove = rt5663_remove,
2972 .suspend = rt5663_suspend,
2973 .resume = rt5663_resume,
2974 .set_bias_level = rt5663_set_bias_level,
2975 .idle_bias_off = true,
2976 .component_driver = {
2977 .controls = rt5663_snd_controls,
2978 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
2979 .dapm_widgets = rt5663_dapm_widgets,
2980 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
2981 .dapm_routes = rt5663_dapm_routes,
2982 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
2986 static const struct regmap_config rt5663_v2_regmap = {
2989 .use_single_rw = true,
2990 .max_register = 0x07fa,
2991 .volatile_reg = rt5663_v2_volatile_register,
2992 .readable_reg = rt5663_v2_readable_register,
2993 .cache_type = REGCACHE_RBTREE,
2994 .reg_defaults = rt5663_v2_reg,
2995 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
2998 static const struct regmap_config rt5663_regmap = {
3001 .use_single_rw = true,
3002 .max_register = 0x03f3,
3003 .volatile_reg = rt5663_volatile_register,
3004 .readable_reg = rt5663_readable_register,
3005 .cache_type = REGCACHE_RBTREE,
3006 .reg_defaults = rt5663_reg,
3007 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3010 static const struct regmap_config temp_regmap = {
3014 .use_single_rw = true,
3015 .max_register = 0x03f3,
3016 .cache_type = REGCACHE_NONE,
3019 static const struct i2c_device_id rt5663_i2c_id[] = {
3023 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3025 #if defined(CONFIG_OF)
3026 static const struct of_device_id rt5663_of_match[] = {
3027 { .compatible = "realtek,rt5663", },
3030 MODULE_DEVICE_TABLE(of, rt5663_of_match);
3034 static const struct acpi_device_id rt5663_acpi_match[] = {
3038 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3041 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3043 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3044 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3045 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3046 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3047 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3048 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3049 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3050 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3051 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3052 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3054 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3055 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3056 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3060 static void rt5663_calibrate(struct rt5663_priv *rt5663)
3064 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3066 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3067 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3068 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3069 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3070 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3071 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3072 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3073 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3074 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3076 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3077 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3078 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3079 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3080 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3081 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3082 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3083 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3084 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3085 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3089 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3090 if (!(value & 0x80))
3091 usleep_range(10000, 10005);
3099 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3100 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3101 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3102 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3103 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3104 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3105 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3106 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3107 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3108 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3110 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3111 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3112 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3113 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3114 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3115 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3116 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3117 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3118 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3119 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3120 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3121 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3122 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3123 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3124 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3125 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3126 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3127 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3128 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3129 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3130 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3131 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3132 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3136 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3138 usleep_range(10000, 10005);
3147 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3148 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3149 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3153 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3155 usleep_range(10000, 10005);
3164 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3165 usleep_range(10000, 10005);
3166 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3167 usleep_range(10000, 10005);
3168 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3169 usleep_range(10000, 10005);
3170 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3171 usleep_range(10000, 10005);
3172 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3173 usleep_range(10000, 10005);
3174 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3175 usleep_range(10000, 10005);
3178 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3180 device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3181 &rt5663->pdata.dc_offset_l_manual);
3182 device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3183 &rt5663->pdata.dc_offset_r_manual);
3184 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3185 &rt5663->pdata.dc_offset_l_manual_mic);
3186 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3187 &rt5663->pdata.dc_offset_r_manual_mic);
3192 static int rt5663_i2c_probe(struct i2c_client *i2c,
3193 const struct i2c_device_id *id)
3195 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3196 struct rt5663_priv *rt5663;
3199 struct regmap *regmap;
3201 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3207 i2c_set_clientdata(i2c, rt5663);
3210 rt5663->pdata = *pdata;
3212 rt5663_parse_dp(rt5663, &i2c->dev);
3214 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3215 if (IS_ERR(regmap)) {
3216 ret = PTR_ERR(regmap);
3217 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3221 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3223 case RT5663_DEVICE_ID_2:
3224 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3225 rt5663->codec_ver = CODEC_VER_1;
3227 case RT5663_DEVICE_ID_1:
3228 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3229 rt5663->codec_ver = CODEC_VER_0;
3233 "Device with ID register %#x is not rt5663\n",
3238 if (IS_ERR(rt5663->regmap)) {
3239 ret = PTR_ERR(rt5663->regmap);
3240 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3245 /* reset and calibrate */
3246 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3247 regcache_cache_bypass(rt5663->regmap, true);
3248 switch (rt5663->codec_ver) {
3250 rt5663_v2_calibrate(rt5663);
3253 rt5663_calibrate(rt5663);
3256 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3258 regcache_cache_bypass(rt5663->regmap, false);
3259 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3260 dev_dbg(&i2c->dev, "calibrate done\n");
3262 switch (rt5663->codec_ver) {
3266 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3267 ARRAY_SIZE(rt5663_patch_list));
3270 "Failed to apply regmap patch: %d\n", ret);
3273 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3277 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3278 RT5663_GP1_PIN_IRQ);
3279 /* 4btn inline command debounce */
3280 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3281 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3283 switch (rt5663->codec_ver) {
3285 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3287 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3288 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3289 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3290 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3291 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3292 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3293 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3295 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3296 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3297 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3298 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3299 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3300 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3301 /* Set GPIO4 and GPIO8 as input for combo jack */
3302 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3303 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3304 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3305 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3306 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3307 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3308 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3311 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3312 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3313 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3314 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3315 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3316 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3317 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3318 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3319 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3320 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3322 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3323 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3324 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3325 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3326 /* DACREF LDO control */
3327 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3329 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3330 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3331 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3332 RT5663_DATA_SWAP_ADCDAT1_MASK,
3333 RT5663_DATA_SWAP_ADCDAT1_LL);
3336 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3339 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3342 ret = request_irq(i2c->irq, rt5663_irq,
3343 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3344 | IRQF_ONESHOT, "rt5663", rt5663);
3346 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3350 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663,
3351 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3355 free_irq(i2c->irq, rt5663);
3361 static int rt5663_i2c_remove(struct i2c_client *i2c)
3363 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3366 free_irq(i2c->irq, rt5663);
3368 snd_soc_unregister_codec(&i2c->dev);
3373 static void rt5663_i2c_shutdown(struct i2c_client *client)
3375 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3377 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3380 static struct i2c_driver rt5663_i2c_driver = {
3383 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3384 .of_match_table = of_match_ptr(rt5663_of_match),
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