7213b1cfb18ac04088f42f125df1fc9490e84a27
[muen/linux.git] / sound / soc / codecs / rt5682.c
1 /*
2  * rt5682.c  --  RT5682 ALSA SoC audio component driver
3  *
4  * Copyright 2018 Realtek Semiconductor Corp.
5  * Author: Bard Liao <bardliao@realtek.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mutex.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/rt5682.h>
34
35 #include "rl6231.h"
36 #include "rt5682.h"
37
38 #define RT5682_NUM_SUPPLIES 3
39
40 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
41         "AVDD",
42         "MICVDD",
43         "VBAT",
44 };
45
46 struct rt5682_priv {
47         struct snd_soc_component *component;
48         struct rt5682_platform_data pdata;
49         struct regmap *regmap;
50         struct snd_soc_jack *hs_jack;
51         struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
52         struct delayed_work jack_detect_work;
53         struct delayed_work jd_check_work;
54         struct mutex calibrate_mutex;
55
56         int sysclk;
57         int sysclk_src;
58         int lrck[RT5682_AIFS];
59         int bclk[RT5682_AIFS];
60         int master[RT5682_AIFS];
61
62         int pll_src;
63         int pll_in;
64         int pll_out;
65
66         int jack_type;
67 };
68
69 static const struct reg_sequence patch_list[] = {
70         {0x01c1, 0x1000},
71 };
72
73 static const struct reg_default rt5682_reg[] = {
74         {0x0002, 0x8080},
75         {0x0003, 0x8000},
76         {0x0005, 0x0000},
77         {0x0006, 0x0000},
78         {0x0008, 0x800f},
79         {0x000b, 0x0000},
80         {0x0010, 0x4040},
81         {0x0011, 0x0000},
82         {0x0012, 0x1404},
83         {0x0013, 0x1000},
84         {0x0014, 0xa00a},
85         {0x0015, 0x0404},
86         {0x0016, 0x0404},
87         {0x0019, 0xafaf},
88         {0x001c, 0x2f2f},
89         {0x001f, 0x0000},
90         {0x0022, 0x5757},
91         {0x0023, 0x0039},
92         {0x0024, 0x000b},
93         {0x0026, 0xc0c4},
94         {0x0029, 0x8080},
95         {0x002a, 0xa0a0},
96         {0x002b, 0x0300},
97         {0x0030, 0x0000},
98         {0x003c, 0x0080},
99         {0x0044, 0x0c0c},
100         {0x0049, 0x0000},
101         {0x0061, 0x0000},
102         {0x0062, 0x0000},
103         {0x0063, 0x003f},
104         {0x0064, 0x0000},
105         {0x0065, 0x0000},
106         {0x0066, 0x0030},
107         {0x0067, 0x0000},
108         {0x006b, 0x0000},
109         {0x006c, 0x0000},
110         {0x006d, 0x2200},
111         {0x006e, 0x0a10},
112         {0x0070, 0x8000},
113         {0x0071, 0x8000},
114         {0x0073, 0x0000},
115         {0x0074, 0x0000},
116         {0x0075, 0x0002},
117         {0x0076, 0x0001},
118         {0x0079, 0x0000},
119         {0x007a, 0x0000},
120         {0x007b, 0x0000},
121         {0x007c, 0x0100},
122         {0x007e, 0x0000},
123         {0x0080, 0x0000},
124         {0x0081, 0x0000},
125         {0x0082, 0x0000},
126         {0x0083, 0x0000},
127         {0x0084, 0x0000},
128         {0x0085, 0x0000},
129         {0x0086, 0x0005},
130         {0x0087, 0x0000},
131         {0x0088, 0x0000},
132         {0x008c, 0x0003},
133         {0x008d, 0x0000},
134         {0x008e, 0x0060},
135         {0x008f, 0x1000},
136         {0x0091, 0x0c26},
137         {0x0092, 0x0073},
138         {0x0093, 0x0000},
139         {0x0094, 0x0080},
140         {0x0098, 0x0000},
141         {0x009a, 0x0000},
142         {0x009b, 0x0000},
143         {0x009c, 0x0000},
144         {0x009d, 0x0000},
145         {0x009e, 0x100c},
146         {0x009f, 0x0000},
147         {0x00a0, 0x0000},
148         {0x00a3, 0x0002},
149         {0x00a4, 0x0001},
150         {0x00ae, 0x2040},
151         {0x00af, 0x0000},
152         {0x00b6, 0x0000},
153         {0x00b7, 0x0000},
154         {0x00b8, 0x0000},
155         {0x00b9, 0x0002},
156         {0x00be, 0x0000},
157         {0x00c0, 0x0160},
158         {0x00c1, 0x82a0},
159         {0x00c2, 0x0000},
160         {0x00d0, 0x0000},
161         {0x00d1, 0x2244},
162         {0x00d2, 0x3300},
163         {0x00d3, 0x2200},
164         {0x00d4, 0x0000},
165         {0x00d9, 0x0009},
166         {0x00da, 0x0000},
167         {0x00db, 0x0000},
168         {0x00dc, 0x00c0},
169         {0x00dd, 0x2220},
170         {0x00de, 0x3131},
171         {0x00df, 0x3131},
172         {0x00e0, 0x3131},
173         {0x00e2, 0x0000},
174         {0x00e3, 0x4000},
175         {0x00e4, 0x0aa0},
176         {0x00e5, 0x3131},
177         {0x00e6, 0x3131},
178         {0x00e7, 0x3131},
179         {0x00e8, 0x3131},
180         {0x00ea, 0xb320},
181         {0x00eb, 0x0000},
182         {0x00f0, 0x0000},
183         {0x00f1, 0x00d0},
184         {0x00f2, 0x00d0},
185         {0x00f6, 0x0000},
186         {0x00fa, 0x0000},
187         {0x00fb, 0x0000},
188         {0x00fc, 0x0000},
189         {0x00fd, 0x0000},
190         {0x00fe, 0x10ec},
191         {0x00ff, 0x6530},
192         {0x0100, 0xa0a0},
193         {0x010b, 0x0000},
194         {0x010c, 0xae00},
195         {0x010d, 0xaaa0},
196         {0x010e, 0x8aa2},
197         {0x010f, 0x02a2},
198         {0x0110, 0xc000},
199         {0x0111, 0x04a2},
200         {0x0112, 0x2800},
201         {0x0113, 0x0000},
202         {0x0117, 0x0100},
203         {0x0125, 0x0410},
204         {0x0132, 0x6026},
205         {0x0136, 0x5555},
206         {0x0138, 0x3700},
207         {0x013a, 0x2000},
208         {0x013b, 0x2000},
209         {0x013c, 0x2005},
210         {0x013f, 0x0000},
211         {0x0142, 0x0000},
212         {0x0145, 0x0002},
213         {0x0146, 0x0000},
214         {0x0147, 0x0000},
215         {0x0148, 0x0000},
216         {0x0149, 0x0000},
217         {0x0150, 0x79a1},
218         {0x0151, 0x0000},
219         {0x0160, 0x4ec0},
220         {0x0161, 0x0080},
221         {0x0162, 0x0200},
222         {0x0163, 0x0800},
223         {0x0164, 0x0000},
224         {0x0165, 0x0000},
225         {0x0166, 0x0000},
226         {0x0167, 0x000f},
227         {0x0168, 0x000f},
228         {0x0169, 0x0021},
229         {0x0190, 0x413d},
230         {0x0194, 0x0000},
231         {0x0195, 0x0000},
232         {0x0197, 0x0022},
233         {0x0198, 0x0000},
234         {0x0199, 0x0000},
235         {0x01af, 0x0000},
236         {0x01b0, 0x0400},
237         {0x01b1, 0x0000},
238         {0x01b2, 0x0000},
239         {0x01b3, 0x0000},
240         {0x01b4, 0x0000},
241         {0x01b5, 0x0000},
242         {0x01b6, 0x01c3},
243         {0x01b7, 0x02a0},
244         {0x01b8, 0x03e9},
245         {0x01b9, 0x1389},
246         {0x01ba, 0xc351},
247         {0x01bb, 0x0009},
248         {0x01bc, 0x0018},
249         {0x01bd, 0x002a},
250         {0x01be, 0x004c},
251         {0x01bf, 0x0097},
252         {0x01c0, 0x433d},
253         {0x01c2, 0x0000},
254         {0x01c3, 0x0000},
255         {0x01c4, 0x0000},
256         {0x01c5, 0x0000},
257         {0x01c6, 0x0000},
258         {0x01c7, 0x0000},
259         {0x01c8, 0x40af},
260         {0x01c9, 0x0702},
261         {0x01ca, 0x0000},
262         {0x01cb, 0x0000},
263         {0x01cc, 0x5757},
264         {0x01cd, 0x5757},
265         {0x01ce, 0x5757},
266         {0x01cf, 0x5757},
267         {0x01d0, 0x5757},
268         {0x01d1, 0x5757},
269         {0x01d2, 0x5757},
270         {0x01d3, 0x5757},
271         {0x01d4, 0x5757},
272         {0x01d5, 0x5757},
273         {0x01d6, 0x0000},
274         {0x01d7, 0x0008},
275         {0x01d8, 0x0029},
276         {0x01d9, 0x3333},
277         {0x01da, 0x0000},
278         {0x01db, 0x0004},
279         {0x01dc, 0x0000},
280         {0x01de, 0x7c00},
281         {0x01df, 0x0320},
282         {0x01e0, 0x06a1},
283         {0x01e1, 0x0000},
284         {0x01e2, 0x0000},
285         {0x01e3, 0x0000},
286         {0x01e4, 0x0000},
287         {0x01e6, 0x0001},
288         {0x01e7, 0x0000},
289         {0x01e8, 0x0000},
290         {0x01ea, 0x0000},
291         {0x01eb, 0x0000},
292         {0x01ec, 0x0000},
293         {0x01ed, 0x0000},
294         {0x01ee, 0x0000},
295         {0x01ef, 0x0000},
296         {0x01f0, 0x0000},
297         {0x01f1, 0x0000},
298         {0x01f2, 0x0000},
299         {0x01f3, 0x0000},
300         {0x01f4, 0x0000},
301         {0x0210, 0x6297},
302         {0x0211, 0xa005},
303         {0x0212, 0x824c},
304         {0x0213, 0xf7ff},
305         {0x0214, 0xf24c},
306         {0x0215, 0x0102},
307         {0x0216, 0x00a3},
308         {0x0217, 0x0048},
309         {0x0218, 0xa2c0},
310         {0x0219, 0x0400},
311         {0x021a, 0x00c8},
312         {0x021b, 0x00c0},
313         {0x021c, 0x0000},
314         {0x0250, 0x4500},
315         {0x0251, 0x40b3},
316         {0x0252, 0x0000},
317         {0x0253, 0x0000},
318         {0x0254, 0x0000},
319         {0x0255, 0x0000},
320         {0x0256, 0x0000},
321         {0x0257, 0x0000},
322         {0x0258, 0x0000},
323         {0x0259, 0x0000},
324         {0x025a, 0x0005},
325         {0x0270, 0x0000},
326         {0x02ff, 0x0110},
327         {0x0300, 0x001f},
328         {0x0301, 0x032c},
329         {0x0302, 0x5f21},
330         {0x0303, 0x4000},
331         {0x0304, 0x4000},
332         {0x0305, 0x06d5},
333         {0x0306, 0x8000},
334         {0x0307, 0x0700},
335         {0x0310, 0x4560},
336         {0x0311, 0xa4a8},
337         {0x0312, 0x7418},
338         {0x0313, 0x0000},
339         {0x0314, 0x0006},
340         {0x0315, 0xffff},
341         {0x0316, 0xc400},
342         {0x0317, 0x0000},
343         {0x03c0, 0x7e00},
344         {0x03c1, 0x8000},
345         {0x03c2, 0x8000},
346         {0x03c3, 0x8000},
347         {0x03c4, 0x8000},
348         {0x03c5, 0x8000},
349         {0x03c6, 0x8000},
350         {0x03c7, 0x8000},
351         {0x03c8, 0x8000},
352         {0x03c9, 0x8000},
353         {0x03ca, 0x8000},
354         {0x03cb, 0x8000},
355         {0x03cc, 0x8000},
356         {0x03d0, 0x0000},
357         {0x03d1, 0x0000},
358         {0x03d2, 0x0000},
359         {0x03d3, 0x0000},
360         {0x03d4, 0x2000},
361         {0x03d5, 0x2000},
362         {0x03d6, 0x0000},
363         {0x03d7, 0x0000},
364         {0x03d8, 0x2000},
365         {0x03d9, 0x2000},
366         {0x03da, 0x2000},
367         {0x03db, 0x2000},
368         {0x03dc, 0x0000},
369         {0x03dd, 0x0000},
370         {0x03de, 0x0000},
371         {0x03df, 0x2000},
372         {0x03e0, 0x0000},
373         {0x03e1, 0x0000},
374         {0x03e2, 0x0000},
375         {0x03e3, 0x0000},
376         {0x03e4, 0x0000},
377         {0x03e5, 0x0000},
378         {0x03e6, 0x0000},
379         {0x03e7, 0x0000},
380         {0x03e8, 0x0000},
381         {0x03e9, 0x0000},
382         {0x03ea, 0x0000},
383         {0x03eb, 0x0000},
384         {0x03ec, 0x0000},
385         {0x03ed, 0x0000},
386         {0x03ee, 0x0000},
387         {0x03ef, 0x0000},
388         {0x03f0, 0x0800},
389         {0x03f1, 0x0800},
390         {0x03f2, 0x0800},
391         {0x03f3, 0x0800},
392 };
393
394 static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
395 {
396         switch (reg) {
397         case RT5682_RESET:
398         case RT5682_CBJ_CTRL_2:
399         case RT5682_INT_ST_1:
400         case RT5682_4BTN_IL_CMD_1:
401         case RT5682_AJD1_CTRL:
402         case RT5682_HP_CALIB_CTRL_1:
403         case RT5682_DEVICE_ID:
404         case RT5682_I2C_MODE:
405         case RT5682_HP_CALIB_CTRL_10:
406         case RT5682_EFUSE_CTRL_2:
407         case RT5682_JD_TOP_VC_VTRL:
408         case RT5682_HP_IMP_SENS_CTRL_19:
409         case RT5682_IL_CMD_1:
410         case RT5682_SAR_IL_CMD_2:
411         case RT5682_SAR_IL_CMD_4:
412         case RT5682_SAR_IL_CMD_10:
413         case RT5682_SAR_IL_CMD_11:
414         case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
415         case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
416                 return true;
417         default:
418                 return false;
419         }
420 }
421
422 static bool rt5682_readable_register(struct device *dev, unsigned int reg)
423 {
424         switch (reg) {
425         case RT5682_RESET:
426         case RT5682_VERSION_ID:
427         case RT5682_VENDOR_ID:
428         case RT5682_DEVICE_ID:
429         case RT5682_HP_CTRL_1:
430         case RT5682_HP_CTRL_2:
431         case RT5682_HPL_GAIN:
432         case RT5682_HPR_GAIN:
433         case RT5682_I2C_CTRL:
434         case RT5682_CBJ_BST_CTRL:
435         case RT5682_CBJ_CTRL_1:
436         case RT5682_CBJ_CTRL_2:
437         case RT5682_CBJ_CTRL_3:
438         case RT5682_CBJ_CTRL_4:
439         case RT5682_CBJ_CTRL_5:
440         case RT5682_CBJ_CTRL_6:
441         case RT5682_CBJ_CTRL_7:
442         case RT5682_DAC1_DIG_VOL:
443         case RT5682_STO1_ADC_DIG_VOL:
444         case RT5682_STO1_ADC_BOOST:
445         case RT5682_HP_IMP_GAIN_1:
446         case RT5682_HP_IMP_GAIN_2:
447         case RT5682_SIDETONE_CTRL:
448         case RT5682_STO1_ADC_MIXER:
449         case RT5682_AD_DA_MIXER:
450         case RT5682_STO1_DAC_MIXER:
451         case RT5682_A_DAC1_MUX:
452         case RT5682_DIG_INF2_DATA:
453         case RT5682_REC_MIXER:
454         case RT5682_CAL_REC:
455         case RT5682_ALC_BACK_GAIN:
456         case RT5682_PWR_DIG_1:
457         case RT5682_PWR_DIG_2:
458         case RT5682_PWR_ANLG_1:
459         case RT5682_PWR_ANLG_2:
460         case RT5682_PWR_ANLG_3:
461         case RT5682_PWR_MIXER:
462         case RT5682_PWR_VOL:
463         case RT5682_CLK_DET:
464         case RT5682_RESET_LPF_CTRL:
465         case RT5682_RESET_HPF_CTRL:
466         case RT5682_DMIC_CTRL_1:
467         case RT5682_I2S1_SDP:
468         case RT5682_I2S2_SDP:
469         case RT5682_ADDA_CLK_1:
470         case RT5682_ADDA_CLK_2:
471         case RT5682_I2S1_F_DIV_CTRL_1:
472         case RT5682_I2S1_F_DIV_CTRL_2:
473         case RT5682_TDM_CTRL:
474         case RT5682_TDM_ADDA_CTRL_1:
475         case RT5682_TDM_ADDA_CTRL_2:
476         case RT5682_DATA_SEL_CTRL_1:
477         case RT5682_TDM_TCON_CTRL:
478         case RT5682_GLB_CLK:
479         case RT5682_PLL_CTRL_1:
480         case RT5682_PLL_CTRL_2:
481         case RT5682_PLL_TRACK_1:
482         case RT5682_PLL_TRACK_2:
483         case RT5682_PLL_TRACK_3:
484         case RT5682_PLL_TRACK_4:
485         case RT5682_PLL_TRACK_5:
486         case RT5682_PLL_TRACK_6:
487         case RT5682_PLL_TRACK_11:
488         case RT5682_SDW_REF_CLK:
489         case RT5682_DEPOP_1:
490         case RT5682_DEPOP_2:
491         case RT5682_HP_CHARGE_PUMP_1:
492         case RT5682_HP_CHARGE_PUMP_2:
493         case RT5682_MICBIAS_1:
494         case RT5682_MICBIAS_2:
495         case RT5682_PLL_TRACK_12:
496         case RT5682_PLL_TRACK_14:
497         case RT5682_PLL2_CTRL_1:
498         case RT5682_PLL2_CTRL_2:
499         case RT5682_PLL2_CTRL_3:
500         case RT5682_PLL2_CTRL_4:
501         case RT5682_RC_CLK_CTRL:
502         case RT5682_I2S_M_CLK_CTRL_1:
503         case RT5682_I2S2_F_DIV_CTRL_1:
504         case RT5682_I2S2_F_DIV_CTRL_2:
505         case RT5682_EQ_CTRL_1:
506         case RT5682_EQ_CTRL_2:
507         case RT5682_IRQ_CTRL_1:
508         case RT5682_IRQ_CTRL_2:
509         case RT5682_IRQ_CTRL_3:
510         case RT5682_IRQ_CTRL_4:
511         case RT5682_INT_ST_1:
512         case RT5682_GPIO_CTRL_1:
513         case RT5682_GPIO_CTRL_2:
514         case RT5682_GPIO_CTRL_3:
515         case RT5682_HP_AMP_DET_CTRL_1:
516         case RT5682_HP_AMP_DET_CTRL_2:
517         case RT5682_MID_HP_AMP_DET:
518         case RT5682_LOW_HP_AMP_DET:
519         case RT5682_DELAY_BUF_CTRL:
520         case RT5682_SV_ZCD_1:
521         case RT5682_SV_ZCD_2:
522         case RT5682_IL_CMD_1:
523         case RT5682_IL_CMD_2:
524         case RT5682_IL_CMD_3:
525         case RT5682_IL_CMD_4:
526         case RT5682_IL_CMD_5:
527         case RT5682_IL_CMD_6:
528         case RT5682_4BTN_IL_CMD_1:
529         case RT5682_4BTN_IL_CMD_2:
530         case RT5682_4BTN_IL_CMD_3:
531         case RT5682_4BTN_IL_CMD_4:
532         case RT5682_4BTN_IL_CMD_5:
533         case RT5682_4BTN_IL_CMD_6:
534         case RT5682_4BTN_IL_CMD_7:
535         case RT5682_ADC_STO1_HP_CTRL_1:
536         case RT5682_ADC_STO1_HP_CTRL_2:
537         case RT5682_AJD1_CTRL:
538         case RT5682_JD1_THD:
539         case RT5682_JD2_THD:
540         case RT5682_JD_CTRL_1:
541         case RT5682_DUMMY_1:
542         case RT5682_DUMMY_2:
543         case RT5682_DUMMY_3:
544         case RT5682_DAC_ADC_DIG_VOL1:
545         case RT5682_BIAS_CUR_CTRL_2:
546         case RT5682_BIAS_CUR_CTRL_3:
547         case RT5682_BIAS_CUR_CTRL_4:
548         case RT5682_BIAS_CUR_CTRL_5:
549         case RT5682_BIAS_CUR_CTRL_6:
550         case RT5682_BIAS_CUR_CTRL_7:
551         case RT5682_BIAS_CUR_CTRL_8:
552         case RT5682_BIAS_CUR_CTRL_9:
553         case RT5682_BIAS_CUR_CTRL_10:
554         case RT5682_VREF_REC_OP_FB_CAP_CTRL:
555         case RT5682_CHARGE_PUMP_1:
556         case RT5682_DIG_IN_CTRL_1:
557         case RT5682_PAD_DRIVING_CTRL:
558         case RT5682_SOFT_RAMP_DEPOP:
559         case RT5682_CHOP_DAC:
560         case RT5682_CHOP_ADC:
561         case RT5682_CALIB_ADC_CTRL:
562         case RT5682_VOL_TEST:
563         case RT5682_SPKVDD_DET_STA:
564         case RT5682_TEST_MODE_CTRL_1:
565         case RT5682_TEST_MODE_CTRL_2:
566         case RT5682_TEST_MODE_CTRL_3:
567         case RT5682_TEST_MODE_CTRL_4:
568         case RT5682_TEST_MODE_CTRL_5:
569         case RT5682_PLL1_INTERNAL:
570         case RT5682_PLL2_INTERNAL:
571         case RT5682_STO_NG2_CTRL_1:
572         case RT5682_STO_NG2_CTRL_2:
573         case RT5682_STO_NG2_CTRL_3:
574         case RT5682_STO_NG2_CTRL_4:
575         case RT5682_STO_NG2_CTRL_5:
576         case RT5682_STO_NG2_CTRL_6:
577         case RT5682_STO_NG2_CTRL_7:
578         case RT5682_STO_NG2_CTRL_8:
579         case RT5682_STO_NG2_CTRL_9:
580         case RT5682_STO_NG2_CTRL_10:
581         case RT5682_STO1_DAC_SIL_DET:
582         case RT5682_SIL_PSV_CTRL1:
583         case RT5682_SIL_PSV_CTRL2:
584         case RT5682_SIL_PSV_CTRL3:
585         case RT5682_SIL_PSV_CTRL4:
586         case RT5682_SIL_PSV_CTRL5:
587         case RT5682_HP_IMP_SENS_CTRL_01:
588         case RT5682_HP_IMP_SENS_CTRL_02:
589         case RT5682_HP_IMP_SENS_CTRL_03:
590         case RT5682_HP_IMP_SENS_CTRL_04:
591         case RT5682_HP_IMP_SENS_CTRL_05:
592         case RT5682_HP_IMP_SENS_CTRL_06:
593         case RT5682_HP_IMP_SENS_CTRL_07:
594         case RT5682_HP_IMP_SENS_CTRL_08:
595         case RT5682_HP_IMP_SENS_CTRL_09:
596         case RT5682_HP_IMP_SENS_CTRL_10:
597         case RT5682_HP_IMP_SENS_CTRL_11:
598         case RT5682_HP_IMP_SENS_CTRL_12:
599         case RT5682_HP_IMP_SENS_CTRL_13:
600         case RT5682_HP_IMP_SENS_CTRL_14:
601         case RT5682_HP_IMP_SENS_CTRL_15:
602         case RT5682_HP_IMP_SENS_CTRL_16:
603         case RT5682_HP_IMP_SENS_CTRL_17:
604         case RT5682_HP_IMP_SENS_CTRL_18:
605         case RT5682_HP_IMP_SENS_CTRL_19:
606         case RT5682_HP_IMP_SENS_CTRL_20:
607         case RT5682_HP_IMP_SENS_CTRL_21:
608         case RT5682_HP_IMP_SENS_CTRL_22:
609         case RT5682_HP_IMP_SENS_CTRL_23:
610         case RT5682_HP_IMP_SENS_CTRL_24:
611         case RT5682_HP_IMP_SENS_CTRL_25:
612         case RT5682_HP_IMP_SENS_CTRL_26:
613         case RT5682_HP_IMP_SENS_CTRL_27:
614         case RT5682_HP_IMP_SENS_CTRL_28:
615         case RT5682_HP_IMP_SENS_CTRL_29:
616         case RT5682_HP_IMP_SENS_CTRL_30:
617         case RT5682_HP_IMP_SENS_CTRL_31:
618         case RT5682_HP_IMP_SENS_CTRL_32:
619         case RT5682_HP_IMP_SENS_CTRL_33:
620         case RT5682_HP_IMP_SENS_CTRL_34:
621         case RT5682_HP_IMP_SENS_CTRL_35:
622         case RT5682_HP_IMP_SENS_CTRL_36:
623         case RT5682_HP_IMP_SENS_CTRL_37:
624         case RT5682_HP_IMP_SENS_CTRL_38:
625         case RT5682_HP_IMP_SENS_CTRL_39:
626         case RT5682_HP_IMP_SENS_CTRL_40:
627         case RT5682_HP_IMP_SENS_CTRL_41:
628         case RT5682_HP_IMP_SENS_CTRL_42:
629         case RT5682_HP_IMP_SENS_CTRL_43:
630         case RT5682_HP_LOGIC_CTRL_1:
631         case RT5682_HP_LOGIC_CTRL_2:
632         case RT5682_HP_LOGIC_CTRL_3:
633         case RT5682_HP_CALIB_CTRL_1:
634         case RT5682_HP_CALIB_CTRL_2:
635         case RT5682_HP_CALIB_CTRL_3:
636         case RT5682_HP_CALIB_CTRL_4:
637         case RT5682_HP_CALIB_CTRL_5:
638         case RT5682_HP_CALIB_CTRL_6:
639         case RT5682_HP_CALIB_CTRL_7:
640         case RT5682_HP_CALIB_CTRL_9:
641         case RT5682_HP_CALIB_CTRL_10:
642         case RT5682_HP_CALIB_CTRL_11:
643         case RT5682_HP_CALIB_STA_1:
644         case RT5682_HP_CALIB_STA_2:
645         case RT5682_HP_CALIB_STA_3:
646         case RT5682_HP_CALIB_STA_4:
647         case RT5682_HP_CALIB_STA_5:
648         case RT5682_HP_CALIB_STA_6:
649         case RT5682_HP_CALIB_STA_7:
650         case RT5682_HP_CALIB_STA_8:
651         case RT5682_HP_CALIB_STA_9:
652         case RT5682_HP_CALIB_STA_10:
653         case RT5682_HP_CALIB_STA_11:
654         case RT5682_SAR_IL_CMD_1:
655         case RT5682_SAR_IL_CMD_2:
656         case RT5682_SAR_IL_CMD_3:
657         case RT5682_SAR_IL_CMD_4:
658         case RT5682_SAR_IL_CMD_5:
659         case RT5682_SAR_IL_CMD_6:
660         case RT5682_SAR_IL_CMD_7:
661         case RT5682_SAR_IL_CMD_8:
662         case RT5682_SAR_IL_CMD_9:
663         case RT5682_SAR_IL_CMD_10:
664         case RT5682_SAR_IL_CMD_11:
665         case RT5682_SAR_IL_CMD_12:
666         case RT5682_SAR_IL_CMD_13:
667         case RT5682_EFUSE_CTRL_1:
668         case RT5682_EFUSE_CTRL_2:
669         case RT5682_EFUSE_CTRL_3:
670         case RT5682_EFUSE_CTRL_4:
671         case RT5682_EFUSE_CTRL_5:
672         case RT5682_EFUSE_CTRL_6:
673         case RT5682_EFUSE_CTRL_7:
674         case RT5682_EFUSE_CTRL_8:
675         case RT5682_EFUSE_CTRL_9:
676         case RT5682_EFUSE_CTRL_10:
677         case RT5682_EFUSE_CTRL_11:
678         case RT5682_JD_TOP_VC_VTRL:
679         case RT5682_DRC1_CTRL_0:
680         case RT5682_DRC1_CTRL_1:
681         case RT5682_DRC1_CTRL_2:
682         case RT5682_DRC1_CTRL_3:
683         case RT5682_DRC1_CTRL_4:
684         case RT5682_DRC1_CTRL_5:
685         case RT5682_DRC1_CTRL_6:
686         case RT5682_DRC1_HARD_LMT_CTRL_1:
687         case RT5682_DRC1_HARD_LMT_CTRL_2:
688         case RT5682_DRC1_PRIV_1:
689         case RT5682_DRC1_PRIV_2:
690         case RT5682_DRC1_PRIV_3:
691         case RT5682_DRC1_PRIV_4:
692         case RT5682_DRC1_PRIV_5:
693         case RT5682_DRC1_PRIV_6:
694         case RT5682_DRC1_PRIV_7:
695         case RT5682_DRC1_PRIV_8:
696         case RT5682_EQ_AUTO_RCV_CTRL1:
697         case RT5682_EQ_AUTO_RCV_CTRL2:
698         case RT5682_EQ_AUTO_RCV_CTRL3:
699         case RT5682_EQ_AUTO_RCV_CTRL4:
700         case RT5682_EQ_AUTO_RCV_CTRL5:
701         case RT5682_EQ_AUTO_RCV_CTRL6:
702         case RT5682_EQ_AUTO_RCV_CTRL7:
703         case RT5682_EQ_AUTO_RCV_CTRL8:
704         case RT5682_EQ_AUTO_RCV_CTRL9:
705         case RT5682_EQ_AUTO_RCV_CTRL10:
706         case RT5682_EQ_AUTO_RCV_CTRL11:
707         case RT5682_EQ_AUTO_RCV_CTRL12:
708         case RT5682_EQ_AUTO_RCV_CTRL13:
709         case RT5682_ADC_L_EQ_LPF1_A1:
710         case RT5682_R_EQ_LPF1_A1:
711         case RT5682_L_EQ_LPF1_H0:
712         case RT5682_R_EQ_LPF1_H0:
713         case RT5682_L_EQ_BPF1_A1:
714         case RT5682_R_EQ_BPF1_A1:
715         case RT5682_L_EQ_BPF1_A2:
716         case RT5682_R_EQ_BPF1_A2:
717         case RT5682_L_EQ_BPF1_H0:
718         case RT5682_R_EQ_BPF1_H0:
719         case RT5682_L_EQ_BPF2_A1:
720         case RT5682_R_EQ_BPF2_A1:
721         case RT5682_L_EQ_BPF2_A2:
722         case RT5682_R_EQ_BPF2_A2:
723         case RT5682_L_EQ_BPF2_H0:
724         case RT5682_R_EQ_BPF2_H0:
725         case RT5682_L_EQ_BPF3_A1:
726         case RT5682_R_EQ_BPF3_A1:
727         case RT5682_L_EQ_BPF3_A2:
728         case RT5682_R_EQ_BPF3_A2:
729         case RT5682_L_EQ_BPF3_H0:
730         case RT5682_R_EQ_BPF3_H0:
731         case RT5682_L_EQ_BPF4_A1:
732         case RT5682_R_EQ_BPF4_A1:
733         case RT5682_L_EQ_BPF4_A2:
734         case RT5682_R_EQ_BPF4_A2:
735         case RT5682_L_EQ_BPF4_H0:
736         case RT5682_R_EQ_BPF4_H0:
737         case RT5682_L_EQ_HPF1_A1:
738         case RT5682_R_EQ_HPF1_A1:
739         case RT5682_L_EQ_HPF1_H0:
740         case RT5682_R_EQ_HPF1_H0:
741         case RT5682_L_EQ_PRE_VOL:
742         case RT5682_R_EQ_PRE_VOL:
743         case RT5682_L_EQ_POST_VOL:
744         case RT5682_R_EQ_POST_VOL:
745         case RT5682_I2C_MODE:
746                 return true;
747         default:
748                 return false;
749         }
750 }
751
752 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
753 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
754 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
755
756 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
757 static const DECLARE_TLV_DB_RANGE(bst_tlv,
758         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
759         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
760         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
761         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
762         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
763         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
764         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
765 );
766
767 /* Interface data select */
768 static const char * const rt5682_data_select[] = {
769         "L/R", "R/L", "L/L", "R/R"
770 };
771
772 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
773         RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
774
775 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
776         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
777
778 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
779         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
780
781 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
782         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
783
784 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
785         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
786
787 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
788         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
789
790 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
791         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
792
793 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
794         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
795
796 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
797         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
798
799 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
800         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
801
802 static void rt5682_reset(struct regmap *regmap)
803 {
804         regmap_write(regmap, RT5682_RESET, 0);
805         regmap_write(regmap, RT5682_I2C_MODE, 1);
806 }
807 /**
808  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
809  * @component: SoC audio component device.
810  * @filter_mask: mask of filters.
811  * @clk_src: clock source
812  *
813  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
814  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
815  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
816  * ASRC function will track i2s clock and generate a corresponding system clock
817  * for codec. This function provides an API to select the clock source for a
818  * set of filters specified by the mask. And the component driver will turn on
819  * ASRC for these filters if ASRC is selected as their clock source.
820  */
821 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
822                 unsigned int filter_mask, unsigned int clk_src)
823 {
824
825         switch (clk_src) {
826         case RT5682_CLK_SEL_SYS:
827         case RT5682_CLK_SEL_I2S1_ASRC:
828         case RT5682_CLK_SEL_I2S2_ASRC:
829                 break;
830
831         default:
832                 return -EINVAL;
833         }
834
835         if (filter_mask & RT5682_DA_STEREO1_FILTER) {
836                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
837                         RT5682_FILTER_CLK_SEL_MASK,
838                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
839         }
840
841         if (filter_mask & RT5682_AD_STEREO1_FILTER) {
842                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
843                         RT5682_FILTER_CLK_SEL_MASK,
844                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
845         }
846
847         return 0;
848 }
849 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
850
851 static int rt5682_button_detect(struct snd_soc_component *component)
852 {
853         int btn_type, val;
854
855         val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
856         btn_type = val & 0xfff0;
857         snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
858         pr_debug("%s btn_type=%x\n", __func__, btn_type);
859         snd_soc_component_update_bits(component,
860                 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
861
862         return btn_type;
863 }
864
865 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
866                 bool enable)
867 {
868         if (enable) {
869                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
870                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
871                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
872                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
873                 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
874                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
875                         RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
876                         RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
877                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
878                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
879         } else {
880                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
881                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
882                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
883                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
884                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
885                         RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
886                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
887                         RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
888                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
889                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
890         }
891 }
892
893 /**
894  * rt5682_headset_detect - Detect headset.
895  * @component: SoC audio component device.
896  * @jack_insert: Jack insert or not.
897  *
898  * Detect whether is headset or not when jack inserted.
899  *
900  * Returns detect status.
901  */
902 static int rt5682_headset_detect(struct snd_soc_component *component,
903                 int jack_insert)
904 {
905         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
906         struct snd_soc_dapm_context *dapm =
907                 snd_soc_component_get_dapm(component);
908         unsigned int val, count;
909
910         if (jack_insert) {
911                 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
912                 snd_soc_dapm_sync(dapm);
913                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
914                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
915
916                 count = 0;
917                 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
918                         & RT5682_JACK_TYPE_MASK;
919                 while (val == 0 && count < 50) {
920                         usleep_range(10000, 15000);
921                         val = snd_soc_component_read32(component,
922                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
923                         count++;
924                 }
925
926                 switch (val) {
927                 case 0x1:
928                 case 0x2:
929                         rt5682->jack_type = SND_JACK_HEADSET;
930                         rt5682_enable_push_button_irq(component, true);
931                         break;
932                 default:
933                         rt5682->jack_type = SND_JACK_HEADPHONE;
934                 }
935
936         } else {
937                 rt5682_enable_push_button_irq(component, false);
938                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
939                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
940                 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
941                 snd_soc_dapm_sync(dapm);
942
943                 rt5682->jack_type = 0;
944         }
945
946         dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
947         return rt5682->jack_type;
948 }
949
950 static irqreturn_t rt5682_irq(int irq, void *data)
951 {
952         struct rt5682_priv *rt5682 = data;
953
954         mod_delayed_work(system_power_efficient_wq,
955                         &rt5682->jack_detect_work, msecs_to_jiffies(250));
956
957         return IRQ_HANDLED;
958 }
959
960 static void rt5682_jd_check_handler(struct work_struct *work)
961 {
962         struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
963                 jd_check_work.work);
964
965         if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
966                 & RT5682_JDH_RS_MASK) {
967                 /* jack out */
968                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
969
970                 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
971                                 SND_JACK_HEADSET |
972                                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
973                                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
974         } else {
975                 schedule_delayed_work(&rt5682->jd_check_work, 500);
976         }
977 }
978
979 static int rt5682_set_jack_detect(struct snd_soc_component *component,
980         struct snd_soc_jack *hs_jack, void *data)
981 {
982         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
983
984         switch (rt5682->pdata.jd_src) {
985         case RT5682_JD1:
986                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
987                         RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
988                 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
989                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
990                         RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
991                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
992                         RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
993                 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
994                         RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
995                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
996                                 RT5682_POW_IRQ | RT5682_POW_JDH |
997                                 RT5682_POW_ANA, RT5682_POW_IRQ |
998                                 RT5682_POW_JDH | RT5682_POW_ANA);
999                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1000                         RT5682_PWR_JDH | RT5682_PWR_JDL,
1001                         RT5682_PWR_JDH | RT5682_PWR_JDL);
1002                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1003                         RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1004                         RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1005                 mod_delayed_work(system_power_efficient_wq,
1006                            &rt5682->jack_detect_work, msecs_to_jiffies(250));
1007                 break;
1008
1009         case RT5682_JD_NULL:
1010                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1011                         RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1012                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1013                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1014                 break;
1015
1016         default:
1017                 dev_warn(component->dev, "Wrong JD source\n");
1018                 break;
1019         }
1020
1021         rt5682->hs_jack = hs_jack;
1022
1023         return 0;
1024 }
1025
1026 static void rt5682_jack_detect_handler(struct work_struct *work)
1027 {
1028         struct rt5682_priv *rt5682 =
1029                 container_of(work, struct rt5682_priv, jack_detect_work.work);
1030         int val, btn_type;
1031
1032         while (!rt5682->component)
1033                 usleep_range(10000, 15000);
1034
1035         while (!rt5682->component->card->instantiated)
1036                 usleep_range(10000, 15000);
1037
1038         mutex_lock(&rt5682->calibrate_mutex);
1039
1040         val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1041                 & RT5682_JDH_RS_MASK;
1042         if (!val) {
1043                 /* jack in */
1044                 if (rt5682->jack_type == 0) {
1045                         /* jack was out, report jack type */
1046                         rt5682->jack_type =
1047                                 rt5682_headset_detect(rt5682->component, 1);
1048                 } else {
1049                         /* jack is already in, report button event */
1050                         rt5682->jack_type = SND_JACK_HEADSET;
1051                         btn_type = rt5682_button_detect(rt5682->component);
1052                         /**
1053                          * rt5682 can report three kinds of button behavior,
1054                          * one click, double click and hold. However,
1055                          * currently we will report button pressed/released
1056                          * event. So all the three button behaviors are
1057                          * treated as button pressed.
1058                          */
1059                         switch (btn_type) {
1060                         case 0x8000:
1061                         case 0x4000:
1062                         case 0x2000:
1063                                 rt5682->jack_type |= SND_JACK_BTN_0;
1064                                 break;
1065                         case 0x1000:
1066                         case 0x0800:
1067                         case 0x0400:
1068                                 rt5682->jack_type |= SND_JACK_BTN_1;
1069                                 break;
1070                         case 0x0200:
1071                         case 0x0100:
1072                         case 0x0080:
1073                                 rt5682->jack_type |= SND_JACK_BTN_2;
1074                                 break;
1075                         case 0x0040:
1076                         case 0x0020:
1077                         case 0x0010:
1078                                 rt5682->jack_type |= SND_JACK_BTN_3;
1079                                 break;
1080                         case 0x0000: /* unpressed */
1081                                 break;
1082                         default:
1083                                 btn_type = 0;
1084                                 dev_err(rt5682->component->dev,
1085                                         "Unexpected button code 0x%04x\n",
1086                                         btn_type);
1087                                 break;
1088                         }
1089                 }
1090         } else {
1091                 /* jack out */
1092                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1093         }
1094
1095         snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1096                         SND_JACK_HEADSET |
1097                             SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1098                             SND_JACK_BTN_2 | SND_JACK_BTN_3);
1099
1100         if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1101                 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1102                 schedule_delayed_work(&rt5682->jd_check_work, 0);
1103         else
1104                 cancel_delayed_work_sync(&rt5682->jd_check_work);
1105
1106         mutex_unlock(&rt5682->calibrate_mutex);
1107 }
1108
1109 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1110         /* DAC Digital Volume */
1111         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1112                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv),
1113
1114         /* IN Boost Volume */
1115         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1116                 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1117
1118         /* ADC Digital Volume Control */
1119         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1120                 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1121         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1122                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1123
1124         /* ADC Boost Volume Control */
1125         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1126                 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1127                 3, 0, adc_bst_tlv),
1128 };
1129
1130
1131 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1132                           int target, const int div[], int size)
1133 {
1134         int i;
1135
1136         if (rt5682->sysclk < target) {
1137                 pr_err("sysclk rate %d is too low\n",
1138                         rt5682->sysclk);
1139                 return 0;
1140         }
1141
1142         for (i = 0; i < size - 1; i++) {
1143                 pr_info("div[%d]=%d\n", i, div[i]);
1144                 if (target * div[i] == rt5682->sysclk)
1145                         return i;
1146                 if (target * div[i + 1] > rt5682->sysclk) {
1147                         pr_err("can't find div for sysclk %d\n",
1148                                 rt5682->sysclk);
1149                         return i;
1150                 }
1151         }
1152
1153         if (target * div[i] < rt5682->sysclk)
1154                 pr_err("sysclk rate %d is too high\n",
1155                         rt5682->sysclk);
1156
1157         return size - 1;
1158
1159 }
1160
1161 /**
1162  * set_dmic_clk - Set parameter of dmic.
1163  *
1164  * @w: DAPM widget.
1165  * @kcontrol: The kcontrol of this widget.
1166  * @event: Event id.
1167  *
1168  * Choose dmic clock between 1MHz and 3MHz.
1169  * It is better for clock to approximate 3MHz.
1170  */
1171 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1172         struct snd_kcontrol *kcontrol, int event)
1173 {
1174         struct snd_soc_component *component =
1175                 snd_soc_dapm_to_component(w->dapm);
1176         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1177         int idx = -EINVAL;
1178         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1179
1180         idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1181
1182         snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1183                 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1184
1185         return 0;
1186 }
1187
1188 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1189         struct snd_kcontrol *kcontrol, int event)
1190 {
1191         struct snd_soc_component *component =
1192                 snd_soc_dapm_to_component(w->dapm);
1193         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1194         int ref, val, reg, sft, mask, idx = -EINVAL;
1195         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1196         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1197
1198         val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1199                 RT5682_GP4_PIN_MASK;
1200         if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1201                 val == RT5682_GP4_PIN_ADCDAT2)
1202                 ref = 256 * rt5682->lrck[RT5682_AIF2];
1203         else
1204                 ref = 256 * rt5682->lrck[RT5682_AIF1];
1205
1206         idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1207
1208         if (w->shift == RT5682_PWR_ADC_S1F_BIT) {
1209                 reg = RT5682_PLL_TRACK_3;
1210                 sft = RT5682_ADC_OSR_SFT;
1211                 mask = RT5682_ADC_OSR_MASK;
1212         } else {
1213                 reg = RT5682_PLL_TRACK_2;
1214                 sft = RT5682_DAC_OSR_SFT;
1215                 mask = RT5682_DAC_OSR_MASK;
1216         }
1217
1218         snd_soc_component_update_bits(component, reg,
1219                 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1220
1221         /* select over sample rate */
1222         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1223                 if (rt5682->sysclk <= 12288000 * div_o[idx])
1224                         break;
1225         }
1226
1227         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1228                 mask, idx << sft);
1229
1230         return 0;
1231 }
1232
1233 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1234                          struct snd_soc_dapm_widget *sink)
1235 {
1236         unsigned int val;
1237         struct snd_soc_component *component =
1238                 snd_soc_dapm_to_component(w->dapm);
1239
1240         val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1241         val &= RT5682_SCLK_SRC_MASK;
1242         if (val == RT5682_SCLK_SRC_PLL1)
1243                 return 1;
1244         else
1245                 return 0;
1246 }
1247
1248 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1249                          struct snd_soc_dapm_widget *sink)
1250 {
1251         unsigned int reg, shift, val;
1252         struct snd_soc_component *component =
1253                 snd_soc_dapm_to_component(w->dapm);
1254
1255         switch (w->shift) {
1256         case RT5682_ADC_STO1_ASRC_SFT:
1257                 reg = RT5682_PLL_TRACK_3;
1258                 shift = RT5682_FILTER_CLK_SEL_SFT;
1259                 break;
1260         case RT5682_DAC_STO1_ASRC_SFT:
1261                 reg = RT5682_PLL_TRACK_2;
1262                 shift = RT5682_FILTER_CLK_SEL_SFT;
1263                 break;
1264         default:
1265                 return 0;
1266         }
1267
1268         val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1269         switch (val) {
1270         case RT5682_CLK_SEL_I2S1_ASRC:
1271         case RT5682_CLK_SEL_I2S2_ASRC:
1272                 return 1;
1273         default:
1274                 return 0;
1275         }
1276
1277 }
1278
1279 /* Digital Mixer */
1280 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1281         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1282                         RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1283         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1284                         RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1285 };
1286
1287 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1288         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1289                         RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1290         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1291                         RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1292 };
1293
1294 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1295         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1296                         RT5682_M_ADCMIX_L_SFT, 1, 1),
1297         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1298                         RT5682_M_DAC1_L_SFT, 1, 1),
1299 };
1300
1301 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1302         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1303                         RT5682_M_ADCMIX_R_SFT, 1, 1),
1304         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1305                         RT5682_M_DAC1_R_SFT, 1, 1),
1306 };
1307
1308 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1309         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1310                         RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1311         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1312                         RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1313 };
1314
1315 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1316         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1317                         RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1318         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1319                         RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1320 };
1321
1322 /* Analog Input Mixer */
1323 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1324         SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1325                         RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1326 };
1327
1328 /* STO1 ADC1 Source */
1329 /* MX-26 [13] [5] */
1330 static const char * const rt5682_sto1_adc1_src[] = {
1331         "DAC MIX", "ADC"
1332 };
1333
1334 static SOC_ENUM_SINGLE_DECL(
1335         rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1336         RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1337
1338 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1339         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1340
1341 static SOC_ENUM_SINGLE_DECL(
1342         rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1343         RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1344
1345 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1346         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1347
1348 /* STO1 ADC Source */
1349 /* MX-26 [11:10] [3:2] */
1350 static const char * const rt5682_sto1_adc_src[] = {
1351         "ADC1 L", "ADC1 R"
1352 };
1353
1354 static SOC_ENUM_SINGLE_DECL(
1355         rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1356         RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1357
1358 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1359         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1360
1361 static SOC_ENUM_SINGLE_DECL(
1362         rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1363         RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1364
1365 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1366         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1367
1368 /* STO1 ADC2 Source */
1369 /* MX-26 [12] [4] */
1370 static const char * const rt5682_sto1_adc2_src[] = {
1371         "DAC MIX", "DMIC"
1372 };
1373
1374 static SOC_ENUM_SINGLE_DECL(
1375         rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1376         RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1377
1378 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1379         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1380
1381 static SOC_ENUM_SINGLE_DECL(
1382         rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1383         RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1384
1385 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1386         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1387
1388 /* MX-79 [6:4] I2S1 ADC data location */
1389 static const unsigned int rt5682_if1_adc_slot_values[] = {
1390         0,
1391         2,
1392         4,
1393         6,
1394 };
1395
1396 static const char * const rt5682_if1_adc_slot_src[] = {
1397         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1398 };
1399
1400 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1401         RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1402         rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1403
1404 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1405         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1406
1407 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1408 /* MX-2B [4], MX-2B [0]*/
1409 static const char * const rt5682_alg_dac1_src[] = {
1410         "Stereo1 DAC Mixer", "DAC1"
1411 };
1412
1413 static SOC_ENUM_SINGLE_DECL(
1414         rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1415         RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1416
1417 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1418         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1419
1420 static SOC_ENUM_SINGLE_DECL(
1421         rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1422         RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1423
1424 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1425         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1426
1427 /* Out Switch */
1428 static const struct snd_kcontrol_new hpol_switch =
1429         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1430                                         RT5682_L_MUTE_SFT, 1, 1);
1431 static const struct snd_kcontrol_new hpor_switch =
1432         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1433                                         RT5682_R_MUTE_SFT, 1, 1);
1434
1435 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w,
1436         struct snd_kcontrol *kcontrol, int event)
1437 {
1438         struct snd_soc_component *component =
1439                 snd_soc_dapm_to_component(w->dapm);
1440
1441         switch (event) {
1442         case SND_SOC_DAPM_PRE_PMU:
1443                 snd_soc_component_update_bits(component,
1444                         RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
1445                 break;
1446         case SND_SOC_DAPM_POST_PMD:
1447                 snd_soc_component_update_bits(component,
1448                         RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV);
1449                 break;
1450         default:
1451                 return 0;
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1458         struct snd_kcontrol *kcontrol, int event)
1459 {
1460         struct snd_soc_component *component =
1461                 snd_soc_dapm_to_component(w->dapm);
1462
1463         switch (event) {
1464         case SND_SOC_DAPM_PRE_PMU:
1465                 snd_soc_component_write(component,
1466                         RT5682_HP_LOGIC_CTRL_2, 0x0012);
1467                 snd_soc_component_write(component,
1468                         RT5682_HP_CTRL_2, 0x6000);
1469                 snd_soc_component_update_bits(component,
1470                         RT5682_DEPOP_1, 0x60, 0x60);
1471                 break;
1472
1473         case SND_SOC_DAPM_POST_PMD:
1474                 snd_soc_component_update_bits(component,
1475                         RT5682_DEPOP_1, 0x60, 0x0);
1476                 snd_soc_component_write(component,
1477                         RT5682_HP_CTRL_2, 0x0000);
1478                 break;
1479
1480         default:
1481                 return 0;
1482         }
1483
1484         return 0;
1485
1486 }
1487
1488 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1489         struct snd_kcontrol *kcontrol, int event)
1490 {
1491         switch (event) {
1492         case SND_SOC_DAPM_POST_PMU:
1493                 /*Add delay to avoid pop noise*/
1494                 msleep(150);
1495                 break;
1496
1497         default:
1498                 return 0;
1499         }
1500
1501         return 0;
1502 }
1503
1504 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1505         struct snd_kcontrol *kcontrol, int event)
1506 {
1507         struct snd_soc_component *component =
1508                 snd_soc_dapm_to_component(w->dapm);
1509
1510         switch (event) {
1511         case SND_SOC_DAPM_PRE_PMU:
1512                 switch (w->shift) {
1513                 case RT5682_PWR_VREF1_BIT:
1514                         snd_soc_component_update_bits(component,
1515                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1516                         break;
1517
1518                 case RT5682_PWR_VREF2_BIT:
1519                         snd_soc_component_update_bits(component,
1520                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1521                         break;
1522
1523                 default:
1524                         break;
1525                 }
1526                 break;
1527
1528         case SND_SOC_DAPM_POST_PMU:
1529                 usleep_range(15000, 20000);
1530                 switch (w->shift) {
1531                 case RT5682_PWR_VREF1_BIT:
1532                         snd_soc_component_update_bits(component,
1533                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1534                                 RT5682_PWR_FV1);
1535                         break;
1536
1537                 case RT5682_PWR_VREF2_BIT:
1538                         snd_soc_component_update_bits(component,
1539                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1540                                 RT5682_PWR_FV2);
1541                         break;
1542
1543                 default:
1544                         break;
1545                 }
1546                 break;
1547
1548         default:
1549                 return 0;
1550         }
1551
1552         return 0;
1553 }
1554
1555 static const unsigned int rt5682_adcdat_pin_values[] = {
1556         1,
1557         3,
1558 };
1559
1560 static const char * const rt5682_adcdat_pin_select[] = {
1561         "ADCDAT1",
1562         "ADCDAT2",
1563 };
1564
1565 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1566         RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1567         rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1568
1569 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1570         SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1571
1572 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1573         SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1574                 0, NULL, 0),
1575         SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1576                 0, NULL, 0),
1577         SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1578                 0, NULL, 0),
1579         SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1580                 0, NULL, 0),
1581         SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1582                 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1583         SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
1584                 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1585
1586         /* ASRC */
1587         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1588                 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1589         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1590                 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1591         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1592                 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1593         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1594                 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1595         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1596                 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1597
1598         /* Input Side */
1599         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1600                 0, NULL, 0),
1601         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1602                 0, NULL, 0),
1603
1604         /* Input Lines */
1605         SND_SOC_DAPM_INPUT("DMIC L1"),
1606         SND_SOC_DAPM_INPUT("DMIC R1"),
1607
1608         SND_SOC_DAPM_INPUT("IN1P"),
1609
1610         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1611                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1612         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1613                 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1614
1615         /* Boost */
1616         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1617                 0, 0, NULL, 0),
1618
1619         SND_SOC_DAPM_SUPPLY("CBJ Power", RT5682_PWR_ANLG_3,
1620                 RT5682_PWR_CBJ_BIT, 0, NULL, 0),
1621
1622         /* REC Mixer */
1623         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1624                 ARRAY_SIZE(rt5682_rec1_l_mix)),
1625         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1626                 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1627
1628         /* ADCs */
1629         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1630         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1631
1632         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1633                 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1634         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1635                 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1636         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1637                 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1638
1639         /* ADC Mux */
1640         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1641                 &rt5682_sto1_adc1l_mux),
1642         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1643                 &rt5682_sto1_adc1r_mux),
1644         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1645                 &rt5682_sto1_adc2l_mux),
1646         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1647                 &rt5682_sto1_adc2r_mux),
1648         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1649                 &rt5682_sto1_adcl_mux),
1650         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1651                 &rt5682_sto1_adcr_mux),
1652         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1653                 &rt5682_if1_adc_slot_mux),
1654
1655         /* ADC Mixer */
1656         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1657                 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1658                 SND_SOC_DAPM_PRE_PMU),
1659         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1660                 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1661                 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1662         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1663                 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1664                 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1665         SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1666                 14, 1, NULL, 0),
1667
1668         /* ADC PGA */
1669         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1670
1671         /* Digital Interface */
1672         SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1673                 0, NULL, 0),
1674         SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1675                 0, NULL, 0),
1676         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1677         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1678         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1679
1680         /* Digital Interface Select */
1681         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1682                         &rt5682_if1_01_adc_swap_mux),
1683         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1684                         &rt5682_if1_23_adc_swap_mux),
1685         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1686                         &rt5682_if1_45_adc_swap_mux),
1687         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1688                         &rt5682_if1_67_adc_swap_mux),
1689         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1690                         &rt5682_if2_adc_swap_mux),
1691
1692         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1693                         &rt5682_adcdat_pin_ctrl),
1694
1695         /* Audio Interface */
1696         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1697                 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1698         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1699                 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1700         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1701
1702         /* Output Side */
1703         /* DAC mixer before sound effect  */
1704         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1705                 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1706         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1707                 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1708
1709         /* DAC channel Mux */
1710         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1711                 &rt5682_alg_dac_l1_mux),
1712         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1713                 &rt5682_alg_dac_r1_mux),
1714
1715         /* DAC Mixer */
1716         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1717                 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1718                 SND_SOC_DAPM_PRE_PMU),
1719         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1720                 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1721         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1722                 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1723
1724         /* DACs */
1725         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1726                 RT5682_PWR_DAC_L1_BIT, 0),
1727         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1728                 RT5682_PWR_DAC_R1_BIT, 0),
1729         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1730                 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1731
1732         /* HPO */
1733         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1734                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1735
1736         SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1737                 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1738         SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1739                 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1740         SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1741                 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event,
1742                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1743         SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1744                 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1745
1746         SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1747                 &hpol_switch),
1748         SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1749                 &hpor_switch),
1750
1751         /* CLK DET */
1752         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1753                 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1754         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1755                 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1756         SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1757                 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1758         SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1759                 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1760
1761         /* Output Lines */
1762         SND_SOC_DAPM_OUTPUT("HPOL"),
1763         SND_SOC_DAPM_OUTPUT("HPOR"),
1764
1765 };
1766
1767 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1768         /*PLL*/
1769         {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1770         {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1771
1772         /*ASRC*/
1773         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1774         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1775         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1776         {"ADC STO1 ASRC", NULL, "CLKDET"},
1777         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1778         {"DAC STO1 ASRC", NULL, "CLKDET"},
1779
1780         /*Vref*/
1781         {"MICBIAS1", NULL, "Vref1"},
1782         {"MICBIAS1", NULL, "Vref2"},
1783         {"MICBIAS2", NULL, "Vref1"},
1784         {"MICBIAS2", NULL, "Vref2"},
1785
1786         {"CLKDET SYS", NULL, "CLKDET"},
1787
1788         {"IN1P", NULL, "LDO2"},
1789
1790         {"BST1 CBJ", NULL, "IN1P"},
1791         {"BST1 CBJ", NULL, "CBJ Power"},
1792         {"CBJ Power", NULL, "Vref2"},
1793
1794         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1795         {"RECMIX1L", NULL, "RECMIX1L Power"},
1796
1797         {"ADC1 L", NULL, "RECMIX1L"},
1798         {"ADC1 L", NULL, "ADC1 L Power"},
1799         {"ADC1 L", NULL, "ADC1 clock"},
1800
1801         {"DMIC L1", NULL, "DMIC CLK"},
1802         {"DMIC L1", NULL, "DMIC1 Power"},
1803         {"DMIC R1", NULL, "DMIC CLK"},
1804         {"DMIC R1", NULL, "DMIC1 Power"},
1805         {"DMIC CLK", NULL, "DMIC ASRC"},
1806
1807         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1808         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1809         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1810         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1811
1812         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1813         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1814         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1815         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1816
1817         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1818         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1819         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1820         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1821
1822         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1823         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1824         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1825
1826         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1827         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1828         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1829
1830         {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1831
1832         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1833         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1834
1835         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1836         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1837         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1838         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1839         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1840         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1841         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1842         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1843         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1844         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1845         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1846         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1847         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1848         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1849         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1850         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1851
1852         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1853         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1854         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1855         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1856         {"IF1_ADC Mux", NULL, "I2S1"},
1857         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1858         {"AIF1TX", NULL, "ADCDAT Mux"},
1859         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1860         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1861         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1862         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1863         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1864         {"AIF2TX", NULL, "ADCDAT Mux"},
1865
1866         {"IF1 DAC1 L", NULL, "AIF1RX"},
1867         {"IF1 DAC1 L", NULL, "I2S1"},
1868         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1869         {"IF1 DAC1 R", NULL, "AIF1RX"},
1870         {"IF1 DAC1 R", NULL, "I2S1"},
1871         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1872
1873         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1874         {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1875         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1876         {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1877
1878         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1879         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1880
1881         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1882         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1883
1884         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1885         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1886         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1887         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1888
1889         {"DAC L1", NULL, "DAC L1 Source"},
1890         {"DAC R1", NULL, "DAC R1 Source"},
1891
1892         {"DAC L1", NULL, "DAC 1 Clock"},
1893         {"DAC R1", NULL, "DAC 1 Clock"},
1894
1895         {"HP Amp", NULL, "DAC L1"},
1896         {"HP Amp", NULL, "DAC R1"},
1897         {"HP Amp", NULL, "HP Amp L"},
1898         {"HP Amp", NULL, "HP Amp R"},
1899         {"HP Amp", NULL, "Capless"},
1900         {"HP Amp", NULL, "Charge Pump"},
1901         {"HP Amp", NULL, "CLKDET SYS"},
1902         {"HP Amp", NULL, "CBJ Power"},
1903         {"HP Amp", NULL, "Vref1"},
1904         {"HP Amp", NULL, "Vref2"},
1905         {"HPOL Playback", "Switch", "HP Amp"},
1906         {"HPOR Playback", "Switch", "HP Amp"},
1907         {"HPOL", NULL, "HPOL Playback"},
1908         {"HPOR", NULL, "HPOR Playback"},
1909 };
1910
1911 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1912                         unsigned int rx_mask, int slots, int slot_width)
1913 {
1914         struct snd_soc_component *component = dai->component;
1915         unsigned int cl, val = 0;
1916
1917         if (tx_mask || rx_mask)
1918                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1919                         RT5682_TDM_EN, RT5682_TDM_EN);
1920         else
1921                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1922                         RT5682_TDM_EN, 0);
1923
1924         switch (slots) {
1925         case 4:
1926                 val |= RT5682_TDM_TX_CH_4;
1927                 val |= RT5682_TDM_RX_CH_4;
1928                 break;
1929         case 6:
1930                 val |= RT5682_TDM_TX_CH_6;
1931                 val |= RT5682_TDM_RX_CH_6;
1932                 break;
1933         case 8:
1934                 val |= RT5682_TDM_TX_CH_8;
1935                 val |= RT5682_TDM_RX_CH_8;
1936                 break;
1937         case 2:
1938                 break;
1939         default:
1940                 return -EINVAL;
1941         }
1942
1943         snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1944                 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1945
1946         switch (slot_width) {
1947         case 8:
1948                 if (tx_mask || rx_mask)
1949                         return -EINVAL;
1950                 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1951                 break;
1952         case 16:
1953                 val = RT5682_TDM_CL_16;
1954                 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1955                 break;
1956         case 20:
1957                 val = RT5682_TDM_CL_20;
1958                 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1959                 break;
1960         case 24:
1961                 val = RT5682_TDM_CL_24;
1962                 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1963                 break;
1964         case 32:
1965                 val = RT5682_TDM_CL_32;
1966                 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1967                 break;
1968         default:
1969                 return -EINVAL;
1970         }
1971
1972         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1973                 RT5682_TDM_CL_MASK, val);
1974         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1975                 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1976
1977         return 0;
1978 }
1979
1980
1981 static int rt5682_hw_params(struct snd_pcm_substream *substream,
1982         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1983 {
1984         struct snd_soc_component *component = dai->component;
1985         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1986         unsigned int len_1 = 0, len_2 = 0;
1987         int pre_div, frame_size;
1988
1989         rt5682->lrck[dai->id] = params_rate(params);
1990         pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
1991
1992         frame_size = snd_soc_params_to_frame_size(params);
1993         if (frame_size < 0) {
1994                 dev_err(component->dev, "Unsupported frame size: %d\n",
1995                         frame_size);
1996                 return -EINVAL;
1997         }
1998
1999         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2000                                 rt5682->lrck[dai->id], pre_div, dai->id);
2001
2002         switch (params_width(params)) {
2003         case 16:
2004                 break;
2005         case 20:
2006                 len_1 |= RT5682_I2S1_DL_20;
2007                 len_2 |= RT5682_I2S2_DL_20;
2008                 break;
2009         case 24:
2010                 len_1 |= RT5682_I2S1_DL_24;
2011                 len_2 |= RT5682_I2S2_DL_24;
2012                 break;
2013         case 32:
2014                 len_1 |= RT5682_I2S1_DL_32;
2015                 len_2 |= RT5682_I2S2_DL_24;
2016                 break;
2017         case 8:
2018                 len_1 |= RT5682_I2S2_DL_8;
2019                 len_2 |= RT5682_I2S2_DL_8;
2020                 break;
2021         default:
2022                 return -EINVAL;
2023         }
2024
2025         switch (dai->id) {
2026         case RT5682_AIF1:
2027                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2028                         RT5682_I2S1_DL_MASK, len_1);
2029                 if (rt5682->master[RT5682_AIF1]) {
2030                         snd_soc_component_update_bits(component,
2031                                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2032                                 pre_div << RT5682_I2S_M_DIV_SFT);
2033                 }
2034                 if (params_channels(params) == 1) /* mono mode */
2035                         snd_soc_component_update_bits(component,
2036                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2037                                 RT5682_I2S1_MONO_EN);
2038                 else
2039                         snd_soc_component_update_bits(component,
2040                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2041                                 RT5682_I2S1_MONO_DIS);
2042                 break;
2043         case RT5682_AIF2:
2044                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2045                         RT5682_I2S2_DL_MASK, len_2);
2046                 if (rt5682->master[RT5682_AIF2]) {
2047                         snd_soc_component_update_bits(component,
2048                                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2049                                 pre_div << RT5682_I2S2_M_PD_SFT);
2050                 }
2051                 if (params_channels(params) == 1) /* mono mode */
2052                         snd_soc_component_update_bits(component,
2053                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2054                                 RT5682_I2S2_MONO_EN);
2055                 else
2056                         snd_soc_component_update_bits(component,
2057                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2058                                 RT5682_I2S2_MONO_DIS);
2059                 break;
2060         default:
2061                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2062                 return -EINVAL;
2063         }
2064
2065         return 0;
2066 }
2067
2068 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2069 {
2070         struct snd_soc_component *component = dai->component;
2071         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2072         unsigned int reg_val = 0, tdm_ctrl = 0;
2073
2074         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2075         case SND_SOC_DAIFMT_CBM_CFM:
2076                 rt5682->master[dai->id] = 1;
2077                 break;
2078         case SND_SOC_DAIFMT_CBS_CFS:
2079                 rt5682->master[dai->id] = 0;
2080                 break;
2081         default:
2082                 return -EINVAL;
2083         }
2084
2085         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2086         case SND_SOC_DAIFMT_NB_NF:
2087                 break;
2088         case SND_SOC_DAIFMT_IB_NF:
2089                 reg_val |= RT5682_I2S_BP_INV;
2090                 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2091                 break;
2092         case SND_SOC_DAIFMT_NB_IF:
2093                 if (dai->id == RT5682_AIF1)
2094                         tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2095                 else
2096                         return -EINVAL;
2097                 break;
2098         case SND_SOC_DAIFMT_IB_IF:
2099                 if (dai->id == RT5682_AIF1)
2100                         tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2101                                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2102                 else
2103                         return -EINVAL;
2104                 break;
2105         default:
2106                 return -EINVAL;
2107         }
2108
2109         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2110         case SND_SOC_DAIFMT_I2S:
2111                 break;
2112         case SND_SOC_DAIFMT_LEFT_J:
2113                 reg_val |= RT5682_I2S_DF_LEFT;
2114                 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2115                 break;
2116         case SND_SOC_DAIFMT_DSP_A:
2117                 reg_val |= RT5682_I2S_DF_PCM_A;
2118                 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2119                 break;
2120         case SND_SOC_DAIFMT_DSP_B:
2121                 reg_val |= RT5682_I2S_DF_PCM_B;
2122                 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2123                 break;
2124         default:
2125                 return -EINVAL;
2126         }
2127
2128         switch (dai->id) {
2129         case RT5682_AIF1:
2130                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2131                         RT5682_I2S_DF_MASK, reg_val);
2132                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2133                         RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2134                         RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2135                         RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2136                         tdm_ctrl | rt5682->master[dai->id]);
2137                 break;
2138         case RT5682_AIF2:
2139                 if (rt5682->master[dai->id] == 0)
2140                         reg_val |= RT5682_I2S2_MS_S;
2141                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2142                         RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2143                         RT5682_I2S_DF_MASK, reg_val);
2144                 break;
2145         default:
2146                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2147                 return -EINVAL;
2148         }
2149         return 0;
2150 }
2151
2152 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2153                 int clk_id, int source, unsigned int freq, int dir)
2154 {
2155         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2156         unsigned int reg_val = 0, src = 0;
2157
2158         if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2159                 return 0;
2160
2161         switch (clk_id) {
2162         case RT5682_SCLK_S_MCLK:
2163                 reg_val |= RT5682_SCLK_SRC_MCLK;
2164                 src = RT5682_CLK_SRC_MCLK;
2165                 break;
2166         case RT5682_SCLK_S_PLL1:
2167                 reg_val |= RT5682_SCLK_SRC_PLL1;
2168                 src = RT5682_CLK_SRC_PLL1;
2169                 break;
2170         case RT5682_SCLK_S_PLL2:
2171                 reg_val |= RT5682_SCLK_SRC_PLL2;
2172                 src = RT5682_CLK_SRC_PLL2;
2173                 break;
2174         case RT5682_SCLK_S_RCCLK:
2175                 reg_val |= RT5682_SCLK_SRC_RCCLK;
2176                 src = RT5682_CLK_SRC_RCCLK;
2177                 break;
2178         default:
2179                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2180                 return -EINVAL;
2181         }
2182         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2183                 RT5682_SCLK_SRC_MASK, reg_val);
2184
2185         if (rt5682->master[RT5682_AIF2]) {
2186                 snd_soc_component_update_bits(component,
2187                         RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2188                         src << RT5682_I2S2_SRC_SFT);
2189         }
2190
2191         rt5682->sysclk = freq;
2192         rt5682->sysclk_src = clk_id;
2193
2194         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2195                 freq, clk_id);
2196
2197         return 0;
2198 }
2199
2200 static int rt5682_set_component_pll(struct snd_soc_component *component,
2201                 int pll_id, int source, unsigned int freq_in,
2202                 unsigned int freq_out)
2203 {
2204         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2205         struct rl6231_pll_code pll_code;
2206         int ret;
2207
2208         if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2209             freq_out == rt5682->pll_out)
2210                 return 0;
2211
2212         if (!freq_in || !freq_out) {
2213                 dev_dbg(component->dev, "PLL disabled\n");
2214
2215                 rt5682->pll_in = 0;
2216                 rt5682->pll_out = 0;
2217                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2218                         RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2219                 return 0;
2220         }
2221
2222         switch (source) {
2223         case RT5682_PLL1_S_MCLK:
2224                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2225                         RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2226                 break;
2227         case RT5682_PLL1_S_BCLK1:
2228                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2229                                 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2230                 break;
2231         default:
2232                 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2233                 return -EINVAL;
2234         }
2235
2236         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2237         if (ret < 0) {
2238                 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2239                 return ret;
2240         }
2241
2242         dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2243                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2244                 pll_code.n_code, pll_code.k_code);
2245
2246         snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2247                 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2248         snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2249                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2250                 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2251
2252         rt5682->pll_in = freq_in;
2253         rt5682->pll_out = freq_out;
2254         rt5682->pll_src = source;
2255
2256         return 0;
2257 }
2258
2259 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2260 {
2261         struct snd_soc_component *component = dai->component;
2262         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2263
2264         rt5682->bclk[dai->id] = ratio;
2265
2266         switch (ratio) {
2267         case 64:
2268                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2269                         RT5682_I2S2_BCLK_MS2_MASK,
2270                         RT5682_I2S2_BCLK_MS2_64);
2271                 break;
2272         case 32:
2273                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2274                         RT5682_I2S2_BCLK_MS2_MASK,
2275                         RT5682_I2S2_BCLK_MS2_32);
2276                 break;
2277         default:
2278                 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2279                 return -EINVAL;
2280         }
2281
2282         return 0;
2283 }
2284
2285 static int rt5682_set_bias_level(struct snd_soc_component *component,
2286                         enum snd_soc_bias_level level)
2287 {
2288         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2289
2290         switch (level) {
2291         case SND_SOC_BIAS_PREPARE:
2292                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2293                         RT5682_PWR_MB | RT5682_PWR_BG,
2294                         RT5682_PWR_MB | RT5682_PWR_BG);
2295                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2296                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2297                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2298                 break;
2299
2300         case SND_SOC_BIAS_STANDBY:
2301                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2302                         RT5682_PWR_MB, RT5682_PWR_MB);
2303                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2304                         RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2305                 break;
2306         case SND_SOC_BIAS_OFF:
2307                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2308                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2309                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2310                         RT5682_PWR_MB | RT5682_PWR_BG, 0);
2311                 break;
2312
2313         default:
2314                 break;
2315         }
2316
2317         return 0;
2318 }
2319
2320 static int rt5682_probe(struct snd_soc_component *component)
2321 {
2322         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2323
2324         rt5682->component = component;
2325
2326         return 0;
2327 }
2328
2329 static void rt5682_remove(struct snd_soc_component *component)
2330 {
2331         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2332
2333         rt5682_reset(rt5682->regmap);
2334 }
2335
2336 #ifdef CONFIG_PM
2337 static int rt5682_suspend(struct snd_soc_component *component)
2338 {
2339         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2340
2341         regcache_cache_only(rt5682->regmap, true);
2342         regcache_mark_dirty(rt5682->regmap);
2343         return 0;
2344 }
2345
2346 static int rt5682_resume(struct snd_soc_component *component)
2347 {
2348         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2349
2350         regcache_cache_only(rt5682->regmap, false);
2351         regcache_sync(rt5682->regmap);
2352
2353         return 0;
2354 }
2355 #else
2356 #define rt5682_suspend NULL
2357 #define rt5682_resume NULL
2358 #endif
2359
2360 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2361 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2362                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2363
2364 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2365         .hw_params = rt5682_hw_params,
2366         .set_fmt = rt5682_set_dai_fmt,
2367         .set_tdm_slot = rt5682_set_tdm_slot,
2368 };
2369
2370 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2371         .hw_params = rt5682_hw_params,
2372         .set_fmt = rt5682_set_dai_fmt,
2373         .set_bclk_ratio = rt5682_set_bclk_ratio,
2374 };
2375
2376 static struct snd_soc_dai_driver rt5682_dai[] = {
2377         {
2378                 .name = "rt5682-aif1",
2379                 .id = RT5682_AIF1,
2380                 .playback = {
2381                         .stream_name = "AIF1 Playback",
2382                         .channels_min = 1,
2383                         .channels_max = 2,
2384                         .rates = RT5682_STEREO_RATES,
2385                         .formats = RT5682_FORMATS,
2386                 },
2387                 .capture = {
2388                         .stream_name = "AIF1 Capture",
2389                         .channels_min = 1,
2390                         .channels_max = 2,
2391                         .rates = RT5682_STEREO_RATES,
2392                         .formats = RT5682_FORMATS,
2393                 },
2394                 .ops = &rt5682_aif1_dai_ops,
2395         },
2396         {
2397                 .name = "rt5682-aif2",
2398                 .id = RT5682_AIF2,
2399                 .capture = {
2400                         .stream_name = "AIF2 Capture",
2401                         .channels_min = 1,
2402                         .channels_max = 2,
2403                         .rates = RT5682_STEREO_RATES,
2404                         .formats = RT5682_FORMATS,
2405                 },
2406                 .ops = &rt5682_aif2_dai_ops,
2407         },
2408 };
2409
2410 static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2411         .probe = rt5682_probe,
2412         .remove = rt5682_remove,
2413         .suspend = rt5682_suspend,
2414         .resume = rt5682_resume,
2415         .set_bias_level = rt5682_set_bias_level,
2416         .controls = rt5682_snd_controls,
2417         .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2418         .dapm_widgets = rt5682_dapm_widgets,
2419         .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2420         .dapm_routes = rt5682_dapm_routes,
2421         .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2422         .set_sysclk = rt5682_set_component_sysclk,
2423         .set_pll = rt5682_set_component_pll,
2424         .set_jack = rt5682_set_jack_detect,
2425         .use_pmdown_time        = 1,
2426         .endianness             = 1,
2427         .non_legacy_dai_naming  = 1,
2428 };
2429
2430 static const struct regmap_config rt5682_regmap = {
2431         .reg_bits = 16,
2432         .val_bits = 16,
2433         .max_register = RT5682_I2C_MODE,
2434         .volatile_reg = rt5682_volatile_register,
2435         .readable_reg = rt5682_readable_register,
2436         .cache_type = REGCACHE_RBTREE,
2437         .reg_defaults = rt5682_reg,
2438         .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2439         .use_single_rw = true,
2440 };
2441
2442 static const struct i2c_device_id rt5682_i2c_id[] = {
2443         {"rt5682", 0},
2444         {}
2445 };
2446 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2447
2448 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2449 {
2450
2451         device_property_read_u32(dev, "realtek,dmic1-data-pin",
2452                 &rt5682->pdata.dmic1_data_pin);
2453         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2454                 &rt5682->pdata.dmic1_clk_pin);
2455         device_property_read_u32(dev, "realtek,jd-src",
2456                 &rt5682->pdata.jd_src);
2457
2458         rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2459                 "realtek,ldo1-en-gpios", 0);
2460
2461         return 0;
2462 }
2463
2464 static void rt5682_calibrate(struct rt5682_priv *rt5682)
2465 {
2466         int value, count;
2467
2468         mutex_lock(&rt5682->calibrate_mutex);
2469
2470         rt5682_reset(rt5682->regmap);
2471         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2bf);
2472         usleep_range(15000, 20000);
2473         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2bf);
2474         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
2475         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
2476         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
2477         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2478         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2479         regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2480         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2481         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2482         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2483
2484         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2485
2486         for (count = 0; count < 60; count++) {
2487                 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2488                 if (!(value & 0x8000))
2489                         break;
2490
2491                 usleep_range(10000, 10005);
2492         }
2493
2494         if (count >= 60)
2495                 pr_err("HP Calibration Failure\n");
2496
2497         /* restore settings */
2498         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
2499         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2500
2501         mutex_unlock(&rt5682->calibrate_mutex);
2502
2503 }
2504
2505 static int rt5682_i2c_probe(struct i2c_client *i2c,
2506                     const struct i2c_device_id *id)
2507 {
2508         struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2509         struct rt5682_priv *rt5682;
2510         int i, ret;
2511         unsigned int val;
2512
2513         rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2514                 GFP_KERNEL);
2515
2516         if (rt5682 == NULL)
2517                 return -ENOMEM;
2518
2519         i2c_set_clientdata(i2c, rt5682);
2520
2521         if (pdata)
2522                 rt5682->pdata = *pdata;
2523         else
2524                 rt5682_parse_dt(rt5682, &i2c->dev);
2525
2526         rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2527         if (IS_ERR(rt5682->regmap)) {
2528                 ret = PTR_ERR(rt5682->regmap);
2529                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2530                         ret);
2531                 return ret;
2532         }
2533
2534         for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2535                 rt5682->supplies[i].supply = rt5682_supply_names[i];
2536
2537         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2538                                       rt5682->supplies);
2539         if (ret != 0) {
2540                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2541                 return ret;
2542         }
2543
2544         ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2545                                     rt5682->supplies);
2546         if (ret != 0) {
2547                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2548                 return ret;
2549         }
2550
2551         if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2552                 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2553                                           GPIOF_OUT_INIT_HIGH, "rt5682"))
2554                         dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2555         }
2556
2557         /* Sleep for 300 ms miniumum */
2558         usleep_range(300000, 350000);
2559
2560         regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2561         usleep_range(10000, 15000);
2562
2563         regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2564         if (val != DEVICE_ID) {
2565                 pr_err("Device with ID register %x is not rt5682\n", val);
2566                 return -ENODEV;
2567         }
2568
2569         rt5682_reset(rt5682->regmap);
2570
2571         rt5682_calibrate(rt5682);
2572
2573         ret = regmap_register_patch(rt5682->regmap, patch_list,
2574                                     ARRAY_SIZE(patch_list));
2575         if (ret != 0)
2576                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2577
2578         regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2579
2580         /* DMIC pin*/
2581         if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2582                 switch (rt5682->pdata.dmic1_data_pin) {
2583                 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2584                         regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2585                                 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2586                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2587                                 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2588                         break;
2589
2590                 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2591                         regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2592                                 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2593                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2594                                 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2595                         break;
2596
2597                 default:
2598                         dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2599                         break;
2600                 }
2601
2602                 switch (rt5682->pdata.dmic1_clk_pin) {
2603                 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2604                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2605                                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2606                         break;
2607
2608                 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2609                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2610                                 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2611                         break;
2612
2613                 default:
2614                         dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2615                         break;
2616                 }
2617         }
2618
2619         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2620                         RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2621                         RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2622         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2623         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2624                         RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2625                         RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2626         regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2627         regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
2628                         RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
2629         regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
2630                         RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
2631
2632         INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2633                                 rt5682_jack_detect_handler);
2634         INIT_DELAYED_WORK(&rt5682->jd_check_work,
2635                                 rt5682_jd_check_handler);
2636
2637         mutex_init(&rt5682->calibrate_mutex);
2638
2639         if (i2c->irq) {
2640                 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2641                         rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2642                         | IRQF_ONESHOT, "rt5682", rt5682);
2643                 if (ret)
2644                         dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2645
2646         }
2647
2648         return devm_snd_soc_register_component(&i2c->dev,
2649                         &soc_component_dev_rt5682,
2650                         rt5682_dai, ARRAY_SIZE(rt5682_dai));
2651 }
2652
2653 static void rt5682_i2c_shutdown(struct i2c_client *client)
2654 {
2655         struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2656
2657         rt5682_reset(rt5682->regmap);
2658 }
2659
2660 #ifdef CONFIG_OF
2661 static const struct of_device_id rt5682_of_match[] = {
2662         {.compatible = "realtek,rt5682i"},
2663         {},
2664 };
2665 MODULE_DEVICE_TABLE(of, rt5682_of_match);
2666 #endif
2667
2668 #ifdef CONFIG_ACPI
2669 static const struct acpi_device_id rt5682_acpi_match[] = {
2670         {"10EC5682", 0,},
2671         {},
2672 };
2673 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2674 #endif
2675
2676 static struct i2c_driver rt5682_i2c_driver = {
2677         .driver = {
2678                 .name = "rt5682",
2679                 .of_match_table = of_match_ptr(rt5682_of_match),
2680                 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2681         },
2682         .probe = rt5682_i2c_probe,
2683         .shutdown = rt5682_i2c_shutdown,
2684         .id_table = rt5682_i2c_id,
2685 };
2686 module_i2c_driver(rt5682_i2c_driver);
2687
2688 MODULE_DESCRIPTION("ASoC RT5682 driver");
2689 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2690 MODULE_LICENSE("GPL v2");