sound/soc/codecs/wm_adsp.c

   1 /*
   2  * wm_adsp.c  --  Wolfson ADSP support
   3  *
   4  * Copyright 2012 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/firmware.h>
  18 #include <linux/list.h>
  19 #include <linux/pm.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/workqueue.h>
  26 #include <linux/debugfs.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/jack.h>
  32 #include <sound/initval.h>
  33 #include <sound/tlv.h>
  34
  35 #include "wm_adsp.h"
  36
  37 #define adsp_crit(_dsp, fmt, ...) \
  38         dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  39 #define adsp_err(_dsp, fmt, ...) \
  40         dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  41 #define adsp_warn(_dsp, fmt, ...) \
  42         dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  43 #define adsp_info(_dsp, fmt, ...) \
  44         dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  45 #define adsp_dbg(_dsp, fmt, ...) \
  46         dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  47
  48 #define ADSP1_CONTROL_1                   0x00
  49 #define ADSP1_CONTROL_2                   0x02
  50 #define ADSP1_CONTROL_3                   0x03
  51 #define ADSP1_CONTROL_4                   0x04
  52 #define ADSP1_CONTROL_5                   0x06
  53 #define ADSP1_CONTROL_6                   0x07
  54 #define ADSP1_CONTROL_7                   0x08
  55 #define ADSP1_CONTROL_8                   0x09
  56 #define ADSP1_CONTROL_9                   0x0A
  57 #define ADSP1_CONTROL_10                  0x0B
  58 #define ADSP1_CONTROL_11                  0x0C
  59 #define ADSP1_CONTROL_12                  0x0D
  60 #define ADSP1_CONTROL_13                  0x0F
  61 #define ADSP1_CONTROL_14                  0x10
  62 #define ADSP1_CONTROL_15                  0x11
  63 #define ADSP1_CONTROL_16                  0x12
  64 #define ADSP1_CONTROL_17                  0x13
  65 #define ADSP1_CONTROL_18                  0x14
  66 #define ADSP1_CONTROL_19                  0x16
  67 #define ADSP1_CONTROL_20                  0x17
  68 #define ADSP1_CONTROL_21                  0x18
  69 #define ADSP1_CONTROL_22                  0x1A
  70 #define ADSP1_CONTROL_23                  0x1B
  71 #define ADSP1_CONTROL_24                  0x1C
  72 #define ADSP1_CONTROL_25                  0x1E
  73 #define ADSP1_CONTROL_26                  0x20
  74 #define ADSP1_CONTROL_27                  0x21
  75 #define ADSP1_CONTROL_28                  0x22
  76 #define ADSP1_CONTROL_29                  0x23
  77 #define ADSP1_CONTROL_30                  0x24
  78 #define ADSP1_CONTROL_31                  0x26
  79
  80 /*
  81  * ADSP1 Control 19
  82  */
  83 #define ADSP1_WDMA_BUFFER_LENGTH_MASK     0x00FF  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  84 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT         0  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  85 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH         8  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  86
  87
  88 /*
  89  * ADSP1 Control 30
  90  */
  91 #define ADSP1_DBG_CLK_ENA                 0x0008  /* DSP1_DBG_CLK_ENA */
  92 #define ADSP1_DBG_CLK_ENA_MASK            0x0008  /* DSP1_DBG_CLK_ENA */
  93 #define ADSP1_DBG_CLK_ENA_SHIFT                3  /* DSP1_DBG_CLK_ENA */
  94 #define ADSP1_DBG_CLK_ENA_WIDTH                1  /* DSP1_DBG_CLK_ENA */
  95 #define ADSP1_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */
  96 #define ADSP1_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */
  97 #define ADSP1_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */
  98 #define ADSP1_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
  99 #define ADSP1_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */
 100 #define ADSP1_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */
 101 #define ADSP1_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
 102 #define ADSP1_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
 103 #define ADSP1_START                       0x0001  /* DSP1_START */
 104 #define ADSP1_START_MASK                  0x0001  /* DSP1_START */
 105 #define ADSP1_START_SHIFT                      0  /* DSP1_START */
 106 #define ADSP1_START_WIDTH                      1  /* DSP1_START */
 107
 108 /*
 109  * ADSP1 Control 31
 110  */
 111 #define ADSP1_CLK_SEL_MASK                0x0007  /* CLK_SEL_ENA */
 112 #define ADSP1_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
 113 #define ADSP1_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
 114
 115 #define ADSP2_CONTROL                     0x0
 116 #define ADSP2_CLOCKING                    0x1
 117 #define ADSP2V2_CLOCKING                  0x2
 118 #define ADSP2_STATUS1                     0x4
 119 #define ADSP2_WDMA_CONFIG_1               0x30
 120 #define ADSP2_WDMA_CONFIG_2               0x31
 121 #define ADSP2V2_WDMA_CONFIG_2             0x32
 122 #define ADSP2_RDMA_CONFIG_1               0x34
 123
 124 #define ADSP2_SCRATCH0                    0x40
 125 #define ADSP2_SCRATCH1                    0x41
 126 #define ADSP2_SCRATCH2                    0x42
 127 #define ADSP2_SCRATCH3                    0x43
 128
 129 #define ADSP2V2_SCRATCH0_1                0x40
 130 #define ADSP2V2_SCRATCH2_3                0x42
 131
 132 /*
 133  * ADSP2 Control
 134  */
 135
 136 #define ADSP2_MEM_ENA                     0x0010  /* DSP1_MEM_ENA */
 137 #define ADSP2_MEM_ENA_MASK                0x0010  /* DSP1_MEM_ENA */
 138 #define ADSP2_MEM_ENA_SHIFT                    4  /* DSP1_MEM_ENA */
 139 #define ADSP2_MEM_ENA_WIDTH                    1  /* DSP1_MEM_ENA */
 140 #define ADSP2_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */
 141 #define ADSP2_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */
 142 #define ADSP2_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */
 143 #define ADSP2_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
 144 #define ADSP2_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */
 145 #define ADSP2_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */
 146 #define ADSP2_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
 147 #define ADSP2_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
 148 #define ADSP2_START                       0x0001  /* DSP1_START */
 149 #define ADSP2_START_MASK                  0x0001  /* DSP1_START */
 150 #define ADSP2_START_SHIFT                      0  /* DSP1_START */
 151 #define ADSP2_START_WIDTH                      1  /* DSP1_START */
 152
 153 /*
 154  * ADSP2 clocking
 155  */
 156 #define ADSP2_CLK_SEL_MASK                0x0007  /* CLK_SEL_ENA */
 157 #define ADSP2_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
 158 #define ADSP2_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
 159
 160 /*
 161  * ADSP2V2 clocking
 162  */
 163 #define ADSP2V2_CLK_SEL_MASK             0x70000  /* CLK_SEL_ENA */
 164 #define ADSP2V2_CLK_SEL_SHIFT                 16  /* CLK_SEL_ENA */
 165 #define ADSP2V2_CLK_SEL_WIDTH                  3  /* CLK_SEL_ENA */
 166
 167 #define ADSP2V2_RATE_MASK                 0x7800  /* DSP_RATE */
 168 #define ADSP2V2_RATE_SHIFT                    11  /* DSP_RATE */
 169 #define ADSP2V2_RATE_WIDTH                     4  /* DSP_RATE */
 170
 171 /*
 172  * ADSP2 Status 1
 173  */
 174 #define ADSP2_RAM_RDY                     0x0001
 175 #define ADSP2_RAM_RDY_MASK                0x0001
 176 #define ADSP2_RAM_RDY_SHIFT                    0
 177 #define ADSP2_RAM_RDY_WIDTH                    1
 178
 179 /*
 180  * ADSP2 Lock support
 181  */
 182 #define ADSP2_LOCK_CODE_0                    0x5555
 183 #define ADSP2_LOCK_CODE_1                    0xAAAA
 184
 185 #define ADSP2_WATCHDOG                       0x0A
 186 #define ADSP2_BUS_ERR_ADDR                   0x52
 187 #define ADSP2_REGION_LOCK_STATUS             0x64
 188 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0    0x66
 189 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2    0x68
 190 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4    0x6A
 191 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6    0x6C
 192 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8    0x6E
 193 #define ADSP2_LOCK_REGION_CTRL               0x7A
 194 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR    0x7C
 195
 196 #define ADSP2_REGION_LOCK_ERR_MASK           0x8000
 197 #define ADSP2_SLAVE_ERR_MASK                 0x4000
 198 #define ADSP2_WDT_TIMEOUT_STS_MASK           0x2000
 199 #define ADSP2_CTRL_ERR_PAUSE_ENA             0x0002
 200 #define ADSP2_CTRL_ERR_EINT                  0x0001
 201
 202 #define ADSP2_BUS_ERR_ADDR_MASK              0x00FFFFFF
 203 #define ADSP2_XMEM_ERR_ADDR_MASK             0x0000FFFF
 204 #define ADSP2_PMEM_ERR_ADDR_MASK             0x7FFF0000
 205 #define ADSP2_PMEM_ERR_ADDR_SHIFT            16
 206 #define ADSP2_WDT_ENA_MASK                   0xFFFFFFFD
 207
 208 #define ADSP2_LOCK_REGION_SHIFT              16
 209
 210 #define ADSP_MAX_STD_CTRL_SIZE               512
 211
 212 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS         100
 213 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS       10
 214 #define WM_ADSP_ACKED_CTL_MIN_VALUE          0
 215 #define WM_ADSP_ACKED_CTL_MAX_VALUE          0xFFFFFF
 216
 217 /*
 218  * Event control messages
 219  */
 220 #define WM_ADSP_FW_EVENT_SHUTDOWN            0x000001
 221
 222 struct wm_adsp_buf {
 223         struct list_head list;
 224         void *buf;
 225 };
 226
 227 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
 228                                              struct list_head *list)
 229 {
 230         struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
 231
 232         if (buf == NULL)
 233                 return NULL;
 234
 235         buf->buf = vmalloc(len);
 236         if (!buf->buf) {
 237                 kfree(buf);
 238                 return NULL;
 239         }
 240         memcpy(buf->buf, src, len);
 241
 242         if (list)
 243                 list_add_tail(&buf->list, list);
 244
 245         return buf;
 246 }
 247
 248 static void wm_adsp_buf_free(struct list_head *list)
 249 {
 250         while (!list_empty(list)) {
 251                 struct wm_adsp_buf *buf = list_first_entry(list,
 252                                                            struct wm_adsp_buf,
 253                                                            list);
 254                 list_del(&buf->list);
 255                 vfree(buf->buf);
 256                 kfree(buf);
 257         }
 258 }
 259
 260 #define WM_ADSP_FW_MBC_VSS  0
 261 #define WM_ADSP_FW_HIFI     1
 262 #define WM_ADSP_FW_TX       2
 263 #define WM_ADSP_FW_TX_SPK   3
 264 #define WM_ADSP_FW_RX       4
 265 #define WM_ADSP_FW_RX_ANC   5
 266 #define WM_ADSP_FW_CTRL     6
 267 #define WM_ADSP_FW_ASR      7
 268 #define WM_ADSP_FW_TRACE    8
 269 #define WM_ADSP_FW_SPK_PROT 9
 270 #define WM_ADSP_FW_MISC     10
 271
 272 #define WM_ADSP_NUM_FW      11
 273
 274 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
 275         [WM_ADSP_FW_MBC_VSS] =  "MBC/VSS",
 276         [WM_ADSP_FW_HIFI] =     "MasterHiFi",
 277         [WM_ADSP_FW_TX] =       "Tx",
 278         [WM_ADSP_FW_TX_SPK] =   "Tx Speaker",
 279         [WM_ADSP_FW_RX] =       "Rx",
 280         [WM_ADSP_FW_RX_ANC] =   "Rx ANC",
 281         [WM_ADSP_FW_CTRL] =     "Voice Ctrl",
 282         [WM_ADSP_FW_ASR] =      "ASR Assist",
 283         [WM_ADSP_FW_TRACE] =    "Dbg Trace",
 284         [WM_ADSP_FW_SPK_PROT] = "Protection",
 285         [WM_ADSP_FW_MISC] =     "Misc",
 286 };
 287
 288 struct wm_adsp_system_config_xm_hdr {
 289         __be32 sys_enable;
 290         __be32 fw_id;
 291         __be32 fw_rev;
 292         __be32 boot_status;
 293         __be32 watchdog;
 294         __be32 dma_buffer_size;
 295         __be32 rdma[6];
 296         __be32 wdma[8];
 297         __be32 build_job_name[3];
 298         __be32 build_job_number;
 299 };
 300
 301 struct wm_adsp_alg_xm_struct {
 302         __be32 magic;
 303         __be32 smoothing;
 304         __be32 threshold;
 305         __be32 host_buf_ptr;
 306         __be32 start_seq;
 307         __be32 high_water_mark;
 308         __be32 low_water_mark;
 309         __be64 smoothed_power;
 310 };
 311
 312 struct wm_adsp_buffer {
 313         __be32 X_buf_base;              /* XM base addr of first X area */
 314         __be32 X_buf_size;              /* Size of 1st X area in words */
 315         __be32 X_buf_base2;             /* XM base addr of 2nd X area */
 316         __be32 X_buf_brk;               /* Total X size in words */
 317         __be32 Y_buf_base;              /* YM base addr of Y area */
 318         __be32 wrap;                    /* Total size X and Y in words */
 319         __be32 high_water_mark;         /* Point at which IRQ is asserted */
 320         __be32 irq_count;               /* bits 1-31 count IRQ assertions */
 321         __be32 irq_ack;                 /* acked IRQ count, bit 0 enables IRQ */
 322         __be32 next_write_index;        /* word index of next write */
 323         __be32 next_read_index;         /* word index of next read */
 324         __be32 error;                   /* error if any */
 325         __be32 oldest_block_index;      /* word index of oldest surviving */
 326         __be32 requested_rewind;        /* how many blocks rewind was done */
 327         __be32 reserved_space;          /* internal */
 328         __be32 min_free;                /* min free space since stream start */
 329         __be32 blocks_written[2];       /* total blocks written (64 bit) */
 330         __be32 words_written[2];        /* total words written (64 bit) */
 331 };
 332
 333 struct wm_adsp_compr;
 334
 335 struct wm_adsp_compr_buf {
 336         struct wm_adsp *dsp;
 337         struct wm_adsp_compr *compr;
 338
 339         struct wm_adsp_buffer_region *regions;
 340         u32 host_buf_ptr;
 341
 342         u32 error;
 343         u32 irq_count;
 344         int read_index;
 345         int avail;
 346 };
 347
 348 struct wm_adsp_compr {
 349         struct wm_adsp *dsp;
 350         struct wm_adsp_compr_buf *buf;
 351
 352         struct snd_compr_stream *stream;
 353         struct snd_compressed_buffer size;
 354
 355         u32 *raw_buf;
 356         unsigned int copied_total;
 357
 358         unsigned int sample_rate;
 359 };
 360
 361 #define WM_ADSP_DATA_WORD_SIZE         3
 362
 363 #define WM_ADSP_MIN_FRAGMENTS          1
 364 #define WM_ADSP_MAX_FRAGMENTS          256
 365 #define WM_ADSP_MIN_FRAGMENT_SIZE      (64 * WM_ADSP_DATA_WORD_SIZE)
 366 #define WM_ADSP_MAX_FRAGMENT_SIZE      (4096 * WM_ADSP_DATA_WORD_SIZE)
 367
 368 #define WM_ADSP_ALG_XM_STRUCT_MAGIC    0x49aec7
 369
 370 #define HOST_BUFFER_FIELD(field) \
 371         (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
 372
 373 #define ALG_XM_FIELD(field) \
 374         (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
 375
 376 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
 377 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
 378
 379 struct wm_adsp_buffer_region {
 380         unsigned int offset;
 381         unsigned int cumulative_size;
 382         unsigned int mem_type;
 383         unsigned int base_addr;
 384 };
 385
 386 struct wm_adsp_buffer_region_def {
 387         unsigned int mem_type;
 388         unsigned int base_offset;
 389         unsigned int size_offset;
 390 };
 391
 392 static const struct wm_adsp_buffer_region_def default_regions[] = {
 393         {
 394                 .mem_type = WMFW_ADSP2_XM,
 395                 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
 396                 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
 397         },
 398         {
 399                 .mem_type = WMFW_ADSP2_XM,
 400                 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
 401                 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
 402         },
 403         {
 404                 .mem_type = WMFW_ADSP2_YM,
 405                 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
 406                 .size_offset = HOST_BUFFER_FIELD(wrap),
 407         },
 408 };
 409
 410 struct wm_adsp_fw_caps {
 411         u32 id;
 412         struct snd_codec_desc desc;
 413         int num_regions;
 414         const struct wm_adsp_buffer_region_def *region_defs;
 415 };
 416
 417 static const struct wm_adsp_fw_caps ctrl_caps[] = {
 418         {
 419                 .id = SND_AUDIOCODEC_BESPOKE,
 420                 .desc = {
 421                         .max_ch = 8,
 422                         .sample_rates = { 16000 },
 423                         .num_sample_rates = 1,
 424                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 425                 },
 426                 .num_regions = ARRAY_SIZE(default_regions),
 427                 .region_defs = default_regions,
 428         },
 429 };
 430
 431 static const struct wm_adsp_fw_caps trace_caps[] = {
 432         {
 433                 .id = SND_AUDIOCODEC_BESPOKE,
 434                 .desc = {
 435                         .max_ch = 8,
 436                         .sample_rates = {
 437                                 4000, 8000, 11025, 12000, 16000, 22050,
 438                                 24000, 32000, 44100, 48000, 64000, 88200,
 439                                 96000, 176400, 192000
 440                         },
 441                         .num_sample_rates = 15,
 442                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 443                 },
 444                 .num_regions = ARRAY_SIZE(default_regions),
 445                 .region_defs = default_regions,
 446         },
 447 };
 448
 449 static const struct {
 450         const char *file;
 451         int compr_direction;
 452         int num_caps;
 453         const struct wm_adsp_fw_caps *caps;
 454         bool voice_trigger;
 455 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
 456         [WM_ADSP_FW_MBC_VSS] =  { .file = "mbc-vss" },
 457         [WM_ADSP_FW_HIFI] =     { .file = "hifi" },
 458         [WM_ADSP_FW_TX] =       { .file = "tx" },
 459         [WM_ADSP_FW_TX_SPK] =   { .file = "tx-spk" },
 460         [WM_ADSP_FW_RX] =       { .file = "rx" },
 461         [WM_ADSP_FW_RX_ANC] =   { .file = "rx-anc" },
 462         [WM_ADSP_FW_CTRL] =     {
 463                 .file = "ctrl",
 464                 .compr_direction = SND_COMPRESS_CAPTURE,
 465                 .num_caps = ARRAY_SIZE(ctrl_caps),
 466                 .caps = ctrl_caps,
 467                 .voice_trigger = true,
 468         },
 469         [WM_ADSP_FW_ASR] =      { .file = "asr" },
 470         [WM_ADSP_FW_TRACE] =    {
 471                 .file = "trace",
 472                 .compr_direction = SND_COMPRESS_CAPTURE,
 473                 .num_caps = ARRAY_SIZE(trace_caps),
 474                 .caps = trace_caps,
 475         },
 476         [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
 477         [WM_ADSP_FW_MISC] =     { .file = "misc" },
 478 };
 479
 480 struct wm_coeff_ctl_ops {
 481         int (*xget)(struct snd_kcontrol *kcontrol,
 482                     struct snd_ctl_elem_value *ucontrol);
 483         int (*xput)(struct snd_kcontrol *kcontrol,
 484                     struct snd_ctl_elem_value *ucontrol);
 485 };
 486
 487 struct wm_coeff_ctl {
 488         const char *name;
 489         const char *fw_name;
 490         struct wm_adsp_alg_region alg_region;
 491         struct wm_coeff_ctl_ops ops;
 492         struct wm_adsp *dsp;
 493         unsigned int enabled:1;
 494         struct list_head list;
 495         void *cache;
 496         unsigned int offset;
 497         size_t len;
 498         unsigned int set:1;
 499         struct soc_bytes_ext bytes_ext;
 500         unsigned int flags;
 501         unsigned int type;
 502 };
 503
 504 static const char *wm_adsp_mem_region_name(unsigned int type)
 505 {
 506         switch (type) {
 507         case WMFW_ADSP1_PM:
 508                 return "PM";
 509         case WMFW_ADSP1_DM:
 510                 return "DM";
 511         case WMFW_ADSP2_XM:
 512                 return "XM";
 513         case WMFW_ADSP2_YM:
 514                 return "YM";
 515         case WMFW_ADSP1_ZM:
 516                 return "ZM";
 517         default:
 518                 return NULL;
 519         }
 520 }
 521
 522 #ifdef CONFIG_DEBUG_FS
 523 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
 524 {
 525         char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
 526
 527         kfree(dsp->wmfw_file_name);
 528         dsp->wmfw_file_name = tmp;
 529 }
 530
 531 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
 532 {
 533         char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
 534
 535         kfree(dsp->bin_file_name);
 536         dsp->bin_file_name = tmp;
 537 }
 538
 539 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
 540 {
 541         kfree(dsp->wmfw_file_name);
 542         kfree(dsp->bin_file_name);
 543         dsp->wmfw_file_name = NULL;
 544         dsp->bin_file_name = NULL;
 545 }
 546
 547 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
 548                                          char __user *user_buf,
 549                                          size_t count, loff_t *ppos)
 550 {
 551         struct wm_adsp *dsp = file->private_data;
 552         ssize_t ret;
 553
 554         mutex_lock(&dsp->pwr_lock);
 555
 556         if (!dsp->wmfw_file_name || !dsp->booted)
 557                 ret = 0;
 558         else
 559                 ret = simple_read_from_buffer(user_buf, count, ppos,
 560                                               dsp->wmfw_file_name,
 561                                               strlen(dsp->wmfw_file_name));
 562
 563         mutex_unlock(&dsp->pwr_lock);
 564         return ret;
 565 }
 566
 567 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
 568                                         char __user *user_buf,
 569                                         size_t count, loff_t *ppos)
 570 {
 571         struct wm_adsp *dsp = file->private_data;
 572         ssize_t ret;
 573
 574         mutex_lock(&dsp->pwr_lock);
 575
 576         if (!dsp->bin_file_name || !dsp->booted)
 577                 ret = 0;
 578         else
 579                 ret = simple_read_from_buffer(user_buf, count, ppos,
 580                                               dsp->bin_file_name,
 581                                               strlen(dsp->bin_file_name));
 582
 583         mutex_unlock(&dsp->pwr_lock);
 584         return ret;
 585 }
 586
 587 static const struct {
 588         const char *name;
 589         const struct file_operations fops;
 590 } wm_adsp_debugfs_fops[] = {
 591         {
 592                 .name = "wmfw_file_name",
 593                 .fops = {
 594                         .open = simple_open,
 595                         .read = wm_adsp_debugfs_wmfw_read,
 596                 },
 597         },
 598         {
 599                 .name = "bin_file_name",
 600                 .fops = {
 601                         .open = simple_open,
 602                         .read = wm_adsp_debugfs_bin_read,
 603                 },
 604         },
 605 };
 606
 607 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
 608                                   struct snd_soc_component *component)
 609 {
 610         struct dentry *root = NULL;
 611         char *root_name;
 612         int i;
 613
 614         if (!component->debugfs_root) {
 615                 adsp_err(dsp, "No codec debugfs root\n");
 616                 goto err;
 617         }
 618
 619         root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
 620         if (!root_name)
 621                 goto err;
 622
 623         snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
 624         root = debugfs_create_dir(root_name, component->debugfs_root);
 625         kfree(root_name);
 626
 627         if (!root)
 628                 goto err;
 629
 630         if (!debugfs_create_bool("booted", 0444, root, &dsp->booted))
 631                 goto err;
 632
 633         if (!debugfs_create_bool("running", 0444, root, &dsp->running))
 634                 goto err;
 635
 636         if (!debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id))
 637                 goto err;
 638
 639         if (!debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version))
 640                 goto err;
 641
 642         for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
 643                 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
 644                                          0444, root, dsp,
 645                                          &wm_adsp_debugfs_fops[i].fops))
 646                         goto err;
 647         }
 648
 649         dsp->debugfs_root = root;
 650         return;
 651
 652 err:
 653         debugfs_remove_recursive(root);
 654         adsp_err(dsp, "Failed to create debugfs\n");
 655 }
 656
 657 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
 658 {
 659         wm_adsp_debugfs_clear(dsp);
 660         debugfs_remove_recursive(dsp->debugfs_root);
 661 }
 662 #else
 663 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
 664                                          struct snd_soc_component *component)
 665 {
 666 }
 667
 668 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
 669 {
 670 }
 671
 672 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
 673                                                  const char *s)
 674 {
 675 }
 676
 677 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
 678                                                 const char *s)
 679 {
 680 }
 681
 682 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
 683 {
 684 }
 685 #endif
 686
 687 int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
 688                    struct snd_ctl_elem_value *ucontrol)
 689 {
 690         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 691         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 692         struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
 693
 694         ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
 695
 696         return 0;
 697 }
 698 EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
 699
 700 int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
 701                    struct snd_ctl_elem_value *ucontrol)
 702 {
 703         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 704         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 705         struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
 706         int ret = 0;
 707
 708         if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
 709                 return 0;
 710
 711         if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
 712                 return -EINVAL;
 713
 714         mutex_lock(&dsp[e->shift_l].pwr_lock);
 715
 716         if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
 717                 ret = -EBUSY;
 718         else
 719                 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
 720
 721         mutex_unlock(&dsp[e->shift_l].pwr_lock);
 722
 723         return ret;
 724 }
 725 EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
 726
 727 const struct soc_enum wm_adsp_fw_enum[] = {
 728         SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 729         SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 730         SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 731         SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 732         SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 733         SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 734         SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 735 };
 736 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
 737
 738 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
 739                                                         int type)
 740 {
 741         int i;
 742
 743         for (i = 0; i < dsp->num_mems; i++)
 744                 if (dsp->mem[i].type == type)
 745                         return &dsp->mem[i];
 746
 747         return NULL;
 748 }
 749
 750 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
 751                                           unsigned int offset)
 752 {
 753         if (WARN_ON(!mem))
 754                 return offset;
 755         switch (mem->type) {
 756         case WMFW_ADSP1_PM:
 757                 return mem->base + (offset * 3);
 758         case WMFW_ADSP1_DM:
 759                 return mem->base + (offset * 2);
 760         case WMFW_ADSP2_XM:
 761                 return mem->base + (offset * 2);
 762         case WMFW_ADSP2_YM:
 763                 return mem->base + (offset * 2);
 764         case WMFW_ADSP1_ZM:
 765                 return mem->base + (offset * 2);
 766         default:
 767                 WARN(1, "Unknown memory region type");
 768                 return offset;
 769         }
 770 }
 771
 772 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
 773 {
 774         u16 scratch[4];
 775         int ret;
 776
 777         ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
 778                                 scratch, sizeof(scratch));
 779         if (ret) {
 780                 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
 781                 return;
 782         }
 783
 784         adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
 785                  be16_to_cpu(scratch[0]),
 786                  be16_to_cpu(scratch[1]),
 787                  be16_to_cpu(scratch[2]),
 788                  be16_to_cpu(scratch[3]));
 789 }
 790
 791 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
 792 {
 793         u32 scratch[2];
 794         int ret;
 795
 796         ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1,
 797                               scratch, sizeof(scratch));
 798
 799         if (ret) {
 800                 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
 801                 return;
 802         }
 803
 804         scratch[0] = be32_to_cpu(scratch[0]);
 805         scratch[1] = be32_to_cpu(scratch[1]);
 806
 807         adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
 808                  scratch[0] & 0xFFFF,
 809                  scratch[0] >> 16,
 810                  scratch[1] & 0xFFFF,
 811                  scratch[1] >> 16);
 812 }
 813
 814 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
 815 {
 816         return container_of(ext, struct wm_coeff_ctl, bytes_ext);
 817 }
 818
 819 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
 820 {
 821         const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
 822         struct wm_adsp *dsp = ctl->dsp;
 823         const struct wm_adsp_region *mem;
 824
 825         mem = wm_adsp_find_region(dsp, alg_region->type);
 826         if (!mem) {
 827                 adsp_err(dsp, "No base for region %x\n",
 828                          alg_region->type);
 829                 return -EINVAL;
 830         }
 831
 832         *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset);
 833
 834         return 0;
 835 }
 836
 837 static int wm_coeff_info(struct snd_kcontrol *kctl,
 838                          struct snd_ctl_elem_info *uinfo)
 839 {
 840         struct soc_bytes_ext *bytes_ext =
 841                 (struct soc_bytes_ext *)kctl->private_value;
 842         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
 843
 844         switch (ctl->type) {
 845         case WMFW_CTL_TYPE_ACKED:
 846                 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 847                 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
 848                 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
 849                 uinfo->value.integer.step = 1;
 850                 uinfo->count = 1;
 851                 break;
 852         default:
 853                 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 854                 uinfo->count = ctl->len;
 855                 break;
 856         }
 857
 858         return 0;
 859 }
 860
 861 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
 862                                         unsigned int event_id)
 863 {
 864         struct wm_adsp *dsp = ctl->dsp;
 865         u32 val = cpu_to_be32(event_id);
 866         unsigned int reg;
 867         int i, ret;
 868
 869         ret = wm_coeff_base_reg(ctl, &reg);
 870         if (ret)
 871                 return ret;
 872
 873         adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
 874                  event_id, ctl->alg_region.alg,
 875                  wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
 876
 877         ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
 878         if (ret) {
 879                 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
 880                 return ret;
 881         }
 882
 883         /*
 884          * Poll for ack, we initially poll at ~1ms intervals for firmwares
 885          * that respond quickly, then go to ~10ms polls. A firmware is unlikely
 886          * to ack instantly so we do the first 1ms delay before reading the
 887          * control to avoid a pointless bus transaction
 888          */
 889         for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
 890                 switch (i) {
 891                 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
 892                         usleep_range(1000, 2000);
 893                         i++;
 894                         break;
 895                 default:
 896                         usleep_range(10000, 20000);
 897                         i += 10;
 898                         break;
 899                 }
 900
 901                 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
 902                 if (ret) {
 903                         adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
 904                         return ret;
 905                 }
 906
 907                 if (val == 0) {
 908                         adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
 909                         return 0;
 910                 }
 911         }
 912
 913         adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
 914                   reg, ctl->alg_region.alg,
 915                   wm_adsp_mem_region_name(ctl->alg_region.type),
 916                   ctl->offset);
 917
 918         return -ETIMEDOUT;
 919 }
 920
 921 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
 922                                   const void *buf, size_t len)
 923 {
 924         struct wm_adsp *dsp = ctl->dsp;
 925         void *scratch;
 926         int ret;
 927         unsigned int reg;
 928
 929         ret = wm_coeff_base_reg(ctl, &reg);
 930         if (ret)
 931                 return ret;
 932
 933         scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
 934         if (!scratch)
 935                 return -ENOMEM;
 936
 937         ret = regmap_raw_write(dsp->regmap, reg, scratch,
 938                                len);
 939         if (ret) {
 940                 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
 941                          len, reg, ret);
 942                 kfree(scratch);
 943                 return ret;
 944         }
 945         adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
 946
 947         kfree(scratch);
 948
 949         return 0;
 950 }
 951
 952 static int wm_coeff_put(struct snd_kcontrol *kctl,
 953                         struct snd_ctl_elem_value *ucontrol)
 954 {
 955         struct soc_bytes_ext *bytes_ext =
 956                 (struct soc_bytes_ext *)kctl->private_value;
 957         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
 958         char *p = ucontrol->value.bytes.data;
 959         int ret = 0;
 960
 961         mutex_lock(&ctl->dsp->pwr_lock);
 962
 963         if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
 964                 ret = -EPERM;
 965         else
 966                 memcpy(ctl->cache, p, ctl->len);
 967
 968         ctl->set = 1;
 969         if (ctl->enabled && ctl->dsp->running)
 970                 ret = wm_coeff_write_control(ctl, p, ctl->len);
 971
 972         mutex_unlock(&ctl->dsp->pwr_lock);
 973
 974         return ret;
 975 }
 976
 977 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
 978                             const unsigned int __user *bytes, unsigned int size)
 979 {
 980         struct soc_bytes_ext *bytes_ext =
 981                 (struct soc_bytes_ext *)kctl->private_value;
 982         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
 983         int ret = 0;
 984
 985         mutex_lock(&ctl->dsp->pwr_lock);
 986
 987         if (copy_from_user(ctl->cache, bytes, size)) {
 988                 ret = -EFAULT;
 989         } else {
 990                 ctl->set = 1;
 991                 if (ctl->enabled && ctl->dsp->running)
 992                         ret = wm_coeff_write_control(ctl, ctl->cache, size);
 993                 else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
 994                         ret = -EPERM;
 995         }
 996
 997         mutex_unlock(&ctl->dsp->pwr_lock);
 998
 999         return ret;
1000 }
1001
1002 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1003                               struct snd_ctl_elem_value *ucontrol)
1004 {
1005         struct soc_bytes_ext *bytes_ext =
1006                 (struct soc_bytes_ext *)kctl->private_value;
1007         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1008         unsigned int val = ucontrol->value.integer.value[0];
1009         int ret;
1010
1011         if (val == 0)
1012                 return 0;       /* 0 means no event */
1013
1014         mutex_lock(&ctl->dsp->pwr_lock);
1015
1016         if (ctl->enabled && ctl->dsp->running)
1017                 ret = wm_coeff_write_acked_control(ctl, val);
1018         else
1019                 ret = -EPERM;
1020
1021         mutex_unlock(&ctl->dsp->pwr_lock);
1022
1023         return ret;
1024 }
1025
1026 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
1027                                  void *buf, size_t len)
1028 {
1029         struct wm_adsp *dsp = ctl->dsp;
1030         void *scratch;
1031         int ret;
1032         unsigned int reg;
1033
1034         ret = wm_coeff_base_reg(ctl, &reg);
1035         if (ret)
1036                 return ret;
1037
1038         scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1039         if (!scratch)
1040                 return -ENOMEM;
1041
1042         ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1043         if (ret) {
1044                 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1045                          len, reg, ret);
1046                 kfree(scratch);
1047                 return ret;
1048         }
1049         adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1050
1051         memcpy(buf, scratch, len);
1052         kfree(scratch);
1053
1054         return 0;
1055 }
1056
1057 static int wm_coeff_get(struct snd_kcontrol *kctl,
1058                         struct snd_ctl_elem_value *ucontrol)
1059 {
1060         struct soc_bytes_ext *bytes_ext =
1061                 (struct soc_bytes_ext *)kctl->private_value;
1062         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1063         char *p = ucontrol->value.bytes.data;
1064         int ret = 0;
1065
1066         mutex_lock(&ctl->dsp->pwr_lock);
1067
1068         if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1069                 if (ctl->enabled && ctl->dsp->running)
1070                         ret = wm_coeff_read_control(ctl, p, ctl->len);
1071                 else
1072                         ret = -EPERM;
1073         } else {
1074                 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1075                         ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1076
1077                 memcpy(p, ctl->cache, ctl->len);
1078         }
1079
1080         mutex_unlock(&ctl->dsp->pwr_lock);
1081
1082         return ret;
1083 }
1084
1085 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1086                             unsigned int __user *bytes, unsigned int size)
1087 {
1088         struct soc_bytes_ext *bytes_ext =
1089                 (struct soc_bytes_ext *)kctl->private_value;
1090         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1091         int ret = 0;
1092
1093         mutex_lock(&ctl->dsp->pwr_lock);
1094
1095         if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1096                 if (ctl->enabled && ctl->dsp->running)
1097                         ret = wm_coeff_read_control(ctl, ctl->cache, size);
1098                 else
1099                         ret = -EPERM;
1100         } else {
1101                 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1102                         ret = wm_coeff_read_control(ctl, ctl->cache, size);
1103         }
1104
1105         if (!ret && copy_to_user(bytes, ctl->cache, size))
1106                 ret = -EFAULT;
1107
1108         mutex_unlock(&ctl->dsp->pwr_lock);
1109
1110         return ret;
1111 }
1112
1113 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1114                               struct snd_ctl_elem_value *ucontrol)
1115 {
1116         /*
1117          * Although it's not useful to read an acked control, we must satisfy
1118          * user-side assumptions that all controls are readable and that a
1119          * write of the same value should be filtered out (it's valid to send
1120          * the same event number again to the firmware). We therefore return 0,
1121          * meaning "no event" so valid event numbers will always be a change
1122          */
1123         ucontrol->value.integer.value[0] = 0;
1124
1125         return 0;
1126 }
1127
1128 struct wmfw_ctl_work {
1129         struct wm_adsp *dsp;
1130         struct wm_coeff_ctl *ctl;
1131         struct work_struct work;
1132 };
1133
1134 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1135 {
1136         unsigned int out, rd, wr, vol;
1137
1138         if (len > ADSP_MAX_STD_CTRL_SIZE) {
1139                 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1140                 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1141                 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1142
1143                 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1144         } else {
1145                 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1146                 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1147                 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1148
1149                 out = 0;
1150         }
1151
1152         if (in) {
1153                 if (in & WMFW_CTL_FLAG_READABLE)
1154                         out |= rd;
1155                 if (in & WMFW_CTL_FLAG_WRITEABLE)
1156                         out |= wr;
1157                 if (in & WMFW_CTL_FLAG_VOLATILE)
1158                         out |= vol;
1159         } else {
1160                 out |= rd | wr | vol;
1161         }
1162
1163         return out;
1164 }
1165
1166 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1167 {
1168         struct snd_kcontrol_new *kcontrol;
1169         int ret;
1170
1171         if (!ctl || !ctl->name)
1172                 return -EINVAL;
1173
1174         kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1175         if (!kcontrol)
1176                 return -ENOMEM;
1177
1178         kcontrol->name = ctl->name;
1179         kcontrol->info = wm_coeff_info;
1180         kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1181         kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1182         kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1183         kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1184
1185         switch (ctl->type) {
1186         case WMFW_CTL_TYPE_ACKED:
1187                 kcontrol->get = wm_coeff_get_acked;
1188                 kcontrol->put = wm_coeff_put_acked;
1189                 break;
1190         default:
1191                 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1192                         ctl->bytes_ext.max = ctl->len;
1193                         ctl->bytes_ext.get = wm_coeff_tlv_get;
1194                         ctl->bytes_ext.put = wm_coeff_tlv_put;
1195                 } else {
1196                         kcontrol->get = wm_coeff_get;
1197                         kcontrol->put = wm_coeff_put;
1198                 }
1199                 break;
1200         }
1201
1202         ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
1203         if (ret < 0)
1204                 goto err_kcontrol;
1205
1206         kfree(kcontrol);
1207
1208         return 0;
1209
1210 err_kcontrol:
1211         kfree(kcontrol);
1212         return ret;
1213 }
1214
1215 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1216 {
1217         struct wm_coeff_ctl *ctl;
1218         int ret;
1219
1220         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1221                 if (!ctl->enabled || ctl->set)
1222                         continue;
1223                 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1224                         continue;
1225
1226                 /*
1227                  * For readable controls populate the cache from the DSP memory.
1228                  * For non-readable controls the cache was zero-filled when
1229                  * created so we don't need to do anything.
1230                  */
1231                 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1232                         ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1233                         if (ret < 0)
1234                                 return ret;
1235                 }
1236         }
1237
1238         return 0;
1239 }
1240
1241 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1242 {
1243         struct wm_coeff_ctl *ctl;
1244         int ret;
1245
1246         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1247                 if (!ctl->enabled)
1248                         continue;
1249                 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1250                         ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
1251                         if (ret < 0)
1252                                 return ret;
1253                 }
1254         }
1255
1256         return 0;
1257 }
1258
1259 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1260                                           unsigned int event)
1261 {
1262         struct wm_coeff_ctl *ctl;
1263         int ret;
1264
1265         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1266                 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1267                         continue;
1268
1269                 if (!ctl->enabled)
1270                         continue;
1271
1272                 ret = wm_coeff_write_acked_control(ctl, event);
1273                 if (ret)
1274                         adsp_warn(dsp,
1275                                   "Failed to send 0x%x event to alg 0x%x (%d)\n",
1276                                   event, ctl->alg_region.alg, ret);
1277         }
1278 }
1279
1280 static void wm_adsp_ctl_work(struct work_struct *work)
1281 {
1282         struct wmfw_ctl_work *ctl_work = container_of(work,
1283                                                       struct wmfw_ctl_work,
1284                                                       work);
1285
1286         wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1287         kfree(ctl_work);
1288 }
1289
1290 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1291 {
1292         kfree(ctl->cache);
1293         kfree(ctl->name);
1294         kfree(ctl);
1295 }
1296
1297 static int wm_adsp_create_control(struct wm_adsp *dsp,
1298                                   const struct wm_adsp_alg_region *alg_region,
1299                                   unsigned int offset, unsigned int len,
1300                                   const char *subname, unsigned int subname_len,
1301                                   unsigned int flags, unsigned int type)
1302 {
1303         struct wm_coeff_ctl *ctl;
1304         struct wmfw_ctl_work *ctl_work;
1305         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1306         const char *region_name;
1307         int ret;
1308
1309         region_name = wm_adsp_mem_region_name(alg_region->type);
1310         if (!region_name) {
1311                 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1312                 return -EINVAL;
1313         }
1314
1315         switch (dsp->fw_ver) {
1316         case 0:
1317         case 1:
1318                 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
1319                          dsp->num, region_name, alg_region->alg);
1320                 break;
1321         default:
1322                 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1323                                 "DSP%d%c %.12s %x", dsp->num, *region_name,
1324                                 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1325
1326                 /* Truncate the subname from the start if it is too long */
1327                 if (subname) {
1328                         int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1329                         int skip = 0;
1330
1331                         if (dsp->component->name_prefix)
1332                                 avail -= strlen(dsp->component->name_prefix) + 1;
1333
1334                         if (subname_len > avail)
1335                                 skip = subname_len - avail;
1336
1337                         snprintf(name + ret,
1338                                  SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1339                                  subname_len - skip, subname + skip);
1340                 }
1341                 break;
1342         }
1343
1344         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1345                 if (!strcmp(ctl->name, name)) {
1346                         if (!ctl->enabled)
1347                                 ctl->enabled = 1;
1348                         return 0;
1349                 }
1350         }
1351
1352         ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1353         if (!ctl)
1354                 return -ENOMEM;
1355         ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1356         ctl->alg_region = *alg_region;
1357         ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1358         if (!ctl->name) {
1359                 ret = -ENOMEM;
1360                 goto err_ctl;
1361         }
1362         ctl->enabled = 1;
1363         ctl->set = 0;
1364         ctl->ops.xget = wm_coeff_get;
1365         ctl->ops.xput = wm_coeff_put;
1366         ctl->dsp = dsp;
1367
1368         ctl->flags = flags;
1369         ctl->type = type;
1370         ctl->offset = offset;
1371         ctl->len = len;
1372         ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1373         if (!ctl->cache) {
1374                 ret = -ENOMEM;
1375                 goto err_ctl_name;
1376         }
1377
1378         list_add(&ctl->list, &dsp->ctl_list);
1379
1380         if (flags & WMFW_CTL_FLAG_SYS)
1381                 return 0;
1382
1383         ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1384         if (!ctl_work) {
1385                 ret = -ENOMEM;
1386                 goto err_ctl_cache;
1387         }
1388
1389         ctl_work->dsp = dsp;
1390         ctl_work->ctl = ctl;
1391         INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1392         schedule_work(&ctl_work->work);
1393
1394         return 0;
1395
1396 err_ctl_cache:
1397         kfree(ctl->cache);
1398 err_ctl_name:
1399         kfree(ctl->name);
1400 err_ctl:
1401         kfree(ctl);
1402
1403         return ret;
1404 }
1405
1406 struct wm_coeff_parsed_alg {
1407         int id;
1408         const u8 *name;
1409         int name_len;
1410         int ncoeff;
1411 };
1412
1413 struct wm_coeff_parsed_coeff {
1414         int offset;
1415         int mem_type;
1416         const u8 *name;
1417         int name_len;
1418         int ctl_type;
1419         int flags;
1420         int len;
1421 };
1422
1423 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1424 {
1425         int length;
1426
1427         switch (bytes) {
1428         case 1:
1429                 length = **pos;
1430                 break;
1431         case 2:
1432                 length = le16_to_cpu(*((__le16 *)*pos));
1433                 break;
1434         default:
1435                 return 0;
1436         }
1437
1438         if (str)
1439                 *str = *pos + bytes;
1440
1441         *pos += ((length + bytes) + 3) & ~0x03;
1442
1443         return length;
1444 }
1445
1446 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1447 {
1448         int val = 0;
1449
1450         switch (bytes) {
1451         case 2:
1452                 val = le16_to_cpu(*((__le16 *)*pos));
1453                 break;
1454         case 4:
1455                 val = le32_to_cpu(*((__le32 *)*pos));
1456                 break;
1457         default:
1458                 break;
1459         }
1460
1461         *pos += bytes;
1462
1463         return val;
1464 }
1465
1466 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1467                                       struct wm_coeff_parsed_alg *blk)
1468 {
1469         const struct wmfw_adsp_alg_data *raw;
1470
1471         switch (dsp->fw_ver) {
1472         case 0:
1473         case 1:
1474                 raw = (const struct wmfw_adsp_alg_data *)*data;
1475                 *data = raw->data;
1476
1477                 blk->id = le32_to_cpu(raw->id);
1478                 blk->name = raw->name;
1479                 blk->name_len = strlen(raw->name);
1480                 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1481                 break;
1482         default:
1483                 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1484                 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1485                                                       &blk->name);
1486                 wm_coeff_parse_string(sizeof(u16), data, NULL);
1487                 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1488                 break;
1489         }
1490
1491         adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1492         adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1493         adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1494 }
1495
1496 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1497                                         struct wm_coeff_parsed_coeff *blk)
1498 {
1499         const struct wmfw_adsp_coeff_data *raw;
1500         const u8 *tmp;
1501         int length;
1502
1503         switch (dsp->fw_ver) {
1504         case 0:
1505         case 1:
1506                 raw = (const struct wmfw_adsp_coeff_data *)*data;
1507                 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1508
1509                 blk->offset = le16_to_cpu(raw->hdr.offset);
1510                 blk->mem_type = le16_to_cpu(raw->hdr.type);
1511                 blk->name = raw->name;
1512                 blk->name_len = strlen(raw->name);
1513                 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1514                 blk->flags = le16_to_cpu(raw->flags);
1515                 blk->len = le32_to_cpu(raw->len);
1516                 break;
1517         default:
1518                 tmp = *data;
1519                 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1520                 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1521                 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1522                 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1523                                                       &blk->name);
1524                 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1525                 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1526                 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1527                 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1528                 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1529
1530                 *data = *data + sizeof(raw->hdr) + length;
1531                 break;
1532         }
1533
1534         adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1535         adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1536         adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1537         adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1538         adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1539         adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1540 }
1541
1542 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1543                                 const struct wm_coeff_parsed_coeff *coeff_blk,
1544                                 unsigned int f_required,
1545                                 unsigned int f_illegal)
1546 {
1547         if ((coeff_blk->flags & f_illegal) ||
1548             ((coeff_blk->flags & f_required) != f_required)) {
1549                 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1550                          coeff_blk->flags, coeff_blk->ctl_type);
1551                 return -EINVAL;
1552         }
1553
1554         return 0;
1555 }
1556
1557 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1558                                const struct wmfw_region *region)
1559 {
1560         struct wm_adsp_alg_region alg_region = {};
1561         struct wm_coeff_parsed_alg alg_blk;
1562         struct wm_coeff_parsed_coeff coeff_blk;
1563         const u8 *data = region->data;
1564         int i, ret;
1565
1566         wm_coeff_parse_alg(dsp, &data, &alg_blk);
1567         for (i = 0; i < alg_blk.ncoeff; i++) {
1568                 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1569
1570                 switch (coeff_blk.ctl_type) {
1571                 case SNDRV_CTL_ELEM_TYPE_BYTES:
1572                         break;
1573                 case WMFW_CTL_TYPE_ACKED:
1574                         if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1575                                 continue;       /* ignore */
1576
1577                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1578                                                 WMFW_CTL_FLAG_VOLATILE |
1579                                                 WMFW_CTL_FLAG_WRITEABLE |
1580                                                 WMFW_CTL_FLAG_READABLE,
1581                                                 0);
1582                         if (ret)
1583                                 return -EINVAL;
1584                         break;
1585                 case WMFW_CTL_TYPE_HOSTEVENT:
1586                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1587                                                 WMFW_CTL_FLAG_SYS |
1588                                                 WMFW_CTL_FLAG_VOLATILE |
1589                                                 WMFW_CTL_FLAG_WRITEABLE |
1590                                                 WMFW_CTL_FLAG_READABLE,
1591                                                 0);
1592                         if (ret)
1593                                 return -EINVAL;
1594                         break;
1595                 case WMFW_CTL_TYPE_HOST_BUFFER:
1596                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1597                                                 WMFW_CTL_FLAG_SYS |
1598                                                 WMFW_CTL_FLAG_VOLATILE |
1599                                                 WMFW_CTL_FLAG_READABLE,
1600                                                 0);
1601                         if (ret)
1602                                 return -EINVAL;
1603                         break;
1604                 default:
1605                         adsp_err(dsp, "Unknown control type: %d\n",
1606                                  coeff_blk.ctl_type);
1607                         return -EINVAL;
1608                 }
1609
1610                 alg_region.type = coeff_blk.mem_type;
1611                 alg_region.alg = alg_blk.id;
1612
1613                 ret = wm_adsp_create_control(dsp, &alg_region,
1614                                              coeff_blk.offset,
1615                                              coeff_blk.len,
1616                                              coeff_blk.name,
1617                                              coeff_blk.name_len,
1618                                              coeff_blk.flags,
1619                                              coeff_blk.ctl_type);
1620                 if (ret < 0)
1621                         adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1622                                  coeff_blk.name_len, coeff_blk.name, ret);
1623         }
1624
1625         return 0;
1626 }
1627
1628 static int wm_adsp_load(struct wm_adsp *dsp)
1629 {
1630         LIST_HEAD(buf_list);
1631         const struct firmware *firmware;
1632         struct regmap *regmap = dsp->regmap;
1633         unsigned int pos = 0;
1634         const struct wmfw_header *header;
1635         const struct wmfw_adsp1_sizes *adsp1_sizes;
1636         const struct wmfw_adsp2_sizes *adsp2_sizes;
1637         const struct wmfw_footer *footer;
1638         const struct wmfw_region *region;
1639         const struct wm_adsp_region *mem;
1640         const char *region_name;
1641         char *file, *text = NULL;
1642         struct wm_adsp_buf *buf;
1643         unsigned int reg;
1644         int regions = 0;
1645         int ret, offset, type, sizes;
1646
1647         file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1648         if (file == NULL)
1649                 return -ENOMEM;
1650
1651         snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1652                  wm_adsp_fw[dsp->fw].file);
1653         file[PAGE_SIZE - 1] = '\0';
1654
1655         ret = request_firmware(&firmware, file, dsp->dev);
1656         if (ret != 0) {
1657                 adsp_err(dsp, "Failed to request '%s'\n", file);
1658                 goto out;
1659         }
1660         ret = -EINVAL;
1661
1662         pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1663         if (pos >= firmware->size) {
1664                 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1665                          file, firmware->size);
1666                 goto out_fw;
1667         }
1668
1669         header = (void *)&firmware->data[0];
1670
1671         if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1672                 adsp_err(dsp, "%s: invalid magic\n", file);
1673                 goto out_fw;
1674         }
1675
1676         switch (header->ver) {
1677         case 0:
1678                 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1679                           file, header->ver);
1680                 break;
1681         case 1:
1682         case 2:
1683                 break;
1684         default:
1685                 adsp_err(dsp, "%s: unknown file format %d\n",
1686                          file, header->ver);
1687                 goto out_fw;
1688         }
1689
1690         adsp_info(dsp, "Firmware version: %d\n", header->ver);
1691         dsp->fw_ver = header->ver;
1692
1693         if (header->core != dsp->type) {
1694                 adsp_err(dsp, "%s: invalid core %d != %d\n",
1695                          file, header->core, dsp->type);
1696                 goto out_fw;
1697         }
1698
1699         switch (dsp->type) {
1700         case WMFW_ADSP1:
1701                 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1702                 adsp1_sizes = (void *)&(header[1]);
1703                 footer = (void *)&(adsp1_sizes[1]);
1704                 sizes = sizeof(*adsp1_sizes);
1705
1706                 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1707                          file, le32_to_cpu(adsp1_sizes->dm),
1708                          le32_to_cpu(adsp1_sizes->pm),
1709                          le32_to_cpu(adsp1_sizes->zm));
1710                 break;
1711
1712         case WMFW_ADSP2:
1713                 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1714                 adsp2_sizes = (void *)&(header[1]);
1715                 footer = (void *)&(adsp2_sizes[1]);
1716                 sizes = sizeof(*adsp2_sizes);
1717
1718                 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1719                          file, le32_to_cpu(adsp2_sizes->xm),
1720                          le32_to_cpu(adsp2_sizes->ym),
1721                          le32_to_cpu(adsp2_sizes->pm),
1722                          le32_to_cpu(adsp2_sizes->zm));
1723                 break;
1724
1725         default:
1726                 WARN(1, "Unknown DSP type");
1727                 goto out_fw;
1728         }
1729
1730         if (le32_to_cpu(header->len) != sizeof(*header) +
1731             sizes + sizeof(*footer)) {
1732                 adsp_err(dsp, "%s: unexpected header length %d\n",
1733                          file, le32_to_cpu(header->len));
1734                 goto out_fw;
1735         }
1736
1737         adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1738                  le64_to_cpu(footer->timestamp));
1739
1740         while (pos < firmware->size &&
1741                sizeof(*region) < firmware->size - pos) {
1742                 region = (void *)&(firmware->data[pos]);
1743                 region_name = "Unknown";
1744                 reg = 0;
1745                 text = NULL;
1746                 offset = le32_to_cpu(region->offset) & 0xffffff;
1747                 type = be32_to_cpu(region->type) & 0xff;
1748                 mem = wm_adsp_find_region(dsp, type);
1749
1750                 switch (type) {
1751                 case WMFW_NAME_TEXT:
1752                         region_name = "Firmware name";
1753                         text = kzalloc(le32_to_cpu(region->len) + 1,
1754                                        GFP_KERNEL);
1755                         break;
1756                 case WMFW_ALGORITHM_DATA:
1757                         region_name = "Algorithm";
1758                         ret = wm_adsp_parse_coeff(dsp, region);
1759                         if (ret != 0)
1760                                 goto out_fw;
1761                         break;
1762                 case WMFW_INFO_TEXT:
1763                         region_name = "Information";
1764                         text = kzalloc(le32_to_cpu(region->len) + 1,
1765                                        GFP_KERNEL);
1766                         break;
1767                 case WMFW_ABSOLUTE:
1768                         region_name = "Absolute";
1769                         reg = offset;
1770                         break;
1771                 case WMFW_ADSP1_PM:
1772                 case WMFW_ADSP1_DM:
1773                 case WMFW_ADSP2_XM:
1774                 case WMFW_ADSP2_YM:
1775                 case WMFW_ADSP1_ZM:
1776                         region_name = wm_adsp_mem_region_name(type);
1777                         reg = wm_adsp_region_to_reg(mem, offset);
1778                         break;
1779                 default:
1780                         adsp_warn(dsp,
1781                                   "%s.%d: Unknown region type %x at %d(%x)\n",
1782                                   file, regions, type, pos, pos);
1783                         break;
1784                 }
1785
1786                 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1787                          regions, le32_to_cpu(region->len), offset,
1788                          region_name);
1789
1790                 if (le32_to_cpu(region->len) >
1791                     firmware->size - pos - sizeof(*region)) {
1792                         adsp_err(dsp,
1793                                  "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1794                                  file, regions, region_name,
1795                                  le32_to_cpu(region->len), firmware->size);
1796                         ret = -EINVAL;
1797                         goto out_fw;
1798                 }
1799
1800                 if (text) {
1801                         memcpy(text, region->data, le32_to_cpu(region->len));
1802                         adsp_info(dsp, "%s: %s\n", file, text);
1803                         kfree(text);
1804                         text = NULL;
1805                 }
1806
1807                 if (reg) {
1808                         buf = wm_adsp_buf_alloc(region->data,
1809                                                 le32_to_cpu(region->len),
1810                                                 &buf_list);
1811                         if (!buf) {
1812                                 adsp_err(dsp, "Out of memory\n");
1813                                 ret = -ENOMEM;
1814                                 goto out_fw;
1815                         }
1816
1817                         ret = regmap_raw_write_async(regmap, reg, buf->buf,
1818                                                      le32_to_cpu(region->len));
1819                         if (ret != 0) {
1820                                 adsp_err(dsp,
1821                                         "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1822                                         file, regions,
1823                                         le32_to_cpu(region->len), offset,
1824                                         region_name, ret);
1825                                 goto out_fw;
1826                         }
1827                 }
1828
1829                 pos += le32_to_cpu(region->len) + sizeof(*region);
1830                 regions++;
1831         }
1832
1833         ret = regmap_async_complete(regmap);
1834         if (ret != 0) {
1835                 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1836                 goto out_fw;
1837         }
1838
1839         if (pos > firmware->size)
1840                 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1841                           file, regions, pos - firmware->size);
1842
1843         wm_adsp_debugfs_save_wmfwname(dsp, file);
1844
1845 out_fw:
1846         regmap_async_complete(regmap);
1847         wm_adsp_buf_free(&buf_list);
1848         release_firmware(firmware);
1849         kfree(text);
1850 out:
1851         kfree(file);
1852
1853         return ret;
1854 }
1855
1856 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1857                                   const struct wm_adsp_alg_region *alg_region)
1858 {
1859         struct wm_coeff_ctl *ctl;
1860
1861         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1862                 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1863                     alg_region->alg == ctl->alg_region.alg &&
1864                     alg_region->type == ctl->alg_region.type) {
1865                         ctl->alg_region.base = alg_region->base;
1866                 }
1867         }
1868 }
1869
1870 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
1871                                const struct wm_adsp_region *mem,
1872                                unsigned int pos, unsigned int len)
1873 {
1874         void *alg;
1875         unsigned int reg;
1876         int ret;
1877         __be32 val;
1878
1879         if (n_algs == 0) {
1880                 adsp_err(dsp, "No algorithms\n");
1881                 return ERR_PTR(-EINVAL);
1882         }
1883
1884         if (n_algs > 1024) {
1885                 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
1886                 return ERR_PTR(-EINVAL);
1887         }
1888
1889         /* Read the terminator first to validate the length */
1890         reg = wm_adsp_region_to_reg(mem, pos + len);
1891
1892         ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
1893         if (ret != 0) {
1894                 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1895                         ret);
1896                 return ERR_PTR(ret);
1897         }
1898
1899         if (be32_to_cpu(val) != 0xbedead)
1900                 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
1901                           reg, be32_to_cpu(val));
1902
1903         /* Convert length from DSP words to bytes */
1904         len *= sizeof(u32);
1905
1906         alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
1907         if (!alg)
1908                 return ERR_PTR(-ENOMEM);
1909
1910         reg = wm_adsp_region_to_reg(mem, pos);
1911
1912         ret = regmap_raw_read(dsp->regmap, reg, alg, len);
1913         if (ret != 0) {
1914                 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
1915                 kfree(alg);
1916                 return ERR_PTR(ret);
1917         }
1918
1919         return alg;
1920 }
1921
1922 static struct wm_adsp_alg_region *
1923         wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1924 {
1925         struct wm_adsp_alg_region *alg_region;
1926
1927         list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1928                 if (id == alg_region->alg && type == alg_region->type)
1929                         return alg_region;
1930         }
1931
1932         return NULL;
1933 }
1934
1935 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1936                                                         int type, __be32 id,
1937                                                         __be32 base)
1938 {
1939         struct wm_adsp_alg_region *alg_region;
1940
1941         alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1942         if (!alg_region)
1943                 return ERR_PTR(-ENOMEM);
1944
1945         alg_region->type = type;
1946         alg_region->alg = be32_to_cpu(id);
1947         alg_region->base = be32_to_cpu(base);
1948
1949         list_add_tail(&alg_region->list, &dsp->alg_regions);
1950
1951         if (dsp->fw_ver > 0)
1952                 wm_adsp_ctl_fixup_base(dsp, alg_region);
1953
1954         return alg_region;
1955 }
1956
1957 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1958 {
1959         struct wm_adsp_alg_region *alg_region;
1960
1961         while (!list_empty(&dsp->alg_regions)) {
1962                 alg_region = list_first_entry(&dsp->alg_regions,
1963                                               struct wm_adsp_alg_region,
1964                                               list);
1965                 list_del(&alg_region->list);
1966                 kfree(alg_region);
1967         }
1968 }
1969
1970 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1971 {
1972         struct wmfw_adsp1_id_hdr adsp1_id;
1973         struct wmfw_adsp1_alg_hdr *adsp1_alg;
1974         struct wm_adsp_alg_region *alg_region;
1975         const struct wm_adsp_region *mem;
1976         unsigned int pos, len;
1977         size_t n_algs;
1978         int i, ret;
1979
1980         mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1981         if (WARN_ON(!mem))
1982                 return -EINVAL;
1983
1984         ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1985                               sizeof(adsp1_id));
1986         if (ret != 0) {
1987                 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1988                          ret);
1989                 return ret;
1990         }
1991
1992         n_algs = be32_to_cpu(adsp1_id.n_algs);
1993         dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1994         adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1995                   dsp->fw_id,
1996                   (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1997                   (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1998                   be32_to_cpu(adsp1_id.fw.ver) & 0xff,
1999                   n_algs);
2000
2001         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2002                                            adsp1_id.fw.id, adsp1_id.zm);
2003         if (IS_ERR(alg_region))
2004                 return PTR_ERR(alg_region);
2005
2006         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2007                                            adsp1_id.fw.id, adsp1_id.dm);
2008         if (IS_ERR(alg_region))
2009                 return PTR_ERR(alg_region);
2010
2011         /* Calculate offset and length in DSP words */
2012         pos = sizeof(adsp1_id) / sizeof(u32);
2013         len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
2014
2015         adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2016         if (IS_ERR(adsp1_alg))
2017                 return PTR_ERR(adsp1_alg);
2018
2019         for (i = 0; i < n_algs; i++) {
2020                 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2021                           i, be32_to_cpu(adsp1_alg[i].alg.id),
2022                           (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2023                           (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2024                           be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2025                           be32_to_cpu(adsp1_alg[i].dm),
2026                           be32_to_cpu(adsp1_alg[i].zm));
2027
2028                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2029                                                    adsp1_alg[i].alg.id,
2030                                                    adsp1_alg[i].dm);
2031                 if (IS_ERR(alg_region)) {
2032                         ret = PTR_ERR(alg_region);
2033                         goto out;
2034                 }
2035                 if (dsp->fw_ver == 0) {
2036                         if (i + 1 < n_algs) {
2037                                 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2038                                 len -= be32_to_cpu(adsp1_alg[i].dm);
2039                                 len *= 4;
2040                                 wm_adsp_create_control(dsp, alg_region, 0,
2041                                                      len, NULL, 0, 0,
2042                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2043                         } else {
2044                                 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2045                                           be32_to_cpu(adsp1_alg[i].alg.id));
2046                         }
2047                 }
2048
2049                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2050                                                    adsp1_alg[i].alg.id,
2051                                                    adsp1_alg[i].zm);
2052                 if (IS_ERR(alg_region)) {
2053                         ret = PTR_ERR(alg_region);
2054                         goto out;
2055                 }
2056                 if (dsp->fw_ver == 0) {
2057                         if (i + 1 < n_algs) {
2058                                 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2059                                 len -= be32_to_cpu(adsp1_alg[i].zm);
2060                                 len *= 4;
2061                                 wm_adsp_create_control(dsp, alg_region, 0,
2062                                                      len, NULL, 0, 0,
2063                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2064                         } else {
2065                                 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2066                                           be32_to_cpu(adsp1_alg[i].alg.id));
2067                         }
2068                 }
2069         }
2070
2071 out:
2072         kfree(adsp1_alg);
2073         return ret;
2074 }
2075
2076 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2077 {
2078         struct wmfw_adsp2_id_hdr adsp2_id;
2079         struct wmfw_adsp2_alg_hdr *adsp2_alg;
2080         struct wm_adsp_alg_region *alg_region;
2081         const struct wm_adsp_region *mem;
2082         unsigned int pos, len;
2083         size_t n_algs;
2084         int i, ret;
2085
2086         mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2087         if (WARN_ON(!mem))
2088                 return -EINVAL;
2089
2090         ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2091                               sizeof(adsp2_id));
2092         if (ret != 0) {
2093                 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2094                          ret);
2095                 return ret;
2096         }
2097
2098         n_algs = be32_to_cpu(adsp2_id.n_algs);
2099         dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
2100         dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
2101         adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
2102                   dsp->fw_id,
2103                   (dsp->fw_id_version & 0xff0000) >> 16,
2104                   (dsp->fw_id_version & 0xff00) >> 8,
2105                   dsp->fw_id_version & 0xff,
2106                   n_algs);
2107
2108         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2109                                            adsp2_id.fw.id, adsp2_id.xm);
2110         if (IS_ERR(alg_region))
2111                 return PTR_ERR(alg_region);
2112
2113         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2114                                            adsp2_id.fw.id, adsp2_id.ym);
2115         if (IS_ERR(alg_region))
2116                 return PTR_ERR(alg_region);
2117
2118         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2119                                            adsp2_id.fw.id, adsp2_id.zm);
2120         if (IS_ERR(alg_region))
2121                 return PTR_ERR(alg_region);
2122
2123         /* Calculate offset and length in DSP words */
2124         pos = sizeof(adsp2_id) / sizeof(u32);
2125         len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
2126
2127         adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2128         if (IS_ERR(adsp2_alg))
2129                 return PTR_ERR(adsp2_alg);
2130
2131         for (i = 0; i < n_algs; i++) {
2132                 adsp_info(dsp,
2133                           "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2134                           i, be32_to_cpu(adsp2_alg[i].alg.id),
2135                           (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2136                           (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2137                           be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2138                           be32_to_cpu(adsp2_alg[i].xm),
2139                           be32_to_cpu(adsp2_alg[i].ym),
2140                           be32_to_cpu(adsp2_alg[i].zm));
2141
2142                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2143                                                    adsp2_alg[i].alg.id,
2144                                                    adsp2_alg[i].xm);
2145                 if (IS_ERR(alg_region)) {
2146                         ret = PTR_ERR(alg_region);
2147                         goto out;
2148                 }
2149                 if (dsp->fw_ver == 0) {
2150                         if (i + 1 < n_algs) {
2151                                 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2152                                 len -= be32_to_cpu(adsp2_alg[i].xm);
2153                                 len *= 4;
2154                                 wm_adsp_create_control(dsp, alg_region, 0,
2155                                                      len, NULL, 0, 0,
2156                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2157                         } else {
2158                                 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2159                                           be32_to_cpu(adsp2_alg[i].alg.id));
2160                         }
2161                 }
2162
2163                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2164                                                    adsp2_alg[i].alg.id,
2165                                                    adsp2_alg[i].ym);
2166                 if (IS_ERR(alg_region)) {
2167                         ret = PTR_ERR(alg_region);
2168                         goto out;
2169                 }
2170                 if (dsp->fw_ver == 0) {
2171                         if (i + 1 < n_algs) {
2172                                 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2173                                 len -= be32_to_cpu(adsp2_alg[i].ym);
2174                                 len *= 4;
2175                                 wm_adsp_create_control(dsp, alg_region, 0,
2176                                                      len, NULL, 0, 0,
2177                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2178                         } else {
2179                                 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2180                                           be32_to_cpu(adsp2_alg[i].alg.id));
2181                         }
2182                 }
2183
2184                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2185                                                    adsp2_alg[i].alg.id,
2186                                                    adsp2_alg[i].zm);
2187                 if (IS_ERR(alg_region)) {
2188                         ret = PTR_ERR(alg_region);
2189                         goto out;
2190                 }
2191                 if (dsp->fw_ver == 0) {
2192                         if (i + 1 < n_algs) {
2193                                 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2194                                 len -= be32_to_cpu(adsp2_alg[i].zm);
2195                                 len *= 4;
2196                                 wm_adsp_create_control(dsp, alg_region, 0,
2197                                                      len, NULL, 0, 0,
2198                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2199                         } else {
2200                                 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2201                                           be32_to_cpu(adsp2_alg[i].alg.id));
2202                         }
2203                 }
2204         }
2205
2206 out:
2207         kfree(adsp2_alg);
2208         return ret;
2209 }
2210
2211 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2212 {
2213         LIST_HEAD(buf_list);
2214         struct regmap *regmap = dsp->regmap;
2215         struct wmfw_coeff_hdr *hdr;
2216         struct wmfw_coeff_item *blk;
2217         const struct firmware *firmware;
2218         const struct wm_adsp_region *mem;
2219         struct wm_adsp_alg_region *alg_region;
2220         const char *region_name;
2221         int ret, pos, blocks, type, offset, reg;
2222         char *file;
2223         struct wm_adsp_buf *buf;
2224
2225         file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2226         if (file == NULL)
2227                 return -ENOMEM;
2228
2229         snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
2230                  wm_adsp_fw[dsp->fw].file);
2231         file[PAGE_SIZE - 1] = '\0';
2232
2233         ret = request_firmware(&firmware, file, dsp->dev);
2234         if (ret != 0) {
2235                 adsp_warn(dsp, "Failed to request '%s'\n", file);
2236                 ret = 0;
2237                 goto out;
2238         }
2239         ret = -EINVAL;
2240
2241         if (sizeof(*hdr) >= firmware->size) {
2242                 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2243                         file, firmware->size);
2244                 goto out_fw;
2245         }
2246
2247         hdr = (void *)&firmware->data[0];
2248         if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2249                 adsp_err(dsp, "%s: invalid magic\n", file);
2250                 goto out_fw;
2251         }
2252
2253         switch (be32_to_cpu(hdr->rev) & 0xff) {
2254         case 1:
2255                 break;
2256         default:
2257                 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2258                          file, be32_to_cpu(hdr->rev) & 0xff);
2259                 ret = -EINVAL;
2260                 goto out_fw;
2261         }
2262
2263         adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2264                 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2265                 (le32_to_cpu(hdr->ver) >>  8) & 0xff,
2266                 le32_to_cpu(hdr->ver) & 0xff);
2267
2268         pos = le32_to_cpu(hdr->len);
2269
2270         blocks = 0;
2271         while (pos < firmware->size &&
2272                sizeof(*blk) < firmware->size - pos) {
2273                 blk = (void *)(&firmware->data[pos]);
2274
2275                 type = le16_to_cpu(blk->type);
2276                 offset = le16_to_cpu(blk->offset);
2277
2278                 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2279                          file, blocks, le32_to_cpu(blk->id),
2280                          (le32_to_cpu(blk->ver) >> 16) & 0xff,
2281                          (le32_to_cpu(blk->ver) >>  8) & 0xff,
2282                          le32_to_cpu(blk->ver) & 0xff);
2283                 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2284                          file, blocks, le32_to_cpu(blk->len), offset, type);
2285
2286                 reg = 0;
2287                 region_name = "Unknown";
2288                 switch (type) {
2289                 case (WMFW_NAME_TEXT << 8):
2290                 case (WMFW_INFO_TEXT << 8):
2291                         break;
2292                 case (WMFW_ABSOLUTE << 8):
2293                         /*
2294                          * Old files may use this for global
2295                          * coefficients.
2296                          */
2297                         if (le32_to_cpu(blk->id) == dsp->fw_id &&
2298                             offset == 0) {
2299                                 region_name = "global coefficients";
2300                                 mem = wm_adsp_find_region(dsp, type);
2301                                 if (!mem) {
2302                                         adsp_err(dsp, "No ZM\n");
2303                                         break;
2304                                 }
2305                                 reg = wm_adsp_region_to_reg(mem, 0);
2306
2307                         } else {
2308                                 region_name = "register";
2309                                 reg = offset;
2310                         }
2311                         break;
2312
2313                 case WMFW_ADSP1_DM:
2314                 case WMFW_ADSP1_ZM:
2315                 case WMFW_ADSP2_XM:
2316                 case WMFW_ADSP2_YM:
2317                         adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2318                                  file, blocks, le32_to_cpu(blk->len),
2319                                  type, le32_to_cpu(blk->id));
2320
2321                         mem = wm_adsp_find_region(dsp, type);
2322                         if (!mem) {
2323                                 adsp_err(dsp, "No base for region %x\n", type);
2324                                 break;
2325                         }
2326
2327                         alg_region = wm_adsp_find_alg_region(dsp, type,
2328                                                 le32_to_cpu(blk->id));
2329                         if (alg_region) {
2330                                 reg = alg_region->base;
2331                                 reg = wm_adsp_region_to_reg(mem, reg);
2332                                 reg += offset;
2333                         } else {
2334                                 adsp_err(dsp, "No %x for algorithm %x\n",
2335                                          type, le32_to_cpu(blk->id));
2336                         }
2337                         break;
2338
2339                 default:
2340                         adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2341                                  file, blocks, type, pos);
2342                         break;
2343                 }
2344
2345                 if (reg) {
2346                         if (le32_to_cpu(blk->len) >
2347                             firmware->size - pos - sizeof(*blk)) {
2348                                 adsp_err(dsp,
2349                                          "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2350                                          file, blocks, region_name,
2351                                          le32_to_cpu(blk->len),
2352                                          firmware->size);
2353                                 ret = -EINVAL;
2354                                 goto out_fw;
2355                         }
2356
2357                         buf = wm_adsp_buf_alloc(blk->data,
2358                                                 le32_to_cpu(blk->len),
2359                                                 &buf_list);
2360                         if (!buf) {
2361                                 adsp_err(dsp, "Out of memory\n");
2362                                 ret = -ENOMEM;
2363                                 goto out_fw;
2364                         }
2365
2366                         adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2367                                  file, blocks, le32_to_cpu(blk->len),
2368                                  reg);
2369                         ret = regmap_raw_write_async(regmap, reg, buf->buf,
2370                                                      le32_to_cpu(blk->len));
2371                         if (ret != 0) {
2372                                 adsp_err(dsp,
2373                                         "%s.%d: Failed to write to %x in %s: %d\n",
2374                                         file, blocks, reg, region_name, ret);
2375                         }
2376                 }
2377
2378                 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2379                 blocks++;
2380         }
2381
2382         ret = regmap_async_complete(regmap);
2383         if (ret != 0)
2384                 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2385
2386         if (pos > firmware->size)
2387                 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2388                           file, blocks, pos - firmware->size);
2389
2390         wm_adsp_debugfs_save_binname(dsp, file);
2391
2392 out_fw:
2393         regmap_async_complete(regmap);
2394         release_firmware(firmware);
2395         wm_adsp_buf_free(&buf_list);
2396 out:
2397         kfree(file);
2398         return ret;
2399 }
2400
2401 int wm_adsp1_init(struct wm_adsp *dsp)
2402 {
2403         INIT_LIST_HEAD(&dsp->alg_regions);
2404
2405         mutex_init(&dsp->pwr_lock);
2406
2407         return 0;
2408 }
2409 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2410
2411 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2412                    struct snd_kcontrol *kcontrol,
2413                    int event)
2414 {
2415         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2416         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2417         struct wm_adsp *dsp = &dsps[w->shift];
2418         struct wm_coeff_ctl *ctl;
2419         int ret;
2420         unsigned int val;
2421
2422         dsp->component = component;
2423
2424         mutex_lock(&dsp->pwr_lock);
2425
2426         switch (event) {
2427         case SND_SOC_DAPM_POST_PMU:
2428                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2429                                    ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2430
2431                 /*
2432                  * For simplicity set the DSP clock rate to be the
2433                  * SYSCLK rate rather than making it configurable.
2434                  */
2435                 if (dsp->sysclk_reg) {
2436                         ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2437                         if (ret != 0) {
2438                                 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2439                                 ret);
2440                                 goto err_mutex;
2441                         }
2442
2443                         val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2444
2445                         ret = regmap_update_bits(dsp->regmap,
2446                                                  dsp->base + ADSP1_CONTROL_31,
2447                                                  ADSP1_CLK_SEL_MASK, val);
2448                         if (ret != 0) {
2449                                 adsp_err(dsp, "Failed to set clock rate: %d\n",
2450                                          ret);
2451                                 goto err_mutex;
2452                         }
2453                 }
2454
2455                 ret = wm_adsp_load(dsp);
2456                 if (ret != 0)
2457                         goto err_ena;
2458
2459                 ret = wm_adsp1_setup_algs(dsp);
2460                 if (ret != 0)
2461                         goto err_ena;
2462
2463                 ret = wm_adsp_load_coeff(dsp);
2464                 if (ret != 0)
2465                         goto err_ena;
2466
2467                 /* Initialize caches for enabled and unset controls */
2468                 ret = wm_coeff_init_control_caches(dsp);
2469                 if (ret != 0)
2470                         goto err_ena;
2471
2472                 /* Sync set controls */
2473                 ret = wm_coeff_sync_controls(dsp);
2474                 if (ret != 0)
2475                         goto err_ena;
2476
2477                 dsp->booted = true;
2478
2479                 /* Start the core running */
2480                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2481                                    ADSP1_CORE_ENA | ADSP1_START,
2482                                    ADSP1_CORE_ENA | ADSP1_START);
2483
2484                 dsp->running = true;
2485                 break;
2486
2487         case SND_SOC_DAPM_PRE_PMD:
2488                 dsp->running = false;
2489                 dsp->booted = false;
2490
2491                 /* Halt the core */
2492                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2493                                    ADSP1_CORE_ENA | ADSP1_START, 0);
2494
2495                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2496                                    ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2497
2498                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2499                                    ADSP1_SYS_ENA, 0);
2500
2501                 list_for_each_entry(ctl, &dsp->ctl_list, list)
2502                         ctl->enabled = 0;
2503
2504
2505                 wm_adsp_free_alg_regions(dsp);
2506                 break;
2507
2508         default:
2509                 break;
2510         }
2511
2512         mutex_unlock(&dsp->pwr_lock);
2513
2514         return 0;
2515
2516 err_ena:
2517         regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2518                            ADSP1_SYS_ENA, 0);
2519 err_mutex:
2520         mutex_unlock(&dsp->pwr_lock);
2521
2522         return ret;
2523 }
2524 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2525
2526 static int wm_adsp2_ena(struct wm_adsp *dsp)
2527 {
2528         unsigned int val;
2529         int ret, count;
2530
2531         switch (dsp->rev) {
2532         case 0:
2533                 ret = regmap_update_bits_async(dsp->regmap,
2534                                                dsp->base + ADSP2_CONTROL,
2535                                                ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2536                 if (ret != 0)
2537                         return ret;
2538                 break;
2539         default:
2540                 break;
2541         }
2542
2543         /* Wait for the RAM to start, should be near instantaneous */
2544         for (count = 0; count < 10; ++count) {
2545                 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2546                 if (ret != 0)
2547                         return ret;
2548
2549                 if (val & ADSP2_RAM_RDY)
2550                         break;
2551
2552                 usleep_range(250, 500);
2553         }
2554
2555         if (!(val & ADSP2_RAM_RDY)) {
2556                 adsp_err(dsp, "Failed to start DSP RAM\n");
2557                 return -EBUSY;
2558         }
2559
2560         adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2561
2562         return 0;
2563 }
2564
2565 static void wm_adsp2_boot_work(struct work_struct *work)
2566 {
2567         struct wm_adsp *dsp = container_of(work,
2568                                            struct wm_adsp,
2569                                            boot_work);
2570         int ret;
2571
2572         mutex_lock(&dsp->pwr_lock);
2573
2574         ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2575                                  ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2576         if (ret != 0)
2577                 goto err_mutex;
2578
2579         ret = wm_adsp2_ena(dsp);
2580         if (ret != 0)
2581                 goto err_mem;
2582
2583         ret = wm_adsp_load(dsp);
2584         if (ret != 0)
2585                 goto err_ena;
2586
2587         ret = wm_adsp2_setup_algs(dsp);
2588         if (ret != 0)
2589                 goto err_ena;
2590
2591         ret = wm_adsp_load_coeff(dsp);
2592         if (ret != 0)
2593                 goto err_ena;
2594
2595         /* Initialize caches for enabled and unset controls */
2596         ret = wm_coeff_init_control_caches(dsp);
2597         if (ret != 0)
2598                 goto err_ena;
2599
2600         switch (dsp->rev) {
2601         case 0:
2602                 /* Turn DSP back off until we are ready to run */
2603                 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2604                                          ADSP2_SYS_ENA, 0);
2605                 if (ret != 0)
2606                         goto err_ena;
2607                 break;
2608         default:
2609                 break;
2610         }
2611
2612         dsp->booted = true;
2613
2614         mutex_unlock(&dsp->pwr_lock);
2615
2616         return;
2617
2618 err_ena:
2619         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2620                            ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2621 err_mem:
2622         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2623                            ADSP2_MEM_ENA, 0);
2624 err_mutex:
2625         mutex_unlock(&dsp->pwr_lock);
2626 }
2627
2628 static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2629 {
2630         int ret;
2631
2632         switch (dsp->rev) {
2633         case 0:
2634                 ret = regmap_update_bits_async(dsp->regmap,
2635                                                dsp->base + ADSP2_CLOCKING,
2636                                                ADSP2_CLK_SEL_MASK,
2637                                                freq << ADSP2_CLK_SEL_SHIFT);
2638                 if (ret) {
2639                         adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2640                         return;
2641                 }
2642                 break;
2643         default:
2644                 /* clock is handled by parent codec driver */
2645                 break;
2646         }
2647 }
2648
2649 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
2650                            struct snd_ctl_elem_value *ucontrol)
2651 {
2652         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2653         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2654         struct soc_mixer_control *mc =
2655                 (struct soc_mixer_control *)kcontrol->private_value;
2656         struct wm_adsp *dsp = &dsps[mc->shift - 1];
2657
2658         ucontrol->value.integer.value[0] = dsp->preloaded;
2659
2660         return 0;
2661 }
2662 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
2663
2664 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
2665                            struct snd_ctl_elem_value *ucontrol)
2666 {
2667         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2668         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2669         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2670         struct soc_mixer_control *mc =
2671                 (struct soc_mixer_control *)kcontrol->private_value;
2672         struct wm_adsp *dsp = &dsps[mc->shift - 1];
2673         char preload[32];
2674
2675         snprintf(preload, ARRAY_SIZE(preload), "DSP%u Preload", mc->shift);
2676
2677         dsp->preloaded = ucontrol->value.integer.value[0];
2678
2679         if (ucontrol->value.integer.value[0])
2680                 snd_soc_component_force_enable_pin(component, preload);
2681         else
2682                 snd_soc_component_disable_pin(component, preload);
2683
2684         snd_soc_dapm_sync(dapm);
2685
2686         flush_work(&dsp->boot_work);
2687
2688         return 0;
2689 }
2690 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
2691
2692 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
2693 {
2694         switch (dsp->rev) {
2695         case 0:
2696         case 1:
2697                 return;
2698         default:
2699                 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
2700                                    ADSP2_WDT_ENA_MASK, 0);
2701         }
2702 }
2703
2704 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
2705                          struct snd_kcontrol *kcontrol, int event,
2706                          unsigned int freq)
2707 {
2708         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2709         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2710         struct wm_adsp *dsp = &dsps[w->shift];
2711         struct wm_coeff_ctl *ctl;
2712
2713         switch (event) {
2714         case SND_SOC_DAPM_PRE_PMU:
2715                 wm_adsp2_set_dspclk(dsp, freq);
2716                 queue_work(system_unbound_wq, &dsp->boot_work);
2717                 break;
2718         case SND_SOC_DAPM_PRE_PMD:
2719                 mutex_lock(&dsp->pwr_lock);
2720
2721                 wm_adsp_debugfs_clear(dsp);
2722
2723                 dsp->fw_id = 0;
2724                 dsp->fw_id_version = 0;
2725
2726                 dsp->booted = false;
2727
2728                 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2729                                    ADSP2_MEM_ENA, 0);
2730
2731                 list_for_each_entry(ctl, &dsp->ctl_list, list)
2732                         ctl->enabled = 0;
2733
2734                 wm_adsp_free_alg_regions(dsp);
2735
2736                 mutex_unlock(&dsp->pwr_lock);
2737
2738                 adsp_dbg(dsp, "Shutdown complete\n");
2739                 break;
2740         default:
2741                 break;
2742         }
2743
2744         return 0;
2745 }
2746 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2747
2748 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2749                    struct snd_kcontrol *kcontrol, int event)
2750 {
2751         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2752         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2753         struct wm_adsp *dsp = &dsps[w->shift];
2754         int ret;
2755
2756         switch (event) {
2757         case SND_SOC_DAPM_POST_PMU:
2758                 flush_work(&dsp->boot_work);
2759
2760                 mutex_lock(&dsp->pwr_lock);
2761
2762                 if (!dsp->booted) {
2763                         ret = -EIO;
2764                         goto err;
2765                 }
2766
2767                 ret = wm_adsp2_ena(dsp);
2768                 if (ret != 0)
2769                         goto err;
2770
2771                 /* Sync set controls */
2772                 ret = wm_coeff_sync_controls(dsp);
2773                 if (ret != 0)
2774                         goto err;
2775
2776                 wm_adsp2_lock(dsp, dsp->lock_regions);
2777
2778                 ret = regmap_update_bits(dsp->regmap,
2779                                          dsp->base + ADSP2_CONTROL,
2780                                          ADSP2_CORE_ENA | ADSP2_START,
2781                                          ADSP2_CORE_ENA | ADSP2_START);
2782                 if (ret != 0)
2783                         goto err;
2784
2785                 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
2786                         ret = wm_adsp_buffer_init(dsp);
2787                         if (ret < 0)
2788                                 goto err;
2789                 }
2790
2791                 dsp->running = true;
2792
2793                 mutex_unlock(&dsp->pwr_lock);
2794
2795                 break;
2796
2797         case SND_SOC_DAPM_PRE_PMD:
2798                 /* Tell the firmware to cleanup */
2799                 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2800
2801                 wm_adsp_stop_watchdog(dsp);
2802
2803                 /* Log firmware state, it can be useful for analysis */
2804                 switch (dsp->rev) {
2805                 case 0:
2806                         wm_adsp2_show_fw_status(dsp);
2807                         break;
2808                 default:
2809                         wm_adsp2v2_show_fw_status(dsp);
2810                         break;
2811                 }
2812
2813                 mutex_lock(&dsp->pwr_lock);
2814
2815                 dsp->running = false;
2816
2817                 regmap_update_bits(dsp->regmap,
2818                                    dsp->base + ADSP2_CONTROL,
2819                                    ADSP2_CORE_ENA | ADSP2_START, 0);
2820
2821                 /* Make sure DMAs are quiesced */
2822                 switch (dsp->rev) {
2823                 case 0:
2824                         regmap_write(dsp->regmap,
2825                                      dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2826                         regmap_write(dsp->regmap,
2827                                      dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2828                         regmap_write(dsp->regmap,
2829                                      dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2830
2831                         regmap_update_bits(dsp->regmap,
2832                                            dsp->base + ADSP2_CONTROL,
2833                                            ADSP2_SYS_ENA, 0);
2834                         break;
2835                 default:
2836                         regmap_write(dsp->regmap,
2837                                      dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2838                         regmap_write(dsp->regmap,
2839                                      dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2840                         regmap_write(dsp->regmap,
2841                                      dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2842                         break;
2843                 }
2844
2845                 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2846                         wm_adsp_buffer_free(dsp);
2847
2848                 mutex_unlock(&dsp->pwr_lock);
2849
2850                 adsp_dbg(dsp, "Execution stopped\n");
2851                 break;
2852
2853         default:
2854                 break;
2855         }
2856
2857         return 0;
2858 err:
2859         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2860                            ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2861         mutex_unlock(&dsp->pwr_lock);
2862         return ret;
2863 }
2864 EXPORT_SYMBOL_GPL(wm_adsp2_event);
2865
2866 int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
2867 {
2868         char preload[32];
2869
2870         snprintf(preload, ARRAY_SIZE(preload), "DSP%d Preload", dsp->num);
2871
2872         snd_soc_component_disable_pin(component, preload);
2873
2874         wm_adsp2_init_debugfs(dsp, component);
2875
2876         dsp->component = component;
2877
2878         return 0;
2879 }
2880 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
2881
2882 int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
2883 {
2884         wm_adsp2_cleanup_debugfs(dsp);
2885
2886         return 0;
2887 }
2888 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
2889
2890 int wm_adsp2_init(struct wm_adsp *dsp)
2891 {
2892         int ret;
2893
2894         switch (dsp->rev) {
2895         case 0:
2896                 /*
2897                  * Disable the DSP memory by default when in reset for a small
2898                  * power saving.
2899                  */
2900                 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2901                                          ADSP2_MEM_ENA, 0);
2902                 if (ret) {
2903                         adsp_err(dsp,
2904                                  "Failed to clear memory retention: %d\n", ret);
2905                         return ret;
2906                 }
2907                 break;
2908         default:
2909                 break;
2910         }
2911
2912         INIT_LIST_HEAD(&dsp->alg_regions);
2913         INIT_LIST_HEAD(&dsp->ctl_list);
2914         INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
2915
2916         mutex_init(&dsp->pwr_lock);
2917
2918         return 0;
2919 }
2920 EXPORT_SYMBOL_GPL(wm_adsp2_init);
2921
2922 void wm_adsp2_remove(struct wm_adsp *dsp)
2923 {
2924         struct wm_coeff_ctl *ctl;
2925
2926         while (!list_empty(&dsp->ctl_list)) {
2927                 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2928                                         list);
2929                 list_del(&ctl->list);
2930                 wm_adsp_free_ctl_blk(ctl);
2931         }
2932 }
2933 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2934
2935 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2936 {
2937         return compr->buf != NULL;
2938 }
2939
2940 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2941 {
2942         /*
2943          * Note this will be more complex once each DSP can support multiple
2944          * streams
2945          */
2946         if (!compr->dsp->buffer)
2947                 return -EINVAL;
2948
2949         compr->buf = compr->dsp->buffer;
2950         compr->buf->compr = compr;
2951
2952         return 0;
2953 }
2954
2955 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
2956 {
2957         if (!compr)
2958                 return;
2959
2960         /* Wake the poll so it can see buffer is no longer attached */
2961         if (compr->stream)
2962                 snd_compr_fragment_elapsed(compr->stream);
2963
2964         if (wm_adsp_compr_attached(compr)) {
2965                 compr->buf->compr = NULL;
2966                 compr->buf = NULL;
2967         }
2968 }
2969
2970 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2971 {
2972         struct wm_adsp_compr *compr;
2973         int ret = 0;
2974
2975         mutex_lock(&dsp->pwr_lock);
2976
2977         if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2978                 adsp_err(dsp, "Firmware does not support compressed API\n");
2979                 ret = -ENXIO;
2980                 goto out;
2981         }
2982
2983         if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2984                 adsp_err(dsp, "Firmware does not support stream direction\n");
2985                 ret = -EINVAL;
2986                 goto out;
2987         }
2988
2989         if (dsp->compr) {
2990                 /* It is expect this limitation will be removed in future */
2991                 adsp_err(dsp, "Only a single stream supported per DSP\n");
2992                 ret = -EBUSY;
2993                 goto out;
2994         }
2995
2996         compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2997         if (!compr) {
2998                 ret = -ENOMEM;
2999                 goto out;
3000         }
3001
3002         compr->dsp = dsp;
3003         compr->stream = stream;
3004
3005         dsp->compr = compr;
3006
3007         stream->runtime->private_data = compr;
3008
3009 out:
3010         mutex_unlock(&dsp->pwr_lock);
3011
3012         return ret;
3013 }
3014 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3015
3016 int wm_adsp_compr_free(struct snd_compr_stream *stream)
3017 {
3018         struct wm_adsp_compr *compr = stream->runtime->private_data;
3019         struct wm_adsp *dsp = compr->dsp;
3020
3021         mutex_lock(&dsp->pwr_lock);
3022
3023         wm_adsp_compr_detach(compr);
3024         dsp->compr = NULL;
3025
3026         kfree(compr->raw_buf);
3027         kfree(compr);
3028
3029         mutex_unlock(&dsp->pwr_lock);
3030
3031         return 0;
3032 }
3033 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3034
3035 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3036                                       struct snd_compr_params *params)
3037 {
3038         struct wm_adsp_compr *compr = stream->runtime->private_data;
3039         struct wm_adsp *dsp = compr->dsp;
3040         const struct wm_adsp_fw_caps *caps;
3041         const struct snd_codec_desc *desc;
3042         int i, j;
3043
3044         if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3045             params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3046             params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3047             params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3048             params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3049                 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
3050                          params->buffer.fragment_size,
3051                          params->buffer.fragments);
3052
3053                 return -EINVAL;
3054         }
3055
3056         for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3057                 caps = &wm_adsp_fw[dsp->fw].caps[i];
3058                 desc = &caps->desc;
3059
3060                 if (caps->id != params->codec.id)
3061                         continue;
3062
3063                 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3064                         if (desc->max_ch < params->codec.ch_out)
3065                                 continue;
3066                 } else {
3067                         if (desc->max_ch < params->codec.ch_in)
3068                                 continue;
3069                 }
3070
3071                 if (!(desc->formats & (1 << params->codec.format)))
3072                         continue;
3073
3074                 for (j = 0; j < desc->num_sample_rates; ++j)
3075                         if (desc->sample_rates[j] == params->codec.sample_rate)
3076                                 return 0;
3077         }
3078
3079         adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3080                  params->codec.id, params->codec.ch_in, params->codec.ch_out,
3081                  params->codec.sample_rate, params->codec.format);
3082         return -EINVAL;
3083 }
3084
3085 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3086 {
3087         return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3088 }
3089
3090 int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
3091                              struct snd_compr_params *params)
3092 {
3093         struct wm_adsp_compr *compr = stream->runtime->private_data;
3094         unsigned int size;
3095         int ret;
3096
3097         ret = wm_adsp_compr_check_params(stream, params);
3098         if (ret)
3099                 return ret;
3100
3101         compr->size = params->buffer;
3102
3103         adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
3104                  compr->size.fragment_size, compr->size.fragments);
3105
3106         size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3107         compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3108         if (!compr->raw_buf)
3109                 return -ENOMEM;
3110
3111         compr->sample_rate = params->codec.sample_rate;
3112
3113         return 0;
3114 }
3115 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3116
3117 int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
3118                            struct snd_compr_caps *caps)
3119 {
3120         struct wm_adsp_compr *compr = stream->runtime->private_data;
3121         int fw = compr->dsp->fw;
3122         int i;
3123
3124         if (wm_adsp_fw[fw].caps) {
3125                 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3126                         caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3127
3128                 caps->num_codecs = i;
3129                 caps->direction = wm_adsp_fw[fw].compr_direction;
3130
3131                 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3132                 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3133                 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3134                 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3135         }
3136
3137         return 0;
3138 }
3139 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3140
3141 static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3142                                    unsigned int mem_addr,
3143                                    unsigned int num_words, u32 *data)
3144 {
3145         struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3146         unsigned int i, reg;
3147         int ret;
3148
3149         if (!mem)
3150                 return -EINVAL;
3151
3152         reg = wm_adsp_region_to_reg(mem, mem_addr);
3153
3154         ret = regmap_raw_read(dsp->regmap, reg, data,
3155                               sizeof(*data) * num_words);
3156         if (ret < 0)
3157                 return ret;
3158
3159         for (i = 0; i < num_words; ++i)
3160                 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3161
3162         return 0;
3163 }
3164
3165 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3166                                          unsigned int mem_addr, u32 *data)
3167 {
3168         return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3169 }
3170
3171 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3172                                    unsigned int mem_addr, u32 data)
3173 {
3174         struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3175         unsigned int reg;
3176
3177         if (!mem)
3178                 return -EINVAL;
3179
3180         reg = wm_adsp_region_to_reg(mem, mem_addr);
3181
3182         data = cpu_to_be32(data & 0x00ffffffu);
3183
3184         return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3185 }
3186
3187 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3188                                       unsigned int field_offset, u32 *data)
3189 {
3190         return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
3191                                       buf->host_buf_ptr + field_offset, data);
3192 }
3193
3194 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3195                                        unsigned int field_offset, u32 data)
3196 {
3197         return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
3198                                        buf->host_buf_ptr + field_offset, data);
3199 }
3200
3201 static int wm_adsp_legacy_host_buf_addr(struct wm_adsp_compr_buf *buf)
3202 {
3203         struct wm_adsp_alg_region *alg_region;
3204         struct wm_adsp *dsp = buf->dsp;
3205         u32 xmalg, addr, magic;
3206         int i, ret;
3207
3208         alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3209         xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
3210
3211         addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3212         ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3213         if (ret < 0)
3214                 return ret;
3215
3216         if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3217                 return -EINVAL;
3218
3219         addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3220         for (i = 0; i < 5; ++i) {
3221                 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3222                                              &buf->host_buf_ptr);
3223                 if (ret < 0)
3224                         return ret;
3225
3226                 if (buf->host_buf_ptr)
3227                         break;
3228
3229                 usleep_range(1000, 2000);
3230         }
3231
3232         if (!buf->host_buf_ptr)
3233                 return -EIO;
3234
3235         adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3236
3237         return 0;
3238 }
3239
3240 static struct wm_coeff_ctl *
3241 wm_adsp_find_host_buffer_ctrl(struct wm_adsp_compr_buf *buf)
3242 {
3243         struct wm_adsp *dsp = buf->dsp;
3244         struct wm_coeff_ctl *ctl;
3245
3246         list_for_each_entry(ctl, &dsp->ctl_list, list) {
3247                 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3248                         continue;
3249
3250                 if (!ctl->enabled)
3251                         continue;
3252
3253                 return ctl;
3254         }
3255
3256         return NULL;
3257 }
3258
3259 static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
3260 {
3261         struct wm_adsp *dsp = buf->dsp;
3262         struct wm_coeff_ctl *ctl;
3263         unsigned int reg;
3264         u32 val;
3265         int i, ret;
3266
3267         ctl = wm_adsp_find_host_buffer_ctrl(buf);
3268         if (!ctl)
3269                 return wm_adsp_legacy_host_buf_addr(buf);
3270
3271         ret = wm_coeff_base_reg(ctl, &reg);
3272         if (ret)
3273                 return ret;
3274
3275         for (i = 0; i < 5; ++i) {
3276                 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
3277                 if (ret < 0)
3278                         return ret;
3279
3280                 if (val)
3281                         break;
3282
3283                 usleep_range(1000, 2000);
3284         }
3285
3286         if (!val)
3287                 return -EIO;
3288
3289         buf->host_buf_ptr = be32_to_cpu(val);
3290         adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3291
3292         return 0;
3293 }
3294
3295 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3296 {
3297         const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;