drm/amdgpu/vcn:Update latest spg mode stop for VCN
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / vcn_v1_0.c
index 5608d21..029ed6d 100644 (file)
@@ -1123,28 +1123,39 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
  */
 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
 {
-       /* force RBC into idle state */
-       WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
+       int ret_code, tmp;
 
-       /* Stall UMC and register bus before resetting VCPU */
-       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
-                       UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
-                       ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-       mdelay(1);
+       SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
+
+       tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+               UVD_LMI_STATUS__READ_CLEAN_MASK |
+               UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+               UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+       SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
 
        /* put VCPU into reset */
-       WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
-                       UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
-       mdelay(5);
+       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+               UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
+               ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+
+       tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+               UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+       SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
 
        /* disable VCPU clock */
-       WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
+       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
+               ~UVD_VCPU_CNTL__CLK_EN_MASK);
 
-       /* Unstall UMC and register bus */
-       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
-                       ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+       /* reset LMI UMC/LMI */
+       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+               UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
+               ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
+
+       WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+               UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
+               ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
 
-       WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
+       WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
 
        vcn_v1_0_enable_clock_gating(adev);
        vcn_1_0_enable_static_power_gating(adev);