Merge branches 'iommu/arm/smmu', 'iommu/updates', 'iommu/vt-d', 'iommu/ipmmu-vmsa...
[muen/linux.git] / drivers / iommu / arm-smmu.c
index e4a82d70d446bb6410933f63bb9c4c0971b8248b..78d4c6b8f1bad57477f598a45430a7e519e7af39 100644 (file)
@@ -59,6 +59,7 @@
 #define ARM_MMU500_ACTLR_CPRE          (1 << 1)
 
 #define ARM_MMU500_ACR_CACHE_LOCK      (1 << 26)
+#define ARM_MMU500_ACR_S2CRB_TLBEN     (1 << 10)
 #define ARM_MMU500_ACR_SMTNMB_TLBEN    (1 << 8)
 
 #define TLB_LOOP_TIMEOUT               1000000 /* 1s! */
@@ -119,14 +120,6 @@ enum arm_smmu_implementation {
        CAVIUM_SMMUV2,
 };
 
-/* Until ACPICA headers cover IORT rev. C */
-#ifndef ACPI_IORT_SMMU_CORELINK_MMU401
-#define ACPI_IORT_SMMU_CORELINK_MMU401 0x4
-#endif
-#ifndef ACPI_IORT_SMMU_CAVIUM_THUNDERX
-#define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x5
-#endif
-
 struct arm_smmu_s2cr {
        struct iommu_group              *group;
        int                             count;
@@ -1616,7 +1609,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
                 * Allow unmatched Stream IDs to allocate bypass
                 * TLB entries for reduced latency.
                 */
-               reg |= ARM_MMU500_ACR_SMTNMB_TLBEN;
+               reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN;
                writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
        }