Merge tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[muen/linux.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
index 35951e7b89d2fae33377dd56529811f8c0c3ad06..7100a2dd65f8c17c6b946f5cd093d4de90af4047 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * R8A7795 ES2.0+ processor support - PFC hardware block.
  *
- * Copyright (C) 2015-2016 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -472,7 +472,7 @@ FM(IP16_31_28)      IP16_31_28      FM(IP17_31_28)  IP17_31_28
 #define MOD_SEL1_26            FM(SEL_TIMER_TMU1_0)    FM(SEL_TIMER_TMU1_1)
 #define MOD_SEL1_25_24         FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 #define MOD_SEL1_23_22_21      FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
-#define MOD_SEL1_20            FM(SEL_SSI_0)           FM(SEL_SSI_1)
+#define MOD_SEL1_20            FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 #define MOD_SEL1_19            FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 #define MOD_SEL1_18_17         FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 #define MOD_SEL1_16            FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
@@ -1218,7 +1218,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
        PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
        PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
-       PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
        PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
        PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
        PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
@@ -1226,14 +1226,14 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
        PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
-       PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
        PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
        PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
        PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
 
        PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
        PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
-       PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
        PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
        PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
        PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
@@ -1241,7 +1241,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
        PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
        PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
-       PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI_0),
+       PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
        PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
        PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
        PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
@@ -1250,7 +1250,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
        PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
        PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
-       PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI_0),
+       PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
        PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
        PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
        PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
@@ -1265,7 +1265,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
        PINMUX_IPSR_GPSR(IP14_3_0,      NFWP_N_A),
        PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
-       PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI_0),
+       PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
        PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
        PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
        PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU1_1),
@@ -1274,7 +1274,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
        PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
        PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
-       PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI_0),
+       PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
        PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
        PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
        PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
@@ -1302,10 +1302,10 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
 
        /* IPSR15 */
-       PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI_0),
+       PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
 
-       PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI_0),
-       PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
+       PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
 
        PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
        PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
@@ -1394,11 +1394,11 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
        PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
 
-       PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI_0),
+       PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
        PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
        PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
        PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
-       PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
        PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
        PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
        PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
@@ -1430,7 +1430,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
        PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
-       PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI_0),
+       PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
        PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
        PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
        PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
@@ -1440,7 +1440,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
        PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
-       PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI_0),
+       PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
        PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
        PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
        PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
@@ -1450,7 +1450,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
        PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
-       PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
        PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
        PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
        PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
@@ -1462,7 +1462,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
        PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
-       PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
        PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
        PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
        PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
@@ -1473,7 +1473,7 @@ static const u16 pinmux_data[] = {
        /* IPSR18 */
        PINMUX_IPSR_GPSR(IP18_3_0,      USB2_CH3_PWEN),
        PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
-       PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
        PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
        PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
        PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
@@ -1483,7 +1483,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP18_7_4,      USB2_CH3_OVC),
        PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
-       PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI_1),
+       PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
        PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
        PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
        PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
@@ -1711,11 +1711,11 @@ static const unsigned int avb_phy_int_pins[] = {
 static const unsigned int avb_phy_int_mux[] = {
        AVB_PHY_INT_MARK,
 };
-static const unsigned int avb_mdc_pins[] = {
+static const unsigned int avb_mdio_pins[] = {
        /* AVB_MDC, AVB_MDIO */
        RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
 };
-static const unsigned int avb_mdc_mux[] = {
+static const unsigned int avb_mdio_mux[] = {
        AVB_MDC_MARK, AVB_MDIO_MARK,
 };
 static const unsigned int avb_mii_pins[] = {
@@ -2127,6 +2127,22 @@ static const unsigned int du_disp_mux[] = {
        DU_DISP_MARK,
 };
 
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi0_cec_pins[] = {
+       /* HDMI0_CEC */
+       RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hdmi0_cec_mux[] = {
+       HDMI0_CEC_MARK,
+};
+static const unsigned int hdmi1_cec_pins[] = {
+       /* HDMI1_CEC */
+       RCAR_GP_PIN(7, 3),
+};
+static const unsigned int hdmi1_cec_mux[] = {
+       HDMI1_CEC_MARK,
+};
+
 /* - HSCIF0 ----------------------------------------------------------------- */
 static const unsigned int hscif0_data_pins[] = {
        /* RX, TX */
@@ -3839,6 +3855,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
        SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
 };
 
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(6, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+       TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(5, 19),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+       TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(6, 19),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+       TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+       TCLK2_B_MARK,
+};
+
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
        /* PWEN, OVC */
@@ -3881,6 +3927,236 @@ static const unsigned int usb30_mux[] = {
        USB30_PWEN_MARK, USB30_OVC_MARK,
 };
 
+/* - VIN4 ------------------------------------------------------------------- */
+static const unsigned int vin4_data18_a_pins[] = {
+       RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+       RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+       RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+       RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+       RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin4_data18_a_mux[] = {
+       VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+       VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+       VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+       VI4_DATA10_MARK, VI4_DATA11_MARK,
+       VI4_DATA12_MARK, VI4_DATA13_MARK,
+       VI4_DATA14_MARK, VI4_DATA15_MARK,
+       VI4_DATA18_MARK, VI4_DATA19_MARK,
+       VI4_DATA20_MARK, VI4_DATA21_MARK,
+       VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+static const unsigned int vin4_data18_b_pins[] = {
+       RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+       RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+       RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+       RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+       RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin4_data18_b_mux[] = {
+       VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+       VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+       VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+       VI4_DATA10_MARK, VI4_DATA11_MARK,
+       VI4_DATA12_MARK, VI4_DATA13_MARK,
+       VI4_DATA14_MARK, VI4_DATA15_MARK,
+       VI4_DATA18_MARK, VI4_DATA19_MARK,
+       VI4_DATA20_MARK, VI4_DATA21_MARK,
+       VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+static const union vin_data vin4_data_a_pins = {
+       .data24 = {
+               RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+               RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+               RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+               RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+               RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+               RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+               RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+               RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+               RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+               RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+               RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+               RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+       },
+};
+static const union vin_data vin4_data_a_mux = {
+       .data24 = {
+               VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+               VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+               VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+               VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+               VI4_DATA8_MARK,  VI4_DATA9_MARK,
+               VI4_DATA10_MARK, VI4_DATA11_MARK,
+               VI4_DATA12_MARK, VI4_DATA13_MARK,
+               VI4_DATA14_MARK, VI4_DATA15_MARK,
+               VI4_DATA16_MARK, VI4_DATA17_MARK,
+               VI4_DATA18_MARK, VI4_DATA19_MARK,
+               VI4_DATA20_MARK, VI4_DATA21_MARK,
+               VI4_DATA22_MARK, VI4_DATA23_MARK,
+       },
+};
+static const union vin_data vin4_data_b_pins = {
+       .data24 = {
+               RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+               RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+               RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+               RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+               RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+               RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+               RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+               RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+               RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+               RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+               RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+               RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+       },
+};
+static const union vin_data vin4_data_b_mux = {
+       .data24 = {
+               VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+               VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+               VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+               VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+               VI4_DATA8_MARK,  VI4_DATA9_MARK,
+               VI4_DATA10_MARK, VI4_DATA11_MARK,
+               VI4_DATA12_MARK, VI4_DATA13_MARK,
+               VI4_DATA14_MARK, VI4_DATA15_MARK,
+               VI4_DATA16_MARK, VI4_DATA17_MARK,
+               VI4_DATA18_MARK, VI4_DATA19_MARK,
+               VI4_DATA20_MARK, VI4_DATA21_MARK,
+               VI4_DATA22_MARK, VI4_DATA23_MARK,
+       },
+};
+static const unsigned int vin4_sync_pins[] = {
+       /* HSYNC#, VSYNC# */
+       RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int vin4_sync_mux[] = {
+       VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
+};
+static const unsigned int vin4_field_pins[] = {
+       /* FIELD */
+       RCAR_GP_PIN(1, 16),
+};
+static const unsigned int vin4_field_mux[] = {
+       VI4_FIELD_MARK,
+};
+static const unsigned int vin4_clkenb_pins[] = {
+       /* CLKENB */
+       RCAR_GP_PIN(1, 19),
+};
+static const unsigned int vin4_clkenb_mux[] = {
+       VI4_CLKENB_MARK,
+};
+static const unsigned int vin4_clk_pins[] = {
+       /* CLK */
+       RCAR_GP_PIN(1, 27),
+};
+static const unsigned int vin4_clk_mux[] = {
+       VI4_CLK_MARK,
+};
+
+/* - VIN5 ------------------------------------------------------------------- */
+static const unsigned int vin5_data8_pins[] = {
+       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin5_data8_mux[] = {
+       VI5_DATA0_MARK, VI5_DATA1_MARK,
+       VI5_DATA2_MARK, VI5_DATA3_MARK,
+       VI5_DATA4_MARK, VI5_DATA5_MARK,
+       VI5_DATA6_MARK, VI5_DATA7_MARK,
+};
+static const unsigned int vin5_data10_pins[] = {
+       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int vin5_data10_mux[] = {
+       VI5_DATA0_MARK, VI5_DATA1_MARK,
+       VI5_DATA2_MARK, VI5_DATA3_MARK,
+       VI5_DATA4_MARK, VI5_DATA5_MARK,
+       VI5_DATA6_MARK, VI5_DATA7_MARK,
+       VI5_DATA8_MARK,  VI5_DATA9_MARK,
+};
+static const unsigned int vin5_data12_pins[] = {
+       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+};
+static const unsigned int vin5_data12_mux[] = {
+       VI5_DATA0_MARK, VI5_DATA1_MARK,
+       VI5_DATA2_MARK, VI5_DATA3_MARK,
+       VI5_DATA4_MARK, VI5_DATA5_MARK,
+       VI5_DATA6_MARK, VI5_DATA7_MARK,
+       VI5_DATA8_MARK,  VI5_DATA9_MARK,
+       VI5_DATA10_MARK, VI5_DATA11_MARK,
+};
+static const unsigned int vin5_data16_pins[] = {
+       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+       RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin5_data16_mux[] = {
+       VI5_DATA0_MARK, VI5_DATA1_MARK,
+       VI5_DATA2_MARK, VI5_DATA3_MARK,
+       VI5_DATA4_MARK, VI5_DATA5_MARK,
+       VI5_DATA6_MARK, VI5_DATA7_MARK,
+       VI5_DATA8_MARK,  VI5_DATA9_MARK,
+       VI5_DATA10_MARK, VI5_DATA11_MARK,
+       VI5_DATA12_MARK, VI5_DATA13_MARK,
+       VI5_DATA14_MARK, VI5_DATA15_MARK,
+};
+static const unsigned int vin5_sync_pins[] = {
+       /* HSYNC#, VSYNC# */
+       RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int vin5_sync_mux[] = {
+       VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
+};
+static const unsigned int vin5_field_pins[] = {
+       RCAR_GP_PIN(1, 11),
+};
+static const unsigned int vin5_field_mux[] = {
+       /* FIELD */
+       VI5_FIELD_MARK,
+};
+static const unsigned int vin5_clkenb_pins[] = {
+       RCAR_GP_PIN(1, 20),
+};
+static const unsigned int vin5_clkenb_mux[] = {
+       /* CLKENB */
+       VI5_CLKENB_MARK,
+};
+static const unsigned int vin5_clk_pins[] = {
+       RCAR_GP_PIN(1, 21),
+};
+static const unsigned int vin5_clk_mux[] = {
+       /* CLK */
+       VI5_CLK_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(audio_clk_a_a),
        SH_PFC_PIN_GROUP(audio_clk_a_b),
@@ -3902,7 +4178,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(avb_link),
        SH_PFC_PIN_GROUP(avb_magic),
        SH_PFC_PIN_GROUP(avb_phy_int),
-       SH_PFC_PIN_GROUP(avb_mdc),
+       SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
+       SH_PFC_PIN_GROUP(avb_mdio),
        SH_PFC_PIN_GROUP(avb_mii),
        SH_PFC_PIN_GROUP(avb_avtp_pps),
        SH_PFC_PIN_GROUP(avb_avtp_match_a),
@@ -3954,6 +4231,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(du_oddf),
        SH_PFC_PIN_GROUP(du_cde),
        SH_PFC_PIN_GROUP(du_disp),
+       SH_PFC_PIN_GROUP(hdmi0_cec),
+       SH_PFC_PIN_GROUP(hdmi1_cec),
        SH_PFC_PIN_GROUP(hscif0_data),
        SH_PFC_PIN_GROUP(hscif0_clk),
        SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4189,11 +4468,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(ssi9_data_b),
        SH_PFC_PIN_GROUP(ssi9_ctrl_a),
        SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+       SH_PFC_PIN_GROUP(tmu_tclk1_a),
+       SH_PFC_PIN_GROUP(tmu_tclk1_b),
+       SH_PFC_PIN_GROUP(tmu_tclk2_a),
+       SH_PFC_PIN_GROUP(tmu_tclk2_b),
        SH_PFC_PIN_GROUP(usb0),
        SH_PFC_PIN_GROUP(usb1),
        SH_PFC_PIN_GROUP(usb2),
        SH_PFC_PIN_GROUP(usb2_ch3),
        SH_PFC_PIN_GROUP(usb30),
+       VIN_DATA_PIN_GROUP(vin4_data_a, 8),
+       VIN_DATA_PIN_GROUP(vin4_data_a, 10),
+       VIN_DATA_PIN_GROUP(vin4_data_a, 12),
+       VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+       SH_PFC_PIN_GROUP(vin4_data18_a),
+       VIN_DATA_PIN_GROUP(vin4_data_a, 20),
+       VIN_DATA_PIN_GROUP(vin4_data_a, 24),
+       VIN_DATA_PIN_GROUP(vin4_data_b, 8),
+       VIN_DATA_PIN_GROUP(vin4_data_b, 10),
+       VIN_DATA_PIN_GROUP(vin4_data_b, 12),
+       VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+       SH_PFC_PIN_GROUP(vin4_data18_b),
+       VIN_DATA_PIN_GROUP(vin4_data_b, 20),
+       VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+       SH_PFC_PIN_GROUP(vin4_sync),
+       SH_PFC_PIN_GROUP(vin4_field),
+       SH_PFC_PIN_GROUP(vin4_clkenb),
+       SH_PFC_PIN_GROUP(vin4_clk),
+       SH_PFC_PIN_GROUP(vin5_data8),
+       SH_PFC_PIN_GROUP(vin5_data10),
+       SH_PFC_PIN_GROUP(vin5_data12),
+       SH_PFC_PIN_GROUP(vin5_data16),
+       SH_PFC_PIN_GROUP(vin5_sync),
+       SH_PFC_PIN_GROUP(vin5_field),
+       SH_PFC_PIN_GROUP(vin5_clkenb),
+       SH_PFC_PIN_GROUP(vin5_clk),
 };
 
 static const char * const audio_clk_groups[] = {
@@ -4220,7 +4529,8 @@ static const char * const avb_groups[] = {
        "avb_link",
        "avb_magic",
        "avb_phy_int",
-       "avb_mdc",
+       "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
+       "avb_mdio",
        "avb_mii",
        "avb_avtp_pps",
        "avb_avtp_match_a",
@@ -4304,6 +4614,14 @@ static const char * const du_groups[] = {
        "du_disp",
 };
 
+static const char * const hdmi0_groups[] = {
+       "hdmi0_cec",
+};
+
+static const char * const hdmi1_groups[] = {
+       "hdmi1_cec",
+};
+
 static const char * const hscif0_groups[] = {
        "hscif0_data",
        "hscif0_clk",
@@ -4638,6 +4956,13 @@ static const char * const ssi_groups[] = {
        "ssi9_ctrl_b",
 };
 
+static const char * const tmu_groups[] = {
+       "tmu_tclk1_a",
+       "tmu_tclk1_b",
+       "tmu_tclk2_a",
+       "tmu_tclk2_b",
+};
+
 static const char * const usb0_groups[] = {
        "usb0",
 };
@@ -4658,6 +4983,38 @@ static const char * const usb30_groups[] = {
        "usb30",
 };
 
+static const char * const vin4_groups[] = {
+       "vin4_data8_a",
+       "vin4_data10_a",
+       "vin4_data12_a",
+       "vin4_data16_a",
+       "vin4_data18_a",
+       "vin4_data20_a",
+       "vin4_data24_a",
+       "vin4_data8_b",
+       "vin4_data10_b",
+       "vin4_data12_b",
+       "vin4_data16_b",
+       "vin4_data18_b",
+       "vin4_data20_b",
+       "vin4_data24_b",
+       "vin4_sync",
+       "vin4_field",
+       "vin4_clkenb",
+       "vin4_clk",
+};
+
+static const char * const vin5_groups[] = {
+       "vin5_data8",
+       "vin5_data10",
+       "vin5_data12",
+       "vin5_data16",
+       "vin5_sync",
+       "vin5_field",
+       "vin5_clkenb",
+       "vin5_clk",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(audio_clk),
        SH_PFC_FUNCTION(avb),
@@ -4671,6 +5028,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(drif2),
        SH_PFC_FUNCTION(drif3),
        SH_PFC_FUNCTION(du),
+       SH_PFC_FUNCTION(hdmi0),
+       SH_PFC_FUNCTION(hdmi1),
        SH_PFC_FUNCTION(hscif0),
        SH_PFC_FUNCTION(hscif1),
        SH_PFC_FUNCTION(hscif2),
@@ -4704,11 +5063,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(sdhi2),
        SH_PFC_FUNCTION(sdhi3),
        SH_PFC_FUNCTION(ssi),
+       SH_PFC_FUNCTION(tmu),
        SH_PFC_FUNCTION(usb0),
        SH_PFC_FUNCTION(usb1),
        SH_PFC_FUNCTION(usb2),
        SH_PFC_FUNCTION(usb2_ch3),
        SH_PFC_FUNCTION(usb30),
+       SH_PFC_FUNCTION(vin4),
+       SH_PFC_FUNCTION(vin5),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {